[ARM] Add support for armv7ve triple in llvm (PR31358).

[manojgupta]

Summary

Gcc supports target armv7ve which is armv7-a with virtualization
extensions. This change add support for this in llvm for gcc
compatibility.

Also remove redundant FeatureHWDiv, FeatureHWDivARM for a few models
as this is specified automatically by FeatureVirtualization.

The corresponding clang change is at https://reviews.llvm.org/D29773 .

Subscribers: aemerson, llvm-commits, rengolin

Differential Revision: https://reviews.llvm.org/D29472

[manojgupta]

Adding reviewers from Arm.

[ab]

I don't think we can unilaterally add MachO subtypes: I would remove all MachO changes.

Otherwise, this seems reasonable. Can you update the TargetParser unittest?

[manojgupta]

Updates as requested:

1. Removed Mach-o changes.
2. Updated TargetParser UnitTest.

[richard.barton.arm]

Hi Manoj

Virtualization requires TrustZone so I have added a few comments where I think this is missing. Looks like there are existing bugs in this area which you have propagated into your patch for ARMv7-VE. Would be good to fix the whole lot at once.

Shouldn't new TargetParser options also get a clang test for the new commandline? I was also expecting a build attributes test added to test/CodeGen/ARM/build-attributes.ll testing the Virtualization and Div attributes are set correctly.

include/llvm/Support/ARMTargetParser.def

86 ↗

(On Diff #86878)

The Virtualization extension requires TrustZone, so I would expect to see AEK_SEC in this list, unless this is implied by AEK_VIRT. I guess from the Divide macros also given that it is not.

lib/Target/ARM/ARM.td

450 ↗

(On Diff #86878)

Same comment here about lack of TrustZone with Virtualization. I think this should reallybe part of the FeatureVirtualization definition higher in the file. This definition also includes the two divide Features, so they are redundant here and can be removed. The same comment could perhaps be made for a number of other targets in this file.

lib/Target/ARM/ARMSubtarget.h

55 ↗

(On Diff #86878)

Being super pedantic, after ARMv7-A would be a more logical order. Super super pedantic there

[manojgupta]

Hi Richard,

After making the changes you suggested, I am getting a test fail in build-attributes for cortex-r52 wrt Tag_Virtualization_use.
I noticed that cortex-r52 uses armv8-r arch model but armv8-r does not have TrustZone in its supported features. Is this correct ?
And if so, I can not add TrustZone to FeatureVirtualization sublist.

If TrustZone is indeed supported for Armv8-r, I'll simply fix the test for cortex-r52.

def : ProcessorModel<"cortex-r52", CortexR52Model, [ARMv8r, ProcR52,

FeatureFPAO]>;

def ARMv8r : Architecture<"armv8-r", "ARMv8r", [HasV8Ops,

FeatureRClass,
FeatureDB,
FeatureHWDiv,
FeatureHWDivARM,
FeatureT2XtPk,
FeatureDSP,
FeatureCRC,
FeatureMP,
FeatureVirtualization,  // No Trustzone in this list
FeatureFPARMv8,
FeatureNEON]>;

Failure details:

Before (ToT):
.eabi_attribute 68, 2 @ Tag_Virtualization_use

After adding TrustZone:
.eabi_attribute 68, 3 @ Tag_Virtualization_use

Thanks,
Manoj

[manojgupta]

Updated as per Richard comments. Did not add TrustZone to FeatureVirtualization since Armv8-r supports virtualization but not TrustZone.
Added more tests for armv7ve.

[richard.barton.arm]

Hi Manoj

Sorry for not getting back to you yesterday. As you have concluded, ARMv8-R has not got the Security extension, which ruins my idea of neatly encapsulating this in the Virtualization extension definiton.

The new patch is fine save for a missing multiprocessing extension feature in the .td

lib/Target/ARM/ARM.td

427 ↗

(On Diff #87833)

FeatureMP is missing from here. The Virtualization extension on ARMv7-A requires the MP extension, Security Extension and Divide extensions (and some other things which are not interesting to MC).

[manojgupta]

Added FeatureMP.

[richard.barton.arm]

Thanks Manoj - this now also LGTM.

[manojgupta]

Thanks Richard. I will wait for Mehdi's approval since he is a blocking reviewer.

[efriedma]

You can ignore that; I added Medhi because the initial version of the patch had some MachO changes that would have needed approval from someone at Apple.

[mehdi_amini]

Yeah ignore me please :)

llvm/trunk/include/llvm/ADT/Triple.h

enum SubArchType {
     ARMSubArch_v8r,
     ARMSubArch_v8m_baseline,
     ARMSubArch_v8m_mainline,
     ARMSubArch_v7,
     ARMSubArch_v7em,
     ARMSubArch_v7m,
     ARMSubArch_v7s,
     ARMSubArch_v7k,
+    ARMSubArch_v7ve,
     ARMSubArch_v6,
     ARMSubArch_v6m,
     ARMSubArch_v6k,
     ARMSubArch_v6t2,
     ARMSubArch_v5,
     ARMSubArch_v5te,
     ARMSubArch_v4t,
 

llvm/trunk/include/llvm/Support/ARMTargetParser.def

 ARM_ARCH("armv6t2", AK_ARMV6T2, "6T2", "v6t2", ARMBuildAttrs::CPUArch::v6T2,
           FK_NONE, ARM::AEK_DSP)
 ARM_ARCH("armv6kz", AK_ARMV6KZ, "6KZ", "v6kz", ARMBuildAttrs::CPUArch::v6KZ,
           FK_VFPV2, (ARM::AEK_SEC | ARM::AEK_DSP))
 ARM_ARCH("armv6-m", AK_ARMV6M, "6-M", "v6m", ARMBuildAttrs::CPUArch::v6_M,
           FK_NONE, ARM::AEK_NONE)
 ARM_ARCH("armv7-a", AK_ARMV7A, "7-A", "v7", ARMBuildAttrs::CPUArch::v7,
           FK_NEON, ARM::AEK_DSP)
+ARM_ARCH("armv7ve", AK_ARMV7VE, "7VE", "v7ve", ARMBuildAttrs::CPUArch::v7,
+          FK_NEON, (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT |
+          ARM::AEK_HWDIVARM | ARM::AEK_HWDIV | ARM::AEK_DSP))
 ARM_ARCH("armv7-r", AK_ARMV7R, "7-R", "v7r", ARMBuildAttrs::CPUArch::v7,
           FK_NONE, (ARM::AEK_HWDIV | ARM::AEK_DSP))
 ARM_ARCH("armv7-m", AK_ARMV7M, "7-M", "v7m", ARMBuildAttrs::CPUArch::v7,
           FK_NONE, ARM::AEK_HWDIV)
 ARM_ARCH("armv7e-m", AK_ARMV7EM, "7E-M", "v7em", ARMBuildAttrs::CPUArch::v7E_M,
           FK_NONE, (ARM::AEK_HWDIV | ARM::AEK_DSP))
 ARM_ARCH("armv8-a", AK_ARMV8A, "8-A", "v8", ARMBuildAttrs::CPUArch::v8_A,
          FK_CRYPTO_NEON_FP_ARMV8,

llvm/trunk/lib/Support/TargetParser.cpp

unsigned llvm::ARM::parseArchProfile(StringRef Arch) {
   case ARM::AK_ARMV7EM:
   case ARM::AK_ARMV8MMainline:
   case ARM::AK_ARMV8MBaseline:
     return ARM::PK_M;
   case ARM::AK_ARMV7R:
   case ARM::AK_ARMV8R:
     return ARM::PK_R;
   case ARM::AK_ARMV7A:
+  case ARM::AK_ARMV7VE:
   case ARM::AK_ARMV7K:
   case ARM::AK_ARMV8A:
   case ARM::AK_ARMV8_1A:
   case ARM::AK_ARMV8_2A:
     return ARM::PK_A;
   }
   return ARM::PK_INVALID;
 }
case ARM::AK_ARMV5TEJ:
     return 5;
   case ARM::AK_ARMV6:
   case ARM::AK_ARMV6K:
   case ARM::AK_ARMV6T2:
   case ARM::AK_ARMV6KZ:
   case ARM::AK_ARMV6M:
     return 6;
   case ARM::AK_ARMV7A:
+  case ARM::AK_ARMV7VE:
   case ARM::AK_ARMV7R:
   case ARM::AK_ARMV7M:
   case ARM::AK_ARMV7S:
   case ARM::AK_ARMV7EM:
   case ARM::AK_ARMV7K:
     return 7;
   case ARM::AK_ARMV8A:
   case ARM::AK_ARMV8_1A:

llvm/trunk/lib/Support/Triple.cpp

case ARM::AK_ARMV6KZ:
     return Triple::ARMSubArch_v6k;
   case ARM::AK_ARMV6T2:
     return Triple::ARMSubArch_v6t2;
   case ARM::AK_ARMV6M:
     return Triple::ARMSubArch_v6m;
   case ARM::AK_ARMV7A:
   case ARM::AK_ARMV7R:
     return Triple::ARMSubArch_v7;
+  case ARM::AK_ARMV7VE:
+    return Triple::ARMSubArch_v7ve;
   case ARM::AK_ARMV7K:
     return Triple::ARMSubArch_v7k;
   case ARM::AK_ARMV7M:
     return Triple::ARMSubArch_v7m;
   case ARM::AK_ARMV7S:
     return Triple::ARMSubArch_v7s;
   case ARM::AK_ARMV7EM:
     return Triple::ARMSubArch_v7em;

llvm/trunk/lib/Target/ARM/ARM.td

 
 def ARMv7a    : Architecture<"armv7-a",   "ARMv7a",   [HasV7Ops,
                                                        FeatureNEON,
                                                        FeatureDB,
                                                        FeatureDSP,
                                                        FeatureAClass,
                                                        FeatureT2XtPk]>;
 
+def ARMv7ve   : Architecture<"armv7ve",   "ARMv7ve",  [HasV7Ops,
+                                                       FeatureNEON,
+                                                       FeatureDB,
+                                                       FeatureDSP,
+                                                       FeatureTrustZone,
+                                                       FeatureMP,
+                                                       FeatureVirtualization,
+                                                       FeatureAClass,
+                                                       FeatureT2XtPk]>;
+
 def ARMv7r    : Architecture<"armv7-r",   "ARMv7r",   [HasV7Ops,
                                                        FeatureDB,
                                                        FeatureDSP,
                                                        FeatureHWDiv,
                                                        FeatureRClass,
                                                        FeatureT2XtPk]>;
 
 def ARMv7m    : Architecture<"armv7-m",   "ARMv7m",   [HasV7Ops,
def ARMv82a   : Architecture<"armv8.2-a", "ARMv82a",  [HasV8_2aOps,
                                                        FeatureVirtualization,
                                                        FeatureCrypto,
                                                        FeatureCRC,
                                                        FeatureRAS]>;
 
 def ARMv8r    : Architecture<"armv8-r",   "ARMv8r",   [HasV8Ops,
                                                        FeatureRClass,
                                                        FeatureDB,
-                                                       FeatureHWDiv,
-                                                       FeatureHWDivARM,
                                                        FeatureT2XtPk,
                                                        FeatureDSP,
                                                        FeatureCRC,
                                                        FeatureMP,
                                                        FeatureVirtualization,
                                                        FeatureFPARMv8,
                                                        FeatureNEON]>;
 
def : ProcessorModel<"cortex-a7",   CortexA8Model,      [ARMv7a, ProcA7,
                                                          FeatureHasRetAddrStack,
                                                          FeatureTrustZone,
                                                          FeatureSlowFPBrcc,
                                                          FeatureHasVMLxHazards,
                                                          FeatureHasSlowFPVMLx,
                                                          FeatureVMLxForwarding,
                                                          FeatureMP,
                                                          FeatureVFP4,
-                                                         FeatureHWDiv,
-                                                         FeatureHWDivARM,
                                                          FeatureVirtualization]>;
 
 def : ProcessorModel<"cortex-a8",   CortexA8Model,      [ARMv7a, ProcA8,
                                                          FeatureHasRetAddrStack,
                                                          FeatureNonpipelinedVFP,
                                                          FeatureTrustZone,
                                                          FeatureSlowFPBrcc,
                                                          FeatureHasVMLxHazards,
def : ProcessorModel<"cortex-a9",   CortexA9Model,      [ARMv7a, ProcA9,
                                                          FeatureMP]>;
 
 // FIXME: A12 has currently the same Schedule model as A9
 def : ProcessorModel<"cortex-a12",  CortexA9Model,      [ARMv7a, ProcA12,
                                                          FeatureHasRetAddrStack,
                                                          FeatureTrustZone,
                                                          FeatureVMLxForwarding,
                                                          FeatureVFP4,
-                                                         FeatureHWDiv,
-                                                         FeatureHWDivARM,
                                                          FeatureAvoidPartialCPSR,
                                                          FeatureVirtualization,
                                                          FeatureMP]>;
 
 // FIXME: A15 has currently the same Schedule model as A9.
 def : ProcessorModel<"cortex-a15",  CortexA9Model,      [ARMv7a, ProcA15,
                                                          FeatureDontWidenVMOVS,
                                                          FeatureHasRetAddrStack,
                                                          FeatureMuxedUnits,
                                                          FeatureTrustZone,
                                                          FeatureVFP4,
                                                          FeatureMP,
                                                          FeatureCheckVLDnAlign,
-                                                         FeatureHWDiv,
-                                                         FeatureHWDivARM,
                                                          FeatureAvoidPartialCPSR,
                                                          FeatureVirtualization]>;
 
 // FIXME: A17 has currently the same Schedule model as A9
 def : ProcessorModel<"cortex-a17",  CortexA9Model,      [ARMv7a, ProcA17,
                                                          FeatureHasRetAddrStack,
                                                          FeatureTrustZone,
                                                          FeatureMP,
                                                          FeatureVMLxForwarding,
                                                          FeatureVFP4,
-                                                         FeatureHWDiv,
-                                                         FeatureHWDivARM,
                                                          FeatureAvoidPartialCPSR,
                                                          FeatureVirtualization]>;
 
 // FIXME: krait has currently the same Schedule model as A9
 // FIXME: krait has currently the same features as A9 plus VFP4 and hardware
 //        division features.
 def : ProcessorModel<"krait",       CortexA9Model,      [ARMv7a, ProcKrait,
                                                          FeatureHasRetAddrStack,

llvm/trunk/lib/Target/ARM/ARMSubtarget.h

enum ARMProcFamilyEnum {
     CortexA32, CortexA35, CortexA53, CortexA57, CortexA72, CortexA73,
     Krait, Swift, ExynosM1
   };
   enum ARMProcClassEnum {
     None, AClass, RClass, MClass
   };
   enum ARMArchEnum {
     ARMv2, ARMv2a, ARMv3, ARMv3m, ARMv4, ARMv4t, ARMv5, ARMv5t, ARMv5te,
-    ARMv5tej, ARMv6, ARMv6k, ARMv6kz, ARMv6t2, ARMv6m, ARMv6sm, ARMv7a, ARMv7r,
-    ARMv7m, ARMv7em, ARMv8a, ARMv81a, ARMv82a, ARMv8mMainline, ARMv8mBaseline,
-    ARMv8r
+    ARMv5tej, ARMv6, ARMv6k, ARMv6kz, ARMv6t2, ARMv6m, ARMv6sm, ARMv7a, ARMv7ve,
+    ARMv7r, ARMv7m, ARMv7em, ARMv8a, ARMv81a, ARMv82a, ARMv8mMainline,
+    ARMv8mBaseline, ARMv8r
   };
 
 public:
   /// What kind of timing do load multiple/store multiple instructions have.
   enum ARMLdStMultipleTiming {
     /// Can load/store 2 registers/cycle.
     DoubleIssue,
     /// Can load/store 2 registers/cycle, but needs an extra cycle if the access

llvm/trunk/test/CodeGen/ARM/build-attributes.ll

 ; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=exynos-m2 | FileCheck %s --check-prefix=NO-STRICT-ALIGN
 ; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=exynos-m2 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
 ; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=exynos-m3 | FileCheck %s --check-prefix=NO-STRICT-ALIGN
 ; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=exynos-m3 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
 
 ; ARMv7a
 ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 | FileCheck %s --check-prefix=NO-STRICT-ALIGN
 ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
+; ARMv7ve
+; RUN: llc < %s -mtriple=armv7ve-none-linux-gnueabi | FileCheck %s --check-prefix=V7VE
 ; ARMv7r
 ; RUN: llc < %s -mtriple=armv7r-none-linux-gnueabi -mcpu=cortex-r5 | FileCheck %s --check-prefix=NO-STRICT-ALIGN
 ; RUN: llc < %s -mtriple=armv7r-none-linux-gnueabi -mcpu=cortex-r5 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
 ; ARMv7m
 ; RUN: llc < %s -mtriple=thumbv7m-none-linux-gnueabi -mcpu=cortex-m3 | FileCheck %s --check-prefix=NO-STRICT-ALIGN
 ; RUN: llc < %s -mtriple=thumbv7m-none-linux-gnueabi -mcpu=cortex-m3 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
 ; ARMv6
 ; RUN: llc < %s -mtriple=armv6-none-netbsd-gnueabi -mcpu=arm1136j-s | FileCheck %s --check-prefix=NO-STRICT-ALIGN

 ; V7-FAST-NOT:   .eabi_attribute 19
 ;; The default CPU does have an FPU and it must be VFPv3 or better, so it flushes
 ;; denormals to zero preserving the sign.
 ; V7-FAST: .eabi_attribute 20, 2
 ; V7-FAST-NOT:   .eabi_attribute 21
 ; V7-FAST-NOT:   .eabi_attribute 22
 ; V7-FAST:   .eabi_attribute 23, 1
 
+; V7VE:      .syntax unified
+; V7VE: .eabi_attribute 6, 10   @ Tag_CPU_arch
+; V7VE: .eabi_attribute 7, 65   @ Tag_CPU_arch_profile
+; V7VE: .eabi_attribute 8, 1    @ Tag_ARM_ISA_use
+; V7VE: .eabi_attribute 9, 2    @ Tag_THUMB_ISA_use
+; V7VE: .eabi_attribute 17, 1   @ Tag_ABI_PCS_GOT_use
+; V7VE: .eabi_attribute 20, 1   @ Tag_ABI_FP_denormal
+; V7VE: .eabi_attribute 21, 1   @ Tag_ABI_FP_exceptions
+; V7VE: .eabi_attribute 23, 3   @ Tag_ABI_FP_number_model
+; V7VE: .eabi_attribute 24, 1   @ Tag_ABI_align_needed
+; V7VE: .eabi_attribute 25, 1   @ Tag_ABI_align_preserved
+; V7VE: .eabi_attribute 38, 1   @ Tag_ABI_FP_16bit_format
+; V7VE: .eabi_attribute 42, 1   @ Tag_MPextension_use
+; V7VE: .eabi_attribute 44, 2   @ Tag_DIV_use
+; V7VE: .eabi_attribute 68, 3   @ Tag_Virtualization_use
+
 ; V8:      .syntax unified
 ; V8: .eabi_attribute 67, "2.09"
 ; V8: .eabi_attribute 6, 14
 ; V8-NOT:   .eabi_attribute 19
 ; V8: .eabi_attribute 20, 1
 ; V8: .eabi_attribute 21, 1
 ; V8-NOT: .eabi_attribute 22
 ; V8: .eabi_attribute 23, 3

llvm/trunk/test/CodeGen/ARM/div.ll

 ; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8    | \
 ; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-SWDIV
 ; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=swift        | \
 ; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-HWDIV
 ; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r4    | \
 ; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-SWDIV
 ; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r4f   | \
 ; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-SWDIV
 ; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r5    | \
 ; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-HWDIV
 ; RUN: llc < %s -mtriple=arm-none-eabi -mcpu=cortex-a8    | \
 ; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-EABI
+; RUN: llc < %s -mtriple=armv7ve-none-linux-gnu           | \
+; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-HWDIV
+; RUN: llc < %s -mtriple=thumbv7ve-none-linux-gnu         | \
+; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-HWDIV \
+; RUN:                  -check-prefix=CHECK-THUMB
 
 define i32 @f1(i32 %a, i32 %b) {
 entry:
 ; CHECK-LABEL: f1
 ; CHECK-SWDIV: __divsi3
 
+; CHECK-THUMB: .thumb_func
 ; CHECK-HWDIV: sdiv
 
 ; CHECK-EABI: __aeabi_idiv
         %tmp1 = sdiv i32 %a, %b         ; <i32> [#uses=1]
         ret i32 %tmp1
 }
 
 define i32 @f2(i32 %a, i32 %b) {
 entry:
 ; CHECK-LABEL: f2
 ; CHECK-SWDIV: __udivsi3
 
+; CHECK-THUMB: .thumb_func
 ; CHECK-HWDIV: udiv
 
 ; CHECK-EABI: __aeabi_uidiv
         %tmp1 = udiv i32 %a, %b         ; <i32> [#uses=1]
         ret i32 %tmp1
 }
 
 define i32 @f3(i32 %a, i32 %b) {
 entry:
 ; CHECK-LABEL: f3
 ; CHECK-SWDIV: __modsi3
 
+; CHECK-THUMB: .thumb_func
 ; CHECK-HWDIV: sdiv
 ; CHECK-HWDIV: mls
 
 ; EABI MODE = Remainder in R1, quotient in R0
 ; CHECK-EABI: __aeabi_idivmod
 ; CHECK-EABI-NEXT: mov r0, r1
         %tmp1 = srem i32 %a, %b         ; <i32> [#uses=1]
         ret i32 %tmp1
 }
 
 define i32 @f4(i32 %a, i32 %b) {
 entry:
 ; CHECK-LABEL: f4
 ; CHECK-SWDIV: __umodsi3
 
+; CHECK-THUMB: .thumb_func
 ; CHECK-HWDIV: udiv
 ; CHECK-HWDIV: mls
 
 ; EABI MODE = Remainder in R1, quotient in R0
 ; CHECK-EABI: __aeabi_uidivmod
 ; CHECK-EABI-NEXT: mov r0, r1
         %tmp1 = urem i32 %a, %b         ; <i32> [#uses=1]
         ret i32 %tmp1

llvm/trunk/unittests/Support/TargetParserTest.cpp

 #include "llvm/Support/TargetParser.h"
 #include "gtest/gtest.h"
 #include <string>
 
 using namespace llvm;
 
 namespace {
 const char *ARMArch[] = {
-    "armv2",        "armv2a",      "armv3",        "armv3m",      "armv4",
-    "armv4t",       "armv5",       "armv5t",       "armv5e",      "armv5te",
-    "armv5tej",     "armv6",       "armv6j",       "armv6k",      "armv6hl",
-    "armv6t2",      "armv6kz",     "armv6z",       "armv6zk",     "armv6-m",
-    "armv6m",       "armv6sm",     "armv6s-m",     "armv7-a",     "armv7",
-    "armv7a",       "armv7hl",     "armv7l",       "armv7-r",     "armv7r",
-    "armv7-m",      "armv7m",      "armv7k",       "armv7s",      "armv7e-m",
-    "armv7em",      "armv8-a",     "armv8",        "armv8a",      "armv8.1-a",
-    "armv8.1a",     "armv8.2-a",   "armv8.2a",     "armv8-r",     "armv8r",
-    "armv8-m.base", "armv8m.base", "armv8-m.main", "armv8m.main", "iwmmxt",
-    "iwmmxt2",      "xscale"};
+    "armv2",     "armv2a",       "armv3",       "armv3m",       "armv4",
+    "armv4t",    "armv5",        "armv5t",      "armv5e",       "armv5te",
+    "armv5tej",  "armv6",        "armv6j",      "armv6k",       "armv6hl",
+    "armv6t2",   "armv6kz",      "armv6z",      "armv6zk",      "armv6-m",
+    "armv6m",    "armv6sm",      "armv6s-m",    "armv7-a",      "armv7",
+    "armv7a",    "armv7ve",      "armv7hl",     "armv7l",       "armv7-r",
+    "armv7r",    "armv7-m",      "armv7m",      "armv7k",       "armv7s",
+    "armv7e-m",  "armv7em",      "armv8-a",     "armv8",        "armv8a",
+    "armv8.1-a", "armv8.1a",     "armv8.2-a",   "armv8.2a",     "armv8-r",
+    "armv8r",    "armv8-m.base", "armv8m.base", "armv8-m.main", "armv8m.main",
+    "iwmmxt",    "iwmmxt2",      "xscale"};
 
 bool testARMCPU(StringRef CPUName, StringRef ExpectedArch,
                 StringRef ExpectedFPU, unsigned ExpectedFlags,
                 StringRef CPUAttr) {
   unsigned ArchKind = ARM::parseCPUArch(CPUName);
   bool pass = ARM::getArchName(ArchKind).equals(ExpectedArch);
   unsigned FPUKind = ARM::getDefaultFPU(CPUName, ArchKind);
   pass &= ARM::getFPUName(FPUKind).equals(ExpectedFPU);
EXPECT_TRUE(
                           ARMBuildAttrs::CPUArch::v6KZ));
   EXPECT_TRUE(
       testARMArch("armv6-m", "cortex-m0", "v6m",
                           ARMBuildAttrs::CPUArch::v6_M));
   EXPECT_TRUE(
       testARMArch("armv7-a", "cortex-a8", "v7",
                           ARMBuildAttrs::CPUArch::v7));
   EXPECT_TRUE(
+      testARMArch("armv7ve", "generic", "v7ve",
+                          ARMBuildAttrs::CPUArch::v7));
+  EXPECT_TRUE(
       testARMArch("armv7-r", "cortex-r4", "v7r",
                           ARMBuildAttrs::CPUArch::v7));
   EXPECT_TRUE(
       testARMArch("armv7-m", "cortex-m3", "v7m",
                           ARMBuildAttrs::CPUArch::v7));
   EXPECT_TRUE(
       testARMArch("armv7e-m", "cortex-m4", "v7em",
                           ARMBuildAttrs::CPUArch::v7E_M));
TEST(TargetParserTest, ARMparseHWDiv) {
   const char *hwdiv[] = {"thumb", "arm", "arm,thumb", "thumb,arm"};
 
   for (unsigned i = 0; i < array_lengthof(hwdiv); i++)
     EXPECT_NE(ARM::AEK_INVALID, ARM::parseHWDiv((StringRef)hwdiv[i]));
 }
 
 TEST(TargetParserTest, ARMparseArchEndianAndISA) {
   const char *Arch[] = {
-      "v2",    "v2a",    "v3",    "v3m",  "v4",   "v4t",  "v5",    "v5t",
-      "v5e",   "v5te",   "v5tej", "v6",   "v6j",  "v6k",  "v6hl",  "v6t2",
-      "v6kz",  "v6z",    "v6zk",  "v6-m", "v6m",  "v6sm", "v6s-m", "v7-a",
-      "v7",    "v7a",    "v7hl",  "v7l",  "v7-r", "v7r",  "v7-m",  "v7m",
-      "v7k",   "v7s",    "v7e-m", "v7em", "v8-a", "v8",   "v8a",   "v8.1-a",
-      "v8.1a", "v8.2-a", "v8.2a", "v8-r"};
+      "v2",     "v2a",   "v3",     "v3m",   "v4",   "v4t",  "v5",    "v5t",
+      "v5e",    "v5te",  "v5tej",  "v6",    "v6j",  "v6k",  "v6hl",  "v6t2",
+      "v6kz",   "v6z",   "v6zk",   "v6-m",  "v6m",  "v6sm", "v6s-m", "v7-a",
+      "v7",     "v7a",   "v7ve",   "v7hl",  "v7l",  "v7-r", "v7r",   "v7-m",
+      "v7m",    "v7k",   "v7s",    "v7e-m", "v7em", "v8-a", "v8",    "v8a",
+      "v8.1-a", "v8.1a", "v8.2-a", "v8.2a", "v8-r"};
 
   for (unsigned i = 0; i < array_lengthof(Arch); i++) {
     std::string arm_1 = "armeb" + (std::string)(Arch[i]);
     std::string arm_2 = "arm" + (std::string)(Arch[i]) + "eb";
     std::string arm_3 = "arm" + (std::string)(Arch[i]);
     std::string thumb_1 = "thumbeb" + (std::string)(Arch[i]);
     std::string thumb_2 = "thumb" + (std::string)(Arch[i]) + "eb";
     std::string thumb_3 = "thumb" + (std::string)(Arch[i]);
for (unsigned i = 0; i < array_lengthof(ARMArch); i++) {
     case ARM::AK_ARMV8MBaseline:
       EXPECT_EQ(ARM::PK_M, ARM::parseArchProfile(ARMArch[i]));
       continue;
     case ARM::AK_ARMV7R:
     case ARM::AK_ARMV8R:
       EXPECT_EQ(ARM::PK_R, ARM::parseArchProfile(ARMArch[i]));
       continue;
     case ARM::AK_ARMV7A:
+    case ARM::AK_ARMV7VE:
     case ARM::AK_ARMV7K:
     case ARM::AK_ARMV8A:
     case ARM::AK_ARMV8_1A:
     case ARM::AK_ARMV8_2A:
       EXPECT_EQ(ARM::PK_A, ARM::parseArchProfile(ARMArch[i]));
       continue;
     }
     EXPECT_EQ(ARM::PK_INVALID, ARM::parseArchProfile(ARMArch[i]));