AMDGPU: Check users in fneg/fabs select combine

[arsenm]

Fix regression with fmin/fmax_legacy

[arsenm]

I'm rediscovering why this was necessary. Should be obsoleted by D142418

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

 }
 
 /// \brief Generate Min/Max node
 SDValue AMDGPUTargetLowering::combineFMinMaxLegacy(const SDLoc &DL, EVT VT,
                                                    SDValue LHS, SDValue RHS,
                                                    SDValue True, SDValue False,
                                                    SDValue CC,
                                                    DAGCombinerInfo &DCI) const {
+  SelectionDAG &DAG = DCI.DAG;
+
+  // select (setcc x, K), (fneg x), -K ->
+  if ((True.getOpcode() == ISD::FNEG || True.getOpcode() == ISD::FABS) &&
+      isa<ConstantFPSDNode>(False)) {
+    SDValue FoldFalse = DAG.getNode(True.getOpcode(), DL, VT, False);
+    return combineFMinMaxLegacy(DL, VT, LHS, RHS,
+                                True.getOperand(0), FoldFalse, CC, DCI);
+  }
+
   if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
     return SDValue();
 
-  SelectionDAG &DAG = DCI.DAG;
   ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
   switch (CCOpcode) {
   case ISD::SETOEQ:
   case ISD::SETONE:
   case ISD::SETUNE:
   case ISD::SETNE:
   case ISD::SETUEQ:
   case ISD::SETEQ:

 static SDValue foldFreeOpFromSelect(TargetLowering::DAGCombinerInfo &DCI,
                                     SDValue N) {
   SelectionDAG &DAG = DCI.DAG;
   SDValue Cond = N.getOperand(0);
   SDValue LHS = N.getOperand(1);
   SDValue RHS = N.getOperand(2);
 
   EVT VT = N.getValueType();
-  if ((LHS.getOpcode() == ISD::FABS && RHS.getOpcode() == ISD::FABS) ||
-      (LHS.getOpcode() == ISD::FNEG && RHS.getOpcode() == ISD::FNEG)) {
+  if (((LHS.getOpcode() == ISD::FABS && RHS.getOpcode() == ISD::FABS) ||
+       (LHS.getOpcode() == ISD::FNEG && RHS.getOpcode() == ISD::FNEG)) &&
+      (!LHS.hasOneUse() || !RHS.hasOneUse() ||
+       allUsesHaveSourceMods(N.getNode()))) {
     return distributeOpThroughSelect(DCI, LHS.getOpcode(),
                                      SDLoc(N), Cond, LHS, RHS);
   }
 
   bool Inv = false;
   if (RHS.getOpcode() == ISD::FABS || RHS.getOpcode() == ISD::FNEG) {
     std::swap(LHS, RHS);
     Inv = true;
   }
 
   // TODO: Support vector constants.
   ConstantFPSDNode *CRHS = dyn_cast<ConstantFPSDNode>(RHS);
-  if ((LHS.getOpcode() == ISD::FNEG || LHS.getOpcode() == ISD::FABS) && CRHS) {
+  if (CRHS && (LHS.getOpcode() == ISD::FNEG || LHS.getOpcode() == ISD::FABS) &&
+      allUsesHaveSourceMods(N.getNode())) {
     SDLoc SL(N);
     // If one side is an fneg/fabs and the other is a constant, we can push the
     // fneg/fabs down. If it's an fabs, the constant needs to be non-negative.
     SDValue NewLHS = LHS.getOperand(0);
     SDValue NewRHS = RHS;
 
     // Careful: if the neg can be folded up, don't try to pull it back down.
     bool ShouldFoldNeg = true;
static SDValue foldFreeOpFromSelect(TargetLowering::DAGCombinerInfo &DCI,
   }
 
   return SDValue();
 }
 
 
 SDValue AMDGPUTargetLowering::performSelectCombine(SDNode *N,
                                                    DAGCombinerInfo &DCI) const {
-  if (SDValue Folded = foldFreeOpFromSelect(DCI, SDValue(N, 0)))
-    return Folded;
-
   SDValue Cond = N->getOperand(0);
-  if (Cond.getOpcode() != ISD::SETCC)
-    return SDValue();
-
+  if (Cond.getOpcode() == ISD::SETCC) {
     EVT VT = N->getValueType(0);
     SDValue LHS = Cond.getOperand(0);
     SDValue RHS = Cond.getOperand(1);
     SDValue CC = Cond.getOperand(2);
 
     SDValue True = N->getOperand(1);
     SDValue False = N->getOperand(2);
 
     if (Cond.hasOneUse()) { // TODO: Look for multiple select uses.
       SelectionDAG &DAG = DCI.DAG;
       if ((DAG.isConstantValueOfAnyType(True) ||
            DAG.isConstantValueOfAnyType(True)) &&
           (!DAG.isConstantValueOfAnyType(False) &&
            !DAG.isConstantValueOfAnyType(False))) {
         // Swap cmp + select pair to move constant to false input.
         // This will allow using VOPC cndmasks more often.
         // select (setcc x, y), k, x -> select (setcc y, x) x, x
 
         SDLoc SL(N);
         ISD::CondCode NewCC = getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
                                               LHS.getValueType().isInteger());
 
         SDValue NewCond = DAG.getSetCC(SL, Cond.getValueType(), LHS, RHS, NewCC);
         return DAG.getNode(ISD::SELECT, SL, VT, NewCond, False, True);
       }
 
       if (VT == MVT::f32 && Subtarget->hasFminFmaxLegacy()) {
         SDValue MinMax
           = combineFMinMaxLegacy(SDLoc(N), VT, LHS, RHS, True, False, CC, DCI);
         // Revisit this node so we can catch min3/max3/med3 patterns.
         //DCI.AddToWorklist(MinMax.getNode());
         return MinMax;
       }
     }
 
     // There's no reason to not do this if the condition has other uses.
     return performCtlzCombine(SDLoc(N), Cond, True, False, DCI);
   }
 
+  if (SDValue Folded = foldFreeOpFromSelect(DCI, SDValue(N, 0)))
+    return Folded;
+
+  return SDValue();
+}
+
 static bool isConstantFPZero(SDValue N) {
   if (const ConstantFPSDNode *C = isConstOrConstSplatFP(N))
     return C->isZero() && !C->isNegative();
   return false;
 }
 
 static unsigned inverseMinMax(unsigned Opc) {
   switch (Opc) {

test/CodeGen/AMDGPU/select-fabs-fneg-extract-legacy.ll

 ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
 
 ; --------------------------------------------------------------------------------
 ; Don't fold if fneg can fold into the source
 ; --------------------------------------------------------------------------------
 
 ; GCN-LABEL: {{^}}select_fneg_posk_src_rcp_legacy_f32:
 ; GCN: buffer_load_dword [[X:v[0-9]+]]
 
-; GCN: v_rcp_legacy_f32_e32 [[RCP:v[0-9]+]], [[X]]
-; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], -2.0, [[RCP]], vcc
-; GCN: v_xor_b32_e32 [[NEG_SELECT:v[0-9]+]], 0x80000000, [[SELECT]]
-; GCN-NEXT: buffer_store_dword [[NEG_SELECT]]
+; GCN: v_rcp_legacy_f32_e64 [[RCP:v[0-9]+]], -[[X]]
+; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], 2.0, [[RCP]], vcc
+; GCN-NEXT: buffer_store_dword [[SELECT]]
 define void @select_fneg_posk_src_rcp_legacy_f32(i32 %c) #2 {
   %x = load volatile float, float addrspace(1)* undef
   %y = load volatile float, float addrspace(1)* undef
   %cmp = icmp eq i32 %c, 0
   %rcp = call float @llvm.amdgcn.rcp.legacy(float %x)
   %fneg = fsub float -0.0, %rcp
   %select = select i1 %cmp, float %fneg, float 2.0
   store volatile float %select, float addrspace(1)* undef
   ret void
 }
 
 ; GCN-LABEL: {{^}}select_fneg_posk_src_mul_legacy_f32:
 ; GCN: buffer_load_dword [[X:v[0-9]+]]
 
-; GCN: v_mul_legacy_f32_e32 [[MUL:v[0-9]+]], 4.0, [[X]]
-; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], -2.0, [[MUL]], vcc
-; GCN: v_xor_b32_e32 [[NEG_SELECT:v[0-9]+]], 0x80000000, [[SELECT]]
-; GCN-NEXT: buffer_store_dword [[NEG_SELECT]]
+; GCN: v_mul_legacy_f32_e32 [[MUL:v[0-9]+]], -4.0, [[X]]
+; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], 2.0, [[MUL]], vcc
+; GCN-NEXT: buffer_store_dword [[SELECT]]
 define void @select_fneg_posk_src_mul_legacy_f32(i32 %c) #2 {
   %x = load volatile float, float addrspace(1)* undef
   %cmp = icmp eq i32 %c, 0
   %mul = call float @llvm.amdgcn.fmul.legacy(float %x, float 4.0)
   %fneg = fsub float -0.0, %mul
   %select = select i1 %cmp, float %fneg, float 2.0
   store volatile float %select, float addrspace(1)* undef
   ret void
 }
 
 declare float @llvm.amdgcn.rcp.legacy(float) #1
 declare float @llvm.amdgcn.fmul.legacy(float, float) #1
 
 attributes #0 = { nounwind }
 attributes #1 = { nounwind readnone }

test/CodeGen/AMDGPU/select-fabs-fneg-extract.ll

define void @select_fneg_posk_src_fmad_f32(i32 %c) #0 {
   %cmp = icmp eq i32 %c, 0
   %fmad = call float @llvm.fmuladd.f32(float %x, float 4.0, float %z)
   %fneg = fsub float -0.0, %fmad
   %select = select i1 %cmp, float %fneg, float 2.0
   store volatile float %select, float addrspace(1)* undef
   ret void
 }
 
-; FIXME: This one should fold to rcp
 ; GCN-LABEL: {{^}}select_fneg_posk_src_rcp_f32:
 ; GCN: buffer_load_dword [[X:v[0-9]+]]
 
-; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[X]]
-; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], -2.0, [[RCP]], vcc
-; GCN: v_xor_b32_e32 [[NEG_SELECT:v[0-9]+]], 0x80000000, [[SELECT]]
-; GCN-NEXT: buffer_store_dword [[NEG_SELECT]]
+; GCN: v_rcp_f32_e64 [[RCP:v[0-9]+]], -[[X]]
+; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], 2.0, [[RCP]], vcc
+; GCN-NEXT: buffer_store_dword [[SELECT]]
 define void @select_fneg_posk_src_rcp_f32(i32 %c) #0 {
   %x = load volatile float, float addrspace(1)* undef
   %y = load volatile float, float addrspace(1)* undef
   %cmp = icmp eq i32 %c, 0
   %rcp = call float @llvm.amdgcn.rcp.f32(float %x)
   %fneg = fsub float -0.0, %rcp
   %select = select i1 %cmp, float %fneg, float 2.0
   store volatile float %select, float addrspace(1)* undef