Merge the TargetLowering::LegalizeAction and TargetLowering::LegalizeTypeAction enums

[dylanmckay]

Summary

This will make it easier for us in the future to modify the instruction selector to support having types that are legal for some instructions.

The vast majority of the AVR instruction set works on 8-bit integers, with only load/store instructions (with some exceptions) working on 16-bit. The instruction selector will currently assume that i16 is legal and not attempt to expand i16 ops into i8 ops.

Regardless of the possible AVR improvements, these enums are basically equivalent so this is a reasonable simplification in itself.

[dylanmckay]

Ping

[dylanmckay]

Rebase

include/llvm/CodeGen/BasicTTIImpl.h

if (Dst->isVectorTy() && Src->isVectorTy()) {
           return SrcLT.first * 1;
       }
 
       // If we are legalizing by splitting, query the concrete TTI for the cost
       // of casting the original vector twice. We also need to factor int the
       // cost of the split itself. Count that as 1, to be consistent with
       // TLI->getTypeLegalizationCost().
       if ((TLI->getTypeAction(Src->getContext(), TLI->getValueType(DL, Src)) ==
-           TargetLowering::TypeSplitVector) ||
+           TargetLowering::SplitVector) ||
           (TLI->getTypeAction(Dst->getContext(), TLI->getValueType(DL, Dst)) ==
-           TargetLowering::TypeSplitVector)) {
+           TargetLowering::SplitVector)) {
         Type *SplitDst = VectorType::get(Dst->getVectorElementType(),
                                          Dst->getVectorNumElements() / 2);
         Type *SplitSrc = VectorType::get(Src->getVectorElementType(),
                                          Src->getVectorNumElements() / 2);
         T *TTI = static_cast<T *>(this);
         return TTI->getVectorSplitCost() +
                (2 * TTI->getCastInstrCost(Opcode, SplitDst, SplitSrc));
       }

include/llvm/Target/TargetLowering.h

 
 public:
   /// This enum indicates whether operations are valid for a target, and if not,
   /// what action should be used to make them valid.
   enum LegalizeAction : uint8_t {
     Legal,      // The target natively supports this operation.
     Promote,    // This operation should be executed in a larger type.
     Expand,     // Try to expand this to other ops, otherwise use a libcall.
+
+    SoftenFloat,     // Convert this float to a same size integer type,
+    ScalarizeVector, // Replace this one-element vector with its element.
+    SplitVector,     // Split this vector into two of half the size.
+    WidenVector,     // This vector should be widened into a larger vector.
+
     LibCall,    // Don't try to expand this to other ops, always use a libcall.
     Custom      // Use the LowerOperation hook to implement custom lowering.
   };
 
-  /// This enum indicates whether a types are legal for a target, and if not,
-  /// what action should be used to make them valid.
-  enum LegalizeTypeAction : uint8_t {
-    TypeLegal,           // The target natively supports this type.
-    TypePromoteInteger,  // Replace this integer with a larger one.
-    TypeExpandInteger,   // Split this integer into two of half the size.
-    TypeSoftenFloat,     // Convert this float to a same size integer type,
-                         // if an operation is not supported in target HW.
-    TypeExpandFloat,     // Split this float into two of half the size.
-    TypeScalarizeVector, // Replace this one-element vector with its element.
-    TypeSplitVector,     // Split this vector into two of half the size.
-    TypeWidenVector,     // This vector should be widened into a larger vector.
-    TypePromoteFloat     // Replace this float with a larger one.
-  };
-
   /// LegalizeKind holds the legalization kind that needs to happen to EVT
   /// in order to type-legalize it.
-  typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind;
+  typedef std::pair<LegalizeAction, EVT> LegalizeKind;
 
   /// Enum that describes how the target represents true/false values.
   enum BooleanContent {
     UndefinedBooleanContent,    // Only bit 0 counts, the rest can hold garbage.
     ZeroOrOneBooleanContent,        // All bits zero except for bit 0.
     ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
   };
 
public:
   bool hasMultipleConditionRegisters() const {
     return HasMultipleConditionRegisters;
   }
 
   /// Return true if the target has BitExtract instructions.
   bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
 
   /// Return the preferred vector type legalization action.
-  virtual TargetLoweringBase::LegalizeTypeAction
+  virtual TargetLoweringBase::LegalizeAction
   getPreferredVectorAction(EVT VT) const {
     // The default action for one element vectors is to scalarize
     if (VT.getVectorNumElements() == 1)
-      return TypeScalarizeVector;
+      return ScalarizeVector;
     // The default action for other vectors is to promote
-    return TypePromoteInteger;
+    return Promote;
   }
 
   // There are two general methods for expanding a BUILD_VECTOR node:
   //  1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
   //     them together.
   //  2. Build the vector on the stack and then load it.
   // If this function returns true, then method (1) will be used, subject to
   // the constraint that all of the necessary shuffles are legal (as determined
public:
   /// promotions or expansions.
   bool isTypeLegal(EVT VT) const {
     assert(!VT.isSimple() ||
            (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
     return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
   }
 
   class ValueTypeActionImpl {
-    /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
+    /// ValueTypeActions - For each value type, keep a LegalizeAction enum
     /// that indicates how instruction selection should deal with the type.
-    LegalizeTypeAction ValueTypeActions[MVT::LAST_VALUETYPE];
+    LegalizeAction ValueTypeActions[MVT::LAST_VALUETYPE];
 
   public:
     ValueTypeActionImpl() {
       std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions),
-                TypeLegal);
+                Legal);
     }
 
-    LegalizeTypeAction getTypeAction(MVT VT) const {
+    LegalizeAction getTypeAction(MVT VT) const {
       return ValueTypeActions[VT.SimpleTy];
     }
 
-    void setTypeAction(MVT VT, LegalizeTypeAction Action) {
+    void setTypeAction(MVT VT, LegalizeAction Action) {
       ValueTypeActions[VT.SimpleTy] = Action;
     }
   };
 
   const ValueTypeActionImpl &getValueTypeActions() const {
     return ValueTypeActions;
   }
 
   /// Return how we should legalize values of this type, either it is already
   /// legal (return 'Legal') or we need to promote it to a larger type (return
   /// 'Promote'), or we need to expand it into multiple registers of smaller
   /// integer type (return 'Expand').  'Custom' is not an option.
-  LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
+  LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const {
     return getTypeConversion(Context, VT).first;
   }
-  LegalizeTypeAction getTypeAction(MVT VT) const {
+  LegalizeAction getTypeAction(MVT VT) const {
     return ValueTypeActions.getTypeAction(VT);
   }
 
   /// For types supported by the target, this is an identity function.  For
   /// types that must be promoted to larger types, this returns the larger type
   /// to promote to.  For integer types that are larger than the largest integer
   /// register, this contains one step in the expansion to get to the smaller
   /// register. For illegal floating point types, this returns the integer type
   /// to transform to.
   EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
     return getTypeConversion(Context, VT).second;
   }
 
   /// For types supported by the target, this is an identity function.  For
   /// types that must be expanded (i.e. integer types that are larger than the
   /// largest integer register or illegal floating point types), this returns
   /// the largest legal type it will be expanded to.
   EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
     assert(!VT.isVector());
     while (true) {
       switch (getTypeAction(Context, VT)) {
-      case TypeLegal:
+      case Legal:
         return VT;
-      case TypeExpandInteger:
+      case Expand:
         VT = getTypeToTransformTo(Context, VT);
         break;
       default:
         llvm_unreachable("Type is not legal nor is it to be expanded!");
       }
     }
   }
 
public:
   virtual bool shouldNormalizeToSelectSequence(LLVMContext &Context,
                                                EVT VT) const {
     // If a target has multiple condition registers, then it likely has logical
     // operations on those registers.
     if (hasMultipleConditionRegisters())
       return false;
     // Only do the transform if the value won't be split into multiple
     // registers.
-    LegalizeTypeAction Action = getTypeAction(Context, VT);
-    return Action != TypeExpandInteger && Action != TypeExpandFloat &&
-      Action != TypeSplitVector;
+    LegalizeAction Action = getTypeAction(Context, VT);
+    return Action != Expand && Action != SplitVector;
   }
 
   //===--------------------------------------------------------------------===//
   // TargetLowering Configuration Methods - These methods should be invoked by
   // the derived class constructor to configure this object for the target.
   //
 protected:
   /// Specify how the target extends the result of integer and floating point

lib/CodeGen/CodeGenPrepare.cpp

static bool OptimizeNoopCopyExpression(CastInst *CI, const TargetLowering &TLI,
 
   // If this is an extension, it will be a zero or sign extension, which
   // isn't a noop.
   if (SrcVT.bitsLT(DstVT)) return false;
 
   // If these values will be promoted, find out what they will be promoted
   // to.  This helps us consider truncates on PPC as noop copies when they
   // are.
-  if (TLI.getTypeAction(CI->getContext(), SrcVT) ==
-      TargetLowering::TypePromoteInteger)
+  if (TLI.getTypeAction(CI->getContext(), SrcVT) == TargetLowering::Promote)
     SrcVT = TLI.getTypeToTransformTo(CI->getContext(), SrcVT);
-  if (TLI.getTypeAction(CI->getContext(), DstVT) ==
-      TargetLowering::TypePromoteInteger)
+  if (TLI.getTypeAction(CI->getContext(), DstVT) == TargetLowering::Promote)
     DstVT = TLI.getTypeToTransformTo(CI->getContext(), DstVT);
 
   // If, after promotion, these are the same types, this is a noop copy.
   if (SrcVT != DstVT)
     return false;
 
   return SinkCast(CI);
 }
if (TLI && OptimizeNoopCopyExpression(CI, *TLI, *DL))
       return true;
 
     if (isa<ZExtInst>(I) || isa<SExtInst>(I)) {
       /// Sink a zext or sext into its user blocks if the target type doesn't
       /// fit in one register
       if (TLI &&
           TLI->getTypeAction(CI->getContext(),
                              TLI->getValueType(*DL, CI->getType())) ==
-              TargetLowering::TypeExpandInteger) {
+              TargetLowering::Expand) {
         return SinkCast(CI);
       } else {
         bool MadeChange = moveExtToFormExtLoad(I);
         return MadeChange | optimizeExtUses(I);
       }
     }
     return false;
   }

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

SDValue DAGCombiner::visitMSCATTER(SDNode *N) {
   // SETCC, then split both nodes and its operands before legalization. This
   // prevents the type legalizer from unrolling SETCC into scalar comparisons
   // and enables future optimizations (e.g. min/max pattern matching on X86).
   if (Mask.getOpcode() != ISD::SETCC)
     return SDValue();
 
   // Check if any splitting is required.
   if (TLI.getTypeAction(*DAG.getContext(), Data.getValueType()) !=
-      TargetLowering::TypeSplitVector)
+      TargetLowering::SplitVector)
     return SDValue();
   SDValue MaskLo, MaskHi, Lo, Hi;
   std::tie(MaskLo, MaskHi) = SplitVSETCC(Mask.getNode(), DAG);
 
   EVT LoVT, HiVT;
   std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MSC->getValueType(0));
 
   SDValue Chain = MSC->getChain();
SDValue DAGCombiner::visitMSTORE(SDNode *N) {
   // If the MSTORE data type requires splitting and the mask is provided by a
   // SETCC, then split both nodes and its operands before legalization. This
   // prevents the type legalizer from unrolling SETCC into scalar comparisons
   // and enables future optimizations (e.g. min/max pattern matching on X86).
   if (Mask.getOpcode() == ISD::SETCC) {
 
     // Check if any splitting is required.
     if (TLI.getTypeAction(*DAG.getContext(), VT) !=
-        TargetLowering::TypeSplitVector)
+        TargetLowering::SplitVector)
       return SDValue();
 
     SDValue MaskLo, MaskHi, Lo, Hi;
     std::tie(MaskLo, MaskHi) = SplitVSETCC(Mask.getNode(), DAG);
 
     SDValue Chain = MST->getChain();
     SDValue Ptr   = MST->getBasePtr();
 
SDValue DAGCombiner::visitMGATHER(SDNode *N) {
 
   if (Mask.getOpcode() != ISD::SETCC)
     return SDValue();
 
   EVT VT = N->getValueType(0);
 
   // Check if any splitting is required.
   if (TLI.getTypeAction(*DAG.getContext(), VT) !=
-      TargetLowering::TypeSplitVector)
+      TargetLowering::SplitVector)
     return SDValue();
 
   SDValue MaskLo, MaskHi, Lo, Hi;
   std::tie(MaskLo, MaskHi) = SplitVSETCC(Mask.getNode(), DAG);
 
   SDValue Src0 = MGT->getValue();
   SDValue Src0Lo, Src0Hi;
   std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, DL);
SDValue DAGCombiner::visitMLOAD(SDNode *N) {
   // prevents the type legalizer from unrolling SETCC into scalar comparisons
   // and enables future optimizations (e.g. min/max pattern matching on X86).
 
   if (Mask.getOpcode() == ISD::SETCC) {
     EVT VT = N->getValueType(0);
 
     // Check if any splitting is required.
     if (TLI.getTypeAction(*DAG.getContext(), VT) !=
-        TargetLowering::TypeSplitVector)
+        TargetLowering::SplitVector)
       return SDValue();
 
     SDValue MaskLo, MaskHi, Lo, Hi;
     std::tie(MaskLo, MaskHi) = SplitVSETCC(Mask.getNode(), DAG);
 
     SDValue Src0 = MLD->getSrc0();
     SDValue Src0Lo, Src0Hi;
     std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, DL);
SDValue DAGCombiner::visitVSELECT(SDNode *N) {
   // SETCC, then split both nodes and its operands before legalization. This
   // prevents the type legalizer from unrolling SETCC into scalar comparisons
   // and enables future optimizations (e.g. min/max pattern matching on X86).
   if (N0.getOpcode() == ISD::SETCC) {
     EVT VT = N->getValueType(0);
 
     // Check if any splitting is required.
     if (TLI.getTypeAction(*DAG.getContext(), VT) !=
-        TargetLowering::TypeSplitVector)
+        TargetLowering::SplitVector)
       return SDValue();
 
     SDValue Lo, Hi, CCLo, CCHi, LL, LH, RL, RH;
     std::tie(CCLo, CCHi) = SplitVSETCC(N0.getNode(), DAG);
     std::tie(LL, LH) = DAG.SplitVectorOperand(N, 1);
     std::tie(RL, RH) = DAG.SplitVectorOperand(N, 2);
 
     Lo = DAG.getNode(N->getOpcode(), DL, LL.getValueType(), CCLo, LL, RL);
for (unsigned i=0; i<LastConsecutiveStore+1; ++i) {
       EVT StoreTy = EVT::getIntegerVT(Context, SizeInBits);
       bool IsFast;
       if (TLI.isTypeLegal(StoreTy) &&
           TLI.allowsMemoryAccess(Context, DL, StoreTy, FirstStoreAS,
                                  FirstStoreAlign, &IsFast) && IsFast) {
         LastLegalType = i+1;
       // Or check whether a truncstore is legal.
       } else if (TLI.getTypeAction(Context, StoreTy) ==
-                 TargetLowering::TypePromoteInteger) {
+                 TargetLowering::Promote) {
         EVT LegalizedStoredValueTy =
           TLI.getTypeToTransformTo(Context, StoredVal.getValueType());
         if (TLI.isTruncStoreLegal(LegalizedStoredValueTy, StoreTy) &&
             TLI.allowsMemoryAccess(Context, DL, LegalizedStoredValueTy,
                                    FirstStoreAS, FirstStoreAlign, &IsFast) &&
             IsFast) {
           LastLegalType = i + 1;
         }
for (unsigned i = 1; i < LoadNodes.size(); ++i) {
     if (TLI.isTypeLegal(StoreTy) &&
         TLI.allowsMemoryAccess(Context, DL, StoreTy, FirstStoreAS,
                                FirstStoreAlign, &IsFastSt) && IsFastSt &&
         TLI.allowsMemoryAccess(Context, DL, StoreTy, FirstLoadAS,
                                FirstLoadAlign, &IsFastLd) && IsFastLd)
       LastLegalIntegerType = i + 1;
     // Or check whether a truncstore and extload is legal.
     else if (TLI.getTypeAction(Context, StoreTy) ==
-             TargetLowering::TypePromoteInteger) {
+             TargetLowering::Promote) {
       EVT LegalizedStoredValueTy =
         TLI.getTypeToTransformTo(Context, StoreTy);
       if (TLI.isTruncStoreLegal(LegalizedStoredValueTy, StoreTy) &&
           TLI.isLoadExtLegal(ISD::ZEXTLOAD, LegalizedStoredValueTy, StoreTy) &&
           TLI.isLoadExtLegal(ISD::SEXTLOAD, LegalizedStoredValueTy, StoreTy) &&
           TLI.isLoadExtLegal(ISD::EXTLOAD, LegalizedStoredValueTy, StoreTy) &&
           TLI.allowsMemoryAccess(Context, DL, LegalizedStoredValueTy,
                                  FirstStoreAS, FirstStoreAlign, &IsFastSt) &&

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
   DEBUG(dbgs() << "\nLegalizing: "; Node->dump(&DAG));
 
   if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
     return;
 
 #ifndef NDEBUG
   for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
     assert((TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
-              TargetLowering::TypeLegal ||
+              TargetLowering::Legal ||
             TLI.isTypeLegal(Node->getValueType(i))) &&
            "Unexpected illegal type!");
 
   for (const SDValue &Op : Node->op_values())
     assert((TLI.getTypeAction(*DAG.getContext(), Op.getValueType()) ==
-              TargetLowering::TypeLegal ||
+              TargetLowering::Legal ||
             TLI.isTypeLegal(Op.getValueType()) ||
             Op.getOpcode() == ISD::TargetConstant) &&
             "Unexpected illegal type!");
 #endif
 
   // Figure out the correct action; the way to query this varies by opcode
   TargetLowering::LegalizeAction Action = TargetLowering::Legal;
   bool SimpleFinishLegalizing = true;
case TargetLowering::Expand:
         return;
       LLVM_FALLTHROUGH;
     case TargetLowering::LibCall:
       ConvertNodeToLibcall(Node);
       return;
     case TargetLowering::Promote:
       PromoteNode(Node);
       return;
+    default:
+      llvm_unreachable("unexpected legalize action");
     }
   }
 
   switch (Node->getOpcode()) {
   default:
 #ifndef NDEBUG
     dbgs() << "NODE: ";
     Node->dump( &DAG);

lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

SDValue DAGTypeLegalizer::SoftenFloatRes_FP_EXTEND(SDNode *N) {
   EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
   SDValue Op = N->getOperand(0);
 
   // There's only a libcall for f16 -> f32, so proceed in two stages. Also, it's
   // entirely possible for both f16 and f32 to be legal, so use the fully
   // hard-float FP_EXTEND rather than FP16_TO_FP.
   if (Op.getValueType() == MVT::f16 && N->getValueType(0) != MVT::f32) {
     Op = DAG.getNode(ISD::FP_EXTEND, SDLoc(N), MVT::f32, Op);
-    if (getTypeAction(MVT::f32) == TargetLowering::TypeSoftenFloat)
+    if (getTypeAction(MVT::f32) == TargetLowering::SoftenFloat)
       SoftenFloatResult(Op.getNode(), 0);
   }
 
-  if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat) {
+  if (getTypeAction(Op.getValueType()) == TargetLowering::Promote) {
     Op = GetPromotedFloat(Op);
     // If the promotion did the FP_EXTEND to the destination type for us,
     // there's nothing left to do here.
     if (Op.getValueType() == N->getValueType(0)) {
       return BitConvertToInteger(Op);
     }
   }
 
   RTLIB::Libcall LC = RTLIB::getFPEXT(Op.getValueType(), N->getValueType(0));
-  if (getTypeAction(Op.getValueType()) == TargetLowering::TypeSoftenFloat)
+  if (getTypeAction(Op.getValueType()) == TargetLowering::SoftenFloat)
     Op = GetSoftenedFloat(Op);
   assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
   return TLI.makeLibCall(DAG, LC, NVT, Op, false, SDLoc(N)).first;
 }
 
 // FIXME: Should we just use 'normal' FP_EXTEND / FP_TRUNC instead of special
 // nodes?
 SDValue DAGTypeLegalizer::SoftenFloatRes_FP16_TO_FP(SDNode *N) {
if (isa<ConstantSDNode>(N->getOperand(1))) {
     SDValue Idx = N->getOperand(1);
     EVT VecVT = Vec->getValueType(0);
     EVT EltVT = VecVT.getVectorElementType();
 
     uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
 
     switch (getTypeAction(VecVT)) {
     default: break;
-    case TargetLowering::TypeScalarizeVector: {
+    case TargetLowering::ScalarizeVector: {
       SDValue Res = GetScalarizedVector(N->getOperand(0));
       ReplaceValueWith(SDValue(N, 0), Res);
       return SDValue();
     }
-    case TargetLowering::TypeWidenVector: {
+    case TargetLowering::WidenVector: {
       Vec = GetWidenedVector(Vec);
       SDValue Res = DAG.getNode(N->getOpcode(), DL, EltVT, Vec, Idx);
       ReplaceValueWith(SDValue(N, 0), Res);
       return SDValue();
     }
-    case TargetLowering::TypeSplitVector: {
+    case TargetLowering::SplitVector: {
       SDValue Lo, Hi;
       GetSplitVector(Vec, Lo, Hi);
 
       uint64_t LoElts = Lo.getValueType().getVectorNumElements();
       SDValue Res;
       if (IdxVal < LoElts)
         Res = DAG.getNode(N->getOpcode(), DL, EltVT, Lo, Idx);
       else

lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
   SDValue InOp = N->getOperand(0);
   EVT InVT = InOp.getValueType();
   EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
   EVT OutVT = N->getValueType(0);
   EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
   SDLoc dl(N);
 
   switch (getTypeAction(InVT)) {
-  case TargetLowering::TypeLegal:
+  case TargetLowering::Legal:
     break;
-  case TargetLowering::TypePromoteInteger:
+  case TargetLowering::Promote:
+    if (InVT.isInteger()) {
       if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector() && !NInVT.isVector())
         // The input promotes to the same size.  Convert the promoted value.
         return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
-    break;
-  case TargetLowering::TypeSoftenFloat:
-    // Promote the integer operand by hand.
-    return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
-  case TargetLowering::TypePromoteFloat: {
+    } else {
       // Convert the promoted float by hand.
       SDValue PromotedOp = GetPromotedFloat(InOp);
       return DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, PromotedOp);
-    break;
     }
-  case TargetLowering::TypeExpandInteger:
-  case TargetLowering::TypeExpandFloat:
     break;
-  case TargetLowering::TypeScalarizeVector:
+  case TargetLowering::SoftenFloat:
+    // Promote the integer operand by hand.
+    return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
+  case TargetLowering::Expand:
+    break;
+  case TargetLowering::ScalarizeVector:
     // Convert the element to an integer and promote it by hand.
     if (!NOutVT.isVector())
       return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
                          BitConvertToInteger(GetScalarizedVector(InOp)));
     break;
-  case TargetLowering::TypeSplitVector: {
+  case TargetLowering::SplitVector: {
     // For example, i32 = BITCAST v2i16 on alpha.  Convert the split
     // pieces of the input into integers and reassemble in the final type.
     SDValue Lo, Hi;
     GetSplitVector(N->getOperand(0), Lo, Hi);
     Lo = BitConvertToInteger(Lo);
     Hi = BitConvertToInteger(Hi);
 
     if (DAG.getDataLayout().isBigEndian())
       std::swap(Lo, Hi);
 
     InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
                        EVT::getIntegerVT(*DAG.getContext(),
                                          NOutVT.getSizeInBits()),
                        JoinIntegers(Lo, Hi));
     return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
   }
-  case TargetLowering::TypeWidenVector:
+  case TargetLowering::WidenVector:
     // The input is widened to the same size. Convert to the widened value.
     // Make sure that the outgoing value is not a vector, because this would
     // make us bitcast between two vectors which are legalized in different ways.
     if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector())
       return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp));
+    break;
+  default:
+    llvm_unreachable("unexpected legalize action");
   }
 
   return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
                      CreateStackStoreLoad(InOp, OutVT));
 }
 
 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
   SDValue Op = GetPromotedInteger(N->getOperand(0));
SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_FP16(SDNode *N) {
   return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
 }
 
 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
   EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
   SDLoc dl(N);
 
   if (getTypeAction(N->getOperand(0).getValueType())
-      == TargetLowering::TypePromoteInteger) {
+      == TargetLowering::Promote) {
     SDValue Res = GetPromotedInteger(N->getOperand(0));
     assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
 
     // If the result and operand types are the same after promotion, simplify
     // to an in-register extension.
     if (NVT == Res.getValueType()) {
       // The high bits are not guaranteed to be anything.  Insert an extend.
       if (N->getOpcode() == ISD::SIGN_EXTEND)
SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
 
   SDLoc dl(N);
   assert(SVT.isVector() == N->getOperand(0).getValueType().isVector() &&
          "Vector compare must return a vector result!");
 
   SDValue LHS = N->getOperand(0);
   SDValue RHS = N->getOperand(1);
   if (LHS.getValueType() != RHS.getValueType()) {
-    if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger &&
+    if (getTypeAction(LHS.getValueType()) == TargetLowering::Promote &&
         !LHS.getValueType().isVector())
       LHS = GetPromotedInteger(LHS);
-    if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger &&
+    if (getTypeAction(RHS.getValueType()) == TargetLowering::Promote &&
         !RHS.getValueType().isVector())
       RHS = GetPromotedInteger(RHS);
   }
 
   // Get the SETCC result using the canonical SETCC type.
   SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, LHS, RHS,
                               N->getOperand(2));
 
   assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
   // Convert to the expected type.
   return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
 }
 
 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
   SDValue LHS = N->getOperand(0);
   SDValue RHS = N->getOperand(1);
-  if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger)
+  if (getTypeAction(LHS.getValueType()) == TargetLowering::Promote)
     LHS = GetPromotedInteger(LHS);
-  if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
+  if (getTypeAction(RHS.getValueType()) == TargetLowering::Promote)
     RHS = ZExtPromotedInteger(RHS);
   return DAG.getNode(ISD::SHL, SDLoc(N), LHS.getValueType(), LHS, RHS);
 }
 
 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
   SDValue Op = GetPromotedInteger(N->getOperand(0));
   return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N),
                      Op.getValueType(), Op, N->getOperand(1));
SDValue DAGTypeLegalizer::PromoteIntRes_ZExtIntBinOp(SDNode *N) {
   return DAG.getNode(N->getOpcode(), SDLoc(N),
                      LHS.getValueType(), LHS, RHS);
 }
 
 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
   SDValue LHS = N->getOperand(0);
   SDValue RHS = N->getOperand(1);
   // The input value must be properly sign extended.
-  if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger)
+  if (getTypeAction(LHS.getValueType()) == TargetLowering::Promote)
     LHS = SExtPromotedInteger(LHS);
-  if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
+  if (getTypeAction(RHS.getValueType()) == TargetLowering::Promote)
     RHS = ZExtPromotedInteger(RHS);
   return DAG.getNode(ISD::SRA, SDLoc(N), LHS.getValueType(), LHS, RHS);
 }
 
 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
   SDValue LHS = N->getOperand(0);
   SDValue RHS = N->getOperand(1);
   // The input value must be properly zero extended.
-  if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger)
+  if (getTypeAction(LHS.getValueType()) == TargetLowering::Promote)
     LHS = ZExtPromotedInteger(LHS);
-  if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
+  if (getTypeAction(RHS.getValueType()) == TargetLowering::Promote)
     RHS = ZExtPromotedInteger(RHS);
   return DAG.getNode(ISD::SRL, SDLoc(N), LHS.getValueType(), LHS, RHS);
 }
 
 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
   EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
   SDValue Res;
   SDValue InOp = N->getOperand(0);
   SDLoc dl(N);
 
   switch (getTypeAction(InOp.getValueType())) {
   default: llvm_unreachable("Unknown type action!");
-  case TargetLowering::TypeLegal:
-  case TargetLowering::TypeExpandInteger:
+  case TargetLowering::Legal:
+  case TargetLowering::Expand:
     Res = InOp;
     break;
-  case TargetLowering::TypePromoteInteger:
+  case TargetLowering::Promote:
     Res = GetPromotedInteger(InOp);
     break;
-  case TargetLowering::TypeSplitVector:
+  case TargetLowering::SplitVector:
     EVT InVT = InOp.getValueType();
     assert(InVT.isVector() && "Cannot split scalar types");
     unsigned NumElts = InVT.getVectorNumElements();
     assert(NumElts == NVT.getVectorNumElements() &&
            "Dst and Src must have the same number of elements");
     assert(isPowerOf2_32(NumElts) &&
            "Promoted vector type must be a power of two");
 
if (OpNo == 2) {
     // Mask comes before the data operand. If the data operand is legal, we just
     // promote the mask.
     // When the data operand has illegal type, we should legalize the data
     // operand first. The mask will be promoted/splitted/widened according to
     // the data operand type.
     if (TLI.isTypeLegal(DataVT))
       Mask = PromoteTargetBoolean(Mask, DataVT);
     else {
-      if (getTypeAction(DataVT) == TargetLowering::TypePromoteInteger)
+      if (getTypeAction(DataVT) == TargetLowering::Promote)
         return PromoteIntOp_MSTORE(N, 3);
 
-      else if (getTypeAction(DataVT) == TargetLowering::TypeWidenVector)
+      else if (getTypeAction(DataVT) == TargetLowering::WidenVector)
         return WidenVecOp_MSTORE(N, 3);
 
       else {
-        assert (getTypeAction(DataVT) == TargetLowering::TypeSplitVector);
+        assert (getTypeAction(DataVT) == TargetLowering::SplitVector);
         return SplitVecOp_MSTORE(N, 3);
       }
     }
   } else { // Data operand
     assert(OpNo == 3 && "Unexpected operand for promotion");
     DataOp = GetPromotedInteger(DataOp);
     Mask = PromoteTargetBoolean(Mask, DataOp.getValueType());
     TruncateStore = true;
void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
   if (Op.getValueType().bitsLE(NVT)) {
     // The low part is any extension of the input (which degenerates to a copy).
     Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
     Hi = DAG.getUNDEF(NVT);   // The high part is undefined.
   } else {
     // For example, extension of an i48 to an i64.  The operand type necessarily
     // promotes to the result type, so will end up being expanded too.
     assert(getTypeAction(Op.getValueType()) ==
-           TargetLowering::TypePromoteInteger &&
+           TargetLowering::Promote &&
            "Only know how to promote this result!");
     SDValue Res = GetPromotedInteger(Op);
     assert(Res.getValueType() == N->getValueType(0) &&
            "Operand over promoted?");
     // Split the promoted operand.  This will simplify when it is expanded.
     SplitInteger(Res, Lo, Hi);
   }
 }

 }
 
 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
                                                SDValue &Hi) {
   SDLoc dl(N);
   EVT VT = N->getValueType(0);
 
   SDValue Op = N->getOperand(0);
-  if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
+  if (Op.getValueType().isFloatingPoint() &&
+      getTypeAction(Op.getValueType()) == TargetLowering::Promote)
     Op = GetPromotedFloat(Op);
 
   RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
   assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
   SplitInteger(TLI.makeLibCall(DAG, LC, VT, Op, true/*irrelevant*/, dl).first,
                Lo, Hi);
 }
 
 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
                                                SDValue &Hi) {
   SDLoc dl(N);
   EVT VT = N->getValueType(0);
 
   SDValue Op = N->getOperand(0);
-  if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
+  if (Op.getValueType().isFloatingPoint() &&
+      getTypeAction(Op.getValueType()) == TargetLowering::Promote)
     Op = GetPromotedFloat(Op);
 
   RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
   assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
   SplitInteger(TLI.makeLibCall(DAG, LC, VT, Op, false/*irrelevant*/, dl).first,
                Lo, Hi);
 }
 
if (Op.getValueType().bitsLE(NVT)) {
     unsigned LoSize = NVT.getSizeInBits();
     Hi = DAG.getNode(
         ISD::SRA, dl, NVT, Lo,
         DAG.getConstant(LoSize - 1, dl, TLI.getPointerTy(DAG.getDataLayout())));
   } else {
     // For example, extension of an i48 to an i64.  The operand type necessarily
     // promotes to the result type, so will end up being expanded too.
     assert(getTypeAction(Op.getValueType()) ==
-           TargetLowering::TypePromoteInteger &&
+           TargetLowering::Promote &&
            "Only know how to promote this result!");
     SDValue Res = GetPromotedInteger(Op);
     assert(Res.getValueType() == N->getValueType(0) &&
            "Operand over promoted?");
     // Split the promoted operand.  This will simplify when it is expanded.
     SplitInteger(Res, Lo, Hi);
     unsigned ExcessBits = Op.getValueSizeInBits() - NVT.getSizeInBits();
     Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
   if (Op.getValueType().bitsLE(NVT)) {
     // The low part is zero extension of the input (degenerates to a copy).
     Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
     Hi = DAG.getConstant(0, dl, NVT);   // The high part is just a zero.
   } else {
     // For example, extension of an i48 to an i64.  The operand type necessarily
     // promotes to the result type, so will end up being expanded too.
     assert(getTypeAction(Op.getValueType()) ==
-           TargetLowering::TypePromoteInteger &&
+           TargetLowering::Promote &&
            "Only know how to promote this result!");
     SDValue Res = GetPromotedInteger(Op);
     assert(Res.getValueType() == N->getValueType(0) &&
            "Operand over promoted?");
     // Split the promoted operand.  This will simplify when it is expanded.
     SplitInteger(Res, Lo, Hi);
     unsigned ExcessBits = Op.getValueSizeInBits() - NVT.getSizeInBits();
     Hi = DAG.getZeroExtendInReg(Hi, dl,
SDValue DAGTypeLegalizer::PromoteIntRes_EXTEND_VECTOR_INREG(SDNode *N) {
 
   SDLoc dl(N);
 
   // For operands whose TypeAction is to promote, extend the promoted node
   // appropriately (ZERO_EXTEND or SIGN_EXTEND) from the original pre-promotion
   // type, and then construct a new *_EXTEND_VECTOR_INREG node to the promote-to
   // type..
   if (getTypeAction(N->getOperand(0).getValueType())
-      == TargetLowering::TypePromoteInteger) {
+      == TargetLowering::Promote) {
     SDValue Promoted;
 
     switch(N->getOpcode()) {
       case ISD::SIGN_EXTEND_VECTOR_INREG:
         Promoted = SExtPromotedInteger(N->getOperand(0));
         break;
       case ISD::ZERO_EXTEND_VECTOR_INREG:
         Promoted = ZExtPromotedInteger(N->getOperand(0));

lib/CodeGen/SelectionDAG/LegalizeTypes.h

 private:
 
   /// This is a bitvector that contains two bits for each simple value type,
   /// where the two bits correspond to the LegalizeAction enum from
   /// TargetLowering. This can be queried with "getTypeAction(VT)".
   TargetLowering::ValueTypeActionImpl ValueTypeActions;
 
   /// Return how we should legalize values of this type.
-  TargetLowering::LegalizeTypeAction getTypeAction(EVT VT) const {
+  TargetLowering::LegalizeAction getTypeAction(EVT VT) const {
     return TLI.getTypeAction(*DAG.getContext(), VT);
   }
 
   /// Return true if this type is legal on this target.
   bool isTypeLegal(EVT VT) const {
-    return TLI.getTypeAction(*DAG.getContext(), VT) == TargetLowering::TypeLegal;
+    return TLI.getTypeAction(*DAG.getContext(), VT) == TargetLowering::Legal;
   }
 
   /// Return true if this is a simple legal type.
   bool isSimpleLegalType(EVT VT) const {
     return VT.isSimple() && TLI.isTypeLegal(VT);
   }
 
   /// Return true if this type can be passed in registers.

lib/CodeGen/SelectionDAG/LegalizeTypes.cpp

#endif
     if (IgnoreNodeResults(N))
       goto ScanOperands;
 
     // Scan the values produced by the node, checking to see if any result
     // types are illegal.
     for (unsigned i = 0, NumResults = N->getNumValues(); i < NumResults; ++i) {
       EVT ResultVT = N->getValueType(i);
       switch (getTypeAction(ResultVT)) {
-      case TargetLowering::TypeLegal:
+      case TargetLowering::Legal:
         break;
       // The following calls must take care of *all* of the node's results,
       // not just the illegal result they were passed (this includes results
       // with a legal type).  Results can be remapped using ReplaceValueWith,
       // or their promoted/expanded/etc values registered in PromotedIntegers,
       // ExpandedIntegers etc.
-      case TargetLowering::TypePromoteInteger:
+      case TargetLowering::Promote:
+        if (ResultVT.isInteger()) {
           PromoteIntegerResult(N, i);
+        } else {
+          assert(ResultVT.isFloatingPoint() && "expected float type");
+          PromoteFloatResult(N, i);
+        }
         Changed = true;
         goto NodeDone;
-      case TargetLowering::TypeExpandInteger:
+      case TargetLowering::Expand:
+        if (ResultVT.isInteger()) {
           ExpandIntegerResult(N, i);
+        } else {
+          assert(ResultVT.isFloatingPoint() && "expected float type");
+          ExpandFloatResult(N, i);
+        }
         Changed = true;
         goto NodeDone;
-      case TargetLowering::TypeSoftenFloat:
+      case TargetLowering::SoftenFloat:
         Changed = SoftenFloatResult(N, i);
         if (Changed)
           goto NodeDone;
         // If not changed, the result type should be legally in register.
         assert(isLegalInHWReg(ResultVT) &&
                "Unchanged SoftenFloatResult should be legal in register!");
         goto ScanOperands;
-      case TargetLowering::TypeExpandFloat:
-        ExpandFloatResult(N, i);
-        Changed = true;
-        goto NodeDone;
-      case TargetLowering::TypeScalarizeVector:
+      case TargetLowering::ScalarizeVector:
         ScalarizeVectorResult(N, i);
         Changed = true;
         goto NodeDone;
-      case TargetLowering::TypeSplitVector:
+      case TargetLowering::SplitVector:
         SplitVectorResult(N, i);
         Changed = true;
         goto NodeDone;
-      case TargetLowering::TypeWidenVector:
+      case TargetLowering::WidenVector:
         WidenVectorResult(N, i);
         Changed = true;
         goto NodeDone;
-      case TargetLowering::TypePromoteFloat:
-        PromoteFloatResult(N, i);
-        Changed = true;
-        goto NodeDone;
+      default:
+        llvm_unreachable("unexpected legalize action");
       }
     }
 
 ScanOperands:
     // Scan the operand list for the node, handling any nodes with operands that
     // are illegal.
     {
     unsigned NumOperands = N->getNumOperands();
     bool NeedsReanalyzing = false;
     unsigned i;
     for (i = 0; i != NumOperands; ++i) {
       if (IgnoreNodeResults(N->getOperand(i).getNode()))
         continue;
 
       EVT OpVT = N->getOperand(i).getValueType();
       switch (getTypeAction(OpVT)) {
-      case TargetLowering::TypeLegal:
+      case TargetLowering::Legal:
         continue;
       // The following calls must either replace all of the node's results
       // using ReplaceValueWith, and return "false"; or update the node's
       // operands in place, and return "true".
-      case TargetLowering::TypePromoteInteger:
+      case TargetLowering::Promote:
+        if (OpVT.isInteger()) {
           NeedsReanalyzing = PromoteIntegerOperand(N, i);
+        } else {
+          assert(OpVT.isFloatingPoint() && "expected float type");
+          NeedsReanalyzing = PromoteFloatOperand(N, i);
+        }
         Changed = true;
         break;
-      case TargetLowering::TypeExpandInteger:
+      case TargetLowering::Expand:
+        if (OpVT.isInteger()) {
           NeedsReanalyzing = ExpandIntegerOperand(N, i);
+        } else {
+          assert(OpVT.isFloatingPoint() && "expected float type");
+          NeedsReanalyzing = ExpandFloatOperand(N, i);
+        }
         Changed = true;
         break;
-      case TargetLowering::TypeSoftenFloat:
+      case TargetLowering::SoftenFloat:
         NeedsReanalyzing = SoftenFloatOperand(N, i);
         Changed = true;
         break;
-      case TargetLowering::TypeExpandFloat:
-        NeedsReanalyzing = ExpandFloatOperand(N, i);
-        Changed = true;
-        break;
-      case TargetLowering::TypeScalarizeVector:
+      case TargetLowering::ScalarizeVector:
         NeedsReanalyzing = ScalarizeVectorOperand(N, i);
         Changed = true;
         break;
-      case TargetLowering::TypeSplitVector:
+      case TargetLowering::SplitVector:
         NeedsReanalyzing = SplitVectorOperand(N, i);
         Changed = true;
         break;
-      case TargetLowering::TypeWidenVector:
+      case TargetLowering::WidenVector:
         NeedsReanalyzing = WidenVectorOperand(N, i);
         Changed = true;
         break;
-      case TargetLowering::TypePromoteFloat:
-        NeedsReanalyzing = PromoteFloatOperand(N, i);
-        Changed = true;
-        break;
+      default:
+        llvm_unreachable("unexpected legalize action");
       }
       break;
     }
 
     // The sub-method updated N in place.  Check to see if any operands are new,
     // and if so, mark them.  If the node needs revisiting, don't add all users
     // to the worklist etc.
     if (NeedsReanalyzing) {

lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp

void DAGTypeLegalizer::ExpandRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi) {
   EVT OutVT = N->getValueType(0);
   EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
   SDValue InOp = N->getOperand(0);
   EVT InVT = InOp.getValueType();
   SDLoc dl(N);
 
   // Handle some special cases efficiently.
   switch (getTypeAction(InVT)) {
-    case TargetLowering::TypeLegal:
-    case TargetLowering::TypePromoteInteger:
+    case TargetLowering::Legal:
       break;
-    case TargetLowering::TypePromoteFloat:
+    case TargetLowering::Promote:
+      if (InVT.isInteger()) {
+        break;
+      }
+
+      assert(InVT.isFloatingPoint() && "unexpected value type");
       llvm_unreachable("Bitcast of a promotion-needing float should never need"
                        "expansion");
-    case TargetLowering::TypeSoftenFloat: {
+    case TargetLowering::SoftenFloat: {
       // Expand the floating point operand only if it was converted to integers.
       // Otherwise, it is a legal type like f128 that can be saved in a register.
       auto SoftenedOp = GetSoftenedFloat(InOp);
       if (SoftenedOp == InOp)
         break;
       SplitInteger(SoftenedOp, Lo, Hi);
       Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
       Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
       return;
     }
-    case TargetLowering::TypeExpandInteger:
-    case TargetLowering::TypeExpandFloat: {
+    case TargetLowering::Expand: {
       auto &DL = DAG.getDataLayout();
       // Convert the expanded pieces of the input.
       GetExpandedOp(InOp, Lo, Hi);
       if (TLI.hasBigEndianPartOrdering(InVT, DL) !=
           TLI.hasBigEndianPartOrdering(OutVT, DL))
         std::swap(Lo, Hi);
       Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
       Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
       return;
     }
-    case TargetLowering::TypeSplitVector:
+    case TargetLowering::SplitVector:
       GetSplitVector(InOp, Lo, Hi);
       if (TLI.hasBigEndianPartOrdering(OutVT, DAG.getDataLayout()))
         std::swap(Lo, Hi);
       Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
       Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
       return;
-    case TargetLowering::TypeScalarizeVector:
+    case TargetLowering::ScalarizeVector:
       // Convert the element instead.
       SplitInteger(BitConvertToInteger(GetScalarizedVector(InOp)), Lo, Hi);
       Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
       Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
       return;
-    case TargetLowering::TypeWidenVector: {
+    case TargetLowering::WidenVector: {
       assert(!(InVT.getVectorNumElements() & 1) && "Unsupported BITCAST");
       InOp = GetWidenedVector(InOp);
       EVT LoVT, HiVT;
       std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(InVT);
       std::tie(Lo, Hi) = DAG.SplitVector(InOp, dl, LoVT, HiVT);
       if (TLI.hasBigEndianPartOrdering(OutVT, DAG.getDataLayout()))
         std::swap(Lo, Hi);
       Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
       Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
       return;
     }
+    default:
+      llvm_unreachable("unexpected legalize action");
   }
 
   if (InVT.isVector() && OutVT.isInteger()) {
     // Handle cases like i64 = BITCAST v1i64 on x86, where the operand
     // is legal but the result is not.
     unsigned NumElems = 2;
     EVT ElemVT = NOutVT;
     EVT NVT = EVT::getVectorVT(*DAG.getContext(), ElemVT, NumElems);
void DAGTypeLegalizer::SplitRes_SELECT(SDNode *N, SDValue &Lo,
   GetSplitOp(N->getOperand(1), LL, LH);
   GetSplitOp(N->getOperand(2), RL, RH);
 
   SDValue Cond = N->getOperand(0);
   CL = CH = Cond;
   if (Cond.getValueType().isVector()) {
     // Check if there are already splitted versions of the vector available and
     // use those instead of splitting the mask operand again.
-    if (getTypeAction(Cond.getValueType()) == TargetLowering::TypeSplitVector)
+    if (getTypeAction(Cond.getValueType()) == TargetLowering::SplitVector)
       GetSplitVector(Cond, CL, CH);
     else
       std::tie(CL, CH) = DAG.SplitVector(Cond, dl);
   }
 
   Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), CL, LL, RL);
   Hi = DAG.getNode(N->getOpcode(), dl, LH.getValueType(), CH, LH, RH);
 }

lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
   SDLoc DL(N);
   // The result needs scalarizing, but it's not a given that the source does.
   // This is a workaround for targets where it's impossible to scalarize the
   // result of a conversion, because the source type is legal.
   // For instance, this happens on AArch64: v1i1 is illegal but v1i{8,16,32}
   // are widened to v8i8, v4i16, and v2i32, which is legal, because v1i64 is
   // legal and was not scalarized.
   // See the similar logic in ScalarizeVecRes_VSETCC
-  if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
+  if (getTypeAction(OpVT) == TargetLowering::ScalarizeVector) {
     Op = GetScalarizedVector(Op);
   } else {
     EVT VT = OpVT.getVectorElementType();
     Op = DAG.getNode(
         ISD::EXTRACT_VECTOR_ELT, DL, VT, Op,
         DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
   }
   return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op);
assert(N->getValueType(0).isVector() &&
          "Operand types must be vectors");
   SDValue LHS = N->getOperand(0);
   SDValue RHS = N->getOperand(1);
   EVT OpVT = LHS.getValueType();
   EVT NVT = N->getValueType(0).getVectorElementType();
   SDLoc DL(N);
 
   // The result needs scalarizing, but it's not a given that the source does.
-  if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
+  if (getTypeAction(OpVT) == TargetLowering::ScalarizeVector) {
     LHS = GetScalarizedVector(LHS);
     RHS = GetScalarizedVector(RHS);
   } else {
     EVT VT = OpVT.getVectorElementType();
     LHS = DAG.getNode(
         ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS,
         DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
     RHS = DAG.getNode(
void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
   std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
   SDLoc dl(N);
 
   SDValue InOp = N->getOperand(0);
   EVT InVT = InOp.getValueType();
 
   // Handle some special cases efficiently.
   switch (getTypeAction(InVT)) {
-  case TargetLowering::TypeLegal:
-  case TargetLowering::TypePromoteInteger:
-  case TargetLowering::TypePromoteFloat:
-  case TargetLowering::TypeSoftenFloat:
-  case TargetLowering::TypeScalarizeVector:
-  case TargetLowering::TypeWidenVector:
+  case TargetLowering::Legal:
+  case TargetLowering::Promote:
+  case TargetLowering::SoftenFloat:
+  case TargetLowering::ScalarizeVector:
+  case TargetLowering::WidenVector:
     break;
-  case TargetLowering::TypeExpandInteger:
-  case TargetLowering::TypeExpandFloat:
+  case TargetLowering::Expand:
     // A scalar to vector conversion, where the scalar needs expansion.
     // If the vector is being split in two then we can just convert the
     // expanded pieces.
     if (LoVT == HiVT) {
       GetExpandedOp(InOp, Lo, Hi);
       if (DAG.getDataLayout().isBigEndian())
         std::swap(Lo, Hi);
       Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
       Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
       return;
     }
     break;
-  case TargetLowering::TypeSplitVector:
+  case TargetLowering::SplitVector:
     // If the input is a vector that needs to be split, convert each split
     // piece of the input now.
     GetSplitVector(InOp, Lo, Hi);
     Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
     Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
     return;
+  default:
+    llvm_unreachable("unexpected legalize action");
   }
 
   // In the general case, convert the input to an integer and split it by hand.
   EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
   EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
   if (DAG.getDataLayout().isBigEndian())
     std::swap(LoIntVT, HiIntVT);
 
void DAGTypeLegalizer::SplitVecRes_FCOPYSIGN(SDNode *N, SDValue &Lo,
                                              SDValue &Hi) {
   SDValue LHSLo, LHSHi;
   GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
   SDLoc DL(N);
 
   SDValue RHSLo, RHSHi;
   SDValue RHS = N->getOperand(1);
   EVT RHSVT = RHS.getValueType();
-  if (getTypeAction(RHSVT) == TargetLowering::TypeSplitVector)
+  if (getTypeAction(RHSVT) == TargetLowering::SplitVector)
     GetSplitVector(RHS, RHSLo, RHSHi);
   else
     std::tie(RHSLo, RHSHi) = DAG.SplitVector(RHS, SDLoc(RHS));
 
 
   Lo = DAG.getNode(ISD::FCOPYSIGN, DL, LHSLo.getValueType(), LHSLo, RHSLo);
   Hi = DAG.getNode(ISD::FCOPYSIGN, DL, LHSHi.getValueType(), LHSHi, RHSHi);
 }
void DAGTypeLegalizer::SplitVecRes_MLOAD(MaskedLoadSDNode *MLD,
   // if Alignment is equal to the vector size,
   // take the half of it for the second part
   unsigned SecondHalfAlignment =
     (Alignment == MLD->getValueType(0).getSizeInBits()/8) ?
      Alignment/2 : Alignment;
 
   // Split Mask operand
   SDValue MaskLo, MaskHi;
-  if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
+  if (getTypeAction(Mask.getValueType()) == TargetLowering::SplitVector)
     GetSplitVector(Mask, MaskLo, MaskHi);
   else
     std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
 
   EVT MemoryVT = MLD->getMemoryVT();
   EVT LoMemVT, HiMemVT;
   std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
 
   SDValue Src0Lo, Src0Hi;
-  if (getTypeAction(Src0.getValueType()) == TargetLowering::TypeSplitVector)
+  if (getTypeAction(Src0.getValueType()) == TargetLowering::SplitVector)
     GetSplitVector(Src0, Src0Lo, Src0Hi);
   else
     std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl);
 
   MachineMemOperand *MMO = DAG.getMachineFunction().
     getMachineMemOperand(MLD->getPointerInfo(),
                          MachineMemOperand::MOLoad,  LoMemVT.getStoreSize(),
                          Alignment, MLD->getAAInfo(), MLD->getRanges());
void DAGTypeLegalizer::SplitVecRes_MGATHER(MaskedGatherSDNode *MGT,
   SDValue Ptr = MGT->getBasePtr();
   SDValue Mask = MGT->getMask();
   SDValue Src0 = MGT->getValue();
   SDValue Index = MGT->getIndex();
   unsigned Alignment = MGT->getOriginalAlignment();
 
   // Split Mask operand
   SDValue MaskLo, MaskHi;
-  if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
+  if (getTypeAction(Mask.getValueType()) == TargetLowering::SplitVector)
     GetSplitVector(Mask, MaskLo, MaskHi);
   else
     std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
 
   EVT MemoryVT = MGT->getMemoryVT();
   EVT LoMemVT, HiMemVT;
   // Split MemoryVT
   std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
 
   SDValue Src0Lo, Src0Hi;
-  if (getTypeAction(Src0.getValueType()) == TargetLowering::TypeSplitVector)
+  if (getTypeAction(Src0.getValueType()) == TargetLowering::SplitVector)
     GetSplitVector(Src0, Src0Lo, Src0Hi);
   else
     std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl);
 
   SDValue IndexHi, IndexLo;
-  if (getTypeAction(Index.getValueType()) == TargetLowering::TypeSplitVector)
+  if (getTypeAction(Index.getValueType()) == TargetLowering::SplitVector)
     GetSplitVector(Index, IndexLo, IndexHi);
   else
     std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, dl);
 
   MachineMemOperand *MMO = DAG.getMachineFunction().
     getMachineMemOperand(MGT->getPointerInfo(),
                          MachineMemOperand::MOLoad,  LoMemVT.getStoreSize(),
                          Alignment, MGT->getAAInfo(), MGT->getRanges());
void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
   // Get the dest types - they may not match the input types, e.g. int_to_fp.
   EVT LoVT, HiVT;
   SDLoc dl(N);
   std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
 
   // If the input also splits, handle it directly for a compile time speedup.
   // Otherwise split it by hand.
   EVT InVT = N->getOperand(0).getValueType();
-  if (getTypeAction(InVT) == TargetLowering::TypeSplitVector)
+  if (getTypeAction(InVT) == TargetLowering::SplitVector)
     GetSplitVector(N->getOperand(0), Lo, Hi);
   else
     std::tie(Lo, Hi) = DAG.SplitVectorOperand(N, 0);
 
   if (N->getOpcode() == ISD::FP_ROUND) {
     Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1));
     Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1));
   } else if (N->getOpcode() == ISD::CONVERT_RNDSAT) {
SDValue DAGTypeLegalizer::SplitVecOp_MGATHER(MaskedGatherSDNode *MGT,
   SDValue Ch = MGT->getChain();
   SDValue Ptr = MGT->getBasePtr();
   SDValue Index = MGT->getIndex();
   SDValue Mask = MGT->getMask();
   SDValue Src0 = MGT->getValue();
   unsigned Alignment = MGT->getOriginalAlignment();
 
   SDValue MaskLo, MaskHi;
-  if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
+  if (getTypeAction(Mask.getValueType()) == TargetLowering::SplitVector)
     // Split Mask operand
     GetSplitVector(Mask, MaskLo, MaskHi);
   else
     std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
 
   EVT MemoryVT = MGT->getMemoryVT();
   EVT LoMemVT, HiMemVT;
   std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
 
   SDValue Src0Lo, Src0Hi;
-  if (getTypeAction(Src0.getValueType()) == TargetLowering::TypeSplitVector)
+  if (getTypeAction(Src0.getValueType()) == TargetLowering::SplitVector)
     GetSplitVector(Src0, Src0Lo, Src0Hi);
   else
     std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl);
 
   SDValue IndexHi, IndexLo;
-  if (getTypeAction(Index.getValueType()) == TargetLowering::TypeSplitVector)
+  if (getTypeAction(Index.getValueType()) == TargetLowering::SplitVector)
     GetSplitVector(Index, IndexLo, IndexHi);
   else
     std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, dl);
 
   MachineMemOperand *MMO = DAG.getMachineFunction().
     getMachineMemOperand(MGT->getPointerInfo(),
                          MachineMemOperand::MOLoad,  LoMemVT.getStoreSize(),
                          Alignment, MGT->getAAInfo(), MGT->getRanges());
SDValue DAGTypeLegalizer::SplitVecOp_MSTORE(MaskedStoreSDNode *N,
   EVT MemoryVT = N->getMemoryVT();
   unsigned Alignment = N->getOriginalAlignment();
   SDLoc DL(N);
 
   EVT LoMemVT, HiMemVT;
   std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
 
   SDValue DataLo, DataHi;
-  if (getTypeAction(Data.getValueType()) == TargetLowering::TypeSplitVector)
+  if (getTypeAction(Data.getValueType()) == TargetLowering::SplitVector)
     // Split Data operand
     GetSplitVector(Data, DataLo, DataHi);
   else
     std::tie(DataLo, DataHi) = DAG.SplitVector(Data, DL);
 
   SDValue MaskLo, MaskHi;
-  if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
+  if (getTypeAction(Mask.getValueType()) == TargetLowering::SplitVector)
     // Split Mask operand
     GetSplitVector(Mask, MaskLo, MaskHi);
   else
     std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, DL);
 
   MaskLo = PromoteTargetBoolean(MaskLo, DataLo.getValueType());
   MaskHi = PromoteTargetBoolean(MaskHi, DataHi.getValueType());
 
SDValue DAGTypeLegalizer::SplitVecOp_MSCATTER(MaskedScatterSDNode *N,
   unsigned Alignment = N->getOriginalAlignment();
   SDLoc DL(N);
 
   // Split all operands
   EVT LoMemVT, HiMemVT;
   std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
 
   SDValue DataLo, DataHi;
-  if (getTypeAction(Data.getValueType()) == TargetLowering::TypeSplitVector)
+  if (getTypeAction(Data.getValueType()) == TargetLowering::SplitVector)
     // Split Data operand
     GetSplitVector(Data, DataLo, DataHi);
   else
     std::tie(DataLo, DataHi) = DAG.SplitVector(Data, DL);
 
   SDValue MaskLo, MaskHi;
-  if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
+  if (getTypeAction(Mask.getValueType()) == TargetLowering::SplitVector)
     // Split Mask operand
     GetSplitVector(Mask, MaskLo, MaskHi);
   else
     std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, DL);
 
   SDValue IndexHi, IndexLo;
-  if (getTypeAction(Index.getValueType()) == TargetLowering::TypeSplitVector)
+  if (getTypeAction(Index.getValueType()) == TargetLowering::SplitVector)
     GetSplitVector(Index, IndexLo, IndexHi);
   else
     std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, DL);
 
   SDValue Lo, Hi;
   MachineMemOperand *MMO = DAG.getMachineFunction().
     getMachineMemOperand(N->getPointerInfo(),
                          MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
 
   EVT InVT = InOp.getValueType();
   EVT InEltVT = InVT.getVectorElementType();
   EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
 
   unsigned Opcode = N->getOpcode();
   unsigned InVTNumElts = InVT.getVectorNumElements();
   const SDNodeFlags *Flags = N->getFlags();
-  if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
+  if (getTypeAction(InVT) == TargetLowering::WidenVector) {
     InOp = GetWidenedVector(N->getOperand(0));
     InVT = InOp.getValueType();
     InVTNumElts = InVT.getVectorNumElements();
     if (InVTNumElts == WidenNumElts) {
       if (N->getNumOperands() == 1)
         return DAG.getNode(Opcode, DL, WidenVT, InOp);
       return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1), Flags);
     }
SDValue DAGTypeLegalizer::WidenVecRes_EXTEND_VECTOR_INREG(SDNode *N) {
   EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
   EVT WidenSVT = WidenVT.getVectorElementType();
   unsigned WidenNumElts = WidenVT.getVectorNumElements();
 
   EVT InVT = InOp.getValueType();
   EVT InSVT = InVT.getVectorElementType();
   unsigned InVTNumElts = InVT.getVectorNumElements();
 
-  if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
+  if (getTypeAction(InVT) == TargetLowering::WidenVector) {
     InOp = GetWidenedVector(InOp);
     InVT = InOp.getValueType();
     if (InVT.getSizeInBits() == WidenVT.getSizeInBits()) {
       switch (Opcode) {
       case ISD::ANY_EXTEND_VECTOR_INREG:
         return DAG.getAnyExtendVectorInReg(InOp, DL, WidenVT);
       case ISD::SIGN_EXTEND_VECTOR_INREG:
         return DAG.getSignExtendVectorInReg(InOp, DL, WidenVT);

 }
 
 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
   EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
   SDValue InOp = GetWidenedVector(N->getOperand(0));
   SDValue ShOp = N->getOperand(1);
 
   EVT ShVT = ShOp.getValueType();
-  if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) {
+  if (getTypeAction(ShVT) == TargetLowering::WidenVector) {
     ShOp = GetWidenedVector(ShOp);
     ShVT = ShOp.getValueType();
   }
   EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(),
                                    ShVT.getVectorElementType(),
                                    WidenVT.getVectorNumElements());
   if (ShVT != ShWidenVT)
     ShOp = ModifyToType(ShOp, ShWidenVT);

 SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) {
   SDValue InOp = N->getOperand(0);
   EVT InVT = InOp.getValueType();
   EVT VT = N->getValueType(0);
   EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
   SDLoc dl(N);
 
   switch (getTypeAction(InVT)) {
-  case TargetLowering::TypeLegal:
+  case TargetLowering::Legal:
     break;
-  case TargetLowering::TypePromoteInteger:
+  case TargetLowering::Promote:
+    if (InVT.isInteger()) {
       // If the incoming type is a vector that is being promoted, then
       // we know that the elements are arranged differently and that we
       // must perform the conversion using a stack slot.
       if (InVT.isVector())
         break;
 
       // If the InOp is promoted to the same size, convert it.  Otherwise,
       // fall out of the switch and widen the promoted input.
       InOp = GetPromotedInteger(InOp);
       InVT = InOp.getValueType();
       if (WidenVT.bitsEq(InVT))
         return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
       break;
-  case TargetLowering::TypeSoftenFloat:
-  case TargetLowering::TypePromoteFloat:
-  case TargetLowering::TypeExpandInteger:
-  case TargetLowering::TypeExpandFloat:
-  case TargetLowering::TypeScalarizeVector:
-  case TargetLowering::TypeSplitVector:
+    } else {
+      assert(InVT.isFloatingPoint() && "expected float value type");
       break;
-  case TargetLowering::TypeWidenVector:
+    }
+  case TargetLowering::Expand:
+  case TargetLowering::SoftenFloat:
+  case TargetLowering::ScalarizeVector:
+  case TargetLowering::SplitVector:
+    break;
+  case TargetLowering::WidenVector:
     // If the InOp is widened to the same size, convert it.  Otherwise, fall
     // out of the switch and widen the widened input.
     InOp = GetWidenedVector(InOp);
     InVT = InOp.getValueType();
     if (WidenVT.bitsEq(InVT))
       // The input widens to the same size. Convert to the widen value.
       return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
     break;
+  default:
+    llvm_unreachable("unexpected value type");
   }
 
   unsigned WidenSize = WidenVT.getSizeInBits();
   unsigned InSize = InVT.getSizeInBits();
   // x86mmx is not an acceptable vector element type, so don't try.
   if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) {
     // Determine new input vector type.  The new input vector type will use
     // the same element type (if its a vector) or use the input type as a
SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
   EVT InVT = N->getOperand(0).getValueType();
   EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
   SDLoc dl(N);
   unsigned WidenNumElts = WidenVT.getVectorNumElements();
   unsigned NumInElts = InVT.getVectorNumElements();
   unsigned NumOperands = N->getNumOperands();
 
   bool InputWidened = false; // Indicates we need to widen the input.
-  if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) {
+  if (getTypeAction(InVT) != TargetLowering::WidenVector) {
     if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
       // Add undef vectors to widen to correct length.
       unsigned NumConcat = WidenVT.getVectorNumElements() /
                            InVT.getVectorNumElements();
       SDValue UndefVal = DAG.getUNDEF(InVT);
       SmallVector<SDValue, 16> Ops(NumConcat);
       for (unsigned i=0; i < NumOperands; ++i)
         Ops[i] = N->getOperand(i);
SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
   EVT InEltVT = InVT.getVectorElementType();
   EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
 
   SDValue DTyOp = DAG.getValueType(WidenVT);
   SDValue STyOp = DAG.getValueType(InWidenVT);
   ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
 
   unsigned InVTNumElts = InVT.getVectorNumElements();
-  if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
+  if (getTypeAction(InVT) == TargetLowering::WidenVector) {
     InOp = GetWidenedVector(InOp);
     InVT = InOp.getValueType();
     InVTNumElts = InVT.getVectorNumElements();
     if (InVTNumElts == WidenNumElts)
       return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
                                   SatOp, CvtCode);
   }
 

 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
   EVT      VT = N->getValueType(0);
   EVT      WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
   unsigned WidenNumElts = WidenVT.getVectorNumElements();
   SDValue  InOp = N->getOperand(0);
   SDValue  Idx  = N->getOperand(1);
   SDLoc dl(N);
 
-  if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
+  if (getTypeAction(InOp.getValueType()) == TargetLowering::WidenVector)
     InOp = GetWidenedVector(InOp);
 
   EVT InVT = InOp.getValueType();
 
   // Check if we can just return the input vector after widening.
   uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
   if (IdxVal == 0 && InVT == WidenVT)
     return InOp;
SDValue DAGTypeLegalizer::WidenVecRes_MLOAD(MaskedLoadSDNode *N) {
 
   EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),N->getValueType(0));
   SDValue Mask = N->getMask();
   EVT MaskVT = Mask.getValueType();
   SDValue Src0 = GetWidenedVector(N->getSrc0());
   ISD::LoadExtType ExtType = N->getExtensionType();
   SDLoc dl(N);
 
-  if (getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
+  if (getTypeAction(MaskVT) == TargetLowering::WidenVector)
     Mask = GetWidenedVector(Mask);
   else {
     EVT BoolVT = getSetCCResultType(WidenVT);
 
     // We can't use ModifyToType() because we should fill the mask with
     // zeroes
     unsigned WidenNumElts = BoolVT.getVectorNumElements();
     unsigned MaskNumElts = MaskVT.getVectorNumElements();
SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
   unsigned WidenNumElts = WidenVT.getVectorNumElements();
 
   SDValue Cond1 = N->getOperand(0);
   EVT CondVT = Cond1.getValueType();
   if (CondVT.isVector()) {
     EVT CondEltVT = CondVT.getVectorElementType();
     EVT CondWidenVT =  EVT::getVectorVT(*DAG.getContext(),
                                         CondEltVT, WidenNumElts);
-    if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector)
+    if (getTypeAction(CondVT) == TargetLowering::WidenVector)
       Cond1 = GetWidenedVector(Cond1);
 
     // If we have to split the condition there is no point in widening the
     // select. This would result in an cycle of widening the select ->
     // widening the condition operand -> splitting the condition operand ->
     // splitting the select -> widening the select. Instead split this select
     // further and widen the resulting type.
-    if (getTypeAction(CondVT) == TargetLowering::TypeSplitVector) {
+    if (getTypeAction(CondVT) == TargetLowering::SplitVector) {
       SDValue SplitSelect = SplitVecOp_VSELECT(N, 0);
       SDValue Res = ModifyToType(SplitSelect, WidenVT);
       return Res;
     }
 
     if (Cond1.getValueType() != CondWidenVT)
       Cond1 = ModifyToType(Cond1, CondWidenVT);
   }
SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
   EVT InVT = InOp1.getValueType();
   assert(InVT.isVector() && "can not widen non-vector type");
   EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(),
                                    InVT.getVectorElementType(), WidenNumElts);
 
   // The input and output types often differ here, and it could be that while
   // we'd prefer to widen the result type, the input operands have been split.
   // In this case, we also need to split the result of this node as well.
-  if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) {
+  if (getTypeAction(InVT) == TargetLowering::SplitVector) {
     SDValue SplitVSetCC = SplitVecOp_VSETCC(N);
     SDValue Res = ModifyToType(SplitVSetCC, WidenVT);
     return Res;
   }
 
   InOp1 = GetWidenedVector(InOp1);
   SDValue InOp2 = GetWidenedVector(N->getOperand(1));
 

 SDValue DAGTypeLegalizer::WidenVecOp_EXTEND(SDNode *N) {
   SDLoc DL(N);
   EVT VT = N->getValueType(0);
 
   SDValue InOp = N->getOperand(0);
   // If some legalization strategy other than widening is used on the operand,
   // we can't safely assume that just extending the low lanes is the correct
   // transformation.
-  if (getTypeAction(InOp.getValueType()) != TargetLowering::TypeWidenVector)
+  if (getTypeAction(InOp.getValueType()) != TargetLowering::WidenVector)
     return WidenVecOp_Convert(N);
   InOp = GetWidenedVector(InOp);
   assert(VT.getVectorNumElements() <
              InOp.getValueType().getVectorNumElements() &&
          "Input wasn't widened!");
 
   // We may need to further widen the operand until it has the same total
   // vector size as the result.
SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
   // Since the result is legal and the input is illegal, it is unlikely that we
   // can fix the input to a legal type so unroll the convert into some scalar
   // code and create a nasty build vector.
   EVT VT = N->getValueType(0);
   EVT EltVT = VT.getVectorElementType();
   SDLoc dl(N);
   unsigned NumElts = VT.getVectorNumElements();
   SDValue InOp = N->getOperand(0);
-  if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
+  if (getTypeAction(InOp.getValueType()) == TargetLowering::WidenVector)
     InOp = GetWidenedVector(InOp);
   EVT InVT = InOp.getValueType();
   EVT InEltVT = InVT.getVectorElementType();
 
   unsigned Opcode = N->getOpcode();
   SmallVector<SDValue, 16> Ops(NumElts);
   for (unsigned i=0; i < NumElts; ++i)
     Ops[i] = DAG.getNode(
SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
 
   EVT InVT = N->getOperand(0).getValueType();
   unsigned NumInElts = InVT.getVectorNumElements();
 
   unsigned Idx = 0;
   unsigned NumOperands = N->getNumOperands();
   for (unsigned i=0; i < NumOperands; ++i) {
     SDValue InOp = N->getOperand(i);
-    if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
+    if (getTypeAction(InOp.getValueType()) == TargetLowering::WidenVector)
       InOp = GetWidenedVector(InOp);
     for (unsigned j=0; j < NumInElts; ++j)
       Ops[Idx++] = DAG.getNode(
           ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
           DAG.getConstant(j, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
   }
   return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
 }
SDValue DAGTypeLegalizer::WidenVecOp_MSTORE(SDNode *N, unsigned OpNo) {
   MaskedStoreSDNode *MST = cast<MaskedStoreSDNode>(N);
   SDValue Mask = MST->getMask();
   EVT MaskVT = Mask.getValueType();
   SDValue StVal = MST->getValue();
   // Widen the value
   SDValue WideVal = GetWidenedVector(StVal);
   SDLoc dl(N);
 
-  if (OpNo == 2 || getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
+  if (OpNo == 2 || getTypeAction(MaskVT) == TargetLowering::WidenVector)
     Mask = GetWidenedVector(Mask);
   else {
     // The mask should be widened as well.
     EVT BoolVT = getSetCCResultType(WideVal.getValueType());
     // We can't use ModifyToType() because we should fill the mask with
     // zeroes.
     unsigned WidenNumElts = BoolVT.getVectorNumElements();
     unsigned MaskNumElts = MaskVT.getVectorNumElements();
static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI,
   unsigned VT;
   for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE;
        VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) {
     EVT MemVT((MVT::SimpleValueType) VT);
     unsigned MemVTWidth = MemVT.getSizeInBits();
     if (MemVT.getSizeInBits() <= WidenEltWidth)
       break;
     auto Action = TLI.getTypeAction(*DAG.getContext(), MemVT);
-    if ((Action == TargetLowering::TypeLegal ||
-         Action == TargetLowering::TypePromoteInteger) &&
+    if ((Action == TargetLowering::Legal ||
+         (MemVT.isInteger() && Action == TargetLowering::Promote)) &&
         (WidenWidth % MemVTWidth) == 0 &&
         isPowerOf2_32(WidenWidth / MemVTWidth) &&
         (MemVTWidth <= Width ||
          (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
       RetVT = MemVT;
       break;
     }
   }

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

SDValue SelectionDAG::getConstant(const ConstantInt &Val, const SDLoc &DL,
 
   EVT EltVT = VT.getScalarType();
   const ConstantInt *Elt = &Val;
 
   // In some cases the vector type is legal but the element type is illegal and
   // needs to be promoted, for example v8i8 on ARM.  In this case, promote the
   // inserted value (the type does not need to match the vector element type).
   // Any extra bits introduced will be truncated away.
-  if (VT.isVector() && TLI->getTypeAction(*getContext(), EltVT) ==
-      TargetLowering::TypePromoteInteger) {
+  if (VT.isVector() && VT.isInteger() &&
+      TLI->getTypeAction(*getContext(), EltVT) == TargetLowering::Promote) {
    EltVT = TLI->getTypeToTransformTo(*getContext(), EltVT);
    APInt NewVal = Elt->getValue().zext(EltVT.getSizeInBits());
    Elt = ConstantInt::get(*getContext(), NewVal);
   }
   // In other cases the element type is illegal and needs to be expanded, for
   // example v2i64 on MIPS32. In this case, find the nearest legal type, split
   // the value into n parts and use a vector type with n-times the elements.
   // Then bitcast to the type requested.
   // Legalizing constants too early makes the DAGCombiner's job harder so we
   // only legalize if the DAG tells us we must produce legal types.
-  else if (NewNodesMustHaveLegalTypes && VT.isVector() &&
-           TLI->getTypeAction(*getContext(), EltVT) ==
-           TargetLowering::TypeExpandInteger) {
+  else if (NewNodesMustHaveLegalTypes && VT.isVector() && VT.isInteger() &&
+           TLI->getTypeAction(*getContext(), EltVT) == TargetLowering::Expand) {
     const APInt &NewVal = Elt->getValue();
     EVT ViaEltVT = TLI->getTypeToTransformTo(*getContext(), EltVT);
     unsigned ViaEltSizeInBits = ViaEltVT.getSizeInBits();
     unsigned ViaVecNumElts = VT.getSizeInBits() / ViaEltSizeInBits;
     EVT ViaVecVT = EVT::getVectorVT(*getContext(), ViaEltVT, ViaVecNumElts);
 
     // Check the temporary vector is the correct size. If this fails then
     // getTypeToTransformTo() probably returned a type whose size (in bits)

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

void SelectionDAGBuilder::visitSelect(const User &I) {
   // Min/max matching is only viable if all output VTs are the same.
   if (std::equal(ValueVTs.begin(), ValueVTs.end(), ValueVTs.begin())) {
     EVT VT = ValueVTs[0];
     LLVMContext &Ctx = *DAG.getContext();
     auto &TLI = DAG.getTargetLoweringInfo();
 
     // We care about the legality of the operation after it has been type
     // legalized.
-    while (TLI.getTypeAction(Ctx, VT) != TargetLoweringBase::TypeLegal &&
+    while (TLI.getTypeAction(Ctx, VT) != TargetLoweringBase::Legal &&
            VT != TLI.getTypeToTransformTo(Ctx, VT))
       VT = TLI.getTypeToTransformTo(Ctx, VT);
 
     // If the vselect is legal, assume we want to leave this as a vector setcc +
     // vselect. Otherwise, if this is going to be scalarized, we want to see if
     // min/max is legal on the scalar type.
     bool UseScalarMinMax = VT.isVector() &&
       !TLI.isOperationLegalOrCustom(ISD::VSELECT, VT);

lib/CodeGen/TargetLoweringBase.cpp

 
 TargetLoweringBase::LegalizeKind
 TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
   // If this is a simple type, use the ComputeRegisterProp mechanism.
   if (VT.isSimple()) {
     MVT SVT = VT.getSimpleVT();
     assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
     MVT NVT = TransformToType[SVT.SimpleTy];
-    LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
+    LegalizeAction LA = ValueTypeActions.getTypeAction(SVT);
 
-    assert((LA == TypeLegal || LA == TypeSoftenFloat ||
-            ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger) &&
+    assert((LA == Legal || LA == SoftenFloat ||
+            ValueTypeActions.getTypeAction(NVT) != Promote) &&
            "Promote may not follow Expand or Promote");
 
-    if (LA == TypeSplitVector)
+    if (LA == SplitVector)
       return LegalizeKind(LA,
                           EVT::getVectorVT(Context, SVT.getVectorElementType(),
                                            SVT.getVectorNumElements() / 2));
-    if (LA == TypeScalarizeVector)
+    if (LA == ScalarizeVector)
       return LegalizeKind(LA, SVT.getVectorElementType());
     return LegalizeKind(LA, NVT);
   }
 
   // Handle Extended Scalar Types.
   if (!VT.isVector()) {
     assert(VT.isInteger() && "Float types must be simple");
     unsigned BitSize = VT.getSizeInBits();
     // First promote to a power-of-two size, then expand if necessary.
     if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
       EVT NVT = VT.getRoundIntegerType(Context);
       assert(NVT != VT && "Unable to round integer VT");
       LegalizeKind NextStep = getTypeConversion(Context, NVT);
       // Avoid multi-step promotion.
-      if (NextStep.first == TypePromoteInteger)
+      if (NextStep.first == Promote)
         return NextStep;
       // Return rounded integer type.
-      return LegalizeKind(TypePromoteInteger, NVT);
+      return LegalizeKind(Promote, NVT);
     }
 
-    return LegalizeKind(TypeExpandInteger,
+    return LegalizeKind(Expand,
                         EVT::getIntegerVT(Context, VT.getSizeInBits() / 2));
   }
 
   // Handle vector types.
   unsigned NumElts = VT.getVectorNumElements();
   EVT EltVT = VT.getVectorElementType();
 
   // Vectors with only one element are always scalarized.
   if (NumElts == 1)
-    return LegalizeKind(TypeScalarizeVector, EltVT);
+    return LegalizeKind(ScalarizeVector, EltVT);
 
   // Try to widen vector elements until the element type is a power of two and
   // promote it to a legal type later on, for example:
   // <3 x i8> -> <4 x i8> -> <4 x i32>
   if (EltVT.isInteger()) {
     // Vectors with a number of elements that is not a power of two are always
     // widened, for example <3 x i8> -> <4 x i8>.
     if (!VT.isPow2VectorType()) {
       NumElts = (unsigned)NextPowerOf2(NumElts);
       EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
-      return LegalizeKind(TypeWidenVector, NVT);
+      return LegalizeKind(WidenVector, NVT);
     }
 
     // Examine the element type.
     LegalizeKind LK = getTypeConversion(Context, EltVT);
 
     // If type is to be expanded, split the vector.
     //  <4 x i140> -> <2 x i140>
-    if (LK.first == TypeExpandInteger)
-      return LegalizeKind(TypeSplitVector,
+    if (LK.first == Expand)
+      return LegalizeKind(SplitVector,
                           EVT::getVectorVT(Context, EltVT, NumElts / 2));
 
     // Promote the integer element types until a legal vector type is found
     // or until the element integer type is too big. If a legal type was not
     // found, fallback to the usual mechanism of widening/splitting the
     // vector.
     EVT OldEltVT = EltVT;
     while (1) {
       // Increase the bitwidth of the element to the next pow-of-two
       // (which is greater than 8 bits).
       EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits())
                   .getRoundIntegerType(Context);
 
       // Stop trying when getting a non-simple element type.
       // Note that vector elements may be greater than legal vector element
       // types. Example: X86 XMM registers hold 64bit element on 32bit
       // systems.
       if (!EltVT.isSimple())
         break;
 
       // Build a new vector type and check if it is legal.
       MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
       // Found a legal promoted vector type.
-      if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
-        return LegalizeKind(TypePromoteInteger,
+      if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == Legal)
+        return LegalizeKind(Promote,
                             EVT::getVectorVT(Context, EltVT, NumElts));
     }
 
     // Reset the type to the unexpanded type if we did not find a legal vector
     // type with a promoted vector element type.
     EltVT = OldEltVT;
   }
 
   // Try to widen the vector until a legal type is found.
   // If there is no wider legal type, split the vector.
   while (1) {
     // Round up to the next power of 2.
     NumElts = (unsigned)NextPowerOf2(NumElts);
 
     // If there is no simple vector type with this many elements then there
     // cannot be a larger legal vector type.  Note that this assumes that
     // there are no skipped intermediate vector types in the simple types.
     if (!EltVT.isSimple())
       break;
     MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
     if (LargerVector == MVT())
       break;
 
     // If this type is legal then widen the vector.
-    if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
-      return LegalizeKind(TypeWidenVector, LargerVector);
+    if (ValueTypeActions.getTypeAction(LargerVector) == Legal)
+      return LegalizeKind(WidenVector, LargerVector);
   }
 
   // Widen odd vectors to next power of two.
   if (!VT.isPow2VectorType()) {
     EVT NVT = VT.getPow2VectorType(Context);
-    return LegalizeKind(TypeWidenVector, NVT);
+    return LegalizeKind(WidenVector, NVT);
   }
 
   // Vectors with illegal element types are expanded.
   EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
-  return LegalizeKind(TypeSplitVector, NVT);
+  return LegalizeKind(SplitVector, NVT);
 }
 
 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
                                           unsigned &NumIntermediates,
                                           MVT &RegisterVT,
                                           TargetLoweringBase *TLI) {
   // Figure out the right, legal destination reg to copy into.
   unsigned NumElts = VT.getVectorNumElements();
void TargetLoweringBase::computeRegisterProperties(
 
   // Every integer value type larger than this largest register takes twice as
   // many registers to represent as the previous ValueType.
   for (unsigned ExpandedReg = LargestIntReg + 1;
        ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
     NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
     RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
     TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
-    ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
-                                   TypeExpandInteger);
+    ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg, Expand);
   }
 
   // Inspect all of the ValueType's smaller than the largest integer
   // register to see which ones need promotion.
   unsigned LegalIntReg = LargestIntReg;
   for (unsigned IntReg = LargestIntReg - 1;
        IntReg >= (unsigned)MVT::i1; --IntReg) {
     MVT IVT = (MVT::SimpleValueType)IntReg;
     if (isTypeLegal(IVT)) {
       LegalIntReg = IntReg;
     } else {
       RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
         (const MVT::SimpleValueType)LegalIntReg;
-      ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
+      ValueTypeActions.setTypeAction(IVT, Promote);
     }
   }
 
   // ppcf128 type is really two f64's.
   if (!isTypeLegal(MVT::ppcf128)) {
     if (isTypeLegal(MVT::f64)) {
       NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
       RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
       TransformToType[MVT::ppcf128] = MVT::f64;
-      ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
+      ValueTypeActions.setTypeAction(MVT::ppcf128, Expand);
     } else {
       NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
       RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
       TransformToType[MVT::ppcf128] = MVT::i128;
-      ValueTypeActions.setTypeAction(MVT::ppcf128, TypeSoftenFloat);
+      ValueTypeActions.setTypeAction(MVT::ppcf128, SoftenFloat);
     }
   }
 
   // Decide how to handle f128. If the target does not have native f128 support,
   // expand it to i128 and we will be generating soft float library calls.
   if (!isTypeLegal(MVT::f128)) {
     NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
     RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
     TransformToType[MVT::f128] = MVT::i128;
-    ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
+    ValueTypeActions.setTypeAction(MVT::f128, SoftenFloat);
   }
 
   // Decide how to handle f64. If the target does not have native f64 support,
   // expand it to i64 and we will be generating soft float library calls.
   if (!isTypeLegal(MVT::f64)) {
     NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
     RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
     TransformToType[MVT::f64] = MVT::i64;
-    ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
+    ValueTypeActions.setTypeAction(MVT::f64, SoftenFloat);
   }
 
   // Decide how to handle f32. If the target does not have native f32 support,
   // expand it to i32 and we will be generating soft float library calls.
   if (!isTypeLegal(MVT::f32)) {
     NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
     RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
     TransformToType[MVT::f32] = MVT::i32;
-    ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
+    ValueTypeActions.setTypeAction(MVT::f32, SoftenFloat);
   }
 
   // Decide how to handle f16. If the target does not have native f16 support,
   // promote it to f32, because there are no f16 library calls (except for
   // conversions).
   if (!isTypeLegal(MVT::f16)) {
     NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
     RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
     TransformToType[MVT::f16] = MVT::f32;
-    ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat);
+    ValueTypeActions.setTypeAction(MVT::f16, Promote);
   }
 
   // Loop over all of the vector value types to see which need transformations.
   for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
        i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
     MVT VT = (MVT::SimpleValueType) i;
     if (isTypeLegal(VT))
       continue;
 
     MVT EltVT = VT.getVectorElementType();
     unsigned NElts = VT.getVectorNumElements();
     bool IsLegalWiderType = false;
-    LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
+    LegalizeAction PreferredAction = getPreferredVectorAction(VT);
     switch (PreferredAction) {
-    case TypePromoteInteger: {
+    case Promote: {
       // Try to promote the elements of integer vectors. If no legal
       // promotion was found, fall through to the widen-vector method.
       for (unsigned nVT = i + 1; nVT <= MVT::LAST_INTEGER_VECTOR_VALUETYPE; ++nVT) {
         MVT SVT = (MVT::SimpleValueType) nVT;
         // Promote vectors of integers to vectors with the same number
         // of elements, with a wider element type.
         if (SVT.getScalarSizeInBits() > EltVT.getSizeInBits() &&
             SVT.getVectorNumElements() == NElts && isTypeLegal(SVT)) {
           TransformToType[i] = SVT;
           RegisterTypeForVT[i] = SVT;
           NumRegistersForVT[i] = 1;
-          ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
+          ValueTypeActions.setTypeAction(VT, Promote);
           IsLegalWiderType = true;
           break;
         }
       }
       if (IsLegalWiderType)
         break;
     }
-    case TypeWidenVector: {
+    case WidenVector: {
       // Try to widen the vector.
       for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
         MVT SVT = (MVT::SimpleValueType) nVT;
         if (SVT.getVectorElementType() == EltVT
             && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) {
           TransformToType[i] = SVT;
           RegisterTypeForVT[i] = SVT;
           NumRegistersForVT[i] = 1;
-          ValueTypeActions.setTypeAction(VT, TypeWidenVector);
+          ValueTypeActions.setTypeAction(VT, WidenVector);
           IsLegalWiderType = true;
           break;
         }
       }
       if (IsLegalWiderType)
         break;
     }
-    case TypeSplitVector:
-    case TypeScalarizeVector: {
+    case SplitVector:
+    case ScalarizeVector: {
       MVT IntermediateVT;
       MVT RegisterVT;
       unsigned NumIntermediates;
       NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT,
           NumIntermediates, RegisterVT, this);
       RegisterTypeForVT[i] = RegisterVT;
 
       MVT NVT = VT.getPow2VectorType();
       if (NVT == VT) {
         // Type is already a power of 2.  The default action is to split.
         TransformToType[i] = MVT::Other;
-        if (PreferredAction == TypeScalarizeVector)
-          ValueTypeActions.setTypeAction(VT, TypeScalarizeVector);
-        else if (PreferredAction == TypeSplitVector)
-          ValueTypeActions.setTypeAction(VT, TypeSplitVector);
+        if (PreferredAction == ScalarizeVector)
+          ValueTypeActions.setTypeAction(VT, ScalarizeVector);
+        else if (PreferredAction == SplitVector)
+          ValueTypeActions.setTypeAction(VT, SplitVector);
         else
           // Set type action according to the number of elements.
-          ValueTypeActions.setTypeAction(VT, NElts == 1 ? TypeScalarizeVector
-                                                        : TypeSplitVector);
+          ValueTypeActions.setTypeAction(VT, NElts == 1 ? ScalarizeVector
+                                                        : SplitVector);
       } else {
         TransformToType[i] = NVT;
-        ValueTypeActions.setTypeAction(VT, TypeWidenVector);
+        ValueTypeActions.setTypeAction(VT, WidenVector);
       }
       break;
     }
     default:
       llvm_unreachable("Unknown vector legalization action!");
     }
   }
 
unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
                                                 MVT &RegisterVT) const {
   unsigned NumElts = VT.getVectorNumElements();
 
   // If there is a wider vector type with the same element type as this one,
   // or a promoted vector type that has the same number of elements which
   // are wider, then we should convert to that legal vector type.
   // This handles things like <2 x float> -> <4 x float> and
   // <4 x i1> -> <4 x i32>.
-  LegalizeTypeAction TA = getTypeAction(Context, VT);
-  if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
+  LegalizeAction TA = getTypeAction(Context, VT);
+  if (NumElts != 1 && (TA == WidenVector || TA == Promote)) {
     EVT RegisterEVT = getTypeToTransformTo(Context, VT);
     if (isTypeLegal(RegisterEVT)) {
       IntermediateVT = RegisterEVT;
       RegisterVT = RegisterEVT.getSimpleVT();
       NumIntermediates = 1;
       return 1;
     }
   }
TargetLoweringBase::getTypeLegalizationCost(const DataLayout &DL,
 
   int Cost = 1;
   // We keep legalizing the type until we find a legal kind. We assume that
   // the only operation that costs anything is the split. After splitting
   // we need to handle two types.
   while (true) {
     LegalizeKind LK = getTypeConversion(C, MTy);
 
-    if (LK.first == TypeLegal)
+    if (LK.first == Legal)
       return std::make_pair(Cost, MTy.getSimpleVT());
 
-    if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
+    if (LK.first == SplitVector || LK.first == Expand)
       Cost *= 2;
 
     // Do not loop with f128 type.
     if (MTy == LK.second)
       return std::make_pair(Cost, MTy.getSimpleVT());
 
     // Keep legalizing the type.
     MTy = LK.second;

lib/Target/AArch64/AArch64ISelLowering.h

public:
   shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
   bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
   TargetLoweringBase::AtomicExpansionKind
   shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
 
   bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
 
   bool useLoadStackGuardNode() const override;
-  TargetLoweringBase::LegalizeTypeAction
+  TargetLoweringBase::LegalizeAction
   getPreferredVectorAction(EVT VT) const override;
 
   /// If the target has a standard location for the stack protector cookie,
   /// returns the address of that location. Otherwise, returns nullptr.
   Value *getIRStackGuard(IRBuilder<> &IRB) const override;
 
   /// If the target has a standard location for the unsafe stack pointer,
   /// returns the address of that location. Otherwise, returns nullptr.

lib/Target/AArch64/AArch64ISelLowering.cpp

void AArch64TargetLowering::LowerAsmOperandForConstraint(
 
   return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
 }
 
 //===----------------------------------------------------------------------===//
 //                     AArch64 Advanced SIMD Support
 //===----------------------------------------------------------------------===//
 
-/// WidenVector - Given a value in the V64 register class, produce the
+/// Given a value in the V64 register class, produce the
 /// equivalent value in the V128 register class.
-static SDValue WidenVector(SDValue V64Reg, SelectionDAG &DAG) {
+static SDValue CreateWidenedVector(SDValue V64Reg, SelectionDAG &DAG) {
   EVT VT = V64Reg.getValueType();
   unsigned NarrowSize = VT.getVectorNumElements();
   MVT EltTy = VT.getVectorElementType().getSimpleVT();
   MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
   SDLoc DL(V64Reg);
 
   return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy),
                      V64Reg, DAG.getConstant(0, DL, MVT::i32));
case OP_VDUP3: {
     else if (EltTy == MVT::i32 || EltTy == MVT::f32)
       Opcode = AArch64ISD::DUPLANE32;
     else if (EltTy == MVT::i64 || EltTy == MVT::f64)
       Opcode = AArch64ISD::DUPLANE64;
     else
       llvm_unreachable("Invalid vector element type?");
 
     if (VT.getSizeInBits() == 64)
-      OpLHS = WidenVector(OpLHS, DAG);
+      OpLHS = CreateWidenedVector(OpLHS, DAG);
     SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, dl, MVT::i64);
     return DAG.getNode(Opcode, dl, VT, OpLHS, Lane);
   }
   case OP_VEXT1:
   case OP_VEXT2:
   case OP_VEXT3: {
     unsigned Imm = (OpNum - OP_VEXT1 + 1) * getExtFactor(OpLHS);
     return DAG.getNode(AArch64ISD::EXT, dl, VT, OpLHS, OpRHS,
if (V1.getOpcode() == ISD::BUILD_VECTOR &&
         !isa<ConstantSDNode>(V1.getOperand(Lane)))
       return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane));
 
     // Otherwise, duplicate from the lane of the input vector.
     unsigned Opcode = getDUPLANEOp(V1.getValueType().getVectorElementType());
 
     // SelectionDAGBuilder may have "helpfully" already extracted or conatenated
     // to make a vector of the same size as this SHUFFLE. We can ignore the
-    // extract entirely, and canonicalise the concat using WidenVector.
+    // extract entirely, and canonicalise the concat using CreateWidenedVector.
     if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
       Lane += cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue();
       V1 = V1.getOperand(0);
     } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) {
       unsigned Idx = Lane >= (int)VT.getVectorNumElements() / 2;
       Lane -= Idx * VT.getVectorNumElements() / 2;
-      V1 = WidenVector(V1.getOperand(Idx), DAG);
+      V1 = CreateWidenedVector(V1.getOperand(Idx), DAG);
     } else if (VT.getSizeInBits() == 64)
-      V1 = WidenVector(V1, DAG);
+      V1 = CreateWidenedVector(V1, DAG);
 
     return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, dl, MVT::i64));
   }
 
   if (isREVMask(ShuffleMask, VT, 64))
     return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2);
   if (isREVMask(ShuffleMask, VT, 32))
     return DAG.getNode(AArch64ISD::REV32, dl, V1.getValueType(), V1, V2);
if (!isConstant) {
         return DAG.getNode(AArch64ISD::DUP, dl, VT, Value);
 
       // This is actually a DUPLANExx operation, which keeps everything vectory.
 
       // DUPLANE works on 128-bit vectors, widen it if necessary.
       SDValue Lane = Value.getOperand(1);
       Value = Value.getOperand(0);
       if (Value.getValueSizeInBits() == 64)
-        Value = WidenVector(Value, DAG);
+        Value = CreateWidenedVector(Value, DAG);
 
       unsigned Opcode = getDUPLANEOp(VT.getVectorElementType());
       return DAG.getNode(Opcode, dl, VT, Value, Lane);
     }
 
     if (VT.getVectorElementType().isFloatingPoint()) {
       SmallVector<SDValue, 8> Ops;
       EVT EltTy = VT.getVectorElementType();
SDValue AArch64TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
 
   if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
       VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
     return SDValue();
 
   // For V64 types, we perform insertion by expanding the value
   // to a V128 type and perform the insertion on that.
   SDLoc DL(Op);
-  SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
+  SDValue WideVec = CreateWidenedVector(Op.getOperand(0), DAG);
   EVT WideTy = WideVec.getValueType();
 
   SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec,
                              Op.getOperand(1), Op.getOperand(2));
   // Re-narrow the resultant vector.
   return NarrowVector(Node, DAG);
 }
 
AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
 
   if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
       VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
     return SDValue();
 
   // For V64 types, we perform extraction by expanding the value
   // to a V128 type and perform the extraction on that.
   SDLoc DL(Op);
-  SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
+  SDValue WideVec = CreateWidenedVector(Op.getOperand(0), DAG);
   EVT WideTy = WideVec.getValueType();
 
   EVT ExtrTy = WideTy.getVectorElementType();
   if (ExtrTy == MVT::i16 || ExtrTy == MVT::i8)
     ExtrTy = MVT::i32;
 
   // For extractions, we just return the result directly.
   return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtrTy, WideVec,
static SDValue performConcatVectorsCombine(SDNode *N,
   if (DCI.isBeforeLegalizeOps())
     return SDValue();
 
   // If we see a (concat_vectors (v1x64 A), (v1x64 A)) it's really a vector
   // splat. The indexed instructions are going to be expecting a DUPLANE64, so
   // canonicalise to that.
   if (N0 == N1 && VT.getVectorNumElements() == 2) {
     assert(VT.getScalarSizeInBits() == 64);
-    return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT, WidenVector(N0, DAG),
+    return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT, CreateWidenedVector(N0, DAG),
                        DAG.getConstant(0, dl, MVT::i64));
   }
 
   // Canonicalise concat_vectors so that the right-hand vector has as few
   // bit-casts as possible before its real operation. The primary matching
   // destination for these operations will be the narrowing "2" instructions,
   // which depend on the operation being performed on this right-hand vector.
   // For example,

 }
 
 unsigned AArch64TargetLowering::combineRepeatedFPDivisors() const {
   // Combine multiple FDIVs with the same divisor into multiple FMULs by the
   // reciprocal if there are three or more FDIVs.
   return 3;
 }
 
-TargetLoweringBase::LegalizeTypeAction
+TargetLoweringBase::LegalizeAction
 AArch64TargetLowering::getPreferredVectorAction(EVT VT) const {
   MVT SVT = VT.getSimpleVT();
   // During type legalization, we prefer to widen v1i8, v1i16, v1i32  to v8i8,
   // v4i16, v2i32 instead of to promote.
   if (SVT == MVT::v1i8 || SVT == MVT::v1i16 || SVT == MVT::v1i32
       || SVT == MVT::v1f32)
-    return TypeWidenVector;
+    return WidenVector;
 
   return TargetLoweringBase::getPreferredVectorAction(VT);
 }
 
 // Loads and stores less than 128-bits are already atomic; ones above that
 // are doomed anyway, so defer to the default libcall and blame the OS when
 // things go wrong.
 bool AArch64TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {

lib/Target/AMDGPU/SIISelLowering.h

EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
                           bool MemcpyStrSrc,
                           MachineFunction &MF) const override;
 
   bool isMemOpUniform(const SDNode *N) const;
   bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const;
   bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
   bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
 
-  TargetLoweringBase::LegalizeTypeAction
+  TargetLoweringBase::LegalizeAction
   getPreferredVectorAction(EVT VT) const override;
 
   bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
                                         Type *Ty) const override;
 
   bool isTypeDesirableForOp(unsigned Op, EVT VT) const override;
 
   bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;

lib/Target/AMDGPU/SIISelLowering.cpp

bool SITargetLowering::isMemOpUniform(const SDNode *N) const {
   if (!Ptr || isa<UndefValue>(Ptr) || isa<Argument>(Ptr) ||
       isa<Constant>(Ptr) || isa<GlobalValue>(Ptr))
     return true;
 
   const Instruction *I = dyn_cast<Instruction>(Ptr);
   return I && I->getMetadata("amdgpu.uniform");
 }
 
-TargetLoweringBase::LegalizeTypeAction
+TargetLoweringBase::LegalizeAction
 SITargetLowering::getPreferredVectorAction(EVT VT) const {
   if (VT.getVectorNumElements() != 1 && VT.getScalarType().bitsLE(MVT::i16))
-    return TypeSplitVector;
+    return SplitVector;
 
   return TargetLoweringBase::getPreferredVectorAction(VT);
 }
 
 bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
                                                          Type *Ty) const {
   // FIXME: Could be smarter if called for vector constants.
   return true;

lib/Target/NVPTX/NVPTXISelLowering.h

public:
 
   const NVPTXTargetMachine *nvTM;
 
   // PTX always uses 32-bit shift amounts
   MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
     return MVT::i32;
   }
 
-  TargetLoweringBase::LegalizeTypeAction
+  TargetLoweringBase::LegalizeAction
   getPreferredVectorAction(EVT VT) const override;
 
   bool allowFMA(MachineFunction &MF, CodeGenOpt::Level OptLevel) const;
 
   bool isFMAFasterThanFMulAndFAdd(EVT) const override { return true; }
 
   bool enableAggressiveFMAFusion(EVT VT) const override { return true; }
 

lib/Target/NVPTX/NVPTXISelLowering.cpp

const char *NVPTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
   case NVPTXISD::Suld3DV2I64Zero:       return "NVPTXISD::Suld3DV2I64Zero";
   case NVPTXISD::Suld3DV4I8Zero:        return "NVPTXISD::Suld3DV4I8Zero";
   case NVPTXISD::Suld3DV4I16Zero:       return "NVPTXISD::Suld3DV4I16Zero";
   case NVPTXISD::Suld3DV4I32Zero:       return "NVPTXISD::Suld3DV4I32Zero";
   }
   return nullptr;
 }
 
-TargetLoweringBase::LegalizeTypeAction
+TargetLoweringBase::LegalizeAction
 NVPTXTargetLowering::getPreferredVectorAction(EVT VT) const {
   if (VT.getVectorNumElements() != 1 && VT.getScalarType() == MVT::i1)
-    return TypeSplitVector;
+    return SplitVector;
 
   return TargetLoweringBase::getPreferredVectorAction(VT);
 }
 
 SDValue
 NVPTXTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
   SDLoc dl(Op);
   const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();

lib/Target/PowerPC/PPCISelLowering.h

public:
     /// getPreferredVectorAction - The code we generate when vector types are
     /// legalized by promoting the integer element type is often much worse
     /// than code we generate if we widen the type for applicable vector types.
     /// The issue with promoting is that the vector is scalaraized, individual
     /// elements promoted and then the vector is rebuilt. So say we load a pair
     /// of v4i8's and shuffle them. This will turn into a mess of 8 extending
     /// loads, moves back into VSR's (or memory ops if we don't have moves) and
     /// then the VPERM for the shuffle. All in all a very slow sequence.
-    TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT)
+    TargetLoweringBase::LegalizeAction getPreferredVectorAction(EVT VT)
       const override {
       if (VT.getScalarSizeInBits() % 8 == 0)
-        return TypeWidenVector;
+        return WidenVector;
       return TargetLoweringBase::getPreferredVectorAction(VT);
     }
     bool useSoftFloat() const override;
 
     MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
       return MVT::i32;
     }
 

lib/Target/SystemZ/SystemZISelLowering.h

public:
   MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
     return MVT::i32;
   }
   MVT getVectorIdxTy(const DataLayout &DL) const override {
     // Only the lower 12 bits of an element index are used, so we don't
     // want to clobber the upper 32 bits of a GPR unnecessarily.
     return MVT::i32;
   }
-  TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT)
+  TargetLoweringBase::LegalizeAction getPreferredVectorAction(EVT VT)
     const override {
     // Widen subvectors to the full width rather than promoting integer
     // elements.  This is better because:
     //
     // (a) it means that we can handle the ABI for passing and returning
     //     sub-128 vectors without having to handle them as legal types.
     //
     // (b) we don't have instructions to extend on load and truncate on store,
     //     so promoting the integers is less efficient.
     //
     // (c) there are no multiplication instructions for the widest integer
     //     type (v2i64).
     if (VT.getScalarSizeInBits() % 8 == 0)
-      return TypeWidenVector;
+      return WidenVector;
     return TargetLoweringBase::getPreferredVectorAction(VT);
   }
   EVT getSetCCResultType(const DataLayout &DL, LLVMContext &,
                          EVT) const override;
   bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
   bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
   bool isLegalICmpImmediate(int64_t Imm) const override;
   bool isLegalAddImmediate(int64_t Imm) const override;

lib/Target/X86/X86ISelLowering.h

public:
     Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const override;
 
     SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
                       SelectionDAG &DAG) const;
 
     bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
 
     /// \brief Customize the preferred legalization strategy for certain types.
-    LegalizeTypeAction getPreferredVectorAction(EVT VT) const override;
+    LegalizeAction getPreferredVectorAction(EVT VT) const override;
 
     bool isIntDivCheap(EVT VT, AttributeSet Attr) const override;
 
     bool supportSwiftError() const override;
 
     unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
 
     /// \brief Lower interleaved load(s) into target specific

lib/Target/X86/X86ISelLowering.cpp

X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
   // We don't support FMA.
   setOperationAction(ISD::FMA, MVT::f64, Expand);
   setOperationAction(ISD::FMA, MVT::f32, Expand);
 
   // Long double always uses X87, except f128 in MMX.
   if (UseX87) {
     if (Subtarget.is64Bit() && Subtarget.hasMMX()) {
       addRegisterClass(MVT::f128, &X86::FR128RegClass);
-      ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
+      ValueTypeActions.setTypeAction(MVT::f128, SoftenFloat);
       setOperationAction(ISD::FABS , MVT::f128, Custom);
       setOperationAction(ISD::FNEG , MVT::f128, Custom);
       setOperationAction(ISD::FCOPYSIGN, MVT::f128, Custom);
     }
 
     addRegisterClass(MVT::f80, &X86::RFP80RegClass);
     setOperationAction(ISD::UNDEF,     MVT::f80, Expand);
     setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);

   verifyIntrinsicTables();
 }
 
 // This has so far only been implemented for 64-bit MachO.
 bool X86TargetLowering::useLoadStackGuardNode() const {
   return Subtarget.isTargetMachO() && Subtarget.is64Bit();
 }
 
-TargetLoweringBase::LegalizeTypeAction
+TargetLoweringBase::LegalizeAction
 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
   if (ExperimentalVectorWideningLegalization &&
       VT.getVectorNumElements() != 1 &&
       VT.getVectorElementType().getSimpleVT() != MVT::i1)
-    return TypeWidenVector;
+    return WidenVector;
 
   return TargetLoweringBase::getPreferredVectorAction(VT);
 }
 
 EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL,
                                           LLVMContext& Context,
                                           EVT VT) const {
   if (!VT.isVector())
if (VVT.is512BitVector()) {
           case 32: return MVT::v32i1;
           case 64: return MVT::v64i1;
         }
     }
 
     if (Subtarget.hasBWI() && Subtarget.hasVLX())
       return MVT::getVectorVT(MVT::i1, NumElts);
 
-    if (!isTypeLegal(VT) && getTypeAction(Context, VT) == TypePromoteInteger) {
+    if (!isTypeLegal(VT) && VT.isInteger() &&
+        getTypeAction(Context, VT) == Promote) {
       EVT LegalVT = getTypeToTransformTo(Context, VT);
       EltVT = LegalVT.getVectorElementType().getSimpleVT();
     }
 
     if (Subtarget.hasVLX() && EltVT.getSizeInBits() >= 32)
       switch(NumElts) {
       case 2: return MVT::v2i1;
       case 4: return MVT::v4i1;