[ARM] GlobalISel: Allow i16 and i8 adds

[rovka]

Summary

This allows i8 and i16 adds, as well as lowering of i8 and i16 function
arguments. Note however that the lowering is incomplete - ABI extensions are
handled in a subsequent patch.

[t.p.northover]

This one also looks like 2 patches really (select more COPY cases, support more args), though again both pretty sensible.

lib/Target/ARM/ARMCallLowering.cpp

36 ↗

(On Diff #81197)

Checking against vectors is probably good here, since you're changing it anyway. Somewhat surprisingly isInteger returns true for them.

llvm/trunk/lib/Target/ARM/ARMCallLowering.cpp

 #endif
 
 ARMCallLowering::ARMCallLowering(const ARMTargetLowering &TLI)
     : CallLowering(&TLI) {}
 
 static bool isSupportedType(const DataLayout DL, const ARMTargetLowering &TLI,
                             Type *T) {
   EVT VT = TLI.getValueType(DL, T);
-  return VT.isSimple() && VT.isInteger() &&
-         VT.getSimpleVT().getSizeInBits() == 32;
+  if (!VT.isSimple() || !VT.isInteger() || VT.isVector())
+    return false;
+
+  unsigned VTSize = VT.getSimpleVT().getSizeInBits();
+  return VTSize == 8 || VTSize == 16 || VTSize == 32;
 }
 
 namespace {
 struct FuncReturnHandler : public CallLowering::ValueHandler {
   FuncReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
                     MachineInstrBuilder &MIB)
       : ValueHandler(MIRBuilder, MRI), MIB(MIB) {}
 
   unsigned getStackAddress(uint64_t Size, int64_t Offset,
                            MachinePointerInfo &MPO) override {
     llvm_unreachable("Don't know how to get a stack address yet");
   }
 
   void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
                         CCValAssign &VA) override {
     assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
     assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
 
-    assert(VA.getValVT().getSizeInBits() == 32 && "Unsupported value size");
+    assert(VA.getValVT().getSizeInBits() <= 32 && "Unsupported value size");
     assert(VA.getLocVT().getSizeInBits() == 32 && "Unsupported location size");
 
+    assert(VA.getLocInfo() != CCValAssign::SExt &&
+           VA.getLocInfo() != CCValAssign::ZExt &&
+           "ABI extensions not supported yet");
+
     MIRBuilder.buildCopy(PhysReg, ValVReg);
     MIB.addUse(PhysReg, RegState::Implicit);
   }
 
   void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
                             MachinePointerInfo &MPO, CCValAssign &VA) override {
     llvm_unreachable("Don't know how to assign a value to an address yet");
   }
void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
     MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
   }
 
   void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
                         CCValAssign &VA) override {
     assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
     assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
 
-    assert(VA.getValVT().getSizeInBits() == 32 && "Unsupported value size");
+    assert(VA.getValVT().getSizeInBits() <= 32 && "Unsupported value size");
     assert(VA.getLocVT().getSizeInBits() == 32 && "Unsupported location size");
 
     MIRBuilder.getMBB().addLiveIn(PhysReg);
     MIRBuilder.buildCopy(ValVReg, PhysReg);
   }
 };
 } // End anonymous namespace
 
 bool ARMCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
                                            const Function &F,
                                            ArrayRef<unsigned> VRegs) const {
   // Quick exit if there aren't any args
   if (F.arg_empty())
     return true;
 
   if (F.isVarArg())
     return false;
 
   auto DL = MIRBuilder.getMF().getDataLayout();
   auto &TLI = *getTLI<ARMTargetLowering>();
 
   auto &Args = F.getArgumentList();
-  for (auto &Arg : Args)
+  unsigned ArgIdx = 0;
+  for (auto &Arg : Args) {
+    ArgIdx++;
     if (!isSupportedType(DL, TLI, Arg.getType()))
       return false;
 
+    // FIXME: This check as well as ArgIdx are going away as soon as we support
+    // loading values < 32 bits.
+    if (ArgIdx > 4 && Arg.getType()->getIntegerBitWidth() != 32)
+      return false;
+  }
+
   CCAssignFn *AssignFn =
       TLI.CCAssignFnForCall(F.getCallingConv(), F.isVarArg());
 
   SmallVector<ArgInfo, 8> ArgInfos;
   unsigned Idx = 0;
   for (auto &Arg : Args) {
     ArgInfo AInfo(VRegs[Idx], Arg.getType());
     setArgFlags(AInfo, Idx + 1, DL, F);
     ArgInfos.push_back(AInfo);
     Idx++;
   }
 
   FormalArgHandler ArgHandler(MIRBuilder, MIRBuilder.getMF().getRegInfo());
   return handleAssignments(MIRBuilder, AssignFn, ArgInfos, ArgHandler);
 }

llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll

 ; RUN: llc -mtriple arm-unknown -global-isel -stop-after=irtranslator %s -o - | FileCheck %s
 
 define void @test_void_return() {
 ; CHECK-LABEL: name: test_void_return
 ; CHECK: BX_RET 14, _
 entry:
   ret void
 }
 
-define i32 @test_add(i32 %x, i32 %y) {
-; CHECK-LABEL: name: test_add
+define i8 @test_add_i8(i8 %x, i8 %y) {
+; CHECK-LABEL: name: test_add_i8
 ; CHECK: liveins: %r0, %r1
-; CHECK: [[VREGX:%[0-9]+]]{{.*}} = COPY %r0
-; CHECK: [[VREGY:%[0-9]+]]{{.*}} = COPY %r1
-; CHECK: [[SUM:%[0-9]+]]{{.*}} = G_ADD [[VREGX]], [[VREGY]]
-; CHECK: %r0 = COPY [[SUM]]
+; CHECK-DAG: [[VREGX:%[0-9]+]](s8) = COPY %r0
+; CHECK-DAG: [[VREGY:%[0-9]+]](s8) = COPY %r1
+; CHECK: [[SUM:%[0-9]+]](s8) = G_ADD [[VREGX]], [[VREGY]]
+; CHECK: %r0 = COPY [[SUM]](s8)
+; CHECK: BX_RET 14, _, implicit %r0
+entry:
+  %sum = add i8 %x, %y
+  ret i8 %sum
+}
+
+define i16 @test_add_i16(i16 %x, i16 %y) {
+; CHECK-LABEL: name: test_add_i16
+; CHECK: liveins: %r0, %r1
+; CHECK-DAG: [[VREGX:%[0-9]+]](s16) = COPY %r0
+; CHECK-DAG: [[VREGY:%[0-9]+]](s16) = COPY %r1
+; CHECK: [[SUM:%[0-9]+]](s16) = G_ADD [[VREGX]], [[VREGY]]
+; CHECK: %r0 = COPY [[SUM]](s16)
+; CHECK: BX_RET 14, _, implicit %r0
+entry:
+  %sum = add i16 %x, %y
+  ret i16 %sum
+}
+
+define i32 @test_add_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: name: test_add_i32
+; CHECK: liveins: %r0, %r1
+; CHECK-DAG: [[VREGX:%[0-9]+]](s32) = COPY %r0
+; CHECK-DAG: [[VREGY:%[0-9]+]](s32) = COPY %r1
+; CHECK: [[SUM:%[0-9]+]](s32) = G_ADD [[VREGX]], [[VREGY]]
+; CHECK: %r0 = COPY [[SUM]](s32)
 ; CHECK: BX_RET 14, _, implicit %r0
 entry:
   %sum = add i32 %x, %y
   ret i32 %sum
 }
 
 define i32 @test_many_args(i32 %p0, i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5) {
 ; CHECK-LABEL: name: test_many_args

llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-isel.ll

 ; RUN: llc -mtriple arm-unknown -global-isel %s -o - | FileCheck %s
 
 define void @test_void_return() {
 ; CHECK-LABEL: test_void_return:
 ; CHECK: bx lr
 entry:
   ret void
 }
 
-define i32 @test_add(i32 %x, i32 %y) {
-; CHECK-LABEL: test_add:
+define i8 @test_add_i8(i8 %x, i8 %y) {
+; CHECK-LABEL: test_add_i8:
+; CHECK: add r0, r0, r1
+; CHECK: bx lr
+entry:
+  %sum = add i8 %x, %y
+  ret i8 %sum
+}
+
+define i16 @test_add_i16(i16 %x, i16 %y) {
+; CHECK-LABEL: test_add_i16:
+; CHECK: add r0, r0, r1
+; CHECK: bx lr
+entry:
+  %sum = add i16 %x, %y
+  ret i16 %sum
+}
+
+define i32 @test_add_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: test_add_i32:
 ; CHECK: add r0, r0, r1
 ; CHECK: bx lr
 entry:
   %sum = add i32 %x, %y
   ret i32 %sum
 }
 
 define i32 @test_many_args(i32 %p0, i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5) {