[SDAG] Add SimplifyDemandedBits support for ISD::SPLAT_VECTOR_PARTS

[luke]

Summary

Similar to https://reviews.llvm.org/D158839, this allows some shift and rotate
operations on RV32 to better select an immediate or scalar operand, due to the
upper bits of the splat being marked as undef.

[craig.topper]

llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll

644

This looks like what we really have is a missing combine on trunc of splat_vector.

644

Not objecting to this patch just that it might not show the proper motivation.

[luke]

llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll

644

Is the combine you're referring to something like:

      t4: i32,ch = CopyFromReg t0, Register:i32 %1
      t6: i32,ch = CopyFromReg t0, Register:i32 %2
    t8: i64 = build_pair t4, t6
  t11: nxv1i64 = splat_vector t8
t13: nxv1i32 = truncate t11

to

      t4: i32,ch = CopyFromReg t0, Register:i32 %1
t13: nxv1i32 = splat_vector t4

And not on splat_vector_parts after legalisation?

[craig.topper]

llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll

644

Do we already have a combine for truncate of build_pair?

From a quick glance, I see that we do convert (truncate (build_vector X, Y, Z)) to (build_vector (trunc X), (trunc Y), (trunc Z)). here.

// Attempt to pre-truncate BUILD_VECTOR sources.                               
if (N0.getOpcode() == ISD::BUILD_VECTOR && !LegalOperations &&                 
    TLI.isTruncateFree(SrcVT.getScalarType(), VT.getScalarType()) &&           
    // Avoid creating illegal types if running after type legalizer.           
    (!LegalTypes || TLI.isTypeLegal(VT.getScalarType()))) {                    
  SDLoc DL(N);                                                                 
  EVT SVT = VT.getScalarType();                                                
  SmallVector<SDValue, 8> TruncOps;                                            
  for (const SDValue &Op : N0->op_values()) {                                  
    SDValue TruncOp = DAG.getNode(ISD::TRUNCATE, DL, SVT, Op);                 
    TruncOps.push_back(TruncOp);                                               
  }                                                                            
  return DAG.getBuildVector(VT, DL, TruncOps);                                 
}

Maybe we should do the same for splat_vector?

[reames]

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

1168

I think Scl is short for Scalar? If so, just write it. Scl isn't a common abbreviation.

llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll

644

I agree with Craig here. We definitely should have a trunc(splat) to splat(trunc) transform. If we don't already, we should fix that.

To be clear, this patch can be landed. You need to add a bit more test coverage for cases which *aren't* truncates so that once the other patch lands we still have test coverage for this code, but that's about the only thing missing.

Or said differently, Craig and I are suggesting *additional* work, not *alternative* work.

[luke]

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

1168

Yeah I had never seen this abbreviation before, but it's what's used in the rest of this function so I just chose it for consistency. Happy to expand it if preferred, I'm not strongly opinionated.

llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll

644

I'm in agreement too here, happy to submit a patch for that.

[luke]

Rebase on top of new test cases

[luke]

llvm/test/CodeGen/RISCV/rvv/splat-vector-split-i64-vl-sdnode.ll

117 ↗

(On Diff #555119)

This a0 is actually undef, it's just selected by coincidence because there's no combine after RISCVDAGToDAGISel::PreprocessISelDAG to remove the store of undef. Might it be worthwhile short-circuiting a store of undef directly in SelectionDAG::getStore?

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

case ISD::SPLAT_VECTOR: {
     if (SimplifyDemandedBits(Scl, DemandedSclBits, KnownScl, TLO, Depth + 1))
       return true;
 
     // Implicitly truncate the bits to match the official semantics of
     // SPLAT_VECTOR.
     Known = KnownScl.trunc(BitWidth);
     break;
   }
+  case ISD::SPLAT_VECTOR_PARTS: {
+    unsigned NumSclBits = Op.getOperand(0).getScalarValueSizeInBits();
+    assert(NumSclBits * Op.getNumOperands() == BitWidth &&
+           "Expected SPLAT_VECTOR_PARTS scalars to cover element width");
+    for (auto [I, Scl] : enumerate(Op->ops())) {
+      APInt DemandedSclBits =
+          DemandedBits.extractBits(NumSclBits, NumSclBits * I);
+      KnownBits KnownScl;
+      if (SimplifyDemandedBits(Scl, DemandedSclBits, KnownScl, TLO, Depth + 1))
+        return true;
+      Known.insertBits(KnownScl, NumSclBits * I);
+    }
+    break;
+  }
   case ISD::LOAD: {
     auto *LD = cast<LoadSDNode>(Op);
     if (getTargetConstantFromLoad(LD)) {
       Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth);
       return false; // Don't fall through, will infinitely loop.
     }
     if (ISD::isZEXTLoad(Op.getNode()) && Op.getResNo() == 0) {
       // If this is a ZEXTLoad and we are looking at the loaded value.

llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll

; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
   %vb = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
   %x = lshr <vscale x 8 x i64> %va, %vb
   %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
   ret <vscale x 8 x i32> %y
 }
 
 define <vscale x 1 x i16> @vnsrl_wx_i64_nxv1i16(<vscale x 1 x i32> %va, i64 %b) {
-; RV32-LABEL: vnsrl_wx_i64_nxv1i16:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
-; RV32-NEXT:    vlse64.v v9, (a0), zero
-; RV32-NEXT:    vnsrl.wi v9, v9, 0
-; RV32-NEXT:    vsrl.vv v8, v8, v9
-; RV32-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
-; RV32-NEXT:    vnsrl.wi v8, v8, 0
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vnsrl_wx_i64_nxv1i16:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
-; RV64-NEXT:    vnsrl.wx v8, v8, a0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vnsrl_wx_i64_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
+; CHECK-NEXT:    vnsrl.wx v8, v8, a0
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
   %vb = trunc <vscale x 1 x i64> %splat to <vscale x 1 x i32>
   %x = lshr <vscale x 1 x i32> %va, %vb
   %y = trunc <vscale x 1 x i32> %x to <vscale x 1 x i16>
   ret <vscale x 1 x i16> %y
 }
 
 define <vscale x 1 x i8> @vnsrl_wx_i64_nxv1i8(<vscale x 1 x i16> %va, i64 %b) {
-; RV32-LABEL: vnsrl_wx_i64_nxv1i8:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
-; RV32-NEXT:    vlse64.v v9, (a0), zero
-; RV32-NEXT:    vnsrl.wi v9, v9, 0
-; RV32-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
-; RV32-NEXT:    vnsrl.wi v9, v9, 0
-; RV32-NEXT:    vsrl.vv v8, v8, v9
-; RV32-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
-; RV32-NEXT:    vnsrl.wi v8, v8, 0
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vnsrl_wx_i64_nxv1i8:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
-; RV64-NEXT:    vnsrl.wx v8, v8, a0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vnsrl_wx_i64_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
+; CHECK-NEXT:    vnsrl.wx v8, v8, a0
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
   %vb = trunc <vscale x 1 x i64> %splat to <vscale x 1 x i16>
   %x = lshr <vscale x 1 x i16> %va, %vb
   %y = trunc <vscale x 1 x i16> %x to <vscale x 1 x i8>
   ret <vscale x 1 x i8> %y
 }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; RV32: {{.*}}
+; RV64: {{.*}}

llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll

 ; CHECK-ZVBB-NEXT:    ret
   %x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>
   %y = zext <vscale x 4 x i16> %b to <vscale x 4 x i32>
   %z = shl <vscale x 4 x i32> %x, %y
   ret <vscale x 4 x i32> %z
 }
 
 define <vscale x 4 x i32> @vwsll_vx_i64_nxv4i32(<vscale x 4 x i16> %a, i64 %b) {
-; CHECK-RV32-LABEL: vwsll_vx_i64_nxv4i32:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    addi sp, sp, -16
-; CHECK-RV32-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-RV32-NEXT:    sw a1, 12(sp)
-; CHECK-RV32-NEXT:    sw a0, 8(sp)
-; CHECK-RV32-NEXT:    addi a0, sp, 8
-; CHECK-RV32-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
-; CHECK-RV32-NEXT:    vlse64.v v12, (a0), zero
-; CHECK-RV32-NEXT:    vzext.vf2 v10, v8
-; CHECK-RV32-NEXT:    vnsrl.wi v8, v12, 0
-; CHECK-RV32-NEXT:    vsll.vv v8, v10, v8
-; CHECK-RV32-NEXT:    addi sp, sp, 16
-; CHECK-RV32-NEXT:    ret
-;
-; CHECK-RV64-LABEL: vwsll_vx_i64_nxv4i32:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
-; CHECK-RV64-NEXT:    vmv.v.x v12, a0
-; CHECK-RV64-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
-; CHECK-RV64-NEXT:    vzext.vf2 v10, v8
-; CHECK-RV64-NEXT:    vnsrl.wi v8, v12, 0
-; CHECK-RV64-NEXT:    vsll.vv v8, v10, v8
-; CHECK-RV64-NEXT:    ret
-;
-; CHECK-ZVBB32-LABEL: vwsll_vx_i64_nxv4i32:
-; CHECK-ZVBB32:       # %bb.0:
-; CHECK-ZVBB32-NEXT:    addi sp, sp, -16
-; CHECK-ZVBB32-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-ZVBB32-NEXT:    sw a1, 12(sp)
-; CHECK-ZVBB32-NEXT:    sw a0, 8(sp)
-; CHECK-ZVBB32-NEXT:    addi a0, sp, 8
-; CHECK-ZVBB32-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
-; CHECK-ZVBB32-NEXT:    vlse64.v v12, (a0), zero
-; CHECK-ZVBB32-NEXT:    vzext.vf2 v10, v8
-; CHECK-ZVBB32-NEXT:    vnsrl.wi v8, v12, 0
-; CHECK-ZVBB32-NEXT:    vsll.vv v8, v10, v8
-; CHECK-ZVBB32-NEXT:    addi sp, sp, 16
-; CHECK-ZVBB32-NEXT:    ret
-;
-; CHECK-ZVBB64-LABEL: vwsll_vx_i64_nxv4i32:
-; CHECK-ZVBB64:       # %bb.0:
-; CHECK-ZVBB64-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
-; CHECK-ZVBB64-NEXT:    vwsll.vx v10, v8, a0
-; CHECK-ZVBB64-NEXT:    vmv2r.v v8, v10
-; CHECK-ZVBB64-NEXT:    ret
+; CHECK-LABEL: vwsll_vx_i64_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
+; CHECK-NEXT:    vmv.v.x v12, a0
+; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT:    vzext.vf2 v10, v8
+; CHECK-NEXT:    vnsrl.wi v8, v12, 0
+; CHECK-NEXT:    vsll.vv v8, v10, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vwsll_vx_i64_nxv4i32:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
+; CHECK-ZVBB-NEXT:    vwsll.vx v10, v8, a0
+; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
+; CHECK-ZVBB-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
   %x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>
   %y = trunc <vscale x 4 x i64> %splat to <vscale x 4 x i32>
   %z = shl <vscale x 4 x i32> %x, %y
   ret <vscale x 4 x i32> %z
 }
 

 ; CHECK-ZVBB-NEXT:    ret
   %x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>
   %y = zext <vscale x 8 x i8> %b to <vscale x 8 x i16>
   %z = shl <vscale x 8 x i16> %x, %y
   ret <vscale x 8 x i16> %z
 }
 
 define <vscale x 8 x i16> @vwsll_vx_i64_nxv8i16(<vscale x 8 x i8> %a, i64 %b) {
-; CHECK-RV32-LABEL: vwsll_vx_i64_nxv8i16:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    addi sp, sp, -16
-; CHECK-RV32-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-RV32-NEXT:    sw a1, 12(sp)
-; CHECK-RV32-NEXT:    sw a0, 8(sp)
-; CHECK-RV32-NEXT:    addi a0, sp, 8
-; CHECK-RV32-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
-; CHECK-RV32-NEXT:    vlse64.v v16, (a0), zero
-; CHECK-RV32-NEXT:    vzext.vf2 v10, v8
-; CHECK-RV32-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
-; CHECK-RV32-NEXT:    vnsrl.wi v12, v16, 0
-; CHECK-RV32-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-RV32-NEXT:    vnsrl.wi v8, v12, 0
-; CHECK-RV32-NEXT:    vsll.vv v8, v10, v8
-; CHECK-RV32-NEXT:    addi sp, sp, 16
-; CHECK-RV32-NEXT:    ret
-;
-; CHECK-RV64-LABEL: vwsll_vx_i64_nxv8i16:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
-; CHECK-RV64-NEXT:    vmv.v.x v16, a0
-; CHECK-RV64-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-RV64-NEXT:    vzext.vf2 v10, v8
-; CHECK-RV64-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
-; CHECK-RV64-NEXT:    vnsrl.wi v12, v16, 0
-; CHECK-RV64-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-RV64-NEXT:    vnsrl.wi v8, v12, 0
-; CHECK-RV64-NEXT:    vsll.vv v8, v10, v8
-; CHECK-RV64-NEXT:    ret
-;
-; CHECK-ZVBB32-LABEL: vwsll_vx_i64_nxv8i16:
-; CHECK-ZVBB32:       # %bb.0:
-; CHECK-ZVBB32-NEXT:    addi sp, sp, -16
-; CHECK-ZVBB32-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-ZVBB32-NEXT:    sw a1, 12(sp)
-; CHECK-ZVBB32-NEXT:    sw a0, 8(sp)
-; CHECK-ZVBB32-NEXT:    addi a0, sp, 8
-; CHECK-ZVBB32-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
-; CHECK-ZVBB32-NEXT:    vlse64.v v16, (a0), zero
-; CHECK-ZVBB32-NEXT:    vzext.vf2 v10, v8
-; CHECK-ZVBB32-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
-; CHECK-ZVBB32-NEXT:    vnsrl.wi v12, v16, 0
-; CHECK-ZVBB32-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-ZVBB32-NEXT:    vnsrl.wi v8, v12, 0
-; CHECK-ZVBB32-NEXT:    vsll.vv v8, v10, v8
-; CHECK-ZVBB32-NEXT:    addi sp, sp, 16
-; CHECK-ZVBB32-NEXT:    ret
-;
-; CHECK-ZVBB64-LABEL: vwsll_vx_i64_nxv8i16:
-; CHECK-ZVBB64:       # %bb.0:
-; CHECK-ZVBB64-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
-; CHECK-ZVBB64-NEXT:    vwsll.vx v10, v8, a0
-; CHECK-ZVBB64-NEXT:    vmv2r.v v8, v10
-; CHECK-ZVBB64-NEXT:    ret
+; CHECK-LABEL: vwsll_vx_i64_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
+; CHECK-NEXT:    vmv.v.x v16, a0
+; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT:    vzext.vf2 v10, v8
+; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT:    vnsrl.wi v12, v16, 0
+; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT:    vnsrl.wi v8, v12, 0
+; CHECK-NEXT:    vsll.vv v8, v10, v8
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVBB-LABEL: vwsll_vx_i64_nxv8i16:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
+; CHECK-ZVBB-NEXT:    vwsll.vx v10, v8, a0
+; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
+; CHECK-ZVBB-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 8 x i32> zeroinitializer
   %x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>
   %y = trunc <vscale x 8 x i64> %splat to <vscale x 8 x i16>
   %z = shl <vscale x 8 x i16> %x, %y
   ret <vscale x 8 x i16> %z
 }
 

 ; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
 ; CHECK-ZVBB-NEXT:    vwsll.vi v10, v8, 2
 ; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
 ; CHECK-ZVBB-NEXT:    ret
   %x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>
   %z = shl <vscale x 8 x i16> %x, shufflevector(<vscale x 8 x i16> insertelement(<vscale x 8 x i16> poison, i16 2, i32 0), <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer)
   ret <vscale x 8 x i16> %z
 }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK-RV32: {{.*}}
+; CHECK-RV64: {{.*}}
+; CHECK-ZVBB32: {{.*}}
+; CHECK-ZVBB64: {{.*}}

llvm/test/CodeGen/RISCV/rvv/vwsll-vp.ll

; CHECK-ZVBB-NEXT:    ret
   %y = zext <vscale x 4 x i16> %b to <vscale x 4 x i32>
   %z = call <vscale x 4 x i32> @llvm.vp.shl.nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i1> %m, i32 %vl)
   ret <vscale x 4 x i32> %z
 }
 
 define <vscale x 4 x i32> @vwsll_vx_i64_nxv4i32(<vscale x 4 x i16> %a, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %vl) {
 ; CHECK-RV32-LABEL: vwsll_vx_i64_nxv4i32:
 ; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    addi sp, sp, -16
-; CHECK-RV32-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-RV32-NEXT:    sw a1, 12(sp)
-; CHECK-RV32-NEXT:    sw a0, 8(sp)
-; CHECK-RV32-NEXT:    addi a0, sp, 8
-; CHECK-RV32-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
-; CHECK-RV32-NEXT:    vlse64.v v12, (a0), zero
+; CHECK-RV32-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
+; CHECK-RV32-NEXT:    vmv.v.x v12, a0
+; CHECK-RV32-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; CHECK-RV32-NEXT:    vzext.vf2 v10, v8
 ; CHECK-RV32-NEXT:    vnsrl.wi v8, v12, 0
 ; CHECK-RV32-NEXT:    vsetvli zero, a2, e32, m2, ta, ma
 ; CHECK-RV32-NEXT:    vsll.vv v8, v10, v8, v0.t
-; CHECK-RV32-NEXT:    addi sp, sp, 16
 ; CHECK-RV32-NEXT:    ret
 ;
 ; CHECK-RV64-LABEL: vwsll_vx_i64_nxv4i32:
 ; CHECK-RV64:       # %bb.0:
 ; CHECK-RV64-NEXT:    vsetvli a2, zero, e64, m4, ta, ma
 ; CHECK-RV64-NEXT:    vmv.v.x v12, a0
 ; CHECK-RV64-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; CHECK-RV64-NEXT:    vzext.vf2 v10, v8
 ; CHECK-RV64-NEXT:    vnsrl.wi v8, v12, 0
 ; CHECK-RV64-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
 ; CHECK-RV64-NEXT:    vsll.vv v8, v10, v8, v0.t
 ; CHECK-RV64-NEXT:    ret
 ;
 ; CHECK-ZVBB32-LABEL: vwsll_vx_i64_nxv4i32:
 ; CHECK-ZVBB32:       # %bb.0:
-; CHECK-ZVBB32-NEXT:    addi sp, sp, -16
-; CHECK-ZVBB32-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-ZVBB32-NEXT:    sw a1, 12(sp)
-; CHECK-ZVBB32-NEXT:    sw a0, 8(sp)
-; CHECK-ZVBB32-NEXT:    addi a0, sp, 8
-; CHECK-ZVBB32-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
-; CHECK-ZVBB32-NEXT:    vlse64.v v12, (a0), zero
-; CHECK-ZVBB32-NEXT:    vzext.vf2 v10, v8
-; CHECK-ZVBB32-NEXT:    vnsrl.wi v8, v12, 0
-; CHECK-ZVBB32-NEXT:    vsetvli zero, a2, e32, m2, ta, ma
-; CHECK-ZVBB32-NEXT:    vsll.vv v8, v10, v8, v0.t
-; CHECK-ZVBB32-NEXT:    addi sp, sp, 16
+; CHECK-ZVBB32-NEXT:    vsetvli zero, a2, e16, m1, ta, ma
+; CHECK-ZVBB32-NEXT:    vwsll.vx v10, v8, a0, v0.t
+; CHECK-ZVBB32-NEXT:    vmv2r.v v8, v10
 ; CHECK-ZVBB32-NEXT:    ret
 ;
 ; CHECK-ZVBB64-LABEL: vwsll_vx_i64_nxv4i32:
 ; CHECK-ZVBB64:       # %bb.0:
 ; CHECK-ZVBB64-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
 ; CHECK-ZVBB64-NEXT:    vwsll.vx v10, v8, a0, v0.t
 ; CHECK-ZVBB64-NEXT:    vmv2r.v v8, v10
 ; CHECK-ZVBB64-NEXT:    ret
; CHECK-ZVBB-NEXT:    ret
   %y = zext <vscale x 8 x i8> %b to <vscale x 8 x i16>
   %z = call <vscale x 8 x i16> @llvm.vp.shl.nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i1> %m, i32 %vl)
   ret <vscale x 8 x i16> %z
 }
 
 define <vscale x 8 x i16> @vwsll_vx_i64_nxv8i16(<vscale x 8 x i8> %a, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %vl) {
 ; CHECK-RV32-LABEL: vwsll_vx_i64_nxv8i16:
 ; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    addi sp, sp, -16
-; CHECK-RV32-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-RV32-NEXT:    sw a1, 12(sp)
-; CHECK-RV32-NEXT:    sw a0, 8(sp)
-; CHECK-RV32-NEXT:    addi a0, sp, 8
-; CHECK-RV32-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
-; CHECK-RV32-NEXT:    vlse64.v v16, (a0), zero
+; CHECK-RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
+; CHECK-RV32-NEXT:    vmv.v.x v16, a0
+; CHECK-RV32-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
 ; CHECK-RV32-NEXT:    vzext.vf2 v10, v8
 ; CHECK-RV32-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
 ; CHECK-RV32-NEXT:    vnsrl.wi v12, v16, 0
 ; CHECK-RV32-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
 ; CHECK-RV32-NEXT:    vnsrl.wi v8, v12, 0
 ; CHECK-RV32-NEXT:    vsetvli zero, a2, e16, m2, ta, ma
 ; CHECK-RV32-NEXT:    vsll.vv v8, v10, v8, v0.t
-; CHECK-RV32-NEXT:    addi sp, sp, 16
 ; CHECK-RV32-NEXT:    ret
 ;
 ; CHECK-RV64-LABEL: vwsll_vx_i64_nxv8i16:
 ; CHECK-RV64:       # %bb.0:
 ; CHECK-RV64-NEXT:    vsetvli a2, zero, e64, m8, ta, ma
 ; CHECK-RV64-NEXT:    vmv.v.x v16, a0
 ; CHECK-RV64-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
 ; CHECK-RV64-NEXT:    vzext.vf2 v10, v8
 ; CHECK-RV64-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
 ; CHECK-RV64-NEXT:    vnsrl.wi v12, v16, 0
 ; CHECK-RV64-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
 ; CHECK-RV64-NEXT:    vnsrl.wi v8, v12, 0
 ; CHECK-RV64-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
 ; CHECK-RV64-NEXT:    vsll.vv v8, v10, v8, v0.t
 ; CHECK-RV64-NEXT:    ret
 ;
 ; CHECK-ZVBB32-LABEL: vwsll_vx_i64_nxv8i16:
 ; CHECK-ZVBB32:       # %bb.0:
-; CHECK-ZVBB32-NEXT:    addi sp, sp, -16
-; CHECK-ZVBB32-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-ZVBB32-NEXT:    sw a1, 12(sp)
-; CHECK-ZVBB32-NEXT:    sw a0, 8(sp)
-; CHECK-ZVBB32-NEXT:    addi a0, sp, 8
-; CHECK-ZVBB32-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
-; CHECK-ZVBB32-NEXT:    vlse64.v v16, (a0), zero
-; CHECK-ZVBB32-NEXT:    vzext.vf2 v10, v8
-; CHECK-ZVBB32-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
-; CHECK-ZVBB32-NEXT:    vnsrl.wi v12, v16, 0
-; CHECK-ZVBB32-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-ZVBB32-NEXT:    vnsrl.wi v8, v12, 0
-; CHECK-ZVBB32-NEXT:    vsetvli zero, a2, e16, m2, ta, ma
-; CHECK-ZVBB32-NEXT:    vsll.vv v8, v10, v8, v0.t
-; CHECK-ZVBB32-NEXT:    addi sp, sp, 16
+; CHECK-ZVBB32-NEXT:    vsetvli zero, a2, e8, m1, ta, ma
+; CHECK-ZVBB32-NEXT:    vwsll.vx v10, v8, a0, v0.t
+; CHECK-ZVBB32-NEXT:    vmv2r.v v8, v10
 ; CHECK-ZVBB32-NEXT:    ret
 ;
 ; CHECK-ZVBB64-LABEL: vwsll_vx_i64_nxv8i16:
 ; CHECK-ZVBB64:       # %bb.0:
 ; CHECK-ZVBB64-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
 ; CHECK-ZVBB64-NEXT:    vwsll.vx v10, v8, a0, v0.t
 ; CHECK-ZVBB64-NEXT:    vmv2r.v v8, v10
 ; CHECK-ZVBB64-NEXT:    ret