[SDAG] Add computeKnownBits support for ISD::SPLAT_VECTOR_PARTS

[luke]

Summary

We can work out the known bits for a given lane by concatenating the known bits of each scalar operand.

In the description of ISD::SPLAT_VECTOR_PARTS in ISDOpcodes.h it says that the
total size of the scalar operands must cover the output element size, but I've
added a stricter assertion here that the total width of the scalar operands
must be exactly equal to the element size. It doesn't seem to trigger, and I'm
not sure if there any targets that use SPLAT_VECTOR_PARTS for anything other
than v4i32 -> v2i64 splats.

We also need to include it in isTargetCanonicalConstantNode, otherwise
returning the known bits introduces an infinite combine loop.

[craig.topper]

LGTM

llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll

2063

There's a missed constant fold of sub of two constant splat_vector parts here. computeKnownBits is hiding it because we constant fold it inside computeKnownBits, but we should handle it in FoldConstantArithmetic

[luke]

llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll

2063

Yeah, this was the first thing I tried. I found that there's a lot of logic that needs shared, and there's some other binop cases that aren't fully handled e.g. a bitcast of a splat_vector, or where one operand is bitcasted and the other isn't. Will give it a revisit.

Some other places I saw where I think we might need to handle splat_vector_parts:

SelectionDAG::isSplatValue
isConstantSplatVector/isConstantSplatVectorAllOnes/isConstantSplatVectorAllZeros/isConstOrConstSplat in SelectionDAGNodes.h
SelectionDAG::getValidShiftAmountConstant and friends
isConstantOrConstantVector in DAGCombiner

llvm/include/llvm/CodeGen/TargetLowering.h

public:
   virtual bool isSplatValueForTargetNode(SDValue Op, const APInt &DemandedElts,
                                          APInt &UndefElts,
                                          const SelectionDAG &DAG,
                                          unsigned Depth = 0) const;
 
   /// Returns true if the given Opc is considered a canonical constant for the
   /// target, which should not be transformed back into a BUILD_VECTOR.
   virtual bool isTargetCanonicalConstantNode(SDValue Op) const {
-    return Op.getOpcode() == ISD::SPLAT_VECTOR;
+    return Op.getOpcode() == ISD::SPLAT_VECTOR ||
+           Op.getOpcode() == ISD::SPLAT_VECTOR_PARTS;
   }
 
   struct DAGCombinerInfo {
     void *DC;  // The DAG Combiner object.
     CombineLevel Level;
     bool CalledByLegalizer;
 
   public:

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

case ISD::SPLAT_VECTOR: {
     SDValue SrcOp = Op.getOperand(0);
     assert(SrcOp.getValueSizeInBits() >= BitWidth &&
            "Expected SPLAT_VECTOR implicit truncation");
     // Implicitly truncate the bits to match the official semantics of
     // SPLAT_VECTOR.
     Known = computeKnownBits(SrcOp, Depth + 1).trunc(BitWidth);
     break;
   }
+  case ISD::SPLAT_VECTOR_PARTS: {
+    unsigned ScalarSize = Op.getOperand(0).getScalarValueSizeInBits();
+    assert(ScalarSize * Op.getNumOperands() == BitWidth &&
+           "Expected SPLAT_VECTOR_PARTS scalars to cover element width");
+    for (auto [I, SrcOp] : enumerate(Op->ops())) {
+      Known.insertBits(computeKnownBits(SrcOp, Depth + 1), ScalarSize * I);
+    }
+    break;
+  }
   case ISD::BUILD_VECTOR:
     assert(!Op.getValueType().isScalableVector());
     // Collect the known bits that are shared by every demanded vector element.
     Known.Zero.setAllBits(); Known.One.setAllBits();
     for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i) {
       if (!DemandedElts[i])
         continue;
 

llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll

 ; CHECK-ZVBB-NEXT:    ret
   %b.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
   %b.splat = shufflevector <vscale x 1 x i64> %b.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
   %x = call <vscale x 1 x i64> @llvm.fshr.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %a, <vscale x 1 x i64> %b.splat)
   ret <vscale x 1 x i64> %x
 }
 
 define <vscale x 1 x i64> @vror_vi_nxv1i64(<vscale x 1 x i64> %a) {
-; CHECK-RV32-LABEL: vror_vi_nxv1i64:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
-; CHECK-RV32-NEXT:    vmv.v.i v9, 1
-; CHECK-RV32-NEXT:    vrsub.vi v9, v9, 0
-; CHECK-RV32-NEXT:    li a0, 63
-; CHECK-RV32-NEXT:    vand.vx v9, v9, a0
-; CHECK-RV32-NEXT:    vsll.vv v9, v8, v9
-; CHECK-RV32-NEXT:    vmv.v.x v10, a0
-; CHECK-RV32-NEXT:    vand.vi v10, v10, 1
-; CHECK-RV32-NEXT:    vsrl.vv v8, v8, v10
-; CHECK-RV32-NEXT:    vor.vv v8, v8, v9
-; CHECK-RV32-NEXT:    ret
-;
-; CHECK-RV64-LABEL: vror_vi_nxv1i64:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    li a0, 63
-; CHECK-RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
-; CHECK-RV64-NEXT:    vsll.vx v9, v8, a0
-; CHECK-RV64-NEXT:    vsrl.vi v8, v8, 1
-; CHECK-RV64-NEXT:    vor.vv v8, v8, v9
-; CHECK-RV64-NEXT:    ret
+; CHECK-LABEL: vror_vi_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 63
+; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
+; CHECK-NEXT:    vsll.vx v9, v8, a0
+; CHECK-NEXT:    vsrl.vi v8, v8, 1
+; CHECK-NEXT:    vor.vv v8, v8, v9
+; CHECK-NEXT:    ret
 ;
 ; CHECK-ZVBB-LABEL: vror_vi_nxv1i64:
 ; CHECK-ZVBB:       # %bb.0:
 ; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
 ; CHECK-ZVBB-NEXT:    vror.vi v8, v8, 1
 ; CHECK-ZVBB-NEXT:    ret
   %x = call <vscale x 1 x i64> @llvm.fshr.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %a, <vscale x 1 x i64> shufflevector(<vscale x 1 x i64> insertelement(<vscale x 1 x i64> poison, i64 1, i32 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer))
   ret <vscale x 1 x i64> %x
 }
 
 define <vscale x 1 x i64> @vror_vi_rotl_nxv1i64(<vscale x 1 x i64> %a) {
-; CHECK-RV32-LABEL: vror_vi_rotl_nxv1i64:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
-; CHECK-RV32-NEXT:    vmv.v.i v9, 1
-; CHECK-RV32-NEXT:    vrsub.vi v9, v9, 0
-; CHECK-RV32-NEXT:    li a0, 63
-; CHECK-RV32-NEXT:    vand.vx v9, v9, a0
-; CHECK-RV32-NEXT:    vsrl.vv v9, v8, v9
-; CHECK-RV32-NEXT:    vmv.v.x v10, a0
-; CHECK-RV32-NEXT:    vand.vi v10, v10, 1
-; CHECK-RV32-NEXT:    vsll.vv v8, v8, v10
-; CHECK-RV32-NEXT:    vor.vv v8, v8, v9
-; CHECK-RV32-NEXT:    ret
-;
-; CHECK-RV64-LABEL: vror_vi_rotl_nxv1i64:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    li a0, 63
-; CHECK-RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
-; CHECK-RV64-NEXT:    vsrl.vx v9, v8, a0
-; CHECK-RV64-NEXT:    vadd.vv v8, v8, v8
-; CHECK-RV64-NEXT:    vor.vv v8, v8, v9
-; CHECK-RV64-NEXT:    ret
+; CHECK-LABEL: vror_vi_rotl_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 63
+; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
+; CHECK-NEXT:    vsrl.vx v9, v8, a0
+; CHECK-NEXT:    vadd.vv v8, v8, v8
+; CHECK-NEXT:    vor.vv v8, v8, v9
+; CHECK-NEXT:    ret
 ;
 ; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv1i64:
 ; CHECK-ZVBB:       # %bb.0:
 ; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
 ; CHECK-ZVBB-NEXT:    vror.vi v8, v8, 63
 ; CHECK-ZVBB-NEXT:    ret
   %x = call <vscale x 1 x i64> @llvm.fshl.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %a, <vscale x 1 x i64> shufflevector(<vscale x 1 x i64> insertelement(<vscale x 1 x i64> poison, i64 1, i32 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer))
   ret <vscale x 1 x i64> %x

 ; CHECK-ZVBB-NEXT:    ret
   %b.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
   %b.splat = shufflevector <vscale x 2 x i64> %b.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
   %x = call <vscale x 2 x i64> @llvm.fshr.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b.splat)
   ret <vscale x 2 x i64> %x
 }
 
 define <vscale x 2 x i64> @vror_vi_nxv2i64(<vscale x 2 x i64> %a) {
-; CHECK-RV32-LABEL: vror_vi_nxv2i64:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
-; CHECK-RV32-NEXT:    vmv.v.i v10, 1
-; CHECK-RV32-NEXT:    vrsub.vi v10, v10, 0
-; CHECK-RV32-NEXT:    li a0, 63
-; CHECK-RV32-NEXT:    vand.vx v10, v10, a0
-; CHECK-RV32-NEXT:    vsll.vv v10, v8, v10
-; CHECK-RV32-NEXT:    vmv.v.x v12, a0
-; CHECK-RV32-NEXT:    vand.vi v12, v12, 1
-; CHECK-RV32-NEXT:    vsrl.vv v8, v8, v12
-; CHECK-RV32-NEXT:    vor.vv v8, v8, v10
-; CHECK-RV32-NEXT:    ret
-;
-; CHECK-RV64-LABEL: vror_vi_nxv2i64:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    li a0, 63
-; CHECK-RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
-; CHECK-RV64-NEXT:    vsll.vx v10, v8, a0
-; CHECK-RV64-NEXT:    vsrl.vi v8, v8, 1
-; CHECK-RV64-NEXT:    vor.vv v8, v8, v10
-; CHECK-RV64-NEXT:    ret
+; CHECK-LABEL: vror_vi_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 63
+; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
+; CHECK-NEXT:    vsll.vx v10, v8, a0
+; CHECK-NEXT:    vsrl.vi v8, v8, 1
+; CHECK-NEXT:    vor.vv v8, v8, v10
+; CHECK-NEXT:    ret
 ;
 ; CHECK-ZVBB-LABEL: vror_vi_nxv2i64:
 ; CHECK-ZVBB:       # %bb.0:
 ; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
 ; CHECK-ZVBB-NEXT:    vror.vi v8, v8, 1
 ; CHECK-ZVBB-NEXT:    ret
   %x = call <vscale x 2 x i64> @llvm.fshr.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %a, <vscale x 2 x i64> shufflevector(<vscale x 2 x i64> insertelement(<vscale x 2 x i64> poison, i64 1, i32 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer))
   ret <vscale x 2 x i64> %x
 }
 
 define <vscale x 2 x i64> @vror_vi_rotl_nxv2i64(<vscale x 2 x i64> %a) {
-; CHECK-RV32-LABEL: vror_vi_rotl_nxv2i64:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
-; CHECK-RV32-NEXT:    vmv.v.i v10, 1
-; CHECK-RV32-NEXT:    vrsub.vi v10, v10, 0
-; CHECK-RV32-NEXT:    li a0, 63
-; CHECK-RV32-NEXT:    vand.vx v10, v10, a0
-; CHECK-RV32-NEXT:    vsrl.vv v10, v8, v10
-; CHECK-RV32-NEXT:    vmv.v.x v12, a0
-; CHECK-RV32-NEXT:    vand.vi v12, v12, 1
-; CHECK-RV32-NEXT:    vsll.vv v8, v8, v12
-; CHECK-RV32-NEXT:    vor.vv v8, v8, v10
-; CHECK-RV32-NEXT:    ret
-;
-; CHECK-RV64-LABEL: vror_vi_rotl_nxv2i64:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    li a0, 63
-; CHECK-RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
-; CHECK-RV64-NEXT:    vsrl.vx v10, v8, a0
-; CHECK-RV64-NEXT:    vadd.vv v8, v8, v8
-; CHECK-RV64-NEXT:    vor.vv v8, v8, v10
-; CHECK-RV64-NEXT:    ret
+; CHECK-LABEL: vror_vi_rotl_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 63
+; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
+; CHECK-NEXT:    vsrl.vx v10, v8, a0
+; CHECK-NEXT:    vadd.vv v8, v8, v8
+; CHECK-NEXT:    vor.vv v8, v8, v10
+; CHECK-NEXT:    ret
 ;
 ; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv2i64:
 ; CHECK-ZVBB:       # %bb.0:
 ; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
 ; CHECK-ZVBB-NEXT:    vror.vi v8, v8, 63
 ; CHECK-ZVBB-NEXT:    ret
   %x = call <vscale x 2 x i64> @llvm.fshl.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %a, <vscale x 2 x i64> shufflevector(<vscale x 2 x i64> insertelement(<vscale x 2 x i64> poison, i64 1, i32 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer))
   ret <vscale x 2 x i64> %x

 ; CHECK-ZVBB-NEXT:    ret
   %b.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
   %b.splat = shufflevector <vscale x 4 x i64> %b.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
   %x = call <vscale x 4 x i64> @llvm.fshr.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %a, <vscale x 4 x i64> %b.splat)
   ret <vscale x 4 x i64> %x
 }
 
 define <vscale x 4 x i64> @vror_vi_nxv4i64(<vscale x 4 x i64> %a) {
-; CHECK-RV32-LABEL: vror_vi_nxv4i64:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
-; CHECK-RV32-NEXT:    vmv.v.i v12, 1
-; CHECK-RV32-NEXT:    vrsub.vi v12, v12, 0
-; CHECK-RV32-NEXT:    li a0, 63
-; CHECK-RV32-NEXT:    vand.vx v12, v12, a0
-; CHECK-RV32-NEXT:    vsll.vv v12, v8, v12
-; CHECK-RV32-NEXT:    vmv.v.x v16, a0
-; CHECK-RV32-NEXT:    vand.vi v16, v16, 1
-; CHECK-RV32-NEXT:    vsrl.vv v8, v8, v16
-; CHECK-RV32-NEXT:    vor.vv v8, v8, v12
-; CHECK-RV32-NEXT:    ret
-;
-; CHECK-RV64-LABEL: vror_vi_nxv4i64:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    li a0, 63
-; CHECK-RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
-; CHECK-RV64-NEXT:    vsll.vx v12, v8, a0
-; CHECK-RV64-NEXT:    vsrl.vi v8, v8, 1
-; CHECK-RV64-NEXT:    vor.vv v8, v8, v12
-; CHECK-RV64-NEXT:    ret
+; CHECK-LABEL: vror_vi_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 63
+; CHECK-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
+; CHECK-NEXT:    vsll.vx v12, v8, a0
+; CHECK-NEXT:    vsrl.vi v8, v8, 1
+; CHECK-NEXT:    vor.vv v8, v8, v12
+; CHECK-NEXT:    ret
 ;
 ; CHECK-ZVBB-LABEL: vror_vi_nxv4i64:
 ; CHECK-ZVBB:       # %bb.0:
 ; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
 ; CHECK-ZVBB-NEXT:    vror.vi v8, v8, 1
 ; CHECK-ZVBB-NEXT:    ret
   %x = call <vscale x 4 x i64> @llvm.fshr.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %a, <vscale x 4 x i64> shufflevector(<vscale x 4 x i64> insertelement(<vscale x 4 x i64> poison, i64 1, i32 0), <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer))
   ret <vscale x 4 x i64> %x
 }
 
 define <vscale x 4 x i64> @vror_vi_rotl_nxv4i64(<vscale x 4 x i64> %a) {
-; CHECK-RV32-LABEL: vror_vi_rotl_nxv4i64:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
-; CHECK-RV32-NEXT:    vmv.v.i v12, 1
-; CHECK-RV32-NEXT:    vrsub.vi v12, v12, 0
-; CHECK-RV32-NEXT:    li a0, 63
-; CHECK-RV32-NEXT:    vand.vx v12, v12, a0
-; CHECK-RV32-NEXT:    vsrl.vv v12, v8, v12
-; CHECK-RV32-NEXT:    vmv.v.x v16, a0
-; CHECK-RV32-NEXT:    vand.vi v16, v16, 1
-; CHECK-RV32-NEXT:    vsll.vv v8, v8, v16
-; CHECK-RV32-NEXT:    vor.vv v8, v8, v12
-; CHECK-RV32-NEXT:    ret
-;
-; CHECK-RV64-LABEL: vror_vi_rotl_nxv4i64:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    li a0, 63
-; CHECK-RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
-; CHECK-RV64-NEXT:    vsrl.vx v12, v8, a0
-; CHECK-RV64-NEXT:    vadd.vv v8, v8, v8
-; CHECK-RV64-NEXT:    vor.vv v8, v8, v12
-; CHECK-RV64-NEXT:    ret
+; CHECK-LABEL: vror_vi_rotl_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 63
+; CHECK-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
+; CHECK-NEXT:    vsrl.vx v12, v8, a0
+; CHECK-NEXT:    vadd.vv v8, v8, v8
+; CHECK-NEXT:    vor.vv v8, v8, v12
+; CHECK-NEXT:    ret
 ;
 ; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv4i64:
 ; CHECK-ZVBB:       # %bb.0:
 ; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
 ; CHECK-ZVBB-NEXT:    vror.vi v8, v8, 63
 ; CHECK-ZVBB-NEXT:    ret
   %x = call <vscale x 4 x i64> @llvm.fshl.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %a, <vscale x 4 x i64> shufflevector(<vscale x 4 x i64> insertelement(<vscale x 4 x i64> poison, i64 1, i32 0), <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer))
   ret <vscale x 4 x i64> %x

 ; CHECK-ZVBB-NEXT:    ret
   %b.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
   %b.splat = shufflevector <vscale x 8 x i64> %b.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
   %x = call <vscale x 8 x i64> @llvm.fshr.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %a, <vscale x 8 x i64> %b.splat)
   ret <vscale x 8 x i64> %x
 }
 
 define <vscale x 8 x i64> @vror_vi_nxv8i64(<vscale x 8 x i64> %a) {
-; CHECK-RV32-LABEL: vror_vi_nxv8i64:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
-; CHECK-RV32-NEXT:    vmv.v.i v16, 1
-; CHECK-RV32-NEXT:    vrsub.vi v16, v16, 0
-; CHECK-RV32-NEXT:    li a0, 63
-; CHECK-RV32-NEXT:    vand.vx v16, v16, a0
-; CHECK-RV32-NEXT:    vsll.vv v16, v8, v16
-; CHECK-RV32-NEXT:    vmv.v.x v24, a0
-; CHECK-RV32-NEXT:    vand.vi v24, v24, 1
-; CHECK-RV32-NEXT:    vsrl.vv v8, v8, v24
-; CHECK-RV32-NEXT:    vor.vv v8, v8, v16
-; CHECK-RV32-NEXT:    ret
-;
-; CHECK-RV64-LABEL: vror_vi_nxv8i64:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    li a0, 63
-; CHECK-RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
-; CHECK-RV64-NEXT:    vsll.vx v16, v8, a0
-; CHECK-RV64-NEXT:    vsrl.vi v8, v8, 1
-; CHECK-RV64-NEXT:    vor.vv v8, v8, v16
-; CHECK-RV64-NEXT:    ret
+; CHECK-LABEL: vror_vi_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 63
+; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
+; CHECK-NEXT:    vsll.vx v16, v8, a0
+; CHECK-NEXT:    vsrl.vi v8, v8, 1
+; CHECK-NEXT:    vor.vv v8, v8, v16
+; CHECK-NEXT:    ret
 ;
 ; CHECK-ZVBB-LABEL: vror_vi_nxv8i64:
 ; CHECK-ZVBB:       # %bb.0:
 ; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
 ; CHECK-ZVBB-NEXT:    vror.vi v8, v8, 1
 ; CHECK-ZVBB-NEXT:    ret
   %x = call <vscale x 8 x i64> @llvm.fshr.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %a, <vscale x 8 x i64> shufflevector(<vscale x 8 x i64> insertelement(<vscale x 8 x i64> poison, i64 1, i32 0), <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer))
   ret <vscale x 8 x i64> %x
 }
 
 define <vscale x 8 x i64> @vror_vi_rotl_nxv8i64(<vscale x 8 x i64> %a) {
-; CHECK-RV32-LABEL: vror_vi_rotl_nxv8i64:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
-; CHECK-RV32-NEXT:    vmv.v.i v16, 1
-; CHECK-RV32-NEXT:    vrsub.vi v16, v16, 0
-; CHECK-RV32-NEXT:    li a0, 63
-; CHECK-RV32-NEXT:    vand.vx v16, v16, a0
-; CHECK-RV32-NEXT:    vsrl.vv v16, v8, v16
-; CHECK-RV32-NEXT:    vmv.v.x v24, a0
-; CHECK-RV32-NEXT:    vand.vi v24, v24, 1
-; CHECK-RV32-NEXT:    vsll.vv v8, v8, v24
-; CHECK-RV32-NEXT:    vor.vv v8, v8, v16
-; CHECK-RV32-NEXT:    ret
-;
-; CHECK-RV64-LABEL: vror_vi_rotl_nxv8i64:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    li a0, 63
-; CHECK-RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
-; CHECK-RV64-NEXT:    vsrl.vx v16, v8, a0
-; CHECK-RV64-NEXT:    vadd.vv v8, v8, v8
-; CHECK-RV64-NEXT:    vor.vv v8, v8, v16
-; CHECK-RV64-NEXT:    ret
+; CHECK-LABEL: vror_vi_rotl_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 63
+; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
+; CHECK-NEXT:    vsrl.vx v16, v8, a0
+; CHECK-NEXT:    vadd.vv v8, v8, v8
+; CHECK-NEXT:    vor.vv v8, v8, v16
+; CHECK-NEXT:    ret
 ;
 ; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv8i64:
 ; CHECK-ZVBB:       # %bb.0:
 ; CHECK-ZVBB-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
 ; CHECK-ZVBB-NEXT:    vror.vi v8, v8, 63
 ; CHECK-ZVBB-NEXT:    ret
   %x = call <vscale x 8 x i64> @llvm.fshl.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %a, <vscale x 8 x i64> shufflevector(<vscale x 8 x i64> insertelement(<vscale x 8 x i64> poison, i64 1, i32 0), <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer))
   ret <vscale x 8 x i64> %x
 }
 
 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
 ; CHECK-ZVBB32: {{.*}}
 ; CHECK-ZVBB64: {{.*}}