[MIPS] Add handing of forbidden slot when IR with inline asm

[yingopq]

Summary

Modify:
Add a global variable 'CurForbiddenSlotAttr' to save current instruction`s forbidden slot and whether set reorder.
This is the judgment condition for whether to add nop.
We would add a couple of '.set noreorder' and '.set reorder' to wrap the current instruction and the next instruction.
Then we can get previous instruction`s forbidden slot attribute and whether set reorder by 'CurForbiddenSlotAttr'.
If previous instruction has forbidden slot and .set reorder is active and current instruction is CTI. Then emit a NOP
after it.

Fix scenarios:
1.When inline asm ends with branch instruction:
1.1)then compiler
generate another CTI immediately, CTI lie in forbidden slot.
test: Use function foo1 in new file llvm/test/CodeGen/Mips/llvm-ir/forbidden-slot-ir.ll.
1.2)and next IR line was also inline asm, need insert nop between them.
test: Use function foo2 in new file llvm/test/CodeGen/Mips/llvm-ir/forbidden-slot-ir.ll.
2.When inline asm includes CTI following branch instruction, need
insert nop between them.
test: Use function foo3 in new file llvm/test/CodeGen/Mips/llvm-ir/forbidden-slot-ir.ll.
3.Also add test for scenario that have been realized in pass, when
CTI follow branch instruction.
test: Use function foo0 in new file llvm/test/CodeGen/Mips/llvm-ir/forbidden-slot-ir.ll.
4.When .set reorder is set in handwritten assembly file, nop need
insert between branch instruction and CTI.
test: in new file llvm/test/MC/Mips/forbidden-slot.s

Test result:
$ sudo ./build/bin/llvm-lit -v llvm/test/CodeGen/Mips/llvm-ir/forbidden-slot-ir.ll llvm/test/MC/Mips/forbidden-slot.s llvm/test/MC/Mips/mips32r6/relocations.s llvm/test/MC/Mips/mips64r6/relocations.s llvm/test/MC/Mips/relocation.s
[sudo] password for huangyin:

• Testing: 5 tests, 5 workers --

PASS: LLVM :: MC/Mips/mips32r6/relocations.s (1 of 5)
PASS: LLVM :: MC/Mips/mips64r6/relocations.s (2 of 5)
PASS: LLVM :: MC/Mips/forbidden-slot.s (3 of 5)
PASS: LLVM :: CodeGen/Mips/llvm-ir/forbidden-slot-ir.ll (4 of 5)
PASS: LLVM :: MC/Mips/relocation.s (5 of 5)
Testing Time: 0.25s
Total Discovered Tests: 5

Passed: 5 (100.00%)

Fix https://github.com/llvm/llvm-project/issues/61045

[MaskRay]

I am quite concerned with extra parameters in AsmPrinter::emitInlineAsm, parseStatement, and similar member functions. Do we have a way not adding them?

@FlyGoat

llvm/include/llvm/MC/MCParser/MCParsedAsmOperand.h

95

Don't repeat the variable/function name in new code.

96

Do we have to have this variable?

llvm/test/MC/Mips/forbidden-slot.s

1

we cannot use clang in llvm tests due to layering reasons https://maskray.me/blog/2021-08-08-toolchain-testing#the-test-checks-at-the-wrong-layer. also, llvm-project may be built with just llvm, not clang, and this would fail.

4

Align instructions for better look

# MIPSELR6:      beqzc	$9, 0x8 <bbb>
# MIPSELR6-NEXT: nop <aaa>
# MIPSELR6:      b	0x8 <bbb>

[jrtc27]

With the exception of 5, these all sound like garbage inline asm input? If you have a dangling delay slot at the end of the inline assembly, that's your problem, not the compiler's. And don't we default to reorder, anyway, so the only way to write that is to first .set noreorder?

[FlyGoat]

In D158589#4612830, @jrtc27 wrote:

With the exception of 5, these all sound like garbage inline asm input? If you have a dangling delay slot at the end of the inline assembly, that's your problem, not the compiler's. And don't we default to reorder, anyway, so the only way to write that is to first .set noreorder?

Well forbidden slot works differs from delay slot. It is introduced in MIPS Release 6.
It does not change execution flow. It simply disallows some CTI instructions (namely branch etc) to be placed after a branch.
Requiring user to fill nop after all inline assembly that ends with those branch instructions sounds appealing.

[wzssyqa]

In D158589#4612830, @jrtc27 wrote:

With the exception of 5, these all sound like garbage inline asm input? If you have a dangling delay slot at the end of the inline assembly, that's your problem, not the compiler's. And don't we default to reorder, anyway, so the only way to write that is to first .set noreorder?

To make this problem more clear, this patch is about forbidden slot, not delay slot.
In MIPSr6, you cannot put a CTI (branch/jump instruction) just after another CTI, even they are compact(no delay slot),
so a nop is needed to insert.

[FlyGoat]

In D158589#4612822, @MaskRay wrote:

I am quite concerned with extra parameters in AsmPrinter::emitInlineAsm, parseStatement, and similar member functions. Do we have a way not adding them?

@FlyGoat

I can't think of another way to achieve similiar functionality.

Another possible method is to let MC process forbidden-slot even with noreorder set.

[FlyGoat]

FYI Github issue I raised for this problem: https://github.com/llvm/llvm-project/issues/61045

Please update into commit message next time.

[MaskRay]

If the patch is related to https://github.com/llvm/llvm-project/issues/61045 , the convention is to add

"Fix https://github.com/llvm/llvm-project/issues/61045" or "Close https://github.com/llvm/llvm-project/issues/61045" to the local commit message and update the summary (arc diff --head=HEAD 'HEAD^' --verbatim amends the summary with the local commit message when uploading a new diff). Personally I prefer "Close" for features.

[yingopq]

Add a global variable 'CurForbiddenSlotAttr' to save current instruction`s forbidden slot and whether set reorder.
This is the judgment condition for whether to add nop.
We would add a couple of '.set noreorder' and '.set reorder' to wrap the current instruction and the next instruction.
Then we can get previous instruction`s forbidden slot attribute and whether set reorder by 'CurForbiddenSlotAttr'.
If previous instruction has forbidden slot and .set reorder is active and current instruction is CTI. Then emit a NOP
after it.

[yingopq]

Fix fail test "lld/test/ELF/mips-pc-relocs.s"

[yingopq]

This comment has been deleted.

llvm/include/llvm/MC/MCParser/MCParsedAsmOperand.h

95

Don't repeat the variable/function name in new code.

You mean we should use another name, not MIp?

96

Do we have to have this variable?

In function MatchAndEmitInstruction, we use this structure Info.ParsedOperands to pass MI to target backend MIPS which need use MI to get next instruction of MBB.

llvm/test/MC/Mips/forbidden-slot.s

1

OK, thanks, I would use llvm-mc, like this llvm-mc -assemble -mcpu=mips64r6 -arch=mips64el -filetype=obj %s -o tmp.o.

$ ./build/bin/llvm-lit -v llvm/test/MC/Mips/forbidden-slot.s

• Testing: 1 tests, 1 workers --

PASS: LLVM :: MC/Mips/forbidden-slot.s (1 of 1)

Testing Time: 0.07s

Passed: 1

[yingopq]

@craig.topper Could you kindly help review this issue patch at your convenience, thanks！

[yingopq]

Ping,
Thanks

[yingopq]

Hi @MaskRay @craig.topper @jrtc27 @FlyGoat,

Ping,
Thanks.

llvm/include/llvm/CodeGen/AsmPrinter.h

private:
 
   /// This method emits the header for the current function.
   virtual void emitFunctionHeader();
 
   /// This method emits a comment next to header for the current function.
   virtual void emitFunctionHeaderComment();
 
   /// Emit a blob of inline asm to the output streamer.
+  /// \p MI - the machine instruction of current inline asm.
   void
   emitInlineAsm(StringRef Str, const MCSubtargetInfo &STI,
                 const MCTargetOptions &MCOptions,
                 const MDNode *LocMDNode = nullptr,
-                InlineAsm::AsmDialect AsmDialect = InlineAsm::AD_ATT) const;
+                InlineAsm::AsmDialect AsmDialect = InlineAsm::AD_ATT,
+                const MachineInstr *MI = nullptr) const;
 
   /// This method formats and emits the specified machine instruction that is an
   /// inline asm.
   void emitInlineAsm(const MachineInstr *MI) const;
 
   /// Add inline assembly info to the diagnostics machinery, so we can
   /// emit file and position info. Returns SrcMgr memory buffer position.
   unsigned addInlineAsmDiagBuffer(StringRef AsmStr,

llvm/include/llvm/MC/MCParser/MCAsmParser.h

 
 #include "llvm/ADT/STLFunctionalExtras.h"
 #include "llvm/ADT/SmallString.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/MC/MCAsmMacro.h"
 #include "llvm/Support/SMLoc.h"
+#include "llvm/CodeGen/MachineInstr.h"
 #include <cstdint>
 #include <string>
 #include <utility>
 
 namespace llvm {
 
 class MCAsmLexer;
 class MCAsmInfo;
public:
 
   virtual unsigned getAssemblerDialect() { return 0;}
   virtual void setAssemblerDialect(unsigned i) { }
 
   bool getShowParsedOperands() const { return ShowParsedOperands; }
   void setShowParsedOperands(bool Value) { ShowParsedOperands = Value; }
 
   /// Run the parser on the input source buffer.
-  virtual bool Run(bool NoInitialTextSection, bool NoFinalize = false) = 0;
+  /// \p MI - the machine instruction of current inline asm.
+  virtual bool Run(bool NoInitialTextSection, bool NoFinalize = false,
+                   const MachineInstr *MI = nullptr) = 0;
 
   virtual void setParsingMSInlineAsm(bool V) = 0;
   virtual bool isParsingMSInlineAsm() = 0;
 
   virtual bool discardLTOSymbol(StringRef) const { return false; }
 
   virtual bool isParsingMasm() const { return false; }
 

llvm/include/llvm/MC/MCParser/MCParsedAsmOperand.h

public:
   /// getOffsetOfLoc - Get the location of the offset operator.
   virtual SMLoc getOffsetOfLoc() const { return SMLoc(); }
 
   /// print - Print a debug representation of the operand to the given stream.
   virtual void print(raw_ostream &OS) const = 0;
 
   /// dump - Print to the debug stream.
   virtual void dump() const;
+
+  /// MIp - Pointer to the machine instruction of the current inlineAsm.
+  const MachineInstr *MIp;
 };
 
 //===----------------------------------------------------------------------===//
 // Debugging Support
 
 inline raw_ostream& operator<<(raw_ostream &OS, const MCParsedAsmOperand &MO) {
   MO.print(OS);
   return OS;
 }
 
 } // end namespace llvm
 
 #endif // LLVM_MC_MCPARSER_MCPARSEDASMOPERAND_H

llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp

unsigned AsmPrinter::addInlineAsmDiagBuffer(StringRef AsmStr,
   return BufNum;
 }
 
 
 /// EmitInlineAsm - Emit a blob of inline asm to the output streamer.
 void AsmPrinter::emitInlineAsm(StringRef Str, const MCSubtargetInfo &STI,
                                const MCTargetOptions &MCOptions,
                                const MDNode *LocMDNode,
-                               InlineAsm::AsmDialect Dialect) const {
+                               InlineAsm::AsmDialect Dialect,
+                               const MachineInstr *MI) const {
   assert(!Str.empty() && "Can't emit empty inline asm block");
 
   // Remember if the buffer is nul terminated or not so we can avoid a copy.
   bool isNullTerminated = Str.back() == 0;
   if (isNullTerminated)
     Str = Str.substr(0, Str.size()-1);
 
   // If the output streamer does not have mature MC support or the integrated
void AsmPrinter::emitInlineAsm(StringRef Str, const MCSubtargetInfo &STI,
   // Enable lexing Masm binary and hex integer literals in intel inline
   // assembly.
   if (Dialect == InlineAsm::AD_Intel)
     Parser->getLexer().setLexMasmIntegers(true);
 
   emitInlineAsmStart();
   // Don't implicitly switch to the text section before the asm.
   (void)Parser->Run(/*NoInitialTextSection*/ true,
-                    /*NoFinalize*/ true);
+                    /*NoFinalize*/ true,
+                    MI);
   emitInlineAsmEnd(STI, &TAP->getSTI());
 }
 
 static void EmitInlineAsmStr(const char *AsmStr, const MachineInstr *MI,
                              MachineModuleInfo *MMI, const MCAsmInfo *MAI,
                              AsmPrinter *AP, uint64_t LocCookie,
                              raw_ostream &OS) {
   bool InputIsIntelDialect = MI->getInlineAsmDialect() == InlineAsm::AD_Intel;
for (const Register RR : RestrRegs) {
               TRI->explainReservedReg(*MF, RR)) {
         MMI->getModule()->getContext().diagnose(DiagnosticInfoInlineAsm(
             LocCookie, *reason, DiagnosticSeverity::DS_Note));
       }
     }
   }
 
   emitInlineAsm(OS.str(), getSubtargetInfo(), TM.Options.MCOptions, LocMD,
-                MI->getInlineAsmDialect());
+                MI->getInlineAsmDialect(), MI);
 
   // Emit the #NOAPP end marker.  This has to happen even if verbose-asm isn't
   // enabled, so we use emitRawComment.
   OutStreamer->emitRawComment(MAI->getInlineAsmEnd());
 }
 
 /// PrintSpecial - Print information related to the specified machine instr
 /// that is independent of the operand, and may be independent of the instr

llvm/lib/MC/MCParser/AsmParser.cpp

 #include "llvm/ADT/SmallString.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringMap.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/BinaryFormat/Dwarf.h"
 #include "llvm/DebugInfo/CodeView/SymbolRecord.h"
+#include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCCodeView.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCDirectives.h"
 #include "llvm/MC/MCDwarf.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInstPrinter.h"
 #include "llvm/MC/MCInstrDesc.h"
private:
 
   /// Did we already inform the user about inconsistent MD5 usage?
   bool ReportedInconsistentMD5 = false;
 
   // Is alt macro mode enabled.
   bool AltMacroMode = false;
 
 protected:
+  /// \p MI - the machine instruction of current inline asm.
+  /// \p ErrorInfo - store the TSFlags of last machine instruction in the inline asm.
   virtual bool parseStatement(ParseStatementInfo &Info,
-                              MCAsmParserSemaCallback *SI);
+                              MCAsmParserSemaCallback *SI,
+                              const MachineInstr *MI,
+                              uint64_t &ErrorInfo);
 
   /// This routine uses the target specific ParseInstruction function to
   /// parse an instruction into Operands, and then call the target specific
   /// MatchAndEmit function to match and emit the instruction.
+  /// \p MI - the machine instruction of current inline asm.
+  /// \p ErrorInfo - store the TSFlags of last machine instruction in the inline asm.
   bool parseAndMatchAndEmitTargetInstruction(ParseStatementInfo &Info,
                                              StringRef IDVal, AsmToken ID,
-                                             SMLoc IDLoc);
+                                             SMLoc IDLoc, const MachineInstr *MI,
+                                             uint64_t &ErrorInfo);
 
   /// Should we emit DWARF describing this assembler source?  (Returns false if
   /// the source has .file directives, which means we don't want to generate
   /// info describing the assembler source itself.)
   bool enabledGenDwarfForAssembly();
 
 public:
   AsmParser(SourceMgr &SM, MCContext &Ctx, MCStreamer &Out,
             const MCAsmInfo &MAI, unsigned CB);
   AsmParser(const AsmParser &) = delete;
   AsmParser &operator=(const AsmParser &) = delete;
   ~AsmParser() override;
 
-  bool Run(bool NoInitialTextSection, bool NoFinalize = false) override;
+  /// \p MI - the machine instruction of current inline asm.
+  bool Run(bool NoInitialTextSection, bool NoFinalize = false,
+           const MachineInstr *MI = nullptr) override;
 
   void addDirectiveHandler(StringRef Directive,
                            ExtensionDirectiveHandler Handler) override {
     ExtensionDirectiveMap[Directive] = Handler;
   }
 
   void addAliasForDirective(StringRef Directive, StringRef Alias) override {
     DirectiveKindMap[Directive.lower()] = DirectiveKindMap[Alias.lower()];
HLASMAsmParser(SourceMgr &SM, MCContext &Ctx, MCStreamer &Out,
     Lexer.setSkipSpace(false);
     Lexer.setAllowHashInIdentifier(true);
     Lexer.setLexHLASMIntegers(true);
     Lexer.setLexHLASMStrings(true);
   }
 
   ~HLASMAsmParser() { Lexer.setSkipSpace(true); }
 
+  /// \p MI - the machine instruction of current inline asm.
+  /// \p ErrorInfo - store the TSFlags of last machine instruction in the inline asm.
   bool parseStatement(ParseStatementInfo &Info,
-                      MCAsmParserSemaCallback *SI) override;
+                      MCAsmParserSemaCallback *SI,
+                      const MachineInstr *MI,
+                      uint64_t &ErrorInfo) override;
 };
 
 } // end anonymous namespace
 
 namespace llvm {
 
 extern cl::opt<unsigned> AsmMacroMaxNestingDepth;
 
const MCDwarfFile &RootFile =
         getContext().getMCDwarfLineTable(/*CUID=*/0).getRootFile();
     getContext().setGenDwarfFileNumber(getStreamer().emitDwarfFileDirective(
         /*CUID=*/0, getContext().getCompilationDir(), RootFile.Name,
         RootFile.Checksum, RootFile.Source));
   }
   return true;
 }
 
-bool AsmParser::Run(bool NoInitialTextSection, bool NoFinalize) {
+bool AsmParser::Run(bool NoInitialTextSection, bool NoFinalize, const MachineInstr *MI) {
   LTODiscardSymbols.clear();
 
   // Create the initial section, if requested.
   if (!NoInitialTextSection)
     Out.initSections(false, getTargetParser().getSTI());
 
   // Prime the lexer.
   Lex();
if (getContext().getGenDwarfForAssembly()) {
     bool InsertResult = getContext().addGenDwarfSection(Sec);
     assert(InsertResult && ".text section should not have debug info yet");
     (void)InsertResult;
   }
 
   getTargetParser().onBeginOfFile();
 
   // While we have input, parse each statement.
+  // ErrorInfo - store the TSFlags of last machine instruction in the
+  // inline asm.  Because target mips needs this TSFlags to check whether
+  // current instruction lie in forbidden slot.  Reuse the parameter
+  // ErrorInfo of function MatchAndEmitInstruction.  The parameter passed
+  // in represents the last instruction TSFlags, passed out represents
+  // the current instruction TSFlags.
+  uint64_t ErrorInfo = 0;
   while (Lexer.isNot(AsmToken::Eof)) {
     ParseStatementInfo Info(&AsmStrRewrites);
-    bool Parsed = parseStatement(Info, nullptr);
+    // MI - the machine instruction of current inline asm.  Because target
+    // mips needs this pointer to get next machine instruction from current
+    // inlineAsm in MBB.
+    bool Parsed = parseStatement(Info, nullptr, MI, ErrorInfo);
 
     // If we have a Lexer Error we are on an Error Token. Load in Lexer Error
     // for printing ErrMsg via Lex() only if no (presumably better) parser error
     // exists.
     if (Parsed && !hasPendingError() && Lexer.getTok().is(AsmToken::Error)) {
       Lex();
     }
 
bool AsmParser::parseBinOpRHS(unsigned Precedence, const MCExpr *&Res,
   }
 }
 
 /// ParseStatement:
 ///   ::= EndOfStatement
 ///   ::= Label* Directive ...Operands... EndOfStatement
 ///   ::= Label* Identifier OperandList* EndOfStatement
 bool AsmParser::parseStatement(ParseStatementInfo &Info,
-                               MCAsmParserSemaCallback *SI) {
+                               MCAsmParserSemaCallback *SI,
+                               const MachineInstr *MI,
+                               uint64_t &ErrorInfo) {
   assert(!hasPendingError() && "parseStatement started with pending error");
   // Eat initial spaces and comments
   while (Lexer.is(AsmToken::Space))
     Lex();
   if (Lexer.is(AsmToken::EndOfStatement)) {
     // if this is a line comment we can drop it safely
     if (getTok().getString().empty() || getTok().getString().front() == '\r' ||
         getTok().getString().front() == '\n')
bool AsmParser::parseStatement(ParseStatementInfo &Info,
   if (ParsingMSInlineAsm && (IDVal == "align" || IDVal == "ALIGN"))
     return parseDirectiveMSAlign(IDLoc, Info);
 
   if (ParsingMSInlineAsm && (IDVal == "even" || IDVal == "EVEN"))
     Info.AsmRewrites->emplace_back(AOK_EVEN, IDLoc, 4);
   if (checkForValidSection())
     return true;
 
-  return parseAndMatchAndEmitTargetInstruction(Info, IDVal, ID, IDLoc);
+  return parseAndMatchAndEmitTargetInstruction(Info, IDVal, ID, IDLoc, MI, ErrorInfo);
 }
 
 bool AsmParser::parseAndMatchAndEmitTargetInstruction(ParseStatementInfo &Info,
                                                       StringRef IDVal,
                                                       AsmToken ID,
-                                                      SMLoc IDLoc) {
+                                                      SMLoc IDLoc,
+                                                      const MachineInstr *MI,
+                                                      uint64_t &ErrorInfo) {
   // Canonicalize the opcode to lower case.
   std::string OpcodeStr = IDVal.lower();
   ParseInstructionInfo IInfo(Info.AsmRewrites);
   bool ParseHadError = getTargetParser().ParseInstruction(IInfo, OpcodeStr, ID,
                                                           Info.ParsedOperands);
   Info.ParseError = ParseHadError;
-
+  Info.ParsedOperands[0]->MIp = MI;
   // Dump the parsed representation, if requested.
   if (getShowParsedOperands()) {
     SmallString<256> Str;
     raw_svector_ostream OS(Str);
     OS << "parsed instruction: [";
     for (unsigned i = 0; i != Info.ParsedOperands.size(); ++i) {
       if (i != 0)
         OS << ", ";
if (!ParseHadError && enabledGenDwarfForAssembly() &&
     getStreamer().emitDwarfLocDirective(
         getContext().getGenDwarfFileNumber(), Line, 0,
         DWARF2_LINE_DEFAULT_IS_STMT ? DWARF2_FLAG_IS_STMT : 0, 0, 0,
         StringRef());
   }
 
   // If parsing succeeded, match the instruction.
   if (!ParseHadError) {
-    uint64_t ErrorInfo;
     if (getTargetParser().MatchAndEmitInstruction(
             IDLoc, Info.Opcode, Info.ParsedOperands, Out, ErrorInfo,
             getTargetParser().isParsingMSInlineAsm()))
       return true;
   }
   return false;
 }
 
bool AsmParser::parseMSInlineAsm(
   SmallVector<AsmRewrite, 4> AsmStrRewrites;
 
   // Prime the lexer.
   Lex();
 
   // While we have input, parse each statement.
   unsigned InputIdx = 0;
   unsigned OutputIdx = 0;
+  uint64_t ErrorInfo = 0;
   while (getLexer().isNot(AsmToken::Eof)) {
     // Parse curly braces marking block start/end
     if (parseCurlyBlockScope(AsmStrRewrites))
       continue;
 
     ParseStatementInfo Info(&AsmStrRewrites);
-    bool StatementErr = parseStatement(Info, &SI);
+    bool StatementErr = parseStatement(Info, &SI, nullptr, ErrorInfo);
 
     if (StatementErr || Info.ParseError) {
       // Emit pending errors if any exist.
       printPendingErrors();
       return true;
     }
 
     // No pending error should exist here.
bool HLASMAsmParser::parseAsMachineInstruction(ParseStatementInfo &Info,
   // Attempt to parse the first token as an Identifier
   if (parseIdentifier(OperationEntryVal))
     return Error(OperationEntryLoc, "unexpected token at start of statement");
 
   // Once we've parsed the operation entry successfully, lex
   // any spaces to get to the OperandEntries.
   lexLeadingSpaces();
 
+  uint64_t ErrorInfo = 0;
   return parseAndMatchAndEmitTargetInstruction(
-      Info, OperationEntryVal, OperationEntryTok, OperationEntryLoc);
+      Info, OperationEntryVal, OperationEntryTok, OperationEntryLoc, nullptr, ErrorInfo);
 }
 
 bool HLASMAsmParser::parseStatement(ParseStatementInfo &Info,
-                                    MCAsmParserSemaCallback *SI) {
+                                    MCAsmParserSemaCallback *SI,
+                                    const MachineInstr *MI,
+                                    uint64_t &ErrorInfo) {
   assert(!hasPendingError() && "parseStatement started with pending error");
 
   // Should the first token be interpreted as a HLASM Label.
   bool ShouldParseAsHLASMLabel = false;
 
   // If a Name Entry exists, it should occur at the very
   // start of the string. In this case, we should parse the
   // first non-space token as a Label.

llvm/lib/MC/MCParser/MasmParser.cpp

 
 public:
   MasmParser(SourceMgr &SM, MCContext &Ctx, MCStreamer &Out,
              const MCAsmInfo &MAI, struct tm TM, unsigned CB = 0);
   MasmParser(const MasmParser &) = delete;
   MasmParser &operator=(const MasmParser &) = delete;
   ~MasmParser() override;
 
-  bool Run(bool NoInitialTextSection, bool NoFinalize = false) override;
+  /// \p MI - the machine instruction of current inline asm.
+  bool Run(bool NoInitialTextSection, bool NoFinalize = false,
+           const MachineInstr *MI = nullptr) override;
 
   void addDirectiveHandler(StringRef Directive,
                            ExtensionDirectiveHandler Handler) override {
     ExtensionDirectiveMap[Directive] = Handler;
     if (!DirectiveKindMap.contains(Directive)) {
       DirectiveKindMap[Directive] = DK_HANDLER_DIRECTIVE;
     }
   }
const MCDwarfFile &RootFile =
         getContext().getMCDwarfLineTable(/*CUID=*/0).getRootFile();
     getContext().setGenDwarfFileNumber(getStreamer().emitDwarfFileDirective(
         /*CUID=*/0, getContext().getCompilationDir(), RootFile.Name,
         RootFile.Checksum, RootFile.Source));
   }
   return true;
 }
 
-bool MasmParser::Run(bool NoInitialTextSection, bool NoFinalize) {
+bool MasmParser::Run(bool NoInitialTextSection, bool NoFinalize, const MachineInstr *MI) {
   // Create the initial section, if requested.
   if (!NoInitialTextSection)
     Out.initSections(false, getTargetParser().getSTI());
 
   // Prime the lexer.
   Lex();
 
   HadError = false;

llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

 #include "TargetInfo/MipsTargetInfo.h"
 #include "llvm/ADT/APFloat.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/BinaryFormat/ELF.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstrDesc.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCObjectFileInfo.h"
 #include "llvm/MC/MCParser/MCAsmLexer.h"
 #include "llvm/MC/MCParser/MCAsmParser.h"
#include "MipsGenAsmMatcher.inc"
 
   /// Returns the internal register number for the current AT. Also checks if
   /// the current AT is unavailable (set to $0) and gives an error if it is.
   /// This should be used in pseudo-instruction expansions which need AT.
   unsigned getATReg(SMLoc Loc);
 
   bool canUseATReg();
 
+  // Get MI from Operands, the parameter ErrorInfo passed in represents the last
+  // instruction TSFlags, passed out represents the current instruction TSFlags.
   bool processInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
-                          const MCSubtargetInfo *STI);
+                          const MCSubtargetInfo *STI, OperandVector &Operands,
+                          uint64_t &ErrorInfo);
 
   // Helper function that checks if the value of a vector index is within the
   // boundaries of accepted values for each RegisterKind
   // Example: INSERT.B $w0[n], $1 => 16 > n >= 0
   bool validateMSAIndex(int Val, int RegKind);
 
   // Selects a new architecture by updating the FeatureBits with the necessary
   // info including implied dependencies.
if (Op.isExpr()) {
     return SR->getKind() == MCSymbolRefExpr::VK_None;
   }
 
   return false;
 }
 
 bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
                                        MCStreamer &Out,
-                                       const MCSubtargetInfo *STI) {
+                                       const MCSubtargetInfo *STI,
+                                       OperandVector &Operands,
+                                       uint64_t &RecvErrorInfo) {
   MipsTargetStreamer &TOut = getTargetStreamer();
   const unsigned Opcode = Inst.getOpcode();
   const MCInstrDesc &MCID = MII.get(Opcode);
   bool ExpandedJalSym = false;
+  // When the previous instruction has forbidden slot and the current
+  // instruction is CTI and .set reorder has been used, need insert nop.
+  bool needInsertNop = false;
+  // When the current instruction has forbidden slot and also is the last
+  // in current inline asm, need go to check next instruction by MI from
+  // the current inline asm in MBB, if it is CTI or inline asm, need insert
+  // nop.
+  bool gonext = false;
+  // Receive the TSFlags of last instruction.
+  uint64_t LastErrorInfo = RecvErrorInfo;
+
 
   Inst.setLoc(IDLoc);
+  if ((LastErrorInfo & MipsII::HasForbiddenSlot) &&
+      (MCID.TSFlags & MipsII::IsCTI)) {
+    needInsertNop = AssemblerOptions.back()->isReorder();
+    if (needInsertNop) {
+      TOut.emitEmptyDelaySlot(hasShortDelaySlot(Inst), IDLoc, STI);
+    }
+  }
+  //Store the TSFlags of current instruction and passed out to the caller.
+  RecvErrorInfo = MCID.TSFlags;
 
   if (MCID.isBranch() || MCID.isCall()) {
     MCOperand Offset;
 
     switch (Opcode) {
     default:
       break;
     case Mips::BBIT0:
if (IsCpRestoreSet) {
                                 STI);
 
       // Load the $gp from the stack.
       TOut.emitGPRestore(CpRestoreOffset, IDLoc, STI);
     } else
       Warning(IDLoc, "no .cprestore used in PIC mode");
   }
 
+  if (MCID.TSFlags & MipsII::HasForbiddenSlot) {
+    AsmToken ID = getTok();
+    getLexer().Lex();
+    if(getLexer().is(AsmToken::Eof)) {
+      gonext = true;
+    }
+    getLexer().UnLex(ID);
+    if (true == gonext) {
+      const MachineInstr *MIp = Operands[0]->MIp;
+      if (MIp != NULL) {
+        auto I = std::next(MIp->getIterator());
+        if (I->isInlineAsm() || (I->getDesc().TSFlags & MipsII::IsCTI))
+          TOut.emitEmptyDelaySlot(hasShortDelaySlot(Inst), IDLoc, STI);
+      }
+    }
+  }
+
   return false;
 }
 
 MipsAsmParser::MacroExpanderResultTy
 MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                                     const MCSubtargetInfo *STI) {
   switch (Inst.getOpcode()) {
   default:

 }
 
 bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                             OperandVector &Operands,
                                             MCStreamer &Out,
                                             uint64_t &ErrorInfo,
                                             bool MatchingInlineAsm) {
   MCInst Inst;
+  uint64_t RecvErrorInfo = ErrorInfo;
   unsigned MatchResult =
       MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
 
   switch (MatchResult) {
   case Match_Success:
-    if (processInstruction(Inst, IDLoc, Out, STI))
+    if (processInstruction(Inst, IDLoc, Out, STI, Operands, RecvErrorInfo)) {
+      //Passed out TSFlags by ErrorInfo.
+      ErrorInfo = RecvErrorInfo;
       return true;
+    }
+    ErrorInfo = RecvErrorInfo;
     return false;
   case Match_MissingFeature:
     Error(IDLoc, "instruction requires a CPU feature not currently enabled");
     return true;
   case Match_InvalidTiedOperand:
     Error(IDLoc, "operand must match destination register");
     return true;
   case Match_InvalidOperand: {

llvm/lib/Target/Mips/MipsInstrInfo.cpp

unsigned MipsInstrInfo::getEquivalentCompactForm(
 
   return 0;
 }
 
 /// Predicate for distingushing between control transfer instructions and all
 /// other instructions for handling forbidden slots. Consider inline assembly
 /// as unsafe as well.
 bool MipsInstrInfo::SafeInForbiddenSlot(const MachineInstr &MI) const {
+  //FIXME: Best to check whether the first instruction of inlineAsm is CTI
   if (MI.isInlineAsm())
     return false;
 
   return (MI.getDesc().TSFlags & MipsII::IsCTI) == 0;
 }
 
 bool MipsInstrInfo::SafeInFPUDelaySlot(const MachineInstr &MIInSlot,
                                        const MachineInstr &FPUMI) const {

llvm/test/CodeGen/Mips/llvm-ir/forbidden-slot-ir.ll

+target triple = "mipsisa32r6el-unknown-linux-gnu"
+
+; RUN: llc -filetype=asm %s -o - | FileCheck %s --check-prefix=MIPSELR6
+; Function Attrs: noinline nounwind optnone uwtable
+define i1 @foo0() nounwind {
+; MIPSELR6: bnezc $1, $BB0_2
+; MIPSELR6-NEXT: nop
+; MIPSELR6: jr  $ra
+entry:
+  %0 = icmp eq i32 0, 1
+  br i1 %0, label %2, label %3
+  ret i1 %0
+2:                                                
+  ret i1 %0
+3:                                                
+  ret i1 %0
+}
+
+define i32 @foo1() nounwind {
+; MIPSELR6: beqzc $2, $tmp0
+; MIPSELR6-NEXT: nop
+; MIPSELR6: jrc $ra
+entry:
+  %0 = tail call i32 asm "1: addiu $0, $$0, 1; beqzc $0, 1b;", "=r"() nounwind
+  ret i32 %0
+}
+
+define i32 @foo2() nounwind {
+; MIPSELR6: beqzc $9, End
+; MIPSELR6-NEXT: nop
+; MIPSELR6: addiu $9, $9, 1
+entry:
+  %0 = tail call i32 asm "beqzc $$t1, End;", "=r"() nounwind
+  %1 = tail call i32 asm "addiu $$t1, $$t1, 1;", "=r"() nounwind
+  %2 = add nsw i32 %1, %0
+  ret i32 %2
+}
+
+define i32 @foo3() nounwind {
+; MIPSELR6: beqzc $2, $tmp1
+; MIPSELR6-NEXT: nop
+; MIPSELR6: j End
+entry:
+  %0 = tail call i32 asm "1: addiu $0, $$0, 1; beqzc $0, 1b; j End;", "=r"() nounwind
+  ret i32 %0
+}

llvm/test/MC/Mips/forbidden-slot.s

+# RUN: clang --target=mipsel-linux-gnu -march=mips32r6 -c %s -o tmp.o
+# RUN: llvm-objdump -d tmp.o | FileCheck %s --check-prefix=MIPSELR6
+
+# MIPSELR6: beqzc $9, 0x0 <aaa>
+# MIPSELR6-NEXT: b  0x0 <aaa>
+# MIPSELR6: beqzc $9, 0x8 <bbb>
+# MIPSELR6-NEXT: nop <aaa>
+# MIPSELR6: b 0x8 <bbb>
+  .set noreorder
+aaa:
+  beqzc $t1, aaa
+  b aaa
+  .set reorder
+bbb:
+  beqzc $t1, bbb
+  b bbb