WIP: [Bitcode][C-API][IR] Introduce bitcode load version 2 and freeze_bits metadata

[jmciver]

Summary

OVERVIEW:

This is the first in a sequence of exploratory patches using poison semantics
for uninitialized memory.

METADATA:

The new metadata, freeze_bits, is used to convert poison to a nondeterministic
value. Application of freeze_bits is limited load type instructions only.

See the following URL for the RFC discussion:
https://discourse.llvm.org/t/rfc-load-instruction-uninitialized-memory-semantics/67481

BITCODE:

To facilitate in place migration of bitcode. A new versions of load and load
atomic are added; numeric identifiers 21 and 53. Auto migration is performed to
older loads by automatically applying freeze_bits metadata.

IR:

For convenience, an isFreezing parameter is add IRBuilder load functions. This
appends the attribute !freeze_bits to a load instruction. All IRBuilder
CreateLoad and CreateAlignedLoad function definitions default isFreezing to
true. This will allow front ends to transition to the new load instruction
semantics in a piecemeal fashion.

C-API:

Load instruction version 1 semantics are supported using the legacy function
LLVMBuildLoad2, which will add attribute !freeze_bits for compatibility. Load
instruction version 2 semantics are supported using function
LLVMBuildLoad3. This commit marks LLVMBuildLoad2 for future deprecation.

llvm/include/llvm-c/Core.h

LLVMValueRef LLVMBuildMemMove(LLVMBuilderRef B,
                               LLVMValueRef Dst, unsigned DstAlign,
                               LLVMValueRef Src, unsigned SrcAlign,
                               LLVMValueRef Size);
 
 LLVMValueRef LLVMBuildAlloca(LLVMBuilderRef, LLVMTypeRef Ty, const char *Name);
 LLVMValueRef LLVMBuildArrayAlloca(LLVMBuilderRef, LLVMTypeRef Ty,
                                   LLVMValueRef Val, const char *Name);
 LLVMValueRef LLVMBuildFree(LLVMBuilderRef, LLVMValueRef PointerVal);
-LLVMValueRef LLVMBuildLoad2(LLVMBuilderRef, LLVMTypeRef Ty,
+LLVM_ATTRIBUTE_C_DEPRECATED(LLVMValueRef LLVMBuildLoad2(LLVMBuilderRef,
+                                                        LLVMTypeRef Ty,
+                                                        LLVMValueRef PointerVal,
+                                                        const char *Name),
+                            "Use LLVMBuildLoad3 instead to support "
+                            "uninitialized memory loads as poison");
+LLVMValueRef LLVMBuildLoad3(LLVMBuilderRef, LLVMTypeRef Ty,
                             LLVMValueRef PointerVal, const char *Name);
 LLVMValueRef LLVMBuildStore(LLVMBuilderRef, LLVMValueRef Val, LLVMValueRef Ptr);
 LLVMValueRef LLVMBuildGEP2(LLVMBuilderRef B, LLVMTypeRef Ty,
                            LLVMValueRef Pointer, LLVMValueRef *Indices,
                            unsigned NumIndices, const char *Name);
 LLVMValueRef LLVMBuildInBoundsGEP2(LLVMBuilderRef B, LLVMTypeRef Ty,
                                    LLVMValueRef Pointer, LLVMValueRef *Indices,
                                    unsigned NumIndices, const char *Name);

llvm/include/llvm/Bitcode/LLVMBitCodes.h

enum FunctionCodes {
   FUNC_CODE_INST_SWITCH = 12, // SWITCH:     [opty, op0, op1, ...]
   FUNC_CODE_INST_INVOKE = 13, // INVOKE:     [attr, fnty, op0,op1, ...]
   // 14 is unused.
   FUNC_CODE_INST_UNREACHABLE = 15, // UNREACHABLE
 
   FUNC_CODE_INST_PHI = 16, // PHI:        [ty, val0,bb0, ...]
   // 17 is unused.
   // 18 is unused.
-  FUNC_CODE_INST_ALLOCA = 19, // ALLOCA:     [instty, opty, op, align]
-  FUNC_CODE_INST_LOAD = 20,   // LOAD:       [opty, op, align, vol]
-  // 21 is unused.
+  FUNC_CODE_INST_ALLOCA = 19,   // ALLOCA:     [instty, opty, op, align]
+  FUNC_CODE_INST_LOAD_OLD = 20, // LOAD:       [opty, op, align, vol]
+  FUNC_CODE_INST_LOAD = 21,     // LOAD:       [opty, op, align, vol]
   // 22 is unused.
   FUNC_CODE_INST_VAARG = 23, // VAARG:      [valistty, valist, instty]
   // This store code encodes the pointer type, rather than the value type
   // this is so information only available in the pointer type (e.g. address
   // spaces) is retained.
   FUNC_CODE_INST_STORE_OLD = 24, // STORE:      [ptrty,ptr,val, align, vol]
   // 25 is unused.
   FUNC_CODE_INST_EXTRACTVAL = 26, // EXTRACTVAL: [n x operands]
FUNC_CODE_INST_CMPXCHG_OLD = 37,   // CMPXCHG: [ptrty, ptr, cmp, val, vol,
                                      //            ordering, synchscope,
                                      //            failure_ordering?, weak?]
   FUNC_CODE_INST_ATOMICRMW_OLD = 38, // ATOMICRMW: [ptrty,ptr,val, operation,
                                      //             align, vol,
                                      //             ordering, synchscope]
   FUNC_CODE_INST_RESUME = 39,        // RESUME:     [opval]
   FUNC_CODE_INST_LANDINGPAD_OLD =
       40,                         // LANDINGPAD: [ty,val,val,num,id0,val0...]
-  FUNC_CODE_INST_LOADATOMIC = 41, // LOAD: [opty, op, align, vol,
+  FUNC_CODE_INST_LOADATOMIC_OLD = 41,  // LOAD: [opty, op, align, vol,
                                        //        ordering, synchscope]
   FUNC_CODE_INST_STOREATOMIC_OLD = 42, // STORE: [ptrty,ptr,val, align, vol
                                        //         ordering, synchscope]
   FUNC_CODE_INST_GEP = 43,             // GEP:  [inbounds, n x operands]
   FUNC_CODE_INST_STORE = 44,       // STORE: [ptrty,ptr,valty,val, align, vol]
   FUNC_CODE_INST_STOREATOMIC = 45, // STORE: [ptrty,ptr,val, align, vol
   FUNC_CODE_INST_CMPXCHG = 46,     // CMPXCHG: [ptrty, ptr, cmp, val, vol,
                                    //           success_ordering, synchscope,
                                    //           failure_ordering, weak]
   FUNC_CODE_INST_LANDINGPAD = 47,  // LANDINGPAD: [ty,val,num,id0,val0...]
   FUNC_CODE_INST_CLEANUPRET = 48,  // CLEANUPRET: [val] or [val,bb#]
   FUNC_CODE_INST_CATCHRET = 49,    // CATCHRET: [val,bb#]
   FUNC_CODE_INST_CATCHPAD = 50,    // CATCHPAD: [bb#,bb#,num,args...]
   FUNC_CODE_INST_CLEANUPPAD = 51,  // CLEANUPPAD: [num,args...]
   FUNC_CODE_INST_CATCHSWITCH =
       52, // CATCHSWITCH: [num,args...] or [num,args...,bb]
-  // 53 is unused.
+  FUNC_CODE_INST_LOADATOMIC = 53,  // LOAD: [opty, op, align, vol,
+                                   //        ordering, synchscope]
   // 54 is unused.
   FUNC_CODE_OPERAND_BUNDLE = 55,  // OPERAND_BUNDLE: [tag#, value...]
   FUNC_CODE_INST_UNOP = 56,       // UNOP:       [opcode, ty, opval]
   FUNC_CODE_INST_CALLBR = 57,     // CALLBR:     [attr, cc, norm, transfs,
                                   //              fnty, fnid, args...]
   FUNC_CODE_INST_FREEZE = 58,     // FREEZE: [opty, opval]
   FUNC_CODE_INST_ATOMICRMW = 59,  // ATOMICRMW: [ptrty, ptr, valty, val,
                                   //             operation, align, vol,
enum AttributeKindCodes {
   ATTR_KIND_ALLOC_ALIGN = 80,
   ATTR_KIND_ALLOCATED_POINTER = 81,
   ATTR_KIND_ALLOC_KIND = 82,
   ATTR_KIND_PRESPLIT_COROUTINE = 83,
   ATTR_KIND_FNRETTHUNK_EXTERN = 84,
   ATTR_KIND_SKIP_PROFILE = 85,
   ATTR_KIND_MEMORY = 86,
   ATTR_KIND_NOFPCLASS = 87,
+  ATTR_KIND_FREEZE_BITS = 88,
 };
 
 enum ComdatSelectionKindCodes {
   COMDAT_SELECTION_KIND_ANY = 1,
   COMDAT_SELECTION_KIND_EXACT_MATCH = 2,
   COMDAT_SELECTION_KIND_LARGEST = 3,
   COMDAT_SELECTION_KIND_NO_DUPLICATES = 4,
   COMDAT_SELECTION_KIND_SAME_SIZE = 5,

llvm/include/llvm/IR/Attributes.td

 
 /// Provide pointer element type to intrinsic.
 def ElementType : TypeAttr<"elementtype", [ParamAttr]>;
 
 /// Whether to keep return instructions, or replace with a jump to an external
 /// symbol.
 def FnRetThunkExtern : EnumAttr<"fn_ret_thunk_extern", [FnAttr]>;
 
+/// Convert unitialized memory per byte to a non-deterministic value.
+def FreezeBits : EnumAttr<"freeze_bits", [ParamAttr]>;
+
 /// Pass structure in an alloca.
 def InAlloca : TypeAttr<"inalloca", [ParamAttr]>;
 
 /// Source said inlining was desirable.
 def InlineHint : EnumAttr<"inlinehint", [FnAttr]>;
 
 /// Force argument to be passed in register.
 def InReg : EnumAttr<"inreg", [ParamAttr, RetAttr]>;

llvm/include/llvm/IR/AutoUpgrade.h

 
 namespace llvm {
   class AttrBuilder;
   class CallBase;
   class Constant;
   class Function;
   class Instruction;
   class GlobalVariable;
+  class LoadInst;
   class MDNode;
   class Module;
   class StringRef;
   class Type;
   class Value;
 
   template <typename T> class OperandBundleDefT;
   using OperandBundleDef = OperandBundleDefT<Value *>;
namespace llvm {
   std::string UpgradeDataLayoutString(StringRef DL, StringRef Triple);
 
   /// Upgrade attributes that changed format or kind.
   void UpgradeAttributes(AttrBuilder &B);
 
   /// Upgrade operand bundles (without knowing about their user instruction).
   void UpgradeOperandBundles(std::vector<OperandBundleDef> &OperandBundles);
 
+  /// Upgrade load instruction version 1 to load instruction version 2.
+  void UpgradeLoadInstruction(Instruction *Inst);
+
 } // End llvm namespace
 
 #endif

llvm/include/llvm/IR/FixedMetadataKinds.def

 LLVM_FIXED_MD_KIND(MD_nosanitize, "nosanitize", 31)
 LLVM_FIXED_MD_KIND(MD_func_sanitize, "func_sanitize", 32)
 LLVM_FIXED_MD_KIND(MD_exclude, "exclude", 33)
 LLVM_FIXED_MD_KIND(MD_memprof, "memprof", 34)
 LLVM_FIXED_MD_KIND(MD_callsite, "callsite", 35)
 LLVM_FIXED_MD_KIND(MD_kcfi_type, "kcfi_type", 36)
 LLVM_FIXED_MD_KIND(MD_pcsections, "pcsections", 37)
 LLVM_FIXED_MD_KIND(MD_DIAssignID, "DIAssignID", 38)
+LLVM_FIXED_MD_KIND(MD_freeze_bits, "freeze_bits", 39)

llvm/include/llvm/IR/IRBuilder.h

AllocaInst *CreateAlloca(Type *Ty, Value *ArraySize = nullptr,
     const DataLayout &DL = BB->getModule()->getDataLayout();
     Align AllocaAlign = DL.getPrefTypeAlign(Ty);
     unsigned AddrSpace = DL.getAllocaAddrSpace();
     return Insert(new AllocaInst(Ty, AddrSpace, ArraySize, AllocaAlign), Name);
   }
 
   /// Provided to resolve 'CreateLoad(Ty, Ptr, "...")' correctly, instead of
   /// converting the string to 'bool' for the isVolatile parameter.
-  LoadInst *CreateLoad(Type *Ty, Value *Ptr, const char *Name) {
-    return CreateAlignedLoad(Ty, Ptr, MaybeAlign(), Name);
+  LoadInst *CreateLoad(Type *Ty, Value *Ptr, const char *Name,
+                       bool isFreezing = true) {
+    return CreateAlignedLoad(Ty, Ptr, MaybeAlign(), Name, isFreezing);
   }
 
-  LoadInst *CreateLoad(Type *Ty, Value *Ptr, const Twine &Name = "") {
-    return CreateAlignedLoad(Ty, Ptr, MaybeAlign(), Name);
+  LoadInst *CreateLoad(Type *Ty, Value *Ptr, const Twine &Name = "",
+                       bool isFreezing = true) {
+    return CreateAlignedLoad(Ty, Ptr, MaybeAlign(), Name, isFreezing);
   }
 
   LoadInst *CreateLoad(Type *Ty, Value *Ptr, bool isVolatile,
-                       const Twine &Name = "") {
-    return CreateAlignedLoad(Ty, Ptr, MaybeAlign(), isVolatile, Name);
+                       const Twine &Name = "", bool isFreezing = true) {
+    return CreateAlignedLoad(Ty, Ptr, MaybeAlign(), isVolatile, Name,
+                             isFreezing);
   }
 
   StoreInst *CreateStore(Value *Val, Value *Ptr, bool isVolatile = false) {
     return CreateAlignedStore(Val, Ptr, MaybeAlign(), isVolatile);
   }
 
   LoadInst *CreateAlignedLoad(Type *Ty, Value *Ptr, MaybeAlign Align,
-                              const char *Name) {
-    return CreateAlignedLoad(Ty, Ptr, Align, /*isVolatile*/false, Name);
+                              const char *Name, bool isFreezing = true) {
+    return CreateAlignedLoad(Ty, Ptr, Align, /*isVolatile*/ false, Name,
+                             isFreezing);
   }
 
   LoadInst *CreateAlignedLoad(Type *Ty, Value *Ptr, MaybeAlign Align,
-                              const Twine &Name = "") {
-    return CreateAlignedLoad(Ty, Ptr, Align, /*isVolatile*/false, Name);
+                              const Twine &Name = "", bool isFreezing = true) {
+    return CreateAlignedLoad(Ty, Ptr, Align, /*isVolatile*/ false, Name,
+                             isFreezing);
   }
 
   LoadInst *CreateAlignedLoad(Type *Ty, Value *Ptr, MaybeAlign Align,
-                              bool isVolatile, const Twine &Name = "") {
+                              bool isVolatile, const Twine &Name = "",
+                              bool isFreezing = true) {
     if (!Align) {
       const DataLayout &DL = BB->getModule()->getDataLayout();
       Align = DL.getABITypeAlign(Ty);
     }
-    return Insert(new LoadInst(Ty, Ptr, Twine(), isVolatile, *Align), Name);
+    auto Load = new LoadInst(Ty, Ptr, Twine(), isVolatile, *Align);
+    if (isFreezing)
+      Load->setMetadata(llvm::LLVMContext::MD_freeze_bits,
+                        llvm::MDNode::get(Load->getContext(), std::nullopt));
+    return Insert(Load, Name);
   }
 
   StoreInst *CreateAlignedStore(Value *Val, Value *Ptr, MaybeAlign Align,
                                 bool isVolatile = false) {
     if (!Align) {
       const DataLayout &DL = BB->getModule()->getDataLayout();
       Align = DL.getABITypeAlign(Val->getType());
     }

llvm/lib/Bitcode/Reader/BitcodeAnalyzer.cpp

default:
       STRINGIFY_CODE(FUNC_CODE, INST_INVOKE)
       STRINGIFY_CODE(FUNC_CODE, INST_UNOP)
       STRINGIFY_CODE(FUNC_CODE, INST_UNREACHABLE)
       STRINGIFY_CODE(FUNC_CODE, INST_CLEANUPRET)
       STRINGIFY_CODE(FUNC_CODE, INST_CATCHRET)
       STRINGIFY_CODE(FUNC_CODE, INST_CATCHPAD)
       STRINGIFY_CODE(FUNC_CODE, INST_PHI)
       STRINGIFY_CODE(FUNC_CODE, INST_ALLOCA)
+      STRINGIFY_CODE(FUNC_CODE, INST_LOAD_OLD)
       STRINGIFY_CODE(FUNC_CODE, INST_LOAD)
       STRINGIFY_CODE(FUNC_CODE, INST_VAARG)
       STRINGIFY_CODE(FUNC_CODE, INST_STORE)
       STRINGIFY_CODE(FUNC_CODE, INST_EXTRACTVAL)
       STRINGIFY_CODE(FUNC_CODE, INST_INSERTVAL)
       STRINGIFY_CODE(FUNC_CODE, INST_CMP2)
       STRINGIFY_CODE(FUNC_CODE, INST_VSELECT)
       STRINGIFY_CODE(FUNC_CODE, DEBUG_LOC_AGAIN)
       STRINGIFY_CODE(FUNC_CODE, INST_CALL)
       STRINGIFY_CODE(FUNC_CODE, DEBUG_LOC)
       STRINGIFY_CODE(FUNC_CODE, INST_GEP)
       STRINGIFY_CODE(FUNC_CODE, OPERAND_BUNDLE)
       STRINGIFY_CODE(FUNC_CODE, INST_FENCE)
       STRINGIFY_CODE(FUNC_CODE, INST_ATOMICRMW)
+      STRINGIFY_CODE(FUNC_CODE, INST_LOADATOMIC_OLD)
       STRINGIFY_CODE(FUNC_CODE, INST_LOADATOMIC)
       STRINGIFY_CODE(FUNC_CODE, INST_STOREATOMIC)
       STRINGIFY_CODE(FUNC_CODE, INST_CMPXCHG)
       STRINGIFY_CODE(FUNC_CODE, INST_CALLBR)
       STRINGIFY_CODE(FUNC_CODE, BLOCKADDR_USERS)
     }
   case bitc::VALUE_SYMTAB_BLOCK_ID:
     switch (CodeID) {

llvm/lib/Bitcode/Reader/BitcodeReader.cpp

static Attribute::AttrKind getAttrFromCode(uint64_t Code) {
   case bitc::ATTR_KIND_CONVERGENT:
     return Attribute::Convergent;
   case bitc::ATTR_KIND_DISABLE_SANITIZER_INSTRUMENTATION:
     return Attribute::DisableSanitizerInstrumentation;
   case bitc::ATTR_KIND_ELEMENTTYPE:
     return Attribute::ElementType;
   case bitc::ATTR_KIND_FNRETTHUNK_EXTERN:
     return Attribute::FnRetThunkExtern;
+  case bitc::ATTR_KIND_FREEZE_BITS:
+    return Attribute::FreezeBits;
   case bitc::ATTR_KIND_INLINE_HINT:
     return Attribute::InlineHint;
   case bitc::ATTR_KIND_IN_REG:
     return Attribute::InReg;
   case bitc::ATTR_KIND_JUMP_TABLE:
     return Attribute::JumpTable;
   case bitc::ATTR_KIND_MEMORY:
     return Attribute::Memory;
case bitc::FUNC_CODE_INST_ALLOCA: { // ALLOCA: [instty, opty, op, align]
       AllocaInst *AI = new AllocaInst(Ty, AS, Size, *Align);
       AI->setUsedWithInAlloca(InAlloca);
       AI->setSwiftError(SwiftError);
       I = AI;
       ResTypeID = getVirtualTypeID(AI->getType(), TyID);
       InstructionList.push_back(I);
       break;
     }
+    case bitc::FUNC_CODE_INST_LOAD_OLD:
     case bitc::FUNC_CODE_INST_LOAD: { // LOAD: [opty, op, align, vol]
       unsigned OpNum = 0;
       Value *Op;
       unsigned OpTypeID;
       if (getValueTypePair(Record, OpNum, NextValueNo, Op, OpTypeID, CurBB) ||
           (OpNum + 2 != Record.size() && OpNum + 3 != Record.size()))
         return error("Invalid record");
 
case bitc::FUNC_CODE_INST_LOAD: { // LOAD: [opty, op, align, vol]
       if (Error Err = parseAlignmentValue(Record[OpNum], Align))
         return Err;
       SmallPtrSet<Type *, 4> Visited;
       if (!Align && !Ty->isSized(&Visited))
         return error("load of unsized type");
       if (!Align)
         Align = TheModule->getDataLayout().getABITypeAlign(Ty);
       I = new LoadInst(Ty, Op, "", Record[OpNum + 1], *Align);
+      if (BitCode == bitc::FUNC_CODE_INST_LOAD_OLD)
+        UpgradeLoadInstruction(I);
       InstructionList.push_back(I);
       break;
     }
+    case bitc::FUNC_CODE_INST_LOADATOMIC_OLD:
     case bitc::FUNC_CODE_INST_LOADATOMIC: {
        // LOADATOMIC: [opty, op, align, vol, ordering, ssid]
       unsigned OpNum = 0;
       Value *Op;
       unsigned OpTypeID;
       if (getValueTypePair(Record, OpNum, NextValueNo, Op, OpTypeID, CurBB) ||
           (OpNum + 4 != Record.size() && OpNum + 5 != Record.size()))
         return error("Invalid record");
case bitc::FUNC_CODE_INST_LOADATOMIC: {
       SyncScope::ID SSID = getDecodedSyncScopeID(Record[OpNum + 3]);
 
       MaybeAlign Align;
       if (Error Err = parseAlignmentValue(Record[OpNum], Align))
         return Err;
       if (!Align)
         return error("Alignment missing from atomic load");
       I = new LoadInst(Ty, Op, "", Record[OpNum + 1], *Align, Ordering, SSID);
+      if (BitCode == bitc::FUNC_CODE_INST_LOADATOMIC_OLD)
+        UpgradeLoadInstruction(I);
       InstructionList.push_back(I);
       break;
     }
     case bitc::FUNC_CODE_INST_STORE:
     case bitc::FUNC_CODE_INST_STORE_OLD: { // STORE2:[ptrty, ptr, val, align, vol]
       unsigned OpNum = 0;
       Value *Val, *Ptr;
       unsigned PtrTypeID, ValTypeID;

llvm/lib/Bitcode/Writer/BitcodeWriter.cpp

static uint64_t getAttrKindEncoding(Attribute::AttrKind Kind) {
   case Attribute::InAlloca:
     return bitc::ATTR_KIND_IN_ALLOCA;
   case Attribute::Cold:
     return bitc::ATTR_KIND_COLD;
   case Attribute::DisableSanitizerInstrumentation:
     return bitc::ATTR_KIND_DISABLE_SANITIZER_INSTRUMENTATION;
   case Attribute::FnRetThunkExtern:
     return bitc::ATTR_KIND_FNRETTHUNK_EXTERN;
+  case Attribute::FreezeBits:
+    return bitc::ATTR_KIND_FREEZE_BITS;
   case Attribute::Hot:
     return bitc::ATTR_KIND_HOT;
   case Attribute::ElementType:
     return bitc::ATTR_KIND_ELEMENTTYPE;
   case Attribute::InlineHint:
     return bitc::ATTR_KIND_INLINE_HINT;
   case Attribute::InReg:
     return bitc::ATTR_KIND_IN_REG;

llvm/lib/IR/AutoUpgrade.cpp

void llvm::UpgradeOperandBundles(std::vector<OperandBundleDef> &Bundles) {
   // If they don't, it's okay to drop them entirely: when there is an operand,
   // the "attachedcall" is meaningful and required, but without an operand,
   // it's just a marker NOP.  Dropping it merely prevents an optimization.
   erase_if(Bundles, [&](OperandBundleDef &OBD) {
     return OBD.getTag() == "clang.arc.attachedcall" &&
            OBD.inputs().empty();
   });
 }
+
+void llvm::UpgradeLoadInstruction(Instruction *Inst) {
+  if (LoadInst *Load = dyn_cast<LoadInst>(Inst))
+    Load->setMetadata(llvm::LLVMContext::MD_freeze_bits,
+                      llvm::MDNode::get(Load->getContext(), std::nullopt));
+}

llvm/lib/IR/Core.cpp

return wrap(unwrap(B)->Insert(
      CallInst::CreateFree(unwrap(PointerVal), unwrap(B)->GetInsertBlock())));
 }
 
 LLVMValueRef LLVMBuildLoad2(LLVMBuilderRef B, LLVMTypeRef Ty,
                             LLVMValueRef PointerVal, const char *Name) {
   return wrap(unwrap(B)->CreateLoad(unwrap(Ty), unwrap(PointerVal), Name));
 }
 
+LLVMValueRef LLVMBuildLoad3(LLVMBuilderRef B, LLVMTypeRef Ty,
+                            LLVMValueRef PointerVal, const char *Name) {
+  return wrap(
+      unwrap(B)->CreateLoad(unwrap(Ty), unwrap(PointerVal), Name, false));
+}
+
 LLVMValueRef LLVMBuildStore(LLVMBuilderRef B, LLVMValueRef Val,
                             LLVMValueRef PointerVal) {
   return wrap(unwrap(B)->CreateStore(unwrap(Val), unwrap(PointerVal)));
 }
 
 static AtomicOrdering mapFromLLVMOrdering(LLVMAtomicOrdering Ordering) {
   switch (Ordering) {
     case LLVMAtomicOrderingNotAtomic: return AtomicOrdering::NotAtomic;

llvm/lib/IR/Verifier.cpp

Check(I.getType()->isPointerTy(), "nonnull applies only to pointer types",
           &I);
     Check(isa<LoadInst>(I),
           "nonnull applies only to load instructions, use attributes"
           " for calls or invokes",
           &I);
     Check(MD->getNumOperands() == 0, "nonnull metadata must be empty", &I);
   }
 
+  if (MDNode *MD = I.getMetadata(LLVMContext::MD_freeze_bits)) {
+    Check(isa<LoadInst>(I), "freeze_bits applies only to load instructions",
+          &I);
+    Check(MD->getNumOperands() == 0, "freeze_bits metadata must be empty",
+          &I);
+  }
+
   if (MDNode *MD = I.getMetadata(LLVMContext::MD_dereferenceable))
     visitDereferenceableMetadata(I, MD);
 
   if (MDNode *MD = I.getMetadata(LLVMContext::MD_dereferenceable_or_null))
     visitDereferenceableMetadata(I, MD);
 
   if (MDNode *TBAA = I.getMetadata(LLVMContext::MD_tbaa))
     TBAAVerifyHelper.visitTBAAMetadata(I, TBAA);

llvm/lib/Transforms/Utils/CodeExtractor.cpp

if (Attr.isStringAttribute()) {
       // These attributes cannot be applied to functions.
       case Attribute::Alignment:
       case Attribute::AllocatedPointer:
       case Attribute::AllocAlign:
       case Attribute::ByVal:
       case Attribute::Dereferenceable:
       case Attribute::DereferenceableOrNull:
       case Attribute::ElementType:
+      case Attribute::FreezeBits:
       case Attribute::InAlloca:
       case Attribute::InReg:
       case Attribute::Nest:
       case Attribute::NoAlias:
       case Attribute::NoCapture:
       case Attribute::NoUndef:
       case Attribute::NonNull:
       case Attribute::Preallocated:

llvm/test/Bitcode/bcanalyzer-atomics.ll

 ; RUN: llvm-as < %s | llvm-bcanalyzer -dump | FileCheck %s
 ; Make sure the names of atomics are known
 
+; CHECK: INST_LOADATOMIC
 ; CHECK: INST_CMPXCHG
 ; CHECK: INST_STOREATOMIC
-; CHECK: INST_LOADATOMIC
 ; CHECK: INST_FENCE
 define void @atomics(i32* %ptr) {
   store atomic i32 0, i32* %ptr monotonic, align 4
   %load = load atomic i32, i32* %ptr monotonic, align 4
   %xchg = cmpxchg i32* %ptr, i32 0, i32 5 acquire monotonic
   fence seq_cst
   ret void
 }

llvm/test/Bitcode/compatibility-3.6.ll

define void @atomics(i32* %word) {
   ; CHECK: fence release
   fence acq_rel
   ; CHECK: fence acq_rel
   fence syncscope("singlethread") seq_cst
   ; CHECK: fence syncscope("singlethread") seq_cst
 
   ; XXX: The parser spits out the load type here.
   %ld.1 = load atomic i32* %word monotonic, align 4
-  ; CHECK: %ld.1 = load atomic i32, ptr %word monotonic, align 4
+  ; CHECK: %ld.1 = load atomic i32, ptr %word monotonic, align 4, !freeze_bits !7
   %ld.2 = load atomic volatile i32* %word acquire, align 8
-  ; CHECK: %ld.2 = load atomic volatile i32, ptr %word acquire, align 8
+  ; CHECK: %ld.2 = load atomic volatile i32, ptr %word acquire, align 8, !freeze_bits !7
   %ld.3 = load atomic volatile i32* %word syncscope("singlethread") seq_cst, align 16
-  ; CHECK: %ld.3 = load atomic volatile i32, ptr %word syncscope("singlethread") seq_cst, align 16
+  ; CHECK: %ld.3 = load atomic volatile i32, ptr %word syncscope("singlethread") seq_cst, align 16, !freeze_bits !7
 
   store atomic i32 23, i32* %word monotonic, align 4
   ; CHECK: store atomic i32 23, ptr %word monotonic, align 4
   store atomic volatile i32 24, i32* %word monotonic, align 4
   ; CHECK: store atomic volatile i32 24, ptr %word monotonic, align 4
   store atomic volatile i32 25, i32* %word syncscope("singlethread") monotonic, align 4
   ; CHECK: store atomic volatile i32 25, ptr %word syncscope("singlethread") monotonic, align 4
   ret void

 !9 = !{i64 4}
 define void @instructions.memops(i32** %base) {
   alloca i32, i8 4, align 4
   ; CHECK: alloca i32, i8 4, align 4
   alloca inalloca i32, i8 4, align 4
   ; CHECK: alloca inalloca i32, i8 4, align 4
 
   load i32** %base, align 8, !invariant.load !7, !nontemporal !8, !nonnull !7, !dereferenceable !9
-  ; CHECK: load ptr, ptr %base, align 8, !invariant.load !7, !nontemporal !8, !nonnull !7, !dereferenceable !9
+  ; CHECK: load ptr, ptr %base, align 8, !invariant.load !8, !nontemporal !7, !nonnull !8, !dereferenceable !9, !freeze_bits !7
   load volatile i32** %base, align 8, !invariant.load !7, !nontemporal !8, !nonnull !7, !dereferenceable !9
-  ; CHECK: load volatile ptr, ptr %base, align 8, !invariant.load !7, !nontemporal !8, !nonnull !7, !dereferenceable !9
+  ; CHECK: load volatile ptr, ptr %base, align 8, !invariant.load !8, !nontemporal !7, !nonnull !8, !dereferenceable !9, !freeze_bits !7
 
-  store i32* null, i32** %base, align 4, !nontemporal !8
-  ; CHECK: store ptr null, ptr %base, align 4, !nontemporal !8
-  store volatile i32* null, i32** %base, align 4, !nontemporal !8
-  ; CHECK: store volatile ptr null, ptr %base, align 4, !nontemporal !8
+  store i32* null, i32** %base, align 4, !nontemporal !7
+  ; CHECK: store ptr null, ptr %base, align 4, !nontemporal !7
+  store volatile i32* null, i32** %base, align 4, !nontemporal !7
+  ; CHECK: store volatile ptr null, ptr %base, align 4, !nontemporal !7
 
   ret void
 }
 
 ; Instructions -- Conversion Operations
 define void @instructions.conversions() {
   trunc i32 -1 to i1
   ; CHECK: trunc i32 -1 to i1

llvm/test/Bitcode/compatibility-3.7.ll

define void @atomics(i32* %word) {
   fence release
   ; CHECK: fence release
   fence acq_rel
   ; CHECK: fence acq_rel
   fence syncscope("singlethread") seq_cst
   ; CHECK: fence syncscope("singlethread") seq_cst
 
   %ld.1 = load atomic i32, i32* %word monotonic, align 4
-  ; CHECK: %ld.1 = load atomic i32, ptr %word monotonic, align 4
+  ; CHECK: %ld.1 = load atomic i32, ptr %word monotonic, align 4, !freeze_bits !7
   %ld.2 = load atomic volatile i32, i32* %word acquire, align 8
-  ; CHECK: %ld.2 = load atomic volatile i32, ptr %word acquire, align 8
+  ; CHECK: %ld.2 = load atomic volatile i32, ptr %word acquire, align 8, !freeze_bits !7
   %ld.3 = load atomic volatile i32, i32* %word syncscope("singlethread") seq_cst, align 16
-  ; CHECK: %ld.3 = load atomic volatile i32, ptr %word syncscope("singlethread") seq_cst, align 16
+  ; CHECK: %ld.3 = load atomic volatile i32, ptr %word syncscope("singlethread") seq_cst, align 16, !freeze_bits !7
 
   store atomic i32 23, i32* %word monotonic, align 4
   ; CHECK: store atomic i32 23, ptr %word monotonic, align 4
   store atomic volatile i32 24, i32* %word monotonic, align 4
   ; CHECK: store atomic volatile i32 24, ptr %word monotonic, align 4
   store atomic volatile i32 25, i32* %word syncscope("singlethread") monotonic, align 4
   ; CHECK: store atomic volatile i32 25, ptr %word syncscope("singlethread") monotonic, align 4
   ret void

 !9 = !{i64 4}
 define void @instructions.memops(i32** %base) {
   alloca i32, i8 4, align 4
   ; CHECK: alloca i32, i8 4, align 4
   alloca inalloca i32, i8 4, align 4
   ; CHECK: alloca inalloca i32, i8 4, align 4
 
   load i32*, i32** %base, align 8, !invariant.load !7, !nontemporal !8, !nonnull !7, !dereferenceable !9, !dereferenceable_or_null !9
-  ; CHECK: load ptr, ptr %base, align 8, !invariant.load !7, !nontemporal !8, !nonnull !7, !dereferenceable !9, !dereferenceable_or_null !9
+  ; CHECK: load ptr, ptr %base, align 8, !invariant.load !8, !nontemporal !7, !nonnull !8, !dereferenceable !9, !dereferenceable_or_null !9, !freeze_bits !7
   load volatile i32*, i32** %base, align 8, !invariant.load !7, !nontemporal !8, !nonnull !7, !dereferenceable !9, !dereferenceable_or_null !9
-  ; CHECK: load volatile ptr, ptr %base, align 8, !invariant.load !7, !nontemporal !8, !nonnull !7, !dereferenceable !9, !dereferenceable_or_null !9
+  ; CHECK: load volatile ptr, ptr %base, align 8, !invariant.load !8, !nontemporal !7, !nonnull !8, !dereferenceable !9, !dereferenceable_or_null !9, !freeze_bits !7
 
   store i32* null, i32** %base, align 4, !nontemporal !8
-  ; CHECK: store ptr null, ptr %base, align 4, !nontemporal !8
+  ; CHECK: store ptr null, ptr %base, align 4, !nontemporal !7
   store volatile i32* null, i32** %base, align 4, !nontemporal !8
-  ; CHECK: store volatile ptr null, ptr %base, align 4, !nontemporal !8
+  ; CHECK: store volatile ptr null, ptr %base, align 4, !nontemporal !7
 
   ret void
 }
 
 ; Instructions -- Conversion Operations
 define void @instructions.conversions() {
   trunc i32 -1 to i1
   ; CHECK: trunc i32 -1 to i1

llvm/test/Bitcode/compatibility-3.8.ll

define void @atomics(i32* %word) {
   fence release
   ; CHECK: fence release
   fence acq_rel
   ; CHECK: fence acq_rel
   fence syncscope("singlethread") seq_cst
   ; CHECK: fence syncscope("singlethread") seq_cst
 
   %ld.1 = load atomic i32, i32* %word monotonic, align 4
-  ; CHECK: %ld.1 = load atomic i32, ptr %word monotonic, align 4
+  ; CHECK: %ld.1 = load atomic i32, ptr %word monotonic, align 4, !freeze_bits !7
   %ld.2 = load atomic volatile i32, i32* %word acquire, align 8
-  ; CHECK: %ld.2 = load atomic volatile i32, ptr %word acquire, align 8
+  ; CHECK: %ld.2 = load atomic volatile i32, ptr %word acquire, align 8, !freeze_bits !7
   %ld.3 = load atomic volatile i32, i32* %word syncscope("singlethread") seq_cst, align 16
-  ; CHECK: %ld.3 = load atomic volatile i32, ptr %word syncscope("singlethread") seq_cst, align 16
+  ; CHECK: %ld.3 = load atomic volatile i32, ptr %word syncscope("singlethread") seq_cst, align 16, !freeze_bits !7
 
   store atomic i32 23, i32* %word monotonic, align 4
   ; CHECK: store atomic i32 23, ptr %word monotonic, align 4
   store atomic volatile i32 24, i32* %word monotonic, align 4
   ; CHECK: store atomic volatile i32 24, ptr %word monotonic, align 4
   store atomic volatile i32 25, i32* %word syncscope("singlethread") monotonic, align 4
   ; CHECK: store atomic volatile i32 25, ptr %word syncscope("singlethread") monotonic, align 4
   ret void

 !9 = !{i64 4}
 define void @instructions.memops(i32** %base) {
   alloca i32, i8 4, align 4
   ; CHECK: alloca i32, i8 4, align 4
   alloca inalloca i32, i8 4, align 4
   ; CHECK: alloca inalloca i32, i8 4, align 4
 
   load i32*, i32** %base, align 8, !invariant.load !7, !nontemporal !8, !nonnull !7, !dereferenceable !9, !dereferenceable_or_null !9
-  ; CHECK: load ptr, ptr %base, align 8, !invariant.load !7, !nontemporal !8, !nonnull !7, !dereferenceable !9, !dereferenceable_or_null !9
+  ; CHECK: load ptr, ptr %base, align 8, !invariant.load !8, !nontemporal !7, !nonnull !8, !dereferenceable !9, !dereferenceable_or_null !9, !freeze_bits !7
   load volatile i32*, i32** %base, align 8, !invariant.load !7, !nontemporal !8, !nonnull !7, !dereferenceable !9, !dereferenceable_or_null !9
-  ; CHECK: load volatile ptr, ptr %base, align 8, !invariant.load !7, !nontemporal !8, !nonnull !7, !dereferenceable !9, !dereferenceable_or_null !9
+  ; CHECK: load volatile ptr, ptr %base, align 8, !invariant.load !8, !nontemporal !7, !nonnull !8, !dereferenceable !9, !dereferenceable_or_null !9, !freeze_bits !7
 
   store i32* null, i32** %base, align 4, !nontemporal !8
-  ; CHECK: store ptr null, ptr %base, align 4, !nontemporal !8
+  ; CHECK: store ptr null, ptr %base, align 4, !nontemporal !7
   store volatile i32* null, i32** %base, align 4, !nontemporal !8
-  ; CHECK: store volatile ptr null, ptr %base, align 4, !nontemporal !8
+  ; CHECK: store volatile ptr null, ptr %base, align 4, !nontemporal !7
 
   ret void
 }
 
 ; Instructions -- Conversion Operations
 define void @instructions.conversions() {
   trunc i32 -1 to i1
   ; CHECK: trunc i32 -1 to i1

llvm/test/Bitcode/compatibility-3.9.ll

 !9 = !{i64 4}
 define void @instructions.memops(i32** %base) {
   alloca i32, i8 4, align 4
   ; CHECK: alloca i32, i8 4, align 4
   alloca inalloca i32, i8 4, align 4
   ; CHECK: alloca inalloca i32, i8 4, align 4
 
   load i32*, i32** %base, align 8, !invariant.load !7, !nontemporal !8, !nonnull !7, !dereferenceable !9, !dereferenceable_or_null !9
-  ; CHECK: load ptr, ptr %base, align 8, !invariant.load !7, !nontemporal !8, !nonnull !7, !dereferenceable !9, !dereferenceable_or_null !9
+  ; CHECK: load ptr, ptr %base, align 8, !invariant.load !8, !nontemporal !7, !nonnull !8, !dereferenceable !9, !dereferenceable_or_null !9, !freeze_bits !7
   load volatile i32*, i32** %base, align 8, !invariant.load !7, !nontemporal !8, !nonnull !7, !dereferenceable !9, !dereferenceable_or_null !9
-  ; CHECK: load volatile ptr, ptr %base, align 8, !invariant.load !7, !nontemporal !8, !nonnull !7, !dereferenceable !9, !dereferenceable_or_null !9
+  ; CHECK: load volatile ptr, ptr %base, align 8, !invariant.load !8, !nontemporal !7, !nonnull !8, !dereferenceable !9, !dereferenceable_or_null !9, !freeze_bits !7
 
   store i32* null, i32** %base, align 4, !nontemporal !8
-  ; CHECK: store ptr null, ptr %base, align 4, !nontemporal !8
+  ; CHECK: store ptr null, ptr %base, align 4, !nontemporal !7
   store volatile i32* null, i32** %base, align 4, !nontemporal !8
-  ; CHECK: store volatile ptr null, ptr %base, align 4, !nontemporal !8
+  ; CHECK: store volatile ptr null, ptr %base, align 4, !nontemporal !7
 
   ret void
 }
 
 ; Instructions -- Conversion Operations
 define void @instructions.conversions() {
   trunc i32 -1 to i1
   ; CHECK: trunc i32 -1 to i1

llvm/test/Bitcode/compatibility-4.0.ll

 !9 = !{i64 4}
 define void @instructions.memops(i32** %base) {
   alloca i32, i8 4, align 4
   ; CHECK: alloca i32, i8 4, align 4
   alloca inalloca i32, i8 4, align 4
   ; CHECK: alloca inalloca i32, i8 4, align 4
 
   load i32*, i32** %base, align 8, !invariant.load !7, !nontemporal !8, !nonnull !7, !dereferenceable !9, !dereferenceable_or_null !9
-  ; CHECK: load ptr, ptr %base, align 8, !invariant.load !7, !nontemporal !8, !nonnull !7, !dereferenceable !9, !dereferenceable_or_null !9
+  ; CHECK: load ptr, ptr %base, align 8, !invariant.load !8, !nontemporal !7, !nonnull !8, !dereferenceable !9, !dereferenceable_or_null !9, !freeze_bits !7
   load volatile i32*, i32** %base, align 8, !invariant.load !7, !nontemporal !8, !nonnull !7, !dereferenceable !9, !dereferenceable_or_null !9
-  ; CHECK: load volatile ptr, ptr %base, align 8, !invariant.load !7, !nontemporal !8, !nonnull !7, !dereferenceable !9, !dereferenceable_or_null !9
+  ; CHECK: load volatile ptr, ptr %base, align 8, !invariant.load !8, !nontemporal !7, !nonnull !8, !dereferenceable !9, !dereferenceable_or_null !9, !freeze_bits !7
 
   store i32* null, i32** %base, align 4, !nontemporal !8
-  ; CHECK: store ptr null, ptr %base, align 4, !nontemporal !8
+  ; CHECK: store ptr null, ptr %base, align 4, !nontemporal !7
   store volatile i32* null, i32** %base, align 4, !nontemporal !8
-  ; CHECK: store volatile ptr null, ptr %base, align 4, !nontemporal !8
+  ; CHECK: store volatile ptr null, ptr %base, align 4, !nontemporal !7
 
   ret void
 }
 
 ; Instructions -- Conversion Operations
 define void @instructions.conversions() {
   trunc i32 -1 to i1
   ; CHECK: trunc i32 -1 to i1

llvm/test/Bitcode/compatibility-5.0.ll

 !9 = !{i64 4}
 define void @instructions.memops(i32** %base) {
   alloca i32, i8 4, align 4
   ; CHECK: alloca i32, i8 4, align 4
   alloca inalloca i32, i8 4, align 4
   ; CHECK: alloca inalloca i32, i8 4, align 4
 
   load i32*, i32** %base, align 8, !invariant.load !7, !nontemporal !8, !nonnull !7, !dereferenceable !9, !dereferenceable_or_null !9
-  ; CHECK: load ptr, ptr %base, align 8, !invariant.load !7, !nontemporal !8, !nonnull !7, !dereferenceable !9, !dereferenceable_or_null !9
+  ; CHECK: load ptr, ptr %base, align 8, !invariant.load !8, !nontemporal !7, !nonnull !8, !dereferenceable !9, !dereferenceable_or_null !9, !freeze_bits !7
   load volatile i32*, i32** %base, align 8, !invariant.load !7, !nontemporal !8, !nonnull !7, !dereferenceable !9, !dereferenceable_or_null !9
-  ; CHECK: load volatile ptr, ptr %base, align 8, !invariant.load !7, !nontemporal !8, !nonnull !7, !dereferenceable !9, !dereferenceable_or_null !9
+  ; CHECK: load volatile ptr, ptr %base, align 8, !invariant.load !8, !nontemporal !7, !nonnull !8, !dereferenceable !9, !dereferenceable_or_null !9, !freeze_bits !7
 
   store i32* null, i32** %base, align 4, !nontemporal !8
-  ; CHECK: store ptr null, ptr %base, align 4, !nontemporal !8
+  ; CHECK: store ptr null, ptr %base, align 4, !nontemporal !7
   store volatile i32* null, i32** %base, align 4, !nontemporal !8
-  ; CHECK: store volatile ptr null, ptr %base, align 4, !nontemporal !8
+  ; CHECK: store volatile ptr null, ptr %base, align 4, !nontemporal !7
 
   ret void
 }
 
 ; Instructions -- Conversion Operations
 define void @instructions.conversions() {
   trunc i32 -1 to i1
   ; CHECK: trunc i32 -1 to i1

llvm/test/Bitcode/compatibility-6.0.ll

 !9 = !{i64 4}
 define void @instructions.memops(i32** %base) {
   alloca i32, i8 4, align 4
   ; CHECK: alloca i32, i8 4, align 4
   alloca inalloca i32, i8 4, align 4
   ; CHECK: alloca inalloca i32, i8 4, align 4
 
   load i32*, i32** %base, align 8, !invariant.load !7, !nontemporal !8, !nonnull !7, !dereferenceable !9, !dereferenceable_or_null !9
-  ; CHECK: load ptr, ptr %base, align 8, !invariant.load !7, !nontemporal !8, !nonnull !7, !dereferenceable !9, !dereferenceable_or_null !9
+  ; CHECK: load ptr, ptr %base, align 8, !invariant.load !8, !nontemporal !7, !nonnull !8, !dereferenceable !9, !dereferenceable_or_null !9, !freeze_bits !7
   load volatile i32*, i32** %base, align 8, !invariant.load !7, !nontemporal !8, !nonnull !7, !dereferenceable !9, !dereferenceable_or_null !9
-  ; CHECK: load volatile ptr, ptr %base, align 8, !invariant.load !7, !nontemporal !8, !nonnull !7, !dereferenceable !9, !dereferenceable_or_null !9
+  ; CHECK: load volatile ptr, ptr %base, align 8, !invariant.load !8, !nontemporal !7, !nonnull !8, !dereferenceable !9, !dereferenceable_or_null !9, !freeze_bits !7
 
   store i32* null, i32** %base, align 4, !nontemporal !8
-  ; CHECK: store ptr null, ptr %base, align 4, !nontemporal !8
+  ; CHECK: store ptr null, ptr %base, align 4, !nontemporal !7
   store volatile i32* null, i32** %base, align 4, !nontemporal !8
-  ; CHECK: store volatile ptr null, ptr %base, align 4, !nontemporal !8
+  ; CHECK: store volatile ptr null, ptr %base, align 4, !nontemporal !7
 
   ret void
 }
 
 ; Instructions -- Conversion Operations
 define void @instructions.conversions() {
   trunc i32 -1 to i1
   ; CHECK: trunc i32 -1 to i1

llvm/test/Bitcode/memInstructions.3.2.ll

; CHECK-NEXT: %res2 = load volatile i8, ptr %ptr1
   %res2 = load volatile i8, i8* %ptr1
 
 ; CHECK-NEXT: %res3 = load i8, ptr %ptr1, align 1
   %res3 = load i8, i8* %ptr1, align 1
 
 ; CHECK-NEXT: %res4 = load volatile i8, ptr %ptr1, align 1
   %res4 = load volatile i8, i8* %ptr1, align 1
 
-; CHECK-NEXT: %res5 = load i8, ptr %ptr1, align 1, !nontemporal !0
+; CHECK-NEXT: %res5 = load i8, ptr %ptr1, align 1, !nontemporal !1
   %res5 = load i8, i8* %ptr1, !nontemporal !0
 
-; CHECK-NEXT: %res6 = load volatile i8, ptr %ptr1, align 1, !nontemporal !0
+; CHECK-NEXT: %res6 = load volatile i8, ptr %ptr1, align 1, !nontemporal !1
   %res6 = load volatile i8, i8* %ptr1, !nontemporal !0
 
-; CHECK-NEXT: %res7 = load i8, ptr %ptr1, align 1, !nontemporal !0
+; CHECK-NEXT: %res7 = load i8, ptr %ptr1, align 1, !nontemporal !1
   %res7 = load i8, i8* %ptr1, align 1, !nontemporal !0
 
-; CHECK-NEXT: %res8 = load volatile i8, ptr %ptr1, align 1, !nontemporal !0
+; CHECK-NEXT: %res8 = load volatile i8, ptr %ptr1, align 1, !nontemporal !1
   %res8 = load volatile i8, i8* %ptr1, align 1, !nontemporal !0
 
-; CHECK-NEXT: %res9 = load i8, ptr %ptr1, align 1, !invariant.load !1
+; CHECK-NEXT: %res9 = load i8, ptr %ptr1, align 1, !invariant.load !0
   %res9 = load i8, i8* %ptr1, !invariant.load !1
 
-; CHECK-NEXT: %res10 = load volatile i8, ptr %ptr1, align 1, !invariant.load !1
+; CHECK-NEXT: %res10 = load volatile i8, ptr %ptr1, align 1, !invariant.load !0
   %res10 = load volatile i8, i8* %ptr1, !invariant.load !1
 
-; CHECK-NEXT: %res11 = load i8, ptr %ptr1, align 1, !invariant.load !1
+; CHECK-NEXT: %res11 = load i8, ptr %ptr1, align 1, !invariant.load !0
   %res11 = load i8, i8* %ptr1, align 1, !invariant.load !1
 
-; CHECK-NEXT: %res12 = load volatile i8, ptr %ptr1, align 1, !invariant.load !1
+; CHECK-NEXT: %res12 = load volatile i8, ptr %ptr1, align 1, !invariant.load !0
   %res12 = load volatile i8, i8* %ptr1, align 1, !invariant.load !1
 
-; CHECK-NEXT: %res13 = load i8, ptr %ptr1, {{[(!nontemporal !0, !invariant.load !1) | (!invariant.load !1, !nontemporal !0)]}}
+; CHECK-NEXT: %res13 = load i8, ptr %ptr1, {{[(!nontemporal !1, !invariant.load !0) | (!invariant.load !0, !nontemporal !1)]}}
   %res13 = load i8, i8* %ptr1, !nontemporal !0, !invariant.load !1
 
-; CHECK-NEXT: %res14 = load volatile i8, ptr %ptr1, {{[(!nontemporal !0, !invariant.load !1) | (!invariant.load !1, !nontemporal !0)]}}
+; CHECK-NEXT: %res14 = load volatile i8, ptr %ptr1, {{[(!nontemporal !1, !invariant.load !0) | (!invariant.load !0, !nontemporal !1)]}}
   %res14 = load volatile i8, i8* %ptr1, !nontemporal !0, !invariant.load !1
 
-; CHECK-NEXT: %res15 = load i8, ptr %ptr1, align 1, {{[(!nontemporal !0, !invariant.load !1) | (!invariant.load !1, !nontemporal !0)]}}
+; CHECK-NEXT: %res15 = load i8, ptr %ptr1, align 1, {{[(!nontemporal !1, !invariant.load !0) | (!invariant.load !0, !nontemporal !1)]}}
   %res15 = load i8, i8* %ptr1, align 1, !nontemporal !0, !invariant.load !1
 
-; CHECK-NEXT: %res16 = load volatile i8, ptr %ptr1, align 1, {{[(!nontemporal !0, !invariant.load !1) | (!invariant.load !1, !nontemporal !0)]}}
+; CHECK-NEXT: %res16 = load volatile i8, ptr %ptr1, align 1, {{[(!nontemporal !1, !invariant.load !0) | (!invariant.load !0, !nontemporal !1)]}}
   %res16 = load volatile i8, i8* %ptr1, align 1, !nontemporal !0, !invariant.load !1
 
   ret void
 }
 
 define void @loadAtomic(){
 entry:
   %ptr1 = alloca i8
; CHECK-NEXT: store volatile i8 2, ptr %ptr1
   store volatile i8 2, i8* %ptr1
 
 ; CHECK-NEXT: store i8 2, ptr %ptr1, align 1
   store i8 2, i8* %ptr1, align 1
 
 ; CHECK-NEXT: store volatile i8 2, ptr %ptr1, align 1
   store volatile i8 2, i8* %ptr1, align 1
 
-; CHECK-NEXT: store i8 2, ptr %ptr1, align 1, !nontemporal !0
+; CHECK-NEXT: store i8 2, ptr %ptr1, align 1, !nontemporal !1
   store i8 2, i8* %ptr1, !nontemporal !0
 
-; CHECK-NEXT: store volatile i8 2, ptr %ptr1, align 1, !nontemporal !0
+; CHECK-NEXT: store volatile i8 2, ptr %ptr1, align 1, !nontemporal !1
   store volatile i8 2, i8* %ptr1, !nontemporal !0
 
-; CHECK-NEXT: store i8 2, ptr %ptr1, align 1, !nontemporal !0
+; CHECK-NEXT: store i8 2, ptr %ptr1, align 1, !nontemporal !1
   store i8 2, i8* %ptr1, align 1, !nontemporal !0
 
-; CHECK-NEXT: store volatile i8 2, ptr %ptr1, align 1, !nontemporal !0
+; CHECK-NEXT: store volatile i8 2, ptr %ptr1, align 1, !nontemporal !1
   store volatile i8 2, i8* %ptr1, align 1, !nontemporal !0
 
   ret void
 }
 
 define void @storeAtomic(){
 entry:
   %ptr1 = alloca i8

llvm/test/Bitcode/upgrade-loadv1-loadv2.ll

+; RUN: llvm-dis < %s.bc | FileCheck %s
+
+; Test auto-upgrade of bitcode from load v1 to load v2. This test uses a
+; non-standard value for !nonnull, which is not an empty metadata value. This
+; distinguishes that all metadata references are correctly updated.
+
+%array = type [10 x ptr]
+
+; CHECK: define i32 @loadPtrPtr(ptr noundef %a)
+; CHECK-NEXT: entry:
+; CHECK-NEXT: %a.0.ptr = getelementptr inbounds [10 x ptr], ptr %a, i64 0, i64 0, !noundef [[NOUNDEF:![0-9]+]]
+; CHECK-NEXT: %v.ptr = load ptr, ptr %a.0.ptr, align 8, !nonnull [[NONNULL:![0-9]+]], !noundef [[NOUNDEF]], !freeze_bits [[NOUNDEF]]
+; CHECK-NEXT: %v = load i32, ptr %v.ptr, align 8, !freeze_bits [[NOUNDEF]]
+; CHECK-NEXT: ret i32 %v
+define i32 @loadPtrPtr(ptr noundef %a) {
+  %a.0.ptr = getelementptr inbounds %array, ptr %a, i64 0, i64 0, !noundef !1
+  %v.ptr = load ptr, ptr %a.0.ptr, align 8, !nonnull !0, !noundef !1
+  %v = load i32, ptr %v.ptr, align 8
+  ret i32 %v
+}
+
+; CHECK: [[NOUNDEF]] = !{}
+; CHECK: [[NONNULL]] = !{i32 1}
+!0 = !{i32 1}
+!1 = !{}

llvm/tools/llvm-c-test/calc.c

case '@': {
 
       if (depth < 1) {
         printf("stack underflow\n");
         return NULL;
       }
 
       LLVMTypeRef ty = LLVMInt64Type();
       off = LLVMBuildGEP2(builder, ty, param, &stack[depth - 1], 1, "");
-      stack[depth - 1] = LLVMBuildLoad2(builder, ty, off, "");
+      stack[depth - 1] = LLVMBuildLoad3(builder, ty, off, "");
 
       break;
     }
 
     default: {
       char *end;
       long val = strtol(tokens[i], &end, 0);
       if (end[0] != '\0') {

llvm/tools/llvm-c-test/echo.cpp

switch(Op) {
       case LLVMAlloca: {
         LLVMTypeRef Ty = CloneType(LLVMGetAllocatedType(Src));
         Dst = LLVMBuildAlloca(Builder, Ty, Name);
         LLVMSetAlignment(Dst, LLVMGetAlignment(Src));
         break;
       }
       case LLVMLoad: {
         LLVMValueRef Ptr = CloneValue(LLVMGetOperand(Src, 0));
-        Dst = LLVMBuildLoad2(Builder, CloneType(Src), Ptr, Name);
+        Dst = LLVMBuildLoad3(Builder, CloneType(Src), Ptr, Name);
         LLVMSetAlignment(Dst, LLVMGetAlignment(Src));
         LLVMSetOrdering(Dst, LLVMGetOrdering(Src));
         LLVMSetVolatile(Dst, LLVMGetVolatile(Src));
         break;
       }
       case LLVMStore: {
         LLVMValueRef Val = CloneValue(LLVMGetOperand(Src, 0));
         LLVMValueRef Ptr = CloneValue(LLVMGetOperand(Src, 1));

llvm/unittests/ExecutionEngine/MCJIT/MCJITCAPITest.cpp

LLVMSetInitializer(GlobalVar, LLVMConstInt(LLVMInt32Type(), 42, 0));
                               LLVMFunctionType(LLVMInt32Type(), nullptr, 0, 0));
         LLVMSetFunctionCallConv(Function, LLVMCCallConv);
         
         LLVMBasicBlockRef Entry = LLVMAppendBasicBlock(Function, "entry");
         LLVMBuilderRef Builder = LLVMCreateBuilder();
         LLVMPositionBuilderAtEnd(Builder, Entry);
         
         LLVMValueRef IntVal =
-            LLVMBuildLoad2(Builder, LLVMInt32Type(), GlobalVar, "intVal");
+            LLVMBuildLoad3(Builder, LLVMInt32Type(), GlobalVar, "intVal");
         LLVMBuildRet(Builder, IntVal);
         
         LLVMVerifyModule(Module, LLVMAbortProcessAction, &Error);
         LLVMDisposeMessage(Error);
         
         LLVMDisposeBuilder(Builder);
     }