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Differential D158343

WIP: [UpdateTestChecks] Add update test check support for freeze_bits metadata
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Authored by jmciver on Aug 19 2023, 11:55 AM.
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Summary

Part of a sequence of exploratory patches using poison semantics for
uninitialized memory.

Add freeze_bits metadata support to update test check utilities.

Diff Detail

Unit TestsFailed

TimeTest
70 msx64 debian > Clang.CodeGen::aarch64-ls64-inline-asm.c
90 msx64 debian > Clang.CodeGen::aarch64-ls64.c
940 msx64 debian > Clang.CodeGen::aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
70 msx64 debian > Clang.CodeGen::asm-goto2.c
540 msx64 debian > Clang.CodeGen::matrix-type-operators.c
View Full Test Results (109 Failed)

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jmciver created this revision.Aug 19 2023, 11:55 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 19 2023, 11:55 AM
Herald added subscribers: luismarques, jdoerfert, arichardson. · View Herald Transcript
jmciver added a parent revision: D158342: WIP: [Bitcode][C-API][IR] Introduce bitcode load version 2 and freeze_bits metadata.Aug 19 2023, 11:55 AM
jmciver retitled this revision from WIP: [UpdateTestChecks] Add update test check support for freeze_bits metadata Part of a sequence of exploratory patches using poison semantics for uninitialized memory. to WIP: [UpdateTestChecks] Add update test check support for freeze_bits metadata.Aug 19 2023, 11:58 AM
jmciver edited the summary of this revision. (Show Details)
jmciver added a child revision: D158344: WIP: [UpdateTestChecks] Add update test check support for fpmath metadata.
Harbormaster completed remote builds in B253678: Diff 551780.Aug 19 2023, 12:44 PM
jmciver added a subscriber: nlopes.Aug 19 2023, 8:09 PM
jmciver edited the summary of this revision. (Show Details)Aug 19 2023, 8:23 PM
jmciver published this revision for review.Aug 21 2023, 10:05 AM
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Revision Contents

Diff 551780

clang/test/utils/update_cc_test_checks/Inputs/basic-cplusplus.cpp.expected

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// Basic C++ test for update_cc_test_checks // Basic C++ test for update_cc_test_checks
// RUN: %clang_cc1 -triple=x86_64-unknown-linux-gnu -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -triple=x86_64-unknown-linux-gnu -emit-llvm -o - %s | FileCheck %s
class Foo { class Foo {
int x; int x;
public: public:
explicit Foo(int x); explicit Foo(int x);
~Foo(); ~Foo();
// CHECK-LABEL: @_ZNK3Foo23function_defined_inlineEi( // CHECK-LABEL: @_ZNK3Foo23function_defined_inlineEi(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8
// CHECK-NEXT: store i32 [[ARG:%.*]], ptr [[ARG_ADDR]], align 4 // CHECK-NEXT: store i32 [[ARG:%.*]], ptr [[ARG_ADDR]], align 4
// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !freeze_bits [[FREEZE_BITS2:![0-9]+]]
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARG_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARG_ADDR]], align 4, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: [[X:%.*]] = getelementptr inbounds [[CLASS_FOO:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK-NEXT: [[X:%.*]] = getelementptr inbounds [[CLASS_FOO:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[X]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[X]], align 4, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] // CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
// CHECK-NEXT: ret i32 [[ADD]] // CHECK-NEXT: ret i32 [[ADD]]
// //
inline int function_defined_inline(int arg) const { inline int function_defined_inline(int arg) const {
return arg + x; return arg + x;
} }
inline int function_defined_out_of_line(int arg) const; inline int function_defined_out_of_line(int arg) const;
}; };
// CHECK-LABEL: @_ZN3FooC1Ei( // CHECK-LABEL: @_ZN3FooC1Ei(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8
// CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4 // CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4
// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: call void @_ZN3FooC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) // CHECK-NEXT: call void @_ZN3FooC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// //
Foo::Foo(int x) : x(x) {} Foo::Foo(int x) : x(x) {}
// CHECK-LABEL: @_ZN3FooD1Ev( // CHECK-LABEL: @_ZN3FooD1Ev(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8
// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: call void @_ZN3FooD2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3:[0-9]+]] // CHECK-NEXT: call void @_ZN3FooD2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3:[0-9]+]]
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// //
Foo::~Foo() {} Foo::~Foo() {}
// CHECK-LABEL: @_ZNK3Foo28function_defined_out_of_lineEi( // CHECK-LABEL: @_ZNK3Foo28function_defined_out_of_lineEi(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8
// CHECK-NEXT: store i32 [[ARG:%.*]], ptr [[ARG_ADDR]], align 4 // CHECK-NEXT: store i32 [[ARG:%.*]], ptr [[ARG_ADDR]], align 4
// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: [[X:%.*]] = getelementptr inbounds [[CLASS_FOO:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK-NEXT: [[X:%.*]] = getelementptr inbounds [[CLASS_FOO:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X]], align 4, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARG_ADDR]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARG_ADDR]], align 4, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] // CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]]
// CHECK-NEXT: ret i32 [[SUB]] // CHECK-NEXT: ret i32 [[SUB]]
// //
int Foo::function_defined_out_of_line(int arg) const { return x - arg; } int Foo::function_defined_out_of_line(int arg) const { return x - arg; }
// Call the inline methods to ensure the LLVM IR is generated: // Call the inline methods to ensure the LLVM IR is generated:
// CHECK-LABEL: @main( // CHECK-LABEL: @main(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
Show All 12 Lines

clang/test/utils/update_cc_test_checks/Inputs/check-attributes.cpp.funcattrs.expected

Show All 10 Linesstruct ST {
struct RT Z; struct RT Z;
}; };
// CHECK: Function Attrs: mustprogress noinline nounwind optnone // CHECK: Function Attrs: mustprogress noinline nounwind optnone
// CHECK-LABEL: @_Z3fooP2ST( // CHECK-LABEL: @_Z3fooP2ST(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: store ptr [[S:%.*]], ptr [[S_ADDR]], align 8 // CHECK-NEXT: store ptr [[S:%.*]], ptr [[S_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8, !freeze_bits [[FREEZE_BITS2:![0-9]+]]
// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP0]], i64 1 // CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP0]], i64 1
// CHECK-NEXT: [[Z:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[ARRAYIDX]], i32 0, i32 2 // CHECK-NEXT: [[Z:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[ARRAYIDX]], i32 0, i32 2
// CHECK-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_RT:%.*]], ptr [[Z]], i32 0, i32 1 // CHECK-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_RT:%.*]], ptr [[Z]], i32 0, i32 1
// CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [10 x [20 x i32]], ptr [[B]], i64 0, i64 5 // CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [10 x [20 x i32]], ptr [[B]], i64 0, i64 5
// CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [20 x i32], ptr [[ARRAYIDX1]], i64 0, i64 13 // CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [20 x i32], ptr [[ARRAYIDX1]], i64 0, i64 13
// CHECK-NEXT: ret ptr [[ARRAYIDX2]] // CHECK-NEXT: ret ptr [[ARRAYIDX2]]
// //
int *foo(struct ST *s) { int *foo(struct ST *s) {
return &s[1].Z.B[5][13]; return &s[1].Z.B[5][13];
} }

clang/test/utils/update_cc_test_checks/Inputs/check-attributes.cpp.plain.expected

Show All 9 Linesstruct ST {
double Y; double Y;
struct RT Z; struct RT Z;
}; };
// CHECK-LABEL: @_Z3fooP2ST( // CHECK-LABEL: @_Z3fooP2ST(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: store ptr [[S:%.*]], ptr [[S_ADDR]], align 8 // CHECK-NEXT: store ptr [[S:%.*]], ptr [[S_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8, !freeze_bits [[FREEZE_BITS2:![0-9]+]]
// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP0]], i64 1 // CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP0]], i64 1
// CHECK-NEXT: [[Z:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[ARRAYIDX]], i32 0, i32 2 // CHECK-NEXT: [[Z:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[ARRAYIDX]], i32 0, i32 2
// CHECK-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_RT:%.*]], ptr [[Z]], i32 0, i32 1 // CHECK-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_RT:%.*]], ptr [[Z]], i32 0, i32 1
// CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [10 x [20 x i32]], ptr [[B]], i64 0, i64 5 // CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [10 x [20 x i32]], ptr [[B]], i64 0, i64 5
// CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [20 x i32], ptr [[ARRAYIDX1]], i64 0, i64 13 // CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [20 x i32], ptr [[ARRAYIDX1]], i64 0, i64 13
// CHECK-NEXT: ret ptr [[ARRAYIDX2]] // CHECK-NEXT: ret ptr [[ARRAYIDX2]]
// //
int *foo(struct ST *s) { int *foo(struct ST *s) {
return &s[1].Z.B[5][13]; return &s[1].Z.B[5][13];
} }

clang/test/utils/update_cc_test_checks/Inputs/def-and-decl.c.expected

Show All 17 Linesint main(void) {
empty_function(); empty_function();
return foo(1); return foo(1);
} }
// CHECK-LABEL: @foo( // CHECK-LABEL: @foo(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[ARG:%.*]], ptr [[ARG_ADDR]], align 4 // CHECK-NEXT: store i32 [[ARG:%.*]], ptr [[ARG_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARG_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARG_ADDR]], align 4, !freeze_bits [[FREEZE_BITS2:![0-9]+]]
// CHECK-NEXT: ret i32 [[TMP0]] // CHECK-NEXT: ret i32 [[TMP0]]
// //
int foo(int arg) { int foo(int arg) {
return arg; return arg;
} }
// CHECK-LABEL: @empty_function( // CHECK-LABEL: @empty_function(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// //
void empty_function(void) {} void empty_function(void) {}

clang/test/utils/update_cc_test_checks/Inputs/explicit-template-instantiation.cpp.expected

Show All 36 Lines
// These two specializations should generate lines for all of Foo's methods. // These two specializations should generate lines for all of Foo's methods.
// CHECK-LABEL: @_ZN3FooIcEC1Ec( // CHECK-LABEL: @_ZN3FooIcEC1Ec(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i8, align 1 // CHECK-NEXT: [[X_ADDR:%.*]] = alloca i8, align 1
// CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8
// CHECK-NEXT: store i8 [[X:%.*]], ptr [[X_ADDR]], align 1 // CHECK-NEXT: store i8 [[X:%.*]], ptr [[X_ADDR]], align 1
// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !freeze_bits [[FREEZE_BITS2:![0-9]+]]
// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[X_ADDR]], align 1 // CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[X_ADDR]], align 1, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: call void @_ZN3FooIcEC2Ec(ptr noundef nonnull align 1 dereferenceable(1) [[THIS1]], i8 noundef signext [[TMP0]]) // CHECK-NEXT: call void @_ZN3FooIcEC2Ec(ptr noundef nonnull align 1 dereferenceable(1) [[THIS1]], i8 noundef signext [[TMP0]])
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// //
// CHECK-LABEL: @_ZN3FooIcED1Ev( // CHECK-LABEL: @_ZN3FooIcED1Ev(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8
// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: call void @_ZN3FooIcED2Ev(ptr noundef nonnull align 1 dereferenceable(1) [[THIS1]]) #[[ATTR2:[0-9]+]] // CHECK-NEXT: call void @_ZN3FooIcED2Ev(ptr noundef nonnull align 1 dereferenceable(1) [[THIS1]]) #[[ATTR2:[0-9]+]]
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// //
// CHECK-LABEL: @_ZN3FooIcE3getEv( // CHECK-LABEL: @_ZN3FooIcE3getEv(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8
// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_FOO:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_FOO:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[X]], align 1 // CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[X]], align 1, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: ret i8 [[TMP0]] // CHECK-NEXT: ret i8 [[TMP0]]
// //
// CHECK-LABEL: @_ZN3FooIcE3setEc( // CHECK-LABEL: @_ZN3FooIcE3setEc(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: [[_X_ADDR:%.*]] = alloca i8, align 1 // CHECK-NEXT: [[_X_ADDR:%.*]] = alloca i8, align 1
// CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8
// CHECK-NEXT: store i8 [[_X:%.*]], ptr [[_X_ADDR]], align 1 // CHECK-NEXT: store i8 [[_X:%.*]], ptr [[_X_ADDR]], align 1
// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[_X_ADDR]], align 1 // CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[_X_ADDR]], align 1, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_FOO:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_FOO:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK-NEXT: store i8 [[TMP0]], ptr [[X]], align 1 // CHECK-NEXT: store i8 [[TMP0]], ptr [[X]], align 1
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// //
template struct Foo<char>; template struct Foo<char>;
// CHECK-LABEL: @_ZN3FooIsEC1Es( // CHECK-LABEL: @_ZN3FooIsEC1Es(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i16, align 2 // CHECK-NEXT: [[X_ADDR:%.*]] = alloca i16, align 2
// CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8
// CHECK-NEXT: store i16 [[X:%.*]], ptr [[X_ADDR]], align 2 // CHECK-NEXT: store i16 [[X:%.*]], ptr [[X_ADDR]], align 2
// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[X_ADDR]], align 2 // CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[X_ADDR]], align 2, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: call void @_ZN3FooIsEC2Es(ptr noundef nonnull align 2 dereferenceable(2) [[THIS1]], i16 noundef signext [[TMP0]]) // CHECK-NEXT: call void @_ZN3FooIsEC2Es(ptr noundef nonnull align 2 dereferenceable(2) [[THIS1]], i16 noundef signext [[TMP0]])
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// //
// CHECK-LABEL: @_ZN3FooIsED1Ev( // CHECK-LABEL: @_ZN3FooIsED1Ev(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8
// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: call void @_ZN3FooIsED2Ev(ptr noundef nonnull align 2 dereferenceable(2) [[THIS1]]) #[[ATTR2]] // CHECK-NEXT: call void @_ZN3FooIsED2Ev(ptr noundef nonnull align 2 dereferenceable(2) [[THIS1]]) #[[ATTR2]]
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// //
// CHECK-LABEL: @_ZN3FooIsE3getEv( // CHECK-LABEL: @_ZN3FooIsE3getEv(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8
// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_FOO_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_FOO_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[X]], align 2 // CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[X]], align 2, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: ret i16 [[TMP0]] // CHECK-NEXT: ret i16 [[TMP0]]
// //
// CHECK-LABEL: @_ZN3FooIsE3setEs( // CHECK-LABEL: @_ZN3FooIsE3setEs(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: [[_X_ADDR:%.*]] = alloca i16, align 2 // CHECK-NEXT: [[_X_ADDR:%.*]] = alloca i16, align 2
// CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8
// CHECK-NEXT: store i16 [[_X:%.*]], ptr [[_X_ADDR]], align 2 // CHECK-NEXT: store i16 [[_X:%.*]], ptr [[_X_ADDR]], align 2
// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[_X_ADDR]], align 2 // CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[_X_ADDR]], align 2, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_FOO_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_FOO_0:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK-NEXT: store i16 [[TMP0]], ptr [[X]], align 2 // CHECK-NEXT: store i16 [[TMP0]], ptr [[X]], align 2
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// //
template struct Foo<short>; template struct Foo<short>;
// This should not generate lines for the implicit specialization of Foo, but // This should not generate lines for the implicit specialization of Foo, but
// should generate lines for the explicit specialization of Bar. // should generate lines for the explicit specialization of Bar.
// CHECK-LABEL: @_ZN3BarIiEC1Ei( // CHECK-LABEL: @_ZN3BarIiEC1Ei(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8
// CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4 // CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4
// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: call void @_ZN3BarIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) // CHECK-NEXT: call void @_ZN3BarIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// //
// CHECK-LABEL: @_ZN3BarIiED1Ev( // CHECK-LABEL: @_ZN3BarIiED1Ev(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8
// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: call void @_ZN3BarIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK-NEXT: call void @_ZN3BarIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// //
// CHECK-LABEL: @_ZN3BarIiE3getEv( // CHECK-LABEL: @_ZN3BarIiE3getEv(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8
// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: [[FOO:%.*]] = getelementptr inbounds [[STRUCT_BAR:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK-NEXT: [[FOO:%.*]] = getelementptr inbounds [[STRUCT_BAR:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN3FooIiE3getEv(ptr noundef nonnull align 4 dereferenceable(4) [[FOO]]) // CHECK-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN3FooIiE3getEv(ptr noundef nonnull align 4 dereferenceable(4) [[FOO]])
// CHECK-NEXT: ret i32 [[CALL]] // CHECK-NEXT: ret i32 [[CALL]]
// //
// CHECK-LABEL: @_ZN3BarIiE3setEi( // CHECK-LABEL: @_ZN3BarIiE3setEi(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: [[_X_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[_X_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8
// CHECK-NEXT: store i32 [[_X:%.*]], ptr [[_X_ADDR]], align 4 // CHECK-NEXT: store i32 [[_X:%.*]], ptr [[_X_ADDR]], align 4
// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: [[FOO:%.*]] = getelementptr inbounds [[STRUCT_BAR:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK-NEXT: [[FOO:%.*]] = getelementptr inbounds [[STRUCT_BAR:%.*]], ptr [[THIS1]], i32 0, i32 0
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[_X_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[_X_ADDR]], align 4, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: call void @_ZN3FooIiE3setEi(ptr noundef nonnull align 4 dereferenceable(4) [[FOO]], i32 noundef [[TMP0]]) // CHECK-NEXT: call void @_ZN3FooIiE3setEi(ptr noundef nonnull align 4 dereferenceable(4) [[FOO]], i32 noundef [[TMP0]])
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// //
template struct Bar<int>; template struct Bar<int>;
// This should not generate lines for the implicit specialization of Foo, but // This should not generate lines for the implicit specialization of Foo, but
// should generate lines for the explicit specialization of Baz. // should generate lines for the explicit specialization of Baz.
// CHECK-LABEL: @_ZN3BazIlEC1El( // CHECK-LABEL: @_ZN3BazIlEC1El(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i64, align 8 // CHECK-NEXT: [[X_ADDR:%.*]] = alloca i64, align 8
// CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8
// CHECK-NEXT: store i64 [[X:%.*]], ptr [[X_ADDR]], align 8 // CHECK-NEXT: store i64 [[X:%.*]], ptr [[X_ADDR]], align 8
// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[X_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[X_ADDR]], align 8, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: call void @_ZN3BazIlEC2El(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]], i64 noundef [[TMP0]]) // CHECK-NEXT: call void @_ZN3BazIlEC2El(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]], i64 noundef [[TMP0]])
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// //
// CHECK-LABEL: @_ZN3BazIlED1Ev( // CHECK-LABEL: @_ZN3BazIlED1Ev(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8
// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: call void @_ZN3BazIlED2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK-NEXT: call void @_ZN3BazIlED2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR2]]
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// //
template struct Baz<long>; template struct Baz<long>;

clang/test/utils/update_cc_test_checks/Inputs/generated-funcs-regex.c.expected

Show All 12 Linesvoid foo(int a)
int somevar_abc123_; int somevar_abc123_;
} }
// CHECK-LABEL: @foo( // CHECK-LABEL: @foo(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK-NEXT: %{{somevar_[a-z0-9]+_}} = alloca i32, align 4 // CHECK-NEXT: %{{somevar_[a-z0-9]+_}} = alloca i32, align 4
// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 // CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !freeze_bits [[FREEZE_BITS3:![0-9]+]]
// CHECK-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 // CHECK-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 // CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8, !freeze_bits [[FREEZE_BITS3]]
// CHECK-NEXT: call void @{{__omp_offloading_[a-z0-9]+_[a-z0-9]+_foo_l[0-9]+}}(i64 [[TMP1]]) #[[ATTR3:[0-9]+]] // CHECK-NEXT: call void @{{__omp_offloading_[a-z0-9]+_[a-z0-9]+_foo_l[0-9]+}}(i64 [[TMP1]]) #[[ATTR3:[0-9]+]]
// CHECK-NEXT: call void @{{__test_offloading_[a-z0-9]+_[a-z0-9]+_bar_l[0-9]+}}() // CHECK-NEXT: call void @{{__test_offloading_[a-z0-9]+_[a-z0-9]+_bar_l[0-9]+}}()
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// //
// //
// CHECK-LABEL: @{{__omp_offloading_[a-z0-9]+_[a-z0-9]+_foo_l[0-9]+}}( // CHECK-LABEL: @{{__omp_offloading_[a-z0-9]+_[a-z0-9]+_foo_l[0-9]+}}(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 8 // CHECK-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !freeze_bits [[FREEZE_BITS3]]
// CHECK-NEXT: call void @use(i32 noundef [[TMP0]]) // CHECK-NEXT: call void @use(i32 noundef [[TMP0]])
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// //

clang/test/utils/update_cc_test_checks/Inputs/generated-funcs.c.generated.expected

Show First 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
// OMP-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // OMP-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// OMP-NEXT: [[I:%.*]] = alloca i32, align 4 // OMP-NEXT: [[I:%.*]] = alloca i32, align 4
// OMP-NEXT: store ptr [[DOTGLOBAL_TID_:%.*]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // OMP-NEXT: store ptr [[DOTGLOBAL_TID_:%.*]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// OMP-NEXT: store ptr [[DOTBOUND_TID_:%.*]], ptr [[DOTBOUND_TID__ADDR]], align 8 // OMP-NEXT: store ptr [[DOTBOUND_TID_:%.*]], ptr [[DOTBOUND_TID__ADDR]], align 8
// OMP-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // OMP-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// OMP-NEXT: store i32 33554431, ptr [[DOTOMP_UB]], align 4 // OMP-NEXT: store i32 33554431, ptr [[DOTOMP_UB]], align 4
// OMP-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // OMP-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// OMP-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // OMP-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// OMP-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // OMP-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !freeze_bits [[FREEZE_BITS3:![0-9]+]]
// OMP-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 // OMP-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4, !freeze_bits [[FREEZE_BITS3]]
// OMP-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) // OMP-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
// OMP-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // OMP-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !freeze_bits [[FREEZE_BITS3]]
// OMP-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 33554431 // OMP-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 33554431
// OMP-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // OMP-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// OMP: cond.true: // OMP: cond.true:
// OMP-NEXT: br label [[COND_END:%.*]] // OMP-NEXT: br label [[COND_END:%.*]]
// OMP: cond.false: // OMP: cond.false:
// OMP-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // OMP-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !freeze_bits [[FREEZE_BITS3]]
// OMP-NEXT: br label [[COND_END]] // OMP-NEXT: br label [[COND_END]]
// OMP: cond.end: // OMP: cond.end:
// OMP-NEXT: [[COND:%.*]] = phi i32 [ 33554431, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] // OMP-NEXT: [[COND:%.*]] = phi i32 [ 33554431, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
// OMP-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 // OMP-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
// OMP-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // OMP-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !freeze_bits [[FREEZE_BITS3]]
// OMP-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // OMP-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// OMP-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // OMP-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// OMP: omp.inner.for.cond: // OMP: omp.inner.for.cond:
// OMP-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // OMP-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !freeze_bits [[FREEZE_BITS3]]
// OMP-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // OMP-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !freeze_bits [[FREEZE_BITS3]]
// OMP-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // OMP-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// OMP-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // OMP-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// OMP: omp.inner.for.body: // OMP: omp.inner.for.body:
// OMP-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // OMP-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !freeze_bits [[FREEZE_BITS3]]
// OMP-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // OMP-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// OMP-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // OMP-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// OMP-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // OMP-NEXT: store i32 [[ADD]], ptr [[I]], align 4
// OMP-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4 // OMP-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4, !freeze_bits [[FREEZE_BITS3]]
// OMP-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP8]] to i64 // OMP-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP8]] to i64
// OMP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [33554432 x double], ptr @A, i64 0, i64 [[IDXPROM]] // OMP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [33554432 x double], ptr @A, i64 0, i64 [[IDXPROM]]
// OMP-NEXT: store double 0.000000e+00, ptr [[ARRAYIDX]], align 8 // OMP-NEXT: store double 0.000000e+00, ptr [[ARRAYIDX]], align 8
// OMP-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // OMP-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// OMP: omp.body.continue: // OMP: omp.body.continue:
// OMP-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // OMP-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// OMP: omp.inner.for.inc: // OMP: omp.inner.for.inc:
// OMP-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // OMP-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !freeze_bits [[FREEZE_BITS3]]
// OMP-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 // OMP-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// OMP-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4 // OMP-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4
// OMP-NEXT: br label [[OMP_INNER_FOR_COND]] // OMP-NEXT: br label [[OMP_INNER_FOR_COND]]
// OMP: omp.inner.for.end: // OMP: omp.inner.for.end:
// OMP-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // OMP-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// OMP: omp.loop.exit: // OMP: omp.loop.exit:
// OMP-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) // OMP-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
// OMP-NEXT: ret void // OMP-NEXT: ret void
Show All 19 Lines
// OMP-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // OMP-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// OMP-NEXT: [[I:%.*]] = alloca i32, align 4 // OMP-NEXT: [[I:%.*]] = alloca i32, align 4
// OMP-NEXT: store ptr [[DOTGLOBAL_TID_:%.*]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // OMP-NEXT: store ptr [[DOTGLOBAL_TID_:%.*]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// OMP-NEXT: store ptr [[DOTBOUND_TID_:%.*]], ptr [[DOTBOUND_TID__ADDR]], align 8 // OMP-NEXT: store ptr [[DOTBOUND_TID_:%.*]], ptr [[DOTBOUND_TID__ADDR]], align 8
// OMP-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // OMP-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// OMP-NEXT: store i32 33554431, ptr [[DOTOMP_UB]], align 4 // OMP-NEXT: store i32 33554431, ptr [[DOTOMP_UB]], align 4
// OMP-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // OMP-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// OMP-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // OMP-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// OMP-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // OMP-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !freeze_bits [[FREEZE_BITS3]]
// OMP-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 // OMP-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4, !freeze_bits [[FREEZE_BITS3]]
// OMP-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) // OMP-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
// OMP-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // OMP-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !freeze_bits [[FREEZE_BITS3]]
// OMP-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 33554431 // OMP-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 33554431
// OMP-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // OMP-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// OMP: cond.true: // OMP: cond.true:
// OMP-NEXT: br label [[COND_END:%.*]] // OMP-NEXT: br label [[COND_END:%.*]]
// OMP: cond.false: // OMP: cond.false:
// OMP-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // OMP-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !freeze_bits [[FREEZE_BITS3]]
// OMP-NEXT: br label [[COND_END]] // OMP-NEXT: br label [[COND_END]]
// OMP: cond.end: // OMP: cond.end:
// OMP-NEXT: [[COND:%.*]] = phi i32 [ 33554431, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] // OMP-NEXT: [[COND:%.*]] = phi i32 [ 33554431, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
// OMP-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 // OMP-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
// OMP-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // OMP-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !freeze_bits [[FREEZE_BITS3]]
// OMP-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // OMP-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// OMP-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // OMP-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// OMP: omp.inner.for.cond: // OMP: omp.inner.for.cond:
// OMP-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // OMP-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !freeze_bits [[FREEZE_BITS3]]
// OMP-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // OMP-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !freeze_bits [[FREEZE_BITS3]]
// OMP-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // OMP-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// OMP-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // OMP-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// OMP: omp.inner.for.body: // OMP: omp.inner.for.body:
// OMP-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // OMP-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !freeze_bits [[FREEZE_BITS3]]
// OMP-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // OMP-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// OMP-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // OMP-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// OMP-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // OMP-NEXT: store i32 [[ADD]], ptr [[I]], align 4
// OMP-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4 // OMP-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4, !freeze_bits [[FREEZE_BITS3]]
// OMP-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP8]] to i64 // OMP-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP8]] to i64
// OMP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [33554432 x double], ptr @A, i64 0, i64 [[IDXPROM]] // OMP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [33554432 x double], ptr @A, i64 0, i64 [[IDXPROM]]
// OMP-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX]], align 8 // OMP-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX]], align 8
// OMP-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // OMP-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// OMP: omp.body.continue: // OMP: omp.body.continue:
// OMP-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // OMP-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// OMP: omp.inner.for.inc: // OMP: omp.inner.for.inc:
// OMP-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // OMP-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !freeze_bits [[FREEZE_BITS3]]
// OMP-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 // OMP-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// OMP-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4 // OMP-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4
// OMP-NEXT: br label [[OMP_INNER_FOR_COND]] // OMP-NEXT: br label [[OMP_INNER_FOR_COND]]
// OMP: omp.inner.for.end: // OMP: omp.inner.for.end:
// OMP-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // OMP-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// OMP: omp.loop.exit: // OMP: omp.loop.exit:
// OMP-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) // OMP-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
// OMP-NEXT: ret void // OMP-NEXT: ret void
// //
// //
// NOOMP-LABEL: @main( // NOOMP-LABEL: @main(
// NOOMP-NEXT: entry: // NOOMP-NEXT: entry:
// NOOMP-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // NOOMP-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
// NOOMP-NEXT: [[I:%.*]] = alloca i32, align 4 // NOOMP-NEXT: [[I:%.*]] = alloca i32, align 4
// NOOMP-NEXT: store i32 0, ptr [[RETVAL]], align 4 // NOOMP-NEXT: store i32 0, ptr [[RETVAL]], align 4
// NOOMP-NEXT: store i32 0, ptr [[I]], align 4 // NOOMP-NEXT: store i32 0, ptr [[I]], align 4
// NOOMP-NEXT: store i32 0, ptr [[I]], align 4 // NOOMP-NEXT: store i32 0, ptr [[I]], align 4
// NOOMP-NEXT: br label [[FOR_COND:%.*]] // NOOMP-NEXT: br label [[FOR_COND:%.*]]
// NOOMP: for.cond: // NOOMP: for.cond:
// NOOMP-NEXT: [[TMP0:%.*]] = load i32, ptr [[I]], align 4 // NOOMP-NEXT: [[TMP0:%.*]] = load i32, ptr [[I]], align 4, !freeze_bits [[FREEZE_BITS2:![0-9]+]]
// NOOMP-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 33554432 // NOOMP-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 33554432
// NOOMP-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] // NOOMP-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
// NOOMP: for.body: // NOOMP: for.body:
// NOOMP-NEXT: [[TMP1:%.*]] = load i32, ptr [[I]], align 4 // NOOMP-NEXT: [[TMP1:%.*]] = load i32, ptr [[I]], align 4, !freeze_bits [[FREEZE_BITS2]]
// NOOMP-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 // NOOMP-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64
// NOOMP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [33554432 x double], ptr @A, i64 0, i64 [[IDXPROM]] // NOOMP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [33554432 x double], ptr @A, i64 0, i64 [[IDXPROM]]
// NOOMP-NEXT: store double 0.000000e+00, ptr [[ARRAYIDX]], align 8 // NOOMP-NEXT: store double 0.000000e+00, ptr [[ARRAYIDX]], align 8
// NOOMP-NEXT: br label [[FOR_INC:%.*]] // NOOMP-NEXT: br label [[FOR_INC:%.*]]
// NOOMP: for.inc: // NOOMP: for.inc:
// NOOMP-NEXT: [[TMP2:%.*]] = load i32, ptr [[I]], align 4 // NOOMP-NEXT: [[TMP2:%.*]] = load i32, ptr [[I]], align 4, !freeze_bits [[FREEZE_BITS2]]
// NOOMP-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 // NOOMP-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1
// NOOMP-NEXT: store i32 [[INC]], ptr [[I]], align 4 // NOOMP-NEXT: store i32 [[INC]], ptr [[I]], align 4
// NOOMP-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] // NOOMP-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
// NOOMP: for.end: // NOOMP: for.end:
// NOOMP-NEXT: call void @foo() // NOOMP-NEXT: call void @foo()
// NOOMP-NEXT: ret i32 0 // NOOMP-NEXT: ret i32 0
// //
// //
// NOOMP-LABEL: @foo( // NOOMP-LABEL: @foo(
// NOOMP-NEXT: entry: // NOOMP-NEXT: entry:
// NOOMP-NEXT: [[I:%.*]] = alloca i32, align 4 // NOOMP-NEXT: [[I:%.*]] = alloca i32, align 4
// NOOMP-NEXT: store i32 0, ptr [[I]], align 4 // NOOMP-NEXT: store i32 0, ptr [[I]], align 4
// NOOMP-NEXT: store i32 0, ptr [[I]], align 4 // NOOMP-NEXT: store i32 0, ptr [[I]], align 4
// NOOMP-NEXT: br label [[FOR_COND:%.*]] // NOOMP-NEXT: br label [[FOR_COND:%.*]]
// NOOMP: for.cond: // NOOMP: for.cond:
// NOOMP-NEXT: [[TMP0:%.*]] = load i32, ptr [[I]], align 4 // NOOMP-NEXT: [[TMP0:%.*]] = load i32, ptr [[I]], align 4, !freeze_bits [[FREEZE_BITS2]]
// NOOMP-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 33554432 // NOOMP-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 33554432
// NOOMP-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] // NOOMP-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
// NOOMP: for.body: // NOOMP: for.body:
// NOOMP-NEXT: [[TMP1:%.*]] = load i32, ptr [[I]], align 4 // NOOMP-NEXT: [[TMP1:%.*]] = load i32, ptr [[I]], align 4, !freeze_bits [[FREEZE_BITS2]]
// NOOMP-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 // NOOMP-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64
// NOOMP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [33554432 x double], ptr @A, i64 0, i64 [[IDXPROM]] // NOOMP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [33554432 x double], ptr @A, i64 0, i64 [[IDXPROM]]
// NOOMP-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX]], align 8 // NOOMP-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX]], align 8
// NOOMP-NEXT: br label [[FOR_INC:%.*]] // NOOMP-NEXT: br label [[FOR_INC:%.*]]
// NOOMP: for.inc: // NOOMP: for.inc:
// NOOMP-NEXT: [[TMP2:%.*]] = load i32, ptr [[I]], align 4 // NOOMP-NEXT: [[TMP2:%.*]] = load i32, ptr [[I]], align 4, !freeze_bits [[FREEZE_BITS2]]
// NOOMP-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 // NOOMP-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1
// NOOMP-NEXT: store i32 [[INC]], ptr [[I]], align 4 // NOOMP-NEXT: store i32 [[INC]], ptr [[I]], align 4
// NOOMP-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // NOOMP-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
// NOOMP: for.end: // NOOMP: for.end:
// NOOMP-NEXT: ret void // NOOMP-NEXT: ret void
// //

clang/test/utils/update_cc_test_checks/Inputs/generated-funcs.c.no-generated.expected

Show All 22 Lines
// NOOMP-NEXT: entry: // NOOMP-NEXT: entry:
// NOOMP-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // NOOMP-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
// NOOMP-NEXT: [[I:%.*]] = alloca i32, align 4 // NOOMP-NEXT: [[I:%.*]] = alloca i32, align 4
// NOOMP-NEXT: store i32 0, ptr [[RETVAL]], align 4 // NOOMP-NEXT: store i32 0, ptr [[RETVAL]], align 4
// NOOMP-NEXT: store i32 0, ptr [[I]], align 4 // NOOMP-NEXT: store i32 0, ptr [[I]], align 4
// NOOMP-NEXT: store i32 0, ptr [[I]], align 4 // NOOMP-NEXT: store i32 0, ptr [[I]], align 4
// NOOMP-NEXT: br label [[FOR_COND:%.*]] // NOOMP-NEXT: br label [[FOR_COND:%.*]]
// NOOMP: for.cond: // NOOMP: for.cond:
// NOOMP-NEXT: [[TMP0:%.*]] = load i32, ptr [[I]], align 4 // NOOMP-NEXT: [[TMP0:%.*]] = load i32, ptr [[I]], align 4, !freeze_bits [[FREEZE_BITS2:![0-9]+]]
// NOOMP-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 33554432 // NOOMP-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 33554432
// NOOMP-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] // NOOMP-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
// NOOMP: for.body: // NOOMP: for.body:
// NOOMP-NEXT: [[TMP1:%.*]] = load i32, ptr [[I]], align 4 // NOOMP-NEXT: [[TMP1:%.*]] = load i32, ptr [[I]], align 4, !freeze_bits [[FREEZE_BITS2]]
// NOOMP-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 // NOOMP-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64
// NOOMP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [33554432 x double], ptr @A, i64 0, i64 [[IDXPROM]] // NOOMP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [33554432 x double], ptr @A, i64 0, i64 [[IDXPROM]]
// NOOMP-NEXT: store double 0.000000e+00, ptr [[ARRAYIDX]], align 8 // NOOMP-NEXT: store double 0.000000e+00, ptr [[ARRAYIDX]], align 8
// NOOMP-NEXT: br label [[FOR_INC:%.*]] // NOOMP-NEXT: br label [[FOR_INC:%.*]]
// NOOMP: for.inc: // NOOMP: for.inc:
// NOOMP-NEXT: [[TMP2:%.*]] = load i32, ptr [[I]], align 4 // NOOMP-NEXT: [[TMP2:%.*]] = load i32, ptr [[I]], align 4, !freeze_bits [[FREEZE_BITS2]]
// NOOMP-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 // NOOMP-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1
// NOOMP-NEXT: store i32 [[INC]], ptr [[I]], align 4 // NOOMP-NEXT: store i32 [[INC]], ptr [[I]], align 4
// NOOMP-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] // NOOMP-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
// NOOMP: for.end: // NOOMP: for.end:
// NOOMP-NEXT: call void @foo() // NOOMP-NEXT: call void @foo()
// NOOMP-NEXT: ret i32 0 // NOOMP-NEXT: ret i32 0
// //
int main(void) { int main(void) {
int i = 0; int i = 0;
#pragma omp parallel for #pragma omp parallel for
Show All 15 Lines
// //
// NOOMP-LABEL: @foo( // NOOMP-LABEL: @foo(
// NOOMP-NEXT: entry: // NOOMP-NEXT: entry:
// NOOMP-NEXT: [[I:%.*]] = alloca i32, align 4 // NOOMP-NEXT: [[I:%.*]] = alloca i32, align 4
// NOOMP-NEXT: store i32 0, ptr [[I]], align 4 // NOOMP-NEXT: store i32 0, ptr [[I]], align 4
// NOOMP-NEXT: store i32 0, ptr [[I]], align 4 // NOOMP-NEXT: store i32 0, ptr [[I]], align 4
// NOOMP-NEXT: br label [[FOR_COND:%.*]] // NOOMP-NEXT: br label [[FOR_COND:%.*]]
// NOOMP: for.cond: // NOOMP: for.cond:
// NOOMP-NEXT: [[TMP0:%.*]] = load i32, ptr [[I]], align 4 // NOOMP-NEXT: [[TMP0:%.*]] = load i32, ptr [[I]], align 4, !freeze_bits [[FREEZE_BITS2]]
// NOOMP-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 33554432 // NOOMP-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 33554432
// NOOMP-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] // NOOMP-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
// NOOMP: for.body: // NOOMP: for.body:
// NOOMP-NEXT: [[TMP1:%.*]] = load i32, ptr [[I]], align 4 // NOOMP-NEXT: [[TMP1:%.*]] = load i32, ptr [[I]], align 4, !freeze_bits [[FREEZE_BITS2]]
// NOOMP-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 // NOOMP-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64
// NOOMP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [33554432 x double], ptr @A, i64 0, i64 [[IDXPROM]] // NOOMP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [33554432 x double], ptr @A, i64 0, i64 [[IDXPROM]]
// NOOMP-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX]], align 8 // NOOMP-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX]], align 8
// NOOMP-NEXT: br label [[FOR_INC:%.*]] // NOOMP-NEXT: br label [[FOR_INC:%.*]]
// NOOMP: for.inc: // NOOMP: for.inc:
// NOOMP-NEXT: [[TMP2:%.*]] = load i32, ptr [[I]], align 4 // NOOMP-NEXT: [[TMP2:%.*]] = load i32, ptr [[I]], align 4, !freeze_bits [[FREEZE_BITS2]]
// NOOMP-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 // NOOMP-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1
// NOOMP-NEXT: store i32 [[INC]], ptr [[I]], align 4 // NOOMP-NEXT: store i32 [[INC]], ptr [[I]], align 4
// NOOMP-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // NOOMP-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
// NOOMP: for.end: // NOOMP: for.end:
// NOOMP-NEXT: ret void // NOOMP-NEXT: ret void
// //
void foo(void) { void foo(void) {
int i = 0; int i = 0;
#pragma omp parallel for #pragma omp parallel for
for (i = 0; i < size; ++i) { for (i = 0; i < size; ++i) {
A[i] = 1.0; A[i] = 1.0;
} }
} }

clang/test/utils/update_cc_test_checks/Inputs/mangled_names.c.expected

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// Example input for update_cc_test_checks // Example input for update_cc_test_checks
// RUN: %clang_cc1 -triple=x86_64-unknown-linux-gnu -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -triple=x86_64-unknown-linux-gnu -emit-llvm -o - %s | FileCheck %s
// CHECK-LABEL: @test( // CHECK-LABEL: @test(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 8 // CHECK-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4 // CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8, !freeze_bits [[FREEZE_BITS2:![0-9]+]]
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 // CHECK-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64
// CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP0]], [[CONV]] // CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP0]], [[CONV]]
// CHECK-NEXT: ret i64 [[ADD]] // CHECK-NEXT: ret i64 [[ADD]]
// //
long test(long a, int b) { long test(long a, int b) {
return a + b; return a + b;
} }
// A function with a mangled name // A function with a mangled name
// CHECK-LABEL: @_Z4testlii( // CHECK-LABEL: @_Z4testlii(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 8 // CHECK-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4 // CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4
// CHECK-NEXT: store i32 [[C:%.*]], ptr [[C_ADDR]], align 4 // CHECK-NEXT: store i32 [[C:%.*]], ptr [[C_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 // CHECK-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64
// CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP0]], [[CONV]] // CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP0]], [[CONV]]
// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[C_ADDR]], align 4 // CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[C_ADDR]], align 4, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: [[CONV1:%.*]] = sext i32 [[TMP2]] to i64 // CHECK-NEXT: [[CONV1:%.*]] = sext i32 [[TMP2]] to i64
// CHECK-NEXT: [[ADD2:%.*]] = add nsw i64 [[ADD]], [[CONV1]] // CHECK-NEXT: [[ADD2:%.*]] = add nsw i64 [[ADD]], [[CONV1]]
// CHECK-NEXT: ret i64 [[ADD2]] // CHECK-NEXT: ret i64 [[ADD2]]
// //
__attribute__((overloadable)) long test(long a, int b, int c) { __attribute__((overloadable)) long test(long a, int b, int c) {
return a + b + c; return a + b + c;
} }

clang/test/utils/update_cc_test_checks/Inputs/mangled_names.c.funcsig.expected

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature
// Example input for update_cc_test_checks // Example input for update_cc_test_checks
// RUN: %clang_cc1 -triple=x86_64-unknown-linux-gnu -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -triple=x86_64-unknown-linux-gnu -emit-llvm -o - %s | FileCheck %s
// CHECK-LABEL: define {{[^@]+}}@test // CHECK-LABEL: define {{[^@]+}}@test
// CHECK-SAME: (i64 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-SAME: (i64 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 // CHECK-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
// CHECK-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 // CHECK-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8, !freeze_bits [[FREEZE_BITS2:![0-9]+]]
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 // CHECK-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64
// CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP0]], [[CONV]] // CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP0]], [[CONV]]
// CHECK-NEXT: ret i64 [[ADD]] // CHECK-NEXT: ret i64 [[ADD]]
// //
long test(long a, int b) { long test(long a, int b) {
return a + b; return a + b;
} }
// A function with a mangled name // A function with a mangled name
// CHECK-LABEL: define {{[^@]+}}@_Z4testlii // CHECK-LABEL: define {{[^@]+}}@_Z4testlii
// CHECK-SAME: (i64 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[C:%.*]]) #[[ATTR0]] { // CHECK-SAME: (i64 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[C:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 // CHECK-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
// CHECK-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 // CHECK-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
// CHECK-NEXT: store i32 [[C]], ptr [[C_ADDR]], align 4 // CHECK-NEXT: store i32 [[C]], ptr [[C_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 // CHECK-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64
// CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP0]], [[CONV]] // CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP0]], [[CONV]]
// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[C_ADDR]], align 4 // CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[C_ADDR]], align 4, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: [[CONV1:%.*]] = sext i32 [[TMP2]] to i64 // CHECK-NEXT: [[CONV1:%.*]] = sext i32 [[TMP2]] to i64
// CHECK-NEXT: [[ADD2:%.*]] = add nsw i64 [[ADD]], [[CONV1]] // CHECK-NEXT: [[ADD2:%.*]] = add nsw i64 [[ADD]], [[CONV1]]
// CHECK-NEXT: ret i64 [[ADD2]] // CHECK-NEXT: ret i64 [[ADD2]]
// //
__attribute__((overloadable)) long test(long a, int b, int c) { __attribute__((overloadable)) long test(long a, int b, int c) {
return a + b + c; return a + b + c;
} }

clang/test/utils/update_cc_test_checks/Inputs/mangled_names.c.funcsig.v2.expected

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// Example input for update_cc_test_checks // Example input for update_cc_test_checks
// RUN: %clang_cc1 -triple=x86_64-unknown-linux-gnu -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -triple=x86_64-unknown-linux-gnu -emit-llvm -o - %s | FileCheck %s
// CHECK-LABEL: define dso_local i64 @test // CHECK-LABEL: define dso_local i64 @test
// CHECK-SAME: (i64 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-SAME: (i64 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 // CHECK-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
// CHECK-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 // CHECK-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8, !freeze_bits [[FREEZE_BITS2:![0-9]+]]
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 // CHECK-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64
// CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP0]], [[CONV]] // CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP0]], [[CONV]]
// CHECK-NEXT: ret i64 [[ADD]] // CHECK-NEXT: ret i64 [[ADD]]
// //
long test(long a, int b) { long test(long a, int b) {
return a + b; return a + b;
} }
// A function with a mangled name // A function with a mangled name
// CHECK-LABEL: define dso_local i64 @_Z4testlii // CHECK-LABEL: define dso_local i64 @_Z4testlii
// CHECK-SAME: (i64 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[C:%.*]]) #[[ATTR0]] { // CHECK-SAME: (i64 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[C:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 // CHECK-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
// CHECK-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 // CHECK-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
// CHECK-NEXT: store i32 [[C]], ptr [[C_ADDR]], align 4 // CHECK-NEXT: store i32 [[C]], ptr [[C_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 // CHECK-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64
// CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP0]], [[CONV]] // CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP0]], [[CONV]]
// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[C_ADDR]], align 4 // CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[C_ADDR]], align 4, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: [[CONV1:%.*]] = sext i32 [[TMP2]] to i64 // CHECK-NEXT: [[CONV1:%.*]] = sext i32 [[TMP2]] to i64
// CHECK-NEXT: [[ADD2:%.*]] = add nsw i64 [[ADD]], [[CONV1]] // CHECK-NEXT: [[ADD2:%.*]] = add nsw i64 [[ADD]], [[CONV1]]
// CHECK-NEXT: ret i64 [[ADD2]] // CHECK-NEXT: ret i64 [[ADD2]]
// //
__attribute__((overloadable)) long test(long a, int b, int c) { __attribute__((overloadable)) long test(long a, int b, int c) {
return a + b + c; return a + b + c;
} }

clang/test/utils/update_cc_test_checks/Inputs/mangled_names.c.v2.expected

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// Example input for update_cc_test_checks // Example input for update_cc_test_checks
// RUN: %clang_cc1 -triple=x86_64-unknown-linux-gnu -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -triple=x86_64-unknown-linux-gnu -emit-llvm -o - %s | FileCheck %s
// CHECK-LABEL: define dso_local i64 @test // CHECK-LABEL: define dso_local i64 @test
// CHECK-SAME: (i64 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-SAME: (i64 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 // CHECK-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
// CHECK-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 // CHECK-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8, !freeze_bits [[FREEZE_BITS2:![0-9]+]]
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 // CHECK-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64
// CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP0]], [[CONV]] // CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP0]], [[CONV]]
// CHECK-NEXT: ret i64 [[ADD]] // CHECK-NEXT: ret i64 [[ADD]]
// //
long test(long a, int b) { long test(long a, int b) {
return a + b; return a + b;
} }
// A function with a mangled name // A function with a mangled name
// CHECK-LABEL: define dso_local i64 @_Z4testlii // CHECK-LABEL: define dso_local i64 @_Z4testlii
// CHECK-SAME: (i64 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[C:%.*]]) #[[ATTR0]] { // CHECK-SAME: (i64 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[C:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 // CHECK-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
// CHECK-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 // CHECK-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
// CHECK-NEXT: store i32 [[C]], ptr [[C_ADDR]], align 4 // CHECK-NEXT: store i32 [[C]], ptr [[C_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64 // CHECK-NEXT: [[CONV:%.*]] = sext i32 [[TMP1]] to i64
// CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP0]], [[CONV]] // CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP0]], [[CONV]]
// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[C_ADDR]], align 4 // CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[C_ADDR]], align 4, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: [[CONV1:%.*]] = sext i32 [[TMP2]] to i64 // CHECK-NEXT: [[CONV1:%.*]] = sext i32 [[TMP2]] to i64
// CHECK-NEXT: [[ADD2:%.*]] = add nsw i64 [[ADD]], [[CONV1]] // CHECK-NEXT: [[ADD2:%.*]] = add nsw i64 [[ADD]], [[CONV1]]
// CHECK-NEXT: ret i64 [[ADD2]] // CHECK-NEXT: ret i64 [[ADD2]]
// //
__attribute__((overloadable)) long test(long a, int b, int c) { __attribute__((overloadable)) long test(long a, int b, int c) {
return a + b + c; return a + b + c;
} }

clang/test/utils/update_cc_test_checks/Inputs/resolve-tmp-conflict.cpp.expected

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --prefix-filecheck-ir-name _ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --prefix-filecheck-ir-name _
// RUN: %clang_cc1 -std=c++11 -triple x86_64-unknown-linux-gnu -emit-llvm %s -o - | FileCheck %s // RUN: %clang_cc1 -std=c++11 -triple x86_64-unknown-linux-gnu -emit-llvm %s -o - | FileCheck %s
// CHECK-LABEL: define {{[^@]+}}@_Z3fooi // CHECK-LABEL: define {{[^@]+}}@_Z3fooi
// CHECK-SAME: (i32 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-SAME: (i32 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[_TMP0:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[_TMP0:%.*]] = alloca ptr, align 8
// CHECK-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8
// CHECK-NEXT: [[REF_TMP:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[REF_TMP:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 // CHECK-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK-NEXT: store ptr [[A_ADDR]], ptr [[_TMP0]], align 8 // CHECK-NEXT: store ptr [[A_ADDR]], ptr [[_TMP0]], align 8
// CHECK-NEXT: store i32 1, ptr [[REF_TMP]], align 4 // CHECK-NEXT: store i32 1, ptr [[REF_TMP]], align 4
// CHECK-NEXT: store ptr [[REF_TMP]], ptr [[_TMP1]], align 8 // CHECK-NEXT: store ptr [[REF_TMP]], ptr [[_TMP1]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !freeze_bits [[FREEZE_BITS2:![0-9]+]]
// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[_TMP1]], align 8 // CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[_TMP1]], align 8, !freeze_bits [[FREEZE_BITS2]]
// CHECK-NEXT: store i32 [[TMP0]], ptr [[TMP1]], align 4 // CHECK-NEXT: store i32 [[TMP0]], ptr [[TMP1]], align 4
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// //
void foo(int a) { void foo(int a) {
int &tmp0 = a; int &tmp0 = a;
int &&tmp1 = 1; int &&tmp1 = 1;
tmp1 = a; tmp1 = a;
return; return;
} }

llvm/utils/UpdateTestChecks/common.py

Show First 20 Lines • Show All 974 Lines • ▼ Show 20 Linesir_nameless_values = [
NamelessValue(r"ATTR", "#", r"#", r"[0-9]+", None), NamelessValue(r"ATTR", "#", r"#", r"[0-9]+", None),
NamelessValue(r"ATTR", "#", r"attributes #", r"[0-9]+", r"{[^}]*}"), NamelessValue(r"ATTR", "#", r"attributes #", r"[0-9]+", r"{[^}]*}"),
NamelessValue(r"GLOB", "@", r"@", r"[0-9]+", None), NamelessValue(r"GLOB", "@", r"@", r"[0-9]+", None),
NamelessValue( NamelessValue(
r"GLOB", "@", r"@", r'[a-zA-Z0-9_$"\\.-]+', r".+", is_before_functions=True r"GLOB", "@", r"@", r'[a-zA-Z0-9_$"\\.-]+', r".+", is_before_functions=True
), ),
NamelessValue(r"DBG", "!", r"!dbg ", r"![0-9]+", None), NamelessValue(r"DBG", "!", r"!dbg ", r"![0-9]+", None),
NamelessValue(r"DIASSIGNID", "!", r"!DIAssignID ", r"![0-9]+", None), NamelessValue(r"DIASSIGNID", "!", r"!DIAssignID ", r"![0-9]+", None),
NamelessValue(r'FREEZE_BITS', '!', r'!freeze_bits ', r'![0-9]+', None),
NamelessValue(r"PROF", "!", r"!prof ", r"![0-9]+", None), NamelessValue(r"PROF", "!", r"!prof ", r"![0-9]+", None),
NamelessValue(r"TBAA", "!", r"!tbaa ", r"![0-9]+", None), NamelessValue(r"TBAA", "!", r"!tbaa ", r"![0-9]+", None),
NamelessValue(r"TBAA_STRUCT", "!", r"!tbaa.struct ", r"![0-9]+", None), NamelessValue(r"TBAA_STRUCT", "!", r"!tbaa.struct ", r"![0-9]+", None),
NamelessValue(r"RNG", "!", r"!range ", r"![0-9]+", None), NamelessValue(r"RNG", "!", r"!range ", r"![0-9]+", None),
NamelessValue(r"LOOP", "!", r"!llvm.loop ", r"![0-9]+", None), NamelessValue(r"LOOP", "!", r"!llvm.loop ", r"![0-9]+", None),
NamelessValue(r"META", "!", r"metadata ", r"![0-9]+", None), NamelessValue(r"META", "!", r"metadata ", r"![0-9]+", None),
NamelessValue(r"META", "!", r"", r"![0-9]+", r"(?:distinct |)!.*"), NamelessValue(r"META", "!", r"", r"![0-9]+", r"(?:distinct |)!.*"),
NamelessValue(r"ACC_GRP", "!", r"!llvm.access.group ", r"![0-9]+", None), NamelessValue(r"ACC_GRP", "!", r"!llvm.access.group ", r"![0-9]+", None),
▲ Show 20 Lines • Show All 739 Lines • Show Last 20 Lines