[RISCV] Add feature checks for vector crypto C intrinsics

[4vtomat]

Update test cases.

[craig.topper]

LGTM

clang/include/clang/Basic/riscv_vector.td

 
 multiclass RVVSignedWidenBinBuiltinSetVwsll
     : RVVWidenBuiltinSet<NAME, "csi",
                          [["vv", "Uw", "UwUvUv"],
                           ["vx", "Uw", "UwUvz"]]>;
 
 let UnMaskedPolicyScheme = HasPassthruOperand in {
   // zvkb
+  let RequiredFeatures = ["Zvkb"] in {
     defm vandn   : RVVUnsignedBinBuiltinSet;
     defm vbrev8  : RVVOutBuiltinSetZvbb;
     defm vrev8   : RVVOutBuiltinSetZvbb;
     defm vrol    : RVVUnsignedShiftBuiltinSet;
     defm vror    : RVVUnsignedShiftBuiltinSet;
+  }
 
   // zvbb
+  let RequiredFeatures = ["Zvbb"] in {
     defm vbrev   : RVVOutBuiltinSetZvbb;
     defm vclz    : RVVOutBuiltinSetZvbb;
     defm vctz    : RVVOutBuiltinSetZvbb;
     defm vcpopv  : RVVOutBuiltinSetZvbb;
     let OverloadedName = "vwsll" in
     defm vwsll   : RVVSignedWidenBinBuiltinSetVwsll;
+  }
 
   // zvbc
+  let RequiredFeatures = ["Zvbc"] in {
     defm vclmul  : RVVInt64BinBuiltinSet;
     defm vclmulh : RVVInt64BinBuiltinSet;
   }
+}
 
 let UnMaskedPolicyScheme = HasPolicyOperand, HasMasked = false in {
   // zvkg
+  let RequiredFeatures = ["Zvkg"] in {
     defm vghsh   : RVVOutOp2BuiltinSetVVZvk;
     defm vgmul   : RVVOutBuiltinSetZvk<HasVV=1, HasVS=0>;
+  }
 
   // zvkned
+  let RequiredFeatures = ["Zvkned"] in {
     defm vaesdf  : RVVOutBuiltinSetZvk;
     defm vaesdm  : RVVOutBuiltinSetZvk;
     defm vaesef  : RVVOutBuiltinSetZvk;
     defm vaesem  : RVVOutBuiltinSetZvk;
     let UnMaskedPolicyScheme = HasPassthruOperand in
     defm vaeskf1 : RVVOutOp1BuiltinSet<"vaeskf1", "i", [["vi", "Uv", "UvUvKz"]]>;
     defm vaeskf2 : RVVOutOp2BuiltinSetVIZvk;
     defm vaesz   : RVVOutBuiltinSetZvk<HasVV=0>;
+  }
 
   // zvknha or zvknhb
+  let RequiredFeatures = ["Zvknha"] in {
     defm vsha2ch : RVVOutOp2BuiltinSetVVZvk<"il">;
     defm vsha2cl : RVVOutOp2BuiltinSetVVZvk<"il">;
     defm vsha2ms : RVVOutOp2BuiltinSetVVZvk<"il">;
+  }
 
   // zvksed
+  let RequiredFeatures = ["Zvksed"] in {
     let UnMaskedPolicyScheme = HasPassthruOperand in
     defm vsm4k   : RVVOutOp1BuiltinSet<"vsm4k", "i", [["vi", "Uv", "UvUvKz"]]>;
     defm vsm4r   : RVVOutBuiltinSetZvk;
+  }
 
   // zvksh
+  let RequiredFeatures = ["Zvksh"] in {
     defm vsm3c   : RVVOutOp2BuiltinSetVIZvk;
     let UnMaskedPolicyScheme = HasPassthruOperand in
     defm vsm3me  : RVVOutOp1BuiltinSet<"vsm3me", "i", [["vv", "Uv", "UvUvUv"]]>;
   }
+}

clang/include/clang/Support/RISCVVIntrinsicUtils.h

public:
   static void updateNamesAndPolicy(bool IsMasked, bool HasPolicy,
                                    std::string &Name, std::string &BuiltinName,
                                    std::string &OverloadedName,
                                    Policy &PolicyAttrs, bool HasFRMRoundModeOp);
 };
 
 // RVVRequire should be sync'ed with target features, but only
 // required features used in riscv_vector.td.
-enum RVVRequire : uint8_t {
+enum RVVRequire : uint16_t {
   RVV_REQ_None = 0,
   RVV_REQ_RV64 = 1 << 0,
   RVV_REQ_ZvfhminOrZvfh = 1 << 1,
   RVV_REQ_Xsfvcp = 1 << 2,
+  RVV_REQ_Zvbb = 1 << 3,
+  RVV_REQ_Zvbc = 1 << 4,
+  RVV_REQ_Zvkb = 1 << 5,
+  RVV_REQ_Zvkg = 1 << 6,
+  RVV_REQ_Zvkned = 1 << 7,
+  RVV_REQ_Zvknha = 1 << 8,
+  RVV_REQ_Zvksed = 1 << 9,
+  RVV_REQ_Zvksh = 1 << 10,
 
-  LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_Xsfvcp)
+  LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_Zvksh)
 };
 
 // Raw RVV intrinsic info, used to expand later.
 // This struct is highly compact for minimized code size.
 struct RVVIntrinsicRecord {
   // Intrinsic name, e.g. vadd_vv
   const char *Name;
 
struct RVVIntrinsicRecord {
 
   // Length of intrinsic name suffix.
   uint8_t SuffixLength;
 
   // Length of overloaded intrinsic suffix.
   uint8_t OverloadedSuffixSize;
 
   // Required target features for this intrinsic.
-  uint8_t RequiredExtensions;
+  uint16_t RequiredExtensions;
 
   // Supported type, mask of BasicType.
   uint8_t TypeRangeMask;
 
   // Supported LMUL.
   uint8_t Log2LMULMask;
 
   // Number of fields, greater than 1 if it's segment load/store.

clang/lib/Sema/SemaRISCVVectorLookup.cpp

public:
   bool CreateIntrinsicIfFound(LookupResult &LR, IdentifierInfo *II,
                               Preprocessor &PP) override;
 };
 } // namespace
 
 void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
     ArrayRef<RVVIntrinsicRecord> Recs, IntrinsicKind K) {
   const TargetInfo &TI = Context.getTargetInfo();
-  static const std::pair<const char *, uint8_t> FeatureCheckList[] = {
+  static const std::pair<const char *, RVVRequire> FeatureCheckList[] = {
       {"64bit", RVV_REQ_RV64},
-      {"xsfvcp", RVV_REQ_Xsfvcp}};
+      {"xsfvcp", RVV_REQ_Xsfvcp},
+      {"experimental-zvbb", RVV_REQ_Zvbb},
+      {"experimental-zvbc", RVV_REQ_Zvbc},
+      {"experimental-zvkb", RVV_REQ_Zvkb},
+      {"experimental-zvkg", RVV_REQ_Zvkg},
+      {"experimental-zvkned", RVV_REQ_Zvkned},
+      {"experimental-zvknha", RVV_REQ_Zvknha},
+      {"experimental-zvksed", RVV_REQ_Zvksed},
+      {"experimental-zvksh", RVV_REQ_Zvksh}};
 
   // Construction of RVVIntrinsicRecords need to sync with createRVVIntrinsics
   // in RISCVVEmitter.cpp.
   for (auto &Record : Recs) {
     // Check requirements.
     if (llvm::any_of(FeatureCheckList, [&](const auto &Item) {
           return (Record.RequiredExtensions & Item.second) == Item.second &&
                  !TI.hasFeature(Item.first);

clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vaeskf1-out-of-range.c

 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
 // RUN:   -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
-// RUN:   -fsyntax-only -verify %s
+// RUN:   -target-feature +experimental-zvkned -fsyntax-only -verify %s
 
 #include <riscv_vector.h>
 
 vuint32m1_t test_vaeskf1_vi_u32m1(vuint32m1_t vs2, size_t vl) {
 // expected-error@+1 {{argument value 33 is outside the valid range [0, 31]}}
   return __riscv_vaeskf1_vi_u32m1(vs2, 33, vl);
 }
 
 vuint32m1_t test_vaeskf1_vi_u32m1_tu(vuint32m1_t merge, vuint32m1_t vs2, size_t vl) {
 // expected-error@+1 {{argument value 33 is outside the valid range [0, 31]}}
   return __riscv_vaeskf1_vi_u32m1_tu(merge, vs2, 33, vl);
 }

clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vaeskf2-out-of-range.c

 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
 // RUN:   -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
-// RUN:   -fsyntax-only -verify %s
+// RUN:   -target-feature +experimental-zvkned -fsyntax-only -verify %s
 
 #include <riscv_vector.h>
 
 vuint32m1_t test_vaeskf2_vi_u32m1(vuint32m1_t vd, vuint32m1_t vs2, size_t vl) {
 // expected-error@+1 {{argument value 33 is outside the valid range [0, 31]}}
   return __riscv_vaeskf2_vi_u32m1(vd, vs2, 33, vl);
 }
 
 vuint32m1_t test_vaeskf2_vi_u32m1_tu(vuint32m1_t merge, vuint32m1_t vs2, size_t vl) {
 // expected-error@+1 {{argument value 33 is outside the valid range [0, 31]}}
   return __riscv_vaeskf2_vi_u32m1_tu(merge, vs2, 33, vl);
 }

clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsm3c-out-of-range.c

 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
 // RUN:   -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
-// RUN:   -fsyntax-only -verify %s
+// RUN:   -target-feature +experimental-zvksh -fsyntax-only -verify %s
 
 #include <riscv_vector.h>
 
 vuint32m2_t test_vsm3c_vi_u32m2(vuint32m2_t vd, vuint32m2_t vs2, size_t vl) {
 // expected-error@+1 {{argument value 33 is outside the valid range [0, 31]}}
   return __riscv_vsm3c_vi_u32m2(vd, vs2, 33, vl);
 }
 
 vuint32m2_t test_vsm3c_vi_u32m2_tu(vuint32m2_t merge, vuint32m2_t vs2, size_t vl) {
 // expected-error@+1 {{argument value 33 is outside the valid range [0, 31]}}
   return __riscv_vsm3c_vi_u32m2_tu(merge, vs2, 33, vl);
 }

clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsm4k-out-of-range.c

 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
 // RUN:   -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
-// RUN:   -fsyntax-only -verify %s
+// RUN:   -target-feature +experimental-zvksed -fsyntax-only -verify %s
 
 #include <riscv_vector.h>
 
 vuint32m1_t test_vsm4k_vi_u32m1(vuint32m1_t vs2, size_t vl) {
 // expected-error@+1 {{argument value 33 is outside the valid range [0, 31]}}
   return __riscv_vsm4k_vi_u32m1(vs2, 33, vl);
 }
 
 vuint32m1_t test_vsm4k_vi_u32m1_tu(vuint32m1_t merge, vuint32m1_t vs2, size_t vl) {
 // expected-error@+1 {{argument value 33 is outside the valid range [0, 31]}}
   return __riscv_vsm4k_vi_u32m1_tu(merge, vs2, 33, vl);
 }

clang/test/Sema/zvk-invalid-features.c

+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 %s -fsyntax-only -verify
+
+void test_zvk_features() {
+  // zvbb
+  __riscv_vbrev(); // expected-error {{call to undeclared function '__riscv_vbrev'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vclz(); // expected-error {{call to undeclared function '__riscv_vclz'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vctz(); // expected-error {{call to undeclared function '__riscv_vctz'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vcpopv(); // expected-error {{call to undeclared function '__riscv_vcpopv'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vwsll(); // expected-error {{call to undeclared function '__riscv_vwsll'; ISO C99 and later do not support implicit function declarations}}
+
+  // zvbc
+  __riscv_vclmul(); // expected-error {{call to undeclared function '__riscv_vclmul'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vclmulh(); // expected-error {{call to undeclared function '__riscv_vclmulh'; ISO C99 and later do not support implicit function declarations}}
+
+  // zvkb
+  __riscv_vandn(); // expected-error {{call to undeclared function '__riscv_vandn'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vbrev8(); // expected-error {{call to undeclared function '__riscv_vbrev8'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vrev8(); // expected-error {{call to undeclared function '__riscv_vrev8'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vrol(); // expected-error {{call to undeclared function '__riscv_vrol'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vror(); // expected-error {{call to undeclared function '__riscv_vror'; ISO C99 and later do not support implicit function declarations}}
+
+  // zvkg
+  __riscv_vghsh(); // expected-error {{call to undeclared function '__riscv_vghsh'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vgmul(); // expected-error {{call to undeclared function '__riscv_vgmul'; ISO C99 and later do not support implicit function declarations}}
+
+  // zvkned
+  __riscv_vaesdf(); // expected-error {{call to undeclared function '__riscv_vaesdf'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vaesdm(); // expected-error {{call to undeclared function '__riscv_vaesdm'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vaesef(); // expected-error {{call to undeclared function '__riscv_vaesef'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vaesem(); // expected-error {{call to undeclared function '__riscv_vaesem'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vaeskf1(); // expected-error {{call to undeclared function '__riscv_vaeskf1'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vaeskf2(); // expected-error {{call to undeclared function '__riscv_vaeskf2'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vaesz(); // expected-error {{call to undeclared function '__riscv_vaesz'; ISO C99 and later do not support implicit function declarations}}
+
+  // zvknha or zvknhb
+  __riscv_vsha2ch(); // expected-error {{call to undeclared function '__riscv_vsha2ch'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vsha2cl(); // expected-error {{call to undeclared function '__riscv_vsha2cl'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vsha2ms(); // expected-error {{call to undeclared function '__riscv_vsha2ms'; ISO C99 and later do not support implicit function declarations}}
+
+  //zvksed
+  __riscv_vsm4k(); // expected-error {{call to undeclared function '__riscv_vsm4k'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vsm4r(); // expected-error {{call to undeclared function '__riscv_vsm4r'; ISO C99 and later do not support implicit function declarations}}
+
+  // zvksh
+  __riscv_vsm3c(); // expected-error {{call to undeclared function '__riscv_vsm3c'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vsm3me(); // expected-error {{call to undeclared function '__riscv_vsm3me'; ISO C99 and later do not support implicit function declarations}}
+}

clang/test/Sema/zvk-invalid-vlen.c

 // REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v %s -fsyntax-only -verify
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvkned \
+// RUN:   -target-feature +experimental-zvksh %s -fsyntax-only -verify
 
 #include <riscv_vector.h>
 
 void test_vaeskf1_tu(vuint32mf2_t vd, vuint32mf2_t vs2, size_t vl) {
   __riscv_vaeskf1_vi_u32mf2_tu(vd, vs2, 0, vl); // expected-error {{RISC-V type 'vuint32mf2_t' (aka '__rvv_uint32mf2_t') requires the 'zvl256b' extension}}
 }
 
 void test_vsm3c_tu(vuint32mf2_t vd, vuint32mf2_t vs2, size_t vl) {

clang/utils/TableGen/RISCVVEmitter.cpp

for (auto *R : RV) {
     SR.Log2LMULMask = Log2LMULMask;
 
     SR.RequiredExtensions = 0;
     for (auto RequiredFeature : RequiredFeatures) {
       RVVRequire RequireExt = StringSwitch<RVVRequire>(RequiredFeature)
                                   .Case("RV64", RVV_REQ_RV64)
                                   .Case("ZvfhminOrZvfh", RVV_REQ_ZvfhminOrZvfh)
                                   .Case("Xsfvcp", RVV_REQ_Xsfvcp)
+                                  .Case("Zvbb", RVV_REQ_Zvbb)
+                                  .Case("Zvbc", RVV_REQ_Zvbc)
+                                  .Case("Zvkb", RVV_REQ_Zvkb)
+                                  .Case("Zvkg", RVV_REQ_Zvkg)
+                                  .Case("Zvkned", RVV_REQ_Zvkned)
+                                  .Case("Zvknha", RVV_REQ_Zvknha)
+                                  .Case("Zvksed", RVV_REQ_Zvksed)
+                                  .Case("Zvksh", RVV_REQ_Zvksh)
                                   .Default(RVV_REQ_None);
       assert(RequireExt != RVV_REQ_None && "Unrecognized required feature?");
       SR.RequiredExtensions |= RequireExt;
     }
 
     SR.NF = NF;
     SR.HasMasked = HasMasked;
     SR.HasVL = HasVL;