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Differential D158232

[GlobalISel][Mips] Sync G_UADDE and G_USUBE legalization with LegalizeDAG.
ClosedPublic

Authored by craig.topper on Aug 17 2023, 4:39 PM.

Details

Reviewers
arsenm
aemerson
atanasyan
dsanders
Petar.Avramovic
eli.friedman
Commits
rGc6dee6982f73: [GlobalISel][Mips] Sync G_UADDE and G_USUBE legalization with LegalizeDAG.
Summary

This modifies the G_UADDE to a version that looks shorter on
Mips and RISC-V when feeding the equivalent IR to SelectionDAG.
This also removes the boolean select from G_USUBE.

Comments taken from LegalizeDAG and tweaked.

Diff Detail

Event Timeline

craig.topper created this revision.Aug 17 2023, 4:39 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 17 2023, 4:39 PM
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craig.topper requested review of this revision.Aug 17 2023, 4:39 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 17 2023, 4:39 PM
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arsenm accepted this revision.Aug 17 2023, 5:03 PM
This revision is now accepted and ready to land.Aug 17 2023, 5:03 PM
Harbormaster completed remote builds in B253346: Diff 551321.Aug 17 2023, 5:58 PM
This revision was landed with ongoing or failed builds.Aug 17 2023, 8:37 PM
Closed by commit rGc6dee6982f73: [GlobalISel][Mips] Sync G_UADDE and G_USUBE legalization with LegalizeDAG. (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rGc6dee6982f73: [GlobalISel][Mips] Sync G_UADDE and G_USUBE legalization with LegalizeDAG..

Revision Contents

PathSize
llvm/
lib/
CodeGen/
GlobalISel/
33 lines
test/
CodeGen/
Mips/
GlobalISel/
legalizer/
17 lines
21 lines
llvm-ir/
40 lines
41 lines

Diff 551361

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 3,433 Lines • ▼ Show 20 Lines case G_UADDO: {
MI.eraseFromParent(); MI.eraseFromParent();
return Legalized; return Legalized;
} }
case G_UADDE: { case G_UADDE: {
auto [Res, CarryOut, LHS, RHS, CarryIn] = MI.getFirst5Regs(); auto [Res, CarryOut, LHS, RHS, CarryIn] = MI.getFirst5Regs();
const LLT CondTy = MRI.getType(CarryOut); const LLT CondTy = MRI.getType(CarryOut);
const LLT Ty = MRI.getType(Res); const LLT Ty = MRI.getType(Res);
// Initial add of the two operands.
auto TmpRes = MIRBuilder.buildAdd(Ty, LHS, RHS); auto TmpRes = MIRBuilder.buildAdd(Ty, LHS, RHS);
// Initial check for carry.
auto Carry = MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CondTy, TmpRes, LHS);
// Add the sum and the carry.
auto ZExtCarryIn = MIRBuilder.buildZExt(Ty, CarryIn); auto ZExtCarryIn = MIRBuilder.buildZExt(Ty, CarryIn);
MIRBuilder.buildAdd(Res, TmpRes, ZExtCarryIn); MIRBuilder.buildAdd(Res, TmpRes, ZExtCarryIn);
auto Res_EQ_LHS = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, CondTy, Res, LHS); // Second check for carry. We can only carry if the initial sum is all 1s
auto Res_ULT_LHS = // and the carry is set, resulting in a new sum of 0.
MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CondTy, Res, LHS); auto Zero = MIRBuilder.buildConstant(Ty, 0);
auto And = MIRBuilder.buildAnd(CondTy, Res_EQ_LHS, CarryIn); auto ResEqZero = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, CondTy, Res, Zero);
MIRBuilder.buildOr(CarryOut, And, Res_ULT_LHS); auto Carry2 = MIRBuilder.buildAnd(CondTy, ResEqZero, CarryIn);
MIRBuilder.buildOr(CarryOut, Carry, Carry2);
MI.eraseFromParent(); MI.eraseFromParent();
return Legalized; return Legalized;
} }
case G_USUBO: { case G_USUBO: {
auto [Res, BorrowOut, LHS, RHS] = MI.getFirst4Regs(); auto [Res, BorrowOut, LHS, RHS] = MI.getFirst4Regs();
MIRBuilder.buildSub(Res, LHS, RHS); MIRBuilder.buildSub(Res, LHS, RHS);
MIRBuilder.buildICmp(CmpInst::ICMP_ULT, BorrowOut, LHS, RHS); MIRBuilder.buildICmp(CmpInst::ICMP_ULT, BorrowOut, LHS, RHS);
MI.eraseFromParent(); MI.eraseFromParent();
return Legalized; return Legalized;
} }
case G_USUBE: { case G_USUBE: {
auto [Res, BorrowOut, LHS, RHS, BorrowIn] = MI.getFirst5Regs(); auto [Res, BorrowOut, LHS, RHS, BorrowIn] = MI.getFirst5Regs();
const LLT CondTy = MRI.getType(BorrowOut); const LLT CondTy = MRI.getType(BorrowOut);
const LLT Ty = MRI.getType(Res); const LLT Ty = MRI.getType(Res);
// Initial subtract of the two operands.
auto TmpRes = MIRBuilder.buildSub(Ty, LHS, RHS); auto TmpRes = MIRBuilder.buildSub(Ty, LHS, RHS);
// Initial check for borrow.
auto Borrow = MIRBuilder.buildICmp(CmpInst::ICMP_UGT, CondTy, TmpRes, LHS);
// Subtract the borrow from the first subtract.
auto ZExtBorrowIn = MIRBuilder.buildZExt(Ty, BorrowIn); auto ZExtBorrowIn = MIRBuilder.buildZExt(Ty, BorrowIn);
MIRBuilder.buildSub(Res, TmpRes, ZExtBorrowIn); MIRBuilder.buildSub(Res, TmpRes, ZExtBorrowIn);
auto LHS_EQ_RHS = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, CondTy, LHS, RHS); // Second check for borrow. We can only borrow if the initial difference is
auto LHS_ULT_RHS = MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CondTy, LHS, RHS); // 0 and the borrow is set, resulting in a new difference of all 1s.
MIRBuilder.buildSelect(BorrowOut, LHS_EQ_RHS, BorrowIn, LHS_ULT_RHS); auto Zero = MIRBuilder.buildConstant(Ty, 0);
auto TmpResEqZero =
MIRBuilder.buildICmp(CmpInst::ICMP_EQ, CondTy, TmpRes, Zero);
auto Borrow2 = MIRBuilder.buildAnd(CondTy, TmpResEqZero, BorrowIn);
MIRBuilder.buildOr(BorrowOut, Borrow, Borrow2);
MI.eraseFromParent(); MI.eraseFromParent();
return Legalized; return Legalized;
} }
case G_UITOFP: case G_UITOFP:
return lowerUITOFP(MI); return lowerUITOFP(MI);
case G_SITOFP: case G_SITOFP:
return lowerSITOFP(MI); return lowerSITOFP(MI);
▲ Show 20 Lines • Show All 4,640 Lines • Show Last 20 Lines

llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir

Show First 20 Lines • Show All 256 Lines • ▼ Show 20 Lines bb.1.entry:
; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load (s32) from %fixed-stack.1) ; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load (s32) from %fixed-stack.1)
; MIPS32: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2 ; MIPS32: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
; MIPS32: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (load (s32) from %fixed-stack.2) ; MIPS32: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (load (s32) from %fixed-stack.2)
; MIPS32: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3 ; MIPS32: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
; MIPS32: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p0) :: (load (s32) from %fixed-stack.3) ; MIPS32: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p0) :: (load (s32) from %fixed-stack.3)
; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[COPY]] ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[COPY]]
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[COPY]] ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[COPY]]
; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LOAD1]], [[COPY1]] ; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LOAD1]], [[COPY1]]
; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD1]](s32), [[LOAD1]]
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]] ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[AND]] ; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[AND]]
; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ADD2]](s32), [[LOAD1]] ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD2]](s32), [[LOAD1]] ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ADD2]](s32), [[C1]]
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[ICMP]] ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP2]], [[ICMP]]
; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[ICMP2]] ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[ICMP1]], [[AND1]]
; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[LOAD2]], [[COPY2]] ; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[LOAD2]], [[COPY2]]
; MIPS32: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[LOAD2]]
; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C]] ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C]]
; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[AND2]] ; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[AND2]]
; MIPS32: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ADD4]](s32), [[LOAD2]] ; MIPS32: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ADD4]](s32), [[C1]]
; MIPS32: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD4]](s32), [[LOAD2]] ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ICMP4]], [[OR]]
; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ICMP3]], [[OR]] ; MIPS32: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ICMP3]], [[AND3]]
; MIPS32: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND3]], [[ICMP4]]
; MIPS32: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[LOAD3]], [[COPY3]] ; MIPS32: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[LOAD3]], [[COPY3]]
; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[OR1]], [[C]] ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[OR1]], [[C]]
; MIPS32: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[ADD5]], [[AND4]] ; MIPS32: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[ADD5]], [[AND4]]
; MIPS32: $v0 = COPY [[ADD]](s32) ; MIPS32: $v0 = COPY [[ADD]](s32)
; MIPS32: $v1 = COPY [[ADD2]](s32) ; MIPS32: $v1 = COPY [[ADD2]](s32)
; MIPS32: $a0 = COPY [[ADD4]](s32) ; MIPS32: $a0 = COPY [[ADD4]](s32)
; MIPS32: $a1 = COPY [[ADD6]](s32) ; MIPS32: $a1 = COPY [[ADD6]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1 ; MIPS32: RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1
▲ Show 20 Lines • Show All 55 Lines • Show Last 20 Lines

llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir

Show First 20 Lines • Show All 255 Lines • ▼ Show 20 Lines bb.1.entry:
; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load (s32) from %fixed-stack.1) ; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load (s32) from %fixed-stack.1)
; MIPS32: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2 ; MIPS32: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
; MIPS32: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (load (s32) from %fixed-stack.2, align 8) ; MIPS32: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (load (s32) from %fixed-stack.2, align 8)
; MIPS32: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3 ; MIPS32: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
; MIPS32: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p0) :: (load (s32) from %fixed-stack.3) ; MIPS32: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p0) :: (load (s32) from %fixed-stack.3)
; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[LOAD]], [[COPY]] ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[LOAD]], [[COPY]]
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[LOAD]](s32), [[COPY]] ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[LOAD]](s32), [[COPY]]
; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[LOAD1]], [[COPY1]] ; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[LOAD1]], [[COPY1]]
; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[SUB1]](s32), [[LOAD1]]
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]] ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
; MIPS32: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[AND]] ; MIPS32: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[AND]]
; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[LOAD1]](s32), [[COPY1]] ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[LOAD1]](s32), [[COPY1]] ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SUB1]](s32), [[C1]]
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]] ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP2]], [[ICMP]]
; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), [[ICMP]], [[ICMP2]] ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[ICMP1]], [[AND1]]
; MIPS32: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[LOAD2]], [[COPY2]] ; MIPS32: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[LOAD2]], [[COPY2]]
; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C]] ; MIPS32: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[SUB3]](s32), [[LOAD2]]
; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C]]
; MIPS32: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SUB3]], [[AND2]] ; MIPS32: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SUB3]], [[AND2]]
; MIPS32: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[LOAD2]](s32), [[COPY2]] ; MIPS32: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SUB3]](s32), [[C1]]
; MIPS32: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[LOAD2]](s32), [[COPY2]] ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ICMP4]], [[OR]]
; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ICMP3]], [[C]] ; MIPS32: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ICMP3]], [[AND3]]
; MIPS32: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND3]](s32), [[SELECT]], [[ICMP4]]
; MIPS32: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[LOAD3]], [[COPY3]] ; MIPS32: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[LOAD3]], [[COPY3]]
; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C]] ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[OR1]], [[C]]
; MIPS32: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB5]], [[AND4]] ; MIPS32: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB5]], [[AND4]]
; MIPS32: $v0 = COPY [[SUB]](s32) ; MIPS32: $v0 = COPY [[SUB]](s32)
; MIPS32: $v1 = COPY [[SUB2]](s32) ; MIPS32: $v1 = COPY [[SUB2]](s32)
; MIPS32: $a0 = COPY [[SUB4]](s32) ; MIPS32: $a0 = COPY [[SUB4]](s32)
; MIPS32: $a1 = COPY [[SUB6]](s32) ; MIPS32: $a1 = COPY [[SUB6]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1 ; MIPS32: RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1
%2:_(s32) = COPY $a0 %2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1 %3:_(s32) = COPY $a1
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llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll

Show First 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
entry: entry:
%add = add i64 %b, %a %add = add i64 %b, %a
ret i64 %add ret i64 %add
} }
define i128 @add_i128(i128 %a, i128 %b) { define i128 @add_i128(i128 %a, i128 %b) {
; MIPS32-LABEL: add_i128: ; MIPS32-LABEL: add_i128:
; MIPS32: # %bb.0: # %entry ; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: move $3, $4 ; MIPS32-NEXT: move $8, $4
; MIPS32-NEXT: move $4, $6 ; MIPS32-NEXT: move $3, $5
; MIPS32-NEXT: addiu $1, $sp, 16 ; MIPS32-NEXT: addiu $1, $sp, 16
; MIPS32-NEXT: lw $2, 0($1) ; MIPS32-NEXT: lw $2, 0($1)
; MIPS32-NEXT: addiu $1, $sp, 20 ; MIPS32-NEXT: addiu $1, $sp, 20
; MIPS32-NEXT: lw $8, 0($1) ; MIPS32-NEXT: lw $4, 0($1)
; MIPS32-NEXT: addiu $1, $sp, 24 ; MIPS32-NEXT: addiu $1, $sp, 24
; MIPS32-NEXT: lw $6, 0($1) ; MIPS32-NEXT: lw $5, 0($1)
; MIPS32-NEXT: addiu $1, $sp, 28 ; MIPS32-NEXT: addiu $1, $sp, 28
; MIPS32-NEXT: lw $1, 0($1) ; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: addu $2, $2, $3 ; MIPS32-NEXT: addu $2, $2, $8
; MIPS32-NEXT: sltu $9, $2, $3 ; MIPS32-NEXT: sltu $9, $2, $8
; MIPS32-NEXT: addu $3, $8, $5 ; MIPS32-NEXT: addu $3, $4, $3
; MIPS32-NEXT: andi $5, $9, 1 ; MIPS32-NEXT: sltu $4, $3, $4
; MIPS32-NEXT: addu $3, $3, $5 ; MIPS32-NEXT: andi $8, $9, 1
; MIPS32-NEXT: xor $5, $3, $8 ; MIPS32-NEXT: addu $3, $3, $8
; MIPS32-NEXT: sltiu $5, $5, 1 ; MIPS32-NEXT: sltiu $8, $3, 1
; MIPS32-NEXT: sltu $8, $3, $8 ; MIPS32-NEXT: and $8, $8, $9
; MIPS32-NEXT: and $5, $5, $9 ; MIPS32-NEXT: or $8, $4, $8
; MIPS32-NEXT: or $8, $5, $8 ; MIPS32-NEXT: addu $4, $5, $6
; MIPS32-NEXT: addu $4, $6, $4 ; MIPS32-NEXT: sltu $5, $4, $5
; MIPS32-NEXT: andi $5, $8, 1 ; MIPS32-NEXT: andi $6, $8, 1
; MIPS32-NEXT: addu $4, $4, $5 ; MIPS32-NEXT: addu $4, $4, $6
; MIPS32-NEXT: xor $5, $4, $6 ; MIPS32-NEXT: sltiu $6, $4, 1
; MIPS32-NEXT: sltiu $5, $5, 1 ; MIPS32-NEXT: and $6, $6, $8
; MIPS32-NEXT: sltu $6, $4, $6
; MIPS32-NEXT: and $5, $5, $8
; MIPS32-NEXT: or $5, $5, $6 ; MIPS32-NEXT: or $5, $5, $6
; MIPS32-NEXT: addu $1, $1, $7 ; MIPS32-NEXT: addu $1, $1, $7
; MIPS32-NEXT: andi $5, $5, 1 ; MIPS32-NEXT: andi $5, $5, 1
; MIPS32-NEXT: addu $5, $1, $5 ; MIPS32-NEXT: addu $5, $1, $5
; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop ; MIPS32-NEXT: nop
entry: entry:
%add = add i128 %b, %a %add = add i128 %b, %a
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llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll

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entry: entry:
%sub = sub i64 %b, %a %sub = sub i64 %b, %a
ret i64 %sub ret i64 %sub
} }
define i128 @sub_i128(i128 %a, i128 %b) { define i128 @sub_i128(i128 %a, i128 %b) {
; MIPS32-LABEL: sub_i128: ; MIPS32-LABEL: sub_i128:
; MIPS32: # %bb.0: # %entry ; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: move $10, $5 ; MIPS32-NEXT: move $9, $4
; MIPS32-NEXT: move $9, $6
; MIPS32-NEXT: addiu $1, $sp, 16 ; MIPS32-NEXT: addiu $1, $sp, 16
; MIPS32-NEXT: lw $3, 0($1) ; MIPS32-NEXT: lw $8, 0($1)
; MIPS32-NEXT: addiu $1, $sp, 20 ; MIPS32-NEXT: addiu $1, $sp, 20
; MIPS32-NEXT: lw $6, 0($1) ; MIPS32-NEXT: lw $3, 0($1)
; MIPS32-NEXT: addiu $1, $sp, 24 ; MIPS32-NEXT: addiu $1, $sp, 24
; MIPS32-NEXT: lw $5, 0($1) ; MIPS32-NEXT: lw $4, 0($1)
; MIPS32-NEXT: addiu $1, $sp, 28 ; MIPS32-NEXT: addiu $1, $sp, 28
; MIPS32-NEXT: lw $1, 0($1) ; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: subu $2, $3, $4 ; MIPS32-NEXT: subu $2, $8, $9
; MIPS32-NEXT: sltu $4, $3, $4 ; MIPS32-NEXT: sltu $9, $8, $9
; MIPS32-NEXT: subu $3, $6, $10 ; MIPS32-NEXT: subu $8, $3, $5
; MIPS32-NEXT: andi $8, $4, 1 ; MIPS32-NEXT: sltu $5, $3, $8
; MIPS32-NEXT: subu $3, $3, $8 ; MIPS32-NEXT: andi $3, $9, 1
; MIPS32-NEXT: xor $8, $6, $10 ; MIPS32-NEXT: subu $3, $8, $3
; MIPS32-NEXT: sltiu $8, $8, 1
; MIPS32-NEXT: sltu $6, $6, $10
; MIPS32-NEXT: andi $8, $8, 1
; MIPS32-NEXT: movn $6, $4, $8
; MIPS32-NEXT: subu $4, $5, $9
; MIPS32-NEXT: andi $8, $6, 1
; MIPS32-NEXT: subu $4, $4, $8
; MIPS32-NEXT: xor $8, $5, $9
; MIPS32-NEXT: sltiu $8, $8, 1 ; MIPS32-NEXT: sltiu $8, $8, 1
; MIPS32-NEXT: sltu $5, $5, $9 ; MIPS32-NEXT: and $8, $8, $9
; MIPS32-NEXT: andi $8, $8, 1 ; MIPS32-NEXT: or $8, $5, $8
; MIPS32-NEXT: movn $5, $6, $8 ; MIPS32-NEXT: subu $6, $4, $6
; MIPS32-NEXT: sltu $5, $4, $6
; MIPS32-NEXT: andi $4, $8, 1
; MIPS32-NEXT: subu $4, $6, $4
; MIPS32-NEXT: sltiu $6, $6, 1
; MIPS32-NEXT: and $6, $6, $8
; MIPS32-NEXT: or $5, $5, $6
; MIPS32-NEXT: subu $1, $1, $7 ; MIPS32-NEXT: subu $1, $1, $7
; MIPS32-NEXT: andi $5, $5, 1 ; MIPS32-NEXT: andi $5, $5, 1
; MIPS32-NEXT: subu $5, $1, $5 ; MIPS32-NEXT: subu $5, $1, $5
; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop ; MIPS32-NEXT: nop
entry: entry:
%sub = sub i128 %b, %a %sub = sub i128 %b, %a
ret i128 %sub ret i128 %sub
} }