[PowerPC] Implement builtin for mffsl

[qiucf]

Summary

mffsl is available since ISA 3.0.

GCC emits extra code to support __builtin_mffsl on targets earlier than Power9, while this patch doesn't do it. In this patch it is actually named __builtin_ppc_mffsl to follow our convention.

[tuliom]

LGTM

[nemanjai]

Thanks for implementing this.

clang/include/clang/Basic/BuiltinsPPC.def

 // store
 BUILTIN(__builtin_ppc_store2r, "vUiUs*", "")
 BUILTIN(__builtin_ppc_store4r, "vUiUi*", "")
 TARGET_BUILTIN(__builtin_ppc_store8r, "vULLiULLi*", "", "isa-v206-instructions")
 TARGET_BUILTIN(__builtin_ppc_extract_exp, "Uid", "", "power9-vector")
 TARGET_BUILTIN(__builtin_ppc_extract_sig, "ULLid", "", "power9-vector")
 BUILTIN(__builtin_ppc_mtfsb0, "vUIi", "")
 BUILTIN(__builtin_ppc_mtfsb1, "vUIi", "")
+TARGET_BUILTIN(__builtin_ppc_mffsl, "d", "", "isa-v30-instructions")
 BUILTIN(__builtin_ppc_mtfsf, "vUIiUi", "")
 BUILTIN(__builtin_ppc_mtfsfi, "vUIiUIi", "")
 TARGET_BUILTIN(__builtin_ppc_insert_exp, "ddULLi", "", "power9-vector")
 BUILTIN(__builtin_ppc_fmsub, "dddd", "")
 BUILTIN(__builtin_ppc_fmsubs, "ffff", "")
 BUILTIN(__builtin_ppc_fnmadd, "dddd", "")
 BUILTIN(__builtin_ppc_fnmadds, "ffff", "")
 BUILTIN(__builtin_ppc_fnmsub, "dddd", "")

clang/test/CodeGen/PowerPC/builtins-ppc.c

 
 void test_builtin_ppc_flm() {
   volatile double res;
   // CHECK: call double @llvm.ppc.readflm()
   res = __builtin_readflm();
 
   // CHECK: call double @llvm.ppc.setflm(double %1)
   res = __builtin_setflm(res);
+
+#ifdef _ARCH_PWR9
+  // P9: call double @llvm.ppc.mffsl()
+  res = __builtin_ppc_mffsl();
+#endif
 }
 
 double test_builtin_unpack_ldbl(long double x) {
   // CHECK: call double @llvm.ppc.unpack.longdouble(ppc_fp128 %0, i32 1)
   return __builtin_unpack_longdouble(x, 1);
 }
 
 long double test_builtin_pack_ldbl(double x, double y) {

llvm/include/llvm/IR/IntrinsicsPowerPC.td

let TargetPrefix = "ppc" in {  // All intrinsics start with "llvm.ppc.".
   def int_ppc_dcbtst_with_hint: Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty],
     [IntrArgMemOnly, NoCapture<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
   def int_ppc_dcbzl : Intrinsic<[], [llvm_ptr_ty], []>;
 
   // Get content from current FPSCR register
   def int_ppc_readflm : ClangBuiltin<"__builtin_readflm">,
                         DefaultAttrsIntrinsic<[llvm_double_ty], [],
                                               [IntrNoMerge, IntrHasSideEffects]>;
+  def int_ppc_mffsl : ClangBuiltin<"__builtin_ppc_mffsl">,
+                      DefaultAttrsIntrinsic<[llvm_double_ty], [],
+                                            [IntrNoMerge, IntrHasSideEffects]>;
+
   // Set FPSCR register, and return previous content
   def int_ppc_setflm : ClangBuiltin<"__builtin_setflm">,
                        DefaultAttrsIntrinsic<[llvm_double_ty], [llvm_double_ty],
                                              [IntrHasSideEffects]>;
 
   // Intrinsics for [double]word extended forms of divide instructions
   def int_ppc_divwe : ClangBuiltin<"__builtin_divwe">,
       DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],

llvm/lib/Target/PowerPC/PPCInstrInfo.td

 
 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
           (TCRETURNdi texternalsym:$dst, imm:$imm)>;
 
 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
           (TCRETURNri CTRRC:$dst, imm:$imm)>;
 
 def : Pat<(int_ppc_readflm), (MFFS)>;
+def : Pat<(int_ppc_mffsl), (MFFSL)>;
 
 // Hi and Lo for Darwin Global Addresses.
 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;

llvm/test/CodeGen/PowerPC/read-set-flm.ll

entry:
   store double %0, ptr %f1, align 8
   call void @readonly_func()
   %1 = call double @llvm.ppc.readflm()
   store double %1, ptr %f2, align 8
   %2 = call contract double @llvm.ppc.setflm(double %f3)
   ret void
 }
 
+define double @mffsl() {
+; CHECK-LABEL: mffsl:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mffsl 1
+; CHECK-NEXT:    blr
+entry:
+  %x = call double @llvm.ppc.mffsl()
+  ret double %x
+}
+
 declare void @effect_func()
 declare void @readonly_func() #1
+declare double @llvm.ppc.mffsl()
 declare double @llvm.ppc.readflm()
 declare double @llvm.ppc.setflm(double)
 declare double @llvm.experimental.constrained.fadd.f64(double, double, metadata, metadata)
 declare double @llvm.experimental.constrained.fdiv.f64(double, double, metadata, metadata)
 
 attributes #0 = { strictfp }
 attributes #1 = { readonly }