[CodeGen] Set regunitmasks for leaf regs to all instead of none

[foad]

Summary

This simplifies every use of MCRegUnitMaskIterator.

llvm/include/llvm/CodeGen/LiveRegUnits.h

for (MCRegUnit Unit : TRI->regunits(Reg))
       Units.set(Unit);
   }
 
   /// Adds register units covered by physical register \p Reg that are
   /// part of the lanemask \p Mask.
   void addRegMasked(MCPhysReg Reg, LaneBitmask Mask) {
     for (MCRegUnitMaskIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) {
       LaneBitmask UnitMask = (*Unit).second;
-      if (UnitMask.none() || (UnitMask & Mask).any())
+      if ((UnitMask & Mask).any())
         Units.set((*Unit).first);
     }
   }
 
   /// Removes all register units covered by physical register \p Reg.
   void removeReg(MCPhysReg Reg) {
     for (MCRegUnit Unit : TRI->regunits(Reg))
       Units.reset(Unit);

llvm/lib/CodeGen/MachineSink.cpp

static void updateLiveIn(MachineInstr *MI, MachineBasicBlock *SuccBB,
   MachineFunction &MF = *SuccBB->getParent();
   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
   for (unsigned DefReg : DefedRegsInCopy)
     for (MCPhysReg S : TRI->subregs_inclusive(DefReg))
       SuccBB->removeLiveIn(S);
   for (auto U : UsedOpsInCopy) {
     Register SrcReg = MI->getOperand(U).getReg();
     LaneBitmask Mask;
-    for (MCRegUnitMaskIterator S(SrcReg, TRI); S.isValid(); ++S) {
+    for (MCRegUnitMaskIterator S(SrcReg, TRI); S.isValid(); ++S)
       Mask |= (*S).second;
-    }
-    SuccBB->addLiveIn(SrcReg, Mask.any() ? Mask : LaneBitmask::getAll());
+    SuccBB->addLiveIn(SrcReg, Mask);
   }
   SuccBB->sortUniqueLiveIns();
 }
 
 static bool hasRegisterDependency(MachineInstr *MI,
                                   SmallVectorImpl<unsigned> &UsedOpsInCopy,
                                   SmallVectorImpl<unsigned> &DefedRegsInCopy,
                                   LiveRegUnits &ModifiedRegUnits,

llvm/lib/CodeGen/RDFRegisters.cpp

for (uint32_t U = 0, NU = TRI.getNumRegUnits(); U != NU; ++U) {
     if (R.isValid()) {
       UnitInfos[U].Mask = LaneBitmask::getAll();
       UnitInfos[U].Reg = F;
     } else {
       for (MCRegUnitMaskIterator I(F, &TRI); I.isValid(); ++I) {
         std::pair<uint32_t, LaneBitmask> P = *I;
         UnitInfo &UI = UnitInfos[P.first];
         UI.Reg = F;
-        if (P.second.any()) {
-          UI.Mask = P.second;
-        } else {
-          if (const TargetRegisterClass *RC = RegInfos[F].RegClass)
-            UI.Mask = RC->LaneMask;
-          else
-            UI.Mask = LaneBitmask::getAll();
-        }
       }
     }
   }
 
   for (const uint32_t *RM : TRI.getRegMasks())
     RegMasks.insert(RM);
   for (const MachineBasicBlock &B : mf)
     for (const MachineInstr &In : B)
std::set<RegisterId> PhysicalRegisterInfo::getUnits(RegisterRef RR) const {
   if (RR.Reg == 0)
     return Units; // Empty
 
   if (RR.isReg()) {
     if (RR.Mask.none())
       return Units; // Empty
     for (MCRegUnitMaskIterator UM(RR.idx(), &TRI); UM.isValid(); ++UM) {
       auto [U, M] = *UM;
-      if (M.none() || (M & RR.Mask).any())
+      if ((M & RR.Mask).any())
         Units.insert(U);
     }
     return Units;
   }
 
   assert(RR.isMask());
   unsigned NumRegs = TRI.getNumRegs();
   const uint32_t *MB = getRegMaskBits(RR.idx());
bool PhysicalRegisterInfo::equal_to(RegisterRef A, RegisterRef B) const {
 
   // Compare reg units lexicographically.
   MCRegUnitMaskIterator AI(A.Reg, &getTRI());
   MCRegUnitMaskIterator BI(B.Reg, &getTRI());
   while (AI.isValid() && BI.isValid()) {
     auto [AReg, AMask] = *AI;
     auto [BReg, BMask] = *BI;
 
-    // Lane masks are "none" for units that don't correspond to subregs
-    // e.g. a single unit in a leaf register, or aliased unit.
-    if (AMask.none())
-      AMask = LaneBitmask::getAll();
-    if (BMask.none())
-      BMask = LaneBitmask::getAll();
-
     // If both iterators point to a unit contained in both A and B, then
     // compare the units.
     if ((AMask & A.Mask).any() && (BMask & B.Mask).any()) {
       if (AReg != BReg)
         return false;
       // Units are equal, move on to the next ones.
       ++AI;
       ++BI;
bool PhysicalRegisterInfo::less(RegisterRef A, RegisterRef B) const {
 
   // Compare reg units lexicographically.
   llvm::MCRegUnitMaskIterator AI(A.Reg, &getTRI());
   llvm::MCRegUnitMaskIterator BI(B.Reg, &getTRI());
   while (AI.isValid() && BI.isValid()) {
     auto [AReg, AMask] = *AI;
     auto [BReg, BMask] = *BI;
 
-    // Lane masks are "none" for units that don't correspond to subregs
-    // e.g. a single unit in a leaf register, or aliased unit.
-    if (AMask.none())
-      AMask = LaneBitmask::getAll();
-    if (BMask.none())
-      BMask = LaneBitmask::getAll();
-
     // If both iterators point to a unit contained in both A and B, then
     // compare the units.
     if ((AMask & A.Mask).any() && (BMask & B.Mask).any()) {
       if (AReg != BReg)
         return AReg < BReg;
       // Units are equal, move on to the next ones.
       ++AI;
       ++BI;

 }
 
 bool RegisterAggr::hasAliasOf(RegisterRef RR) const {
   if (RR.isMask())
     return Units.anyCommon(PRI.getMaskUnits(RR.Reg));
 
   for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) {
     std::pair<uint32_t, LaneBitmask> P = *U;
-    if (P.second.none() || (P.second & RR.Mask).any())
+    if ((P.second & RR.Mask).any())
       if (Units.test(P.first))
         return true;
   }
   return false;
 }
 
 bool RegisterAggr::hasCoverOf(RegisterRef RR) const {
   if (RR.isMask()) {
     BitVector T(PRI.getMaskUnits(RR.Reg));
     return T.reset(Units).none();
   }
 
   for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) {
     std::pair<uint32_t, LaneBitmask> P = *U;
-    if (P.second.none() || (P.second & RR.Mask).any())
+    if ((P.second & RR.Mask).any())
       if (!Units.test(P.first))
         return false;
   }
   return true;
 }
 
 RegisterAggr &RegisterAggr::insert(RegisterRef RR) {
   if (RR.isMask()) {
     Units |= PRI.getMaskUnits(RR.Reg);
     return *this;
   }
 
   for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) {
     std::pair<uint32_t, LaneBitmask> P = *U;
-    if (P.second.none() || (P.second & RR.Mask).any())
+    if ((P.second & RR.Mask).any())
       Units.set(P.first);
   }
   return *this;
 }
 
 RegisterAggr &RegisterAggr::insert(const RegisterAggr &RG) {
   Units |= RG.Units;
   return *this;
RegisterRef RegisterAggr::makeRegRef() const {
   int F = Regs.find_first();
   if (F <= 0)
     return RegisterRef();
 
   LaneBitmask M;
   for (MCRegUnitMaskIterator I(F, &PRI.getTRI()); I.isValid(); ++I) {
     std::pair<uint32_t, LaneBitmask> P = *I;
     if (Units.test(P.first))
-      M |= P.second.none() ? LaneBitmask::getAll() : P.second;
+      M |= P.second;
   }
   return RegisterRef(F, M);
 }
 
 RegisterAggr::ref_iterator::ref_iterator(const RegisterAggr &RG, bool End)
     : Owner(&RG) {
   for (int U = RG.Units.find_first(); U >= 0; U = RG.Units.find_next(U)) {
     RegisterRef R = RG.PRI.getRefForUnit(U);

llvm/utils/TableGen/CodeGenRegisters.cpp

for (unsigned UnitIdx = 0, UnitEnd = NumNativeRegUnits;
     }
   }
 }
 
 void CodeGenRegBank::computeRegUnitLaneMasks() {
   for (auto &Register : Registers) {
     // Create an initial lane mask for all register units.
     const auto &RegUnits = Register.getRegUnits();
-    CodeGenRegister::RegUnitLaneMaskList
-        RegUnitLaneMasks(RegUnits.count(), LaneBitmask::getNone());
+    CodeGenRegister::RegUnitLaneMaskList RegUnitLaneMasks(
+        RegUnits.count(), LaneBitmask::getAll());
     // Iterate through SubRegisters.
     typedef CodeGenRegister::SubRegMap SubRegMap;
     const SubRegMap &SubRegs = Register.getSubRegs();
     for (auto S : SubRegs) {
       CodeGenRegister *SubReg = S.second;
       // Ignore non-leaf subregisters, their lane masks are fully covered by
       // the leaf subregisters anyway.
       if (!SubReg->getSubRegs().empty())
         continue;
       CodeGenSubRegIndex *SubRegIndex = S.first;
       const CodeGenRegister *SubRegister = S.second;
       LaneBitmask LaneMask = SubRegIndex->LaneMask;
       // Distribute LaneMask to Register Units touched.
       for (unsigned SUI : SubRegister->getRegUnits()) {
         bool Found = false;
         unsigned u = 0;
         for (unsigned RU : RegUnits) {
           if (SUI == RU) {
-            RegUnitLaneMasks[u] |= LaneMask;
+            RegUnitLaneMasks[u] &= LaneMask;
             assert(!Found);
             Found = true;
           }
           ++u;
         }
         (void)Found;
         assert(Found);
       }

llvm/utils/TableGen/RegisterInfoEmitter.cpp

for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I, ++i) {
 
     const SparseBitVector<> &RUs = Reg.getNativeRegUnits();
     DiffSeqs.add(diffEncode(RegUnitLists[i], RUs));
 
     const auto &RUMasks = Reg.getRegUnitLaneMasks();
     MaskVec &LaneMaskVec = RegUnitLaneMasks[i];
     assert(LaneMaskVec.empty());
     llvm::append_range(LaneMaskVec, RUMasks);
-    // Terminator mask should not be used inside of the list.
-#ifndef NDEBUG
-    for (LaneBitmask M : LaneMaskVec) {
-      assert(!M.all() && "terminator mask should not be part of the list");
-    }
-#endif
     LaneMaskSeqs.add(LaneMaskVec);
   }
 
   // Compute the final layout of the sequence table.
   DiffSeqs.layout();
   LaneMaskSeqs.layout();
   SubRegIdxSeqs.layout();
 
   OS << "namespace llvm {\n\n";
 
   const std::string &TargetName = std::string(Target.getName());
 
   // Emit the shared table of differential lists.
   OS << "extern const int16_t " << TargetName << "RegDiffLists[] = {\n";
   DiffSeqs.emit(OS, printDiff16);
   OS << "};\n\n";
 
   // Emit the shared table of regunit lane mask sequences.
   OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[] = {\n";
+  // TODO: Omit the terminator since it is never used. The length of this list
+  // is known implicitly from the corresponding reg unit list.
   LaneMaskSeqs.emit(OS, printMask, "LaneBitmask::getAll()");
   OS << "};\n\n";
 
   // Emit the table of sub-register indexes.
   OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n";
   SubRegIdxSeqs.emit(OS, printSubRegIndex);
   OS << "};\n\n";