This is an archive of the discontinued LLVM Phabricator instance.

[MachineScheduler] Account for lane masks in basic block liveins
ClosedPublic

Authored by foad on Aug 10 2023, 9:24 AM.

Diff Detail

Event Timeline

foad created this revision.Aug 10 2023, 9:24 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 10 2023, 9:24 AM
foad requested review of this revision.Aug 10 2023, 9:24 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 10 2023, 9:24 AM
foad added a comment.Aug 10 2023, 9:26 AM

This seems to have very little effect. I have not looked into why.

llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
228–229

This seems to be some weird special case in the generated LaneMaskLists for registers with a single regunit. Or something.

foad updated this revision to Diff 549349.Aug 11 2023, 5:26 AM

Simplify

arsenm added a subscriber: arsenm.Aug 11 2023, 10:35 AM
arsenm added inline comments.
llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
228–229

the none is just broken, it should emit all

foad added inline comments.Aug 14 2023, 12:46 AM
llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
228–229

Yeah, that was the first thing I tried changing, but it seemed to break a whole load of other tests and I didn't have time to investigate.

foad added inline comments.Aug 14 2023, 6:34 AM
llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
228–229

I got it working: D157864

arsenm accepted this revision.Aug 14 2023, 10:11 AM

Slightly surprised there aren't more test diffs

This revision is now accepted and ready to land.Aug 14 2023, 10:11 AM
foad added a comment.Aug 15 2023, 1:53 AM

Slightly surprised there aren't more test diffs

Yeah. My hunch is that the masks in liveins are almost always all-1s.