[MachineScheduler] Account for lane masks in basic block liveins

[foad]

This seems to have very little effect. I have not looked into why.

llvm/lib/CodeGen/ScheduleDAGInstrs.cpp

228–229

This seems to be some weird special case in the generated LaneMaskLists for registers with a single regunit. Or something.

[foad]

Simplify

[arsenm]

llvm/lib/CodeGen/ScheduleDAGInstrs.cpp

228–229

the none is just broken, it should emit all

[foad]

llvm/lib/CodeGen/ScheduleDAGInstrs.cpp

228–229

Yeah, that was the first thing I tried changing, but it seemed to break a whole load of other tests and I didn't have time to investigate.

[foad]

llvm/lib/CodeGen/ScheduleDAGInstrs.cpp

228–229

I got it working: D157864

[foad]

Rebase on D157864

[arsenm]

Slightly surprised there aren't more test diffs

[foad]

In D157633#4585681, @arsenm wrote:

Slightly surprised there aren't more test diffs

Yeah. My hunch is that the masks in liveins are almost always all-1s.

llvm/lib/CodeGen/ScheduleDAGInstrs.cpp

for (const MachineOperand &MO : ExitMI->all_uses()) {
       }
     }
   }
   if (!ExitMI || (!ExitMI->isCall() && !ExitMI->isBarrier())) {
     // For others, e.g. fallthrough, conditional branch, assume the exit
     // uses all the registers that are livein to the successor blocks.
     for (const MachineBasicBlock *Succ : BB->successors()) {
       for (const auto &LI : Succ->liveins()) {
-        // TODO: Use LI.LaneMask to refine this.
-        for (MCRegUnit Unit : TRI->regunits(LI.PhysReg)) {
-          if (!Uses.contains(Unit))
+        for (MCRegUnitMaskIterator U(LI.PhysReg, TRI); U.isValid(); ++U) {
+          auto [Unit, Mask] = *U;
+          if ((Mask & LI.LaneMask).any() && !Uses.contains(Unit))
             Uses.insert(PhysRegSUOper(&ExitSU, -1, Unit));
         }
       }
     }
   }
 }
 
 /// MO is an operand of SU's instruction that defines a physical register. Adds
 /// data dependencies from SU to any uses of the physical register.

llvm/test/CodeGen/AMDGPU/loop-live-out-copy-undef-subrange.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck %s
 
 ; This example used to produce a verifier error resulting from the
 ; register coalescer leaving behind a false live interval when a live
 ; out copy introduced new liveness for a subregister.
 
 define <3 x float> @liveout_undef_subrange(<3 x float> %arg) {
 ; CHECK-LABEL: liveout_undef_subrange:
 ; CHECK:       ; %bb.0: ; %bb
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_add_f32_e32 v3, v2, v2
-; CHECK-NEXT:    v_add_f32_e32 v0, v0, v0
 ; CHECK-NEXT:    s_mov_b64 s[4:5], 0
 ; CHECK-NEXT:    ; kill: killed $vgpr1
+; CHECK-NEXT:    v_add_f32_e32 v0, v0, v0
 ; CHECK-NEXT:  .LBB0_1: ; %bb1
 ; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    v_cmp_neq_f32_e32 vcc, 0, v2
 ; CHECK-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
 ; CHECK-NEXT:    s_andn2_b64 exec, exec, s[4:5]
 ; CHECK-NEXT:    s_cbranch_execnz .LBB0_1
 ; CHECK-NEXT:  ; %bb.2: ; %bb2
 ; CHECK-NEXT:    ; in Loop: Header=BB0_1 Depth=1