[JITLink][AArch32] Implement ELF::R_ARM_CALL relocation

[Eymay]

Summary

• Added WritableArmRelocation and ArmRelocation Structs
• Encode/Decode funcs for B/BL A1 and BLX A2 encodings
• Add ARM helper functions, consistent with the existing Thumb helper functions
• Add Test for ELF::R_ARM_CALL

[sgraenitz]

Looks great, thanks! I think at some point we should add a .thumb section with .thumb_func functions to our tests, so we get coverage for the code that handles ARM-Thumb transitions. However, I guess we need ARM stubs for it first?

llvm/lib/ExecutionEngine/JITLink/aarch32.cpp

295

Oh right, this has to go away!

424

I think we don't need to worry about alignment here, because Thumb requirements are lower than ARM. Ideally we'd have test coverage though :)

[Eymay]

In D157533#4574209, @sgraenitz wrote:

Looks great, thanks! I think at some point we should add a .thumb section with .thumb_func functions to our tests, so we get coverage for the code that handles ARM-Thumb transitions. However, I guess we need ARM stubs for it first?

Great idea, I agree an arm_thumb_interworking test is necessary. Without stubs for Arm, we should be able to test bl thumb_func as long as it is in range.
Another thing we need, for this test to work, is a TargetFlag dependent triple like @lhames mentioned on discourse.

[Eymay]

NFC

• Add descr to Arm_Call enum.
• Remove alignment related comments.
• Standardize comment marker as '#'

[sgraenitz]

Can we align the test with the (now) existing ELF_static_arm_reloc.s please? The rest should be ready to land I think.

llvm/lib/ExecutionEngine/JITLink/aarch32.cpp

21

You include it in the header already, so it isn't necessary here.

[Eymay]

Updated test regarding ELF_static_thumb_reloc.s and squashed commits

[Eymay]

In D157533#4641795, @sgraenitz wrote:

Can we align the test with the (now) existing ELF_static_arm_reloc.s please? The rest should be ready to land I think.

Sure, updated the test.

[Eymay]

(NFC) Updated enc/decode description comment bits with precise number of 0's

[Eymay]

(NFC) Removed leading zeros from immediates in comments

[sgraenitz]

Thanks for the updates! Please have a look at one last detail in the test.

llvm/test/ExecutionEngine/JITLink/AArch32/ELF_static_arm_reloc.s

17

This is correct and works, but the attentive reader might wonder where the -4 is coming from.

The branch offset in Thumb state is equivalent to the size of the branch instruction, i.e. next_pc does a +4 and thus we don't need the -4 in the Thumb test here.

Surprisingly, the branch offset in ARM state is 8 and not 4 as next_pc tells us. That's because the branch instruction increments the PC register twice since it runs an implicit prefetch instruction (seems to be a ARM legacy thing that the linker has to know that). I guess ideally we could write next_pc(next_pc(call_site)) but the checker cannot evaluate that expression. Thus, I wonder if it would be better to drop the next_pc here, write out the branch offset explicitly and add a comment like this.

What do you think?

[Eymay]

llvm/test/ExecutionEngine/JITLink/AArch32/ELF_static_arm_reloc.s

17

The magic number 4 doesn't really look good and it makes sense to show the condition explicitly. Thanks for the explanation of why the offset is present!

[Eymay]

Update jitlink-check test to indicate the offset explicitly.

[Eymay]

update author mail

[sgraenitz]

Thanks! Let me double-check the tests on my machine and land this for you.

[dyung]

@Eymay and @sgraenitz this commit seems to be causing build failures on Windows build bots, can you take a look and revert if you need time to investigate?

C:\bin\ccache.exe C:\PROGRA~2\MICROS~1\2019\BUILDT~1\VC\Tools\MSVC\1429~1.301\bin\HostX64\x64\cl.exe  /nologo /TP -DGTEST_HAS_RTTI=0 -DUNICODE -D_CRT_NONSTDC_NO_DEPRECATE -D_CRT_NONSTDC_NO_WARNINGS -D_CRT_SECURE_NO_DEPRECATE -D_CRT_SECURE_NO_WARNINGS -D_GLIBCXX_ASSERTIONS -D_HAS_EXCEPTIONS=0 -D_LIBCPP_ENABLE_HARDENED_MODE -D_SCL_SECURE_NO_DEPRECATE -D_SCL_SECURE_NO_WARNINGS -D_UNICODE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -Iunittests\ExecutionEngine\JITLink -IZ:\b\llvm-clang-x86_64-sie-win\llvm-project\llvm\unittests\ExecutionEngine\JITLink -Iinclude -IZ:\b\llvm-clang-x86_64-sie-win\llvm-project\llvm\include -IZ:\b\llvm-clang-x86_64-sie-win\llvm-project\third-party\unittest\googletest\include -IZ:\b\llvm-clang-x86_64-sie-win\llvm-project\third-party\unittest\googlemock\include /DWIN32 /D_WINDOWS   /Zc:inline /Zc:preprocessor /Zc:__cplusplus /Oi /bigobj /permissive- /W4 -wd4141 -wd4146 -wd4244 -wd4267 -wd4291 -wd4351 -wd4456 -wd4457 -wd4458 -wd4459 -wd4503 -wd4624 -wd4722 -wd4100 -wd4127 -wd4512 -wd4505 -wd4610 -wd4510 -wd4702 -wd4245 -wd4706 -wd4310 -wd4701 -wd4703 -wd4389 -wd4611 -wd4805 -wd4204 -wd4577 -wd4091 -wd4592 -wd4319 -wd4709 -wd5105 -wd4324 -w14062 -we4238 /Gw /O2 /Ob2  -MD  /EHs-c- /GR- -UNDEBUG -std:c++17 /showIncludes /Founittests\ExecutionEngine\JITLink\CMakeFiles\JITLinkTests.dir\AArch32Tests.cpp.obj /Fdunittests\ExecutionEngine\JITLink\CMakeFiles\JITLinkTests.dir\ /FS -c Z:\b\llvm-clang-x86_64-sie-win\llvm-project\llvm\unittests\ExecutionEngine\JITLink\AArch32Tests.cpp
Z:\b\llvm-clang-x86_64-sie-win\llvm-project\llvm\unittests\ExecutionEngine\JITLink\AArch32Tests.cpp(187): error C3493: 'ImmMask' cannot be implicitly captured because no default capture mode has been specified
Z:\b\llvm-clang-x86_64-sie-win\llvm-project\llvm\unittests\ExecutionEngine\JITLink\AArch32Tests.cpp(194): error C2064: term does not evaluate to a function taking 2 arguments
Z:\b\llvm-clang-x86_64-sie-win\llvm-project\llvm\unittests\ExecutionEngine\JITLink\AArch32Tests.cpp(194): error C2660: 'testing::internal::EqHelper::Compare': function does not take 3 arguments
Z:\b\llvm-clang-x86_64-sie-win\llvm-project\third-party\unittest\googletest\include\gtest/gtest.h(1562): note: see declaration of 'testing::internal::EqHelper::Compare'
Z:\b\llvm-clang-x86_64-sie-win\llvm-project\llvm\unittests\ExecutionEngine\JITLink\AArch32Tests.cpp(194): error C2737: 'gtest_ar': const object must be initialized
Z:\b\llvm-clang-x86_64-sie-win\llvm-project\llvm\unittests\ExecutionEngine\JITLink\AArch32Tests.cpp(195): error C2064: term does not evaluate to a function taking 2 arguments
Z:\b\llvm-clang-x86_64-sie-win\llvm-project\llvm\unittests\ExecutionEngine\JITLink\AArch32Tests.cpp(195): error C2660: 'testing::internal::EqHelper::Compare': function does not take 3 arguments
Z:\b\llvm-clang-x86_64-sie-win\llvm-project\third-party\unittest\googletest\include\gtest/gtest.h(1562): note: see declaration of 'testing::internal::EqHelper::Compare'
Z:\b\llvm-clang-x86_64-sie-win\llvm-project\llvm\unittests\ExecutionEngine\JITLink\AArch32Tests.cpp(195): error C2737: 'gtest_ar': const object must be initialized
Z:\b\llvm-clang-x86_64-sie-win\llvm-project\llvm\unittests\ExecutionEngine\JITLink\AArch32Tests.cpp(196): error C2064: term does not evaluate to a function taking 2 arguments
Z:\b\llvm-clang-x86_64-sie-win\llvm-project\llvm\unittests\ExecutionEngine\JITLink\AArch32Tests.cpp(196): error C2660: 'testing::internal::EqHelper::Compare': function does not take 3 arguments
Z:\b\llvm-clang-x86_64-sie-win\llvm-project\third-party\unittest\googletest\include\gtest/gtest.h(1562): note: see declaration of 'testing::internal::EqHelper::Compare'
Z:\b\llvm-clang-x86_64-sie-win\llvm-project\llvm\unittests\ExecutionEngine\JITLink\AArch32Tests.cpp(196): error C2737: 'gtest_ar': const object must be initialized
Z:\b\llvm-clang-x86_64-sie-win\llvm-project\llvm\unittests\ExecutionEngine\JITLink\AArch32Tests.cpp(197): error C2064: term does not evaluate to a function taking 2 arguments
Z:\b\llvm-clang-x86_64-sie-win\llvm-project\llvm\unittests\ExecutionEngine\JITLink\AArch32Tests.cpp(197): error C2660: 'testing::internal::EqHelper::Compare': function does not take 3 arguments
Z:\b\llvm-clang-x86_64-sie-win\llvm-project\third-party\unittest\googletest\include\gtest/gtest.h(1562): note: see declaration of 'testing::internal::EqHelper::Compare'
Z:\b\llvm-clang-x86_64-sie-win\llvm-project\llvm\unittests\ExecutionEngine\JITLink\AArch32Tests.cpp(197): error C2737: 'gtest_ar': const object must be initialized
Z:\b\llvm-clang-x86_64-sie-win\llvm-project\llvm\unittests\ExecutionEngine\JITLink\AArch32Tests.cpp(198): error C2064: term does not evaluate to a function taking 2 arguments
Z:\b\llvm-clang-x86_64-sie-win\llvm-project\llvm\unittests\ExecutionEngine\JITLink\AArch32Tests.cpp(198): error C2660: 'testing::internal::CmpHelperNE': function does not take 3 arguments
Z:\b\llvm-clang-x86_64-sie-win\llvm-project\third-party\unittest\googletest\include\gtest/gtest.h(1620): note: see declaration of 'testing::internal::CmpHelperNE'
Z:\b\llvm-clang-x86_64-sie-win\llvm-project\llvm\unittests\ExecutionEngine\JITLink\AArch32Tests.cpp(198): error C2737: 'gtest_ar': const object must be initialized
Z:\b\llvm-clang-x86_64-sie-win\llvm-project\llvm\unittests\ExecutionEngine\JITLink\AArch32Tests.cpp(199): error C2064: term does not evaluate to a function taking 2 arguments
Z:\b\llvm-clang-x86_64-sie-win\llvm-project\llvm\unittests\ExecutionEngine\JITLink\AArch32Tests.cpp(199): error C2660: 'testing::internal::CmpHelperNE': function does not take 3 arguments
Z:\b\llvm-clang-x86_64-sie-win\llvm-project\third-party\unittest\googletest\include\gtest/gtest.h(1620): note: see declaration of 'testing::internal::CmpHelperNE'
Z:\b\llvm-clang-x86_64-sie-win\llvm-project\llvm\unittests\ExecutionEngine\JITLink\AArch32Tests.cpp(199): error C2737: 'gtest_ar': const object must be initialized

Some affected build bots:

• https://lab.llvm.org/buildbot/#/builders/216/builds/27224
• https://lab.llvm.org/buildbot/#/builders/123/builds/22266

[nickdesaulniers]

I can confirm this seems to be holding up presubmit testing on windows builds.
https://buildkite.com/llvm-project/github-pull-requests/builds/1789#018a8faa-2d4f-4850-93a2-13fa03d20dac

[Eymay]

We've experienced a similar issue and added a fix in an upcoming patch Implement ELF::R_ARM_MOVT_ABS and R_ARM_MOVW_ABS_NC. I don't have commit access so you may revert it until the new patch arrives and fixes it.

[dyung]

In D157533#4645500, @Eymay wrote:

We've experienced a similar issue and added a fix in an upcoming patch Implement ELF::R_ARM_MOVT_ABS and R_ARM_MOVW_ABS_NC. I don't have commit access so you may revert it until the new patch arrives and fixes it.

Is there an estimate when you might be able to commit the upcoming patch with a fix? A quick revert attempt shows conflicts meaning I would have to revert some further downline patches as well.

[sgraenitz]

I can fix it now

[sgraenitz]

https://github.com/llvm/llvm-project/commit/29f6c0fdfeb48f5f766d2ba02014358df69e8170 should avoid the issue

[dyung]

In D157533#4645527, @sgraenitz wrote:

https://github.com/llvm/llvm-project/commit/29f6c0fdfeb48f5f766d2ba02014358df69e8170 should avoid the issue

That worked, thanks!

llvm/include/llvm/ExecutionEngine/JITLink/aarch32.h

enum EdgeKind_aarch32 : Edge::Kind {
 
   LastDataRelocation = Data_Pointer32,
 
   ///
   /// Relocations of class Arm (covers fixed-width 4-byte instruction subset)
   ///
   FirstArmRelocation,
 
-  /// TODO: Arm_Call is here only as a placeholder for now.
+  /// Write immediate value for PC-relative branch with link (can bridge between
+  /// Arm and Thumb).
   Arm_Call = FirstArmRelocation,
 
   LastArmRelocation = Arm_Call,
 
   ///
   /// Relocations of class Thumb16 and Thumb32 (covers Thumb instruction subset)
   ///
   FirstThumbRelocation,

 ///   Opcode      - Values of the op-code bits in the instruction, with
 ///                 unaffected bits nulled
 ///   OpcodeMask  - Mask with all bits set that encode the op-code
 ///   ImmMask     - Mask with all bits set that encode the immediate value
 ///   RegMask     - Mask with all bits set that encode the register
 ///
 template <EdgeKind_aarch32 Kind> struct FixupInfo {};
 
+template <> struct FixupInfo<Arm_Call> {
+  static constexpr uint32_t Opcode = 0x0a000000;
+  static constexpr uint32_t OpcodeMask = 0x0e000000;
+  static constexpr uint32_t ImmMask = 0x00ffffff;
+  static constexpr uint32_t Unconditional = 0xe0000000;
+  static constexpr uint32_t CondMask = 0xe0000000; // excluding BLX bit
+  static constexpr uint32_t BitH = 0x01000000;
+  static constexpr uint32_t BitBlx = 0x10000000;
+};
+
 template <> struct FixupInfo<Thumb_Jump24> {
   static constexpr HalfWords Opcode{0xf000, 0x8000};
   static constexpr HalfWords OpcodeMask{0xf800, 0x8000};
   static constexpr HalfWords ImmMask{0x07ff, 0x2fff};
 };
 
 template <> struct FixupInfo<Thumb_Call> {
   static constexpr HalfWords Opcode{0xf000, 0xc000};

llvm/lib/ExecutionEngine/JITLink/aarch32.cpp

 #include "llvm/ExecutionEngine/JITLink/aarch32.h"
 
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/BinaryFormat/ELF.h"
 #include "llvm/ExecutionEngine/JITLink/JITLink.h"
 #include "llvm/Object/ELFObjectFile.h"
 #include "llvm/Support/Endian.h"
 #include "llvm/Support/MathExtras.h"
 
 #define DEBUG_TYPE "jitlink"
 
 namespace llvm {
 namespace jitlink {
 namespace aarch32 {
 
 /// Check whether the given target flags are set for this Symbol.
 bool hasTargetFlags(Symbol &Sym, TargetFlagsType Flags) {
int64_t decodeImmBT4BlT1BlxT2_J1J2(uint32_t Hi, uint32_t Lo) {
   uint32_t S = Hi & 0x0400;
   uint32_t I1 = ~((Lo ^ (Hi << 3)) << 10) & 0x00800000;
   uint32_t I2 = ~((Lo ^ (Hi << 1)) << 11) & 0x00400000;
   uint32_t Imm10 = Hi & 0x03ff;
   uint32_t Imm11 = Lo & 0x07ff;
   return SignExtend64<25>(S << 14 | I1 | I2 | Imm10 << 12 | Imm11 << 1);
 }
 
+/// Encode 26-bit immediate value for branch instructions
+/// (formats B A1, BL A1 and BLX A2).
+///
+///   Imm24:00 ->  00000000:Imm24
+///
+uint32_t encodeImmBA1BlA1BlxA2(int64_t Value) {
+  return (Value >> 2) & 0x00ffffff;
+}
+
+/// Decode 26-bit immediate value for branch instructions
+/// (formats B A1, BL A1 and BLX A2).
+///
+///   00000000:Imm24 ->  Imm24:00
+///
+int64_t decodeImmBA1BlA1BlxA2(int64_t Value) {
+  return SignExtend64<26>((Value & 0x00ffffff) << 2);
+}
+
 /// Encode 16-bit immediate value for move instruction formats MOVT T1 and
 /// MOVW T3.
 ///
 ///   Imm4:Imm1:Imm3:Imm8 -> [ 00000:i:000000:Imm4, 0:Imm3:0000:Imm8 ]
 ///
 HalfWords encodeImmMovtT1MovwT3(uint16_t Value) {
   uint32_t Imm4 = (Value >> 12) & 0x0f;
   uint32_t Imm1 = (Value >> 11) & 0x01;
struct ThumbRelocation {
   /// Create a read-only Thumb32 fixup from a writeable one.
   ThumbRelocation(WritableThumbRelocation &Writable)
       : Hi{Writable.Hi}, Lo(Writable.Lo) {}
 
   const support::ulittle16_t &Hi; // First halfword
   const support::ulittle16_t &Lo; // Second halfword
 };
 
+struct WritableArmRelocation {
+  WritableArmRelocation(char *FixupPtr)
+      : Wd{*reinterpret_cast<support::ulittle32_t *>(FixupPtr)} {}
+
+  support::ulittle32_t &Wd;
+};
+
+struct ArmRelocation {
+
+  ArmRelocation(const char *FixupPtr)
+      : Wd{*reinterpret_cast<const support::ulittle32_t *>(FixupPtr)} {}
+
+  ArmRelocation(WritableArmRelocation &Writable) : Wd{Writable.Wd} {}
+
+  const support::ulittle32_t &Wd;
+};
+
 Error makeUnexpectedOpcodeError(const LinkGraph &G, const ThumbRelocation &R,
                                 Edge::Kind Kind) {
   return make_error<JITLinkError>(
       formatv("Invalid opcode [ 0x{0:x4}, 0x{1:x4} ] for relocation: {2}",
               static_cast<uint16_t>(R.Hi), static_cast<uint16_t>(R.Lo),
               G.getEdgeKindName(Kind)));
 }
 
+Error makeUnexpectedOpcodeError(const LinkGraph &G, const ArmRelocation &R,
+                                Edge::Kind Kind) {
+  return make_error<JITLinkError>(
+      formatv("Invalid opcode [ 0x{0:x8} ] for relocation: {1}",
+              static_cast<uint32_t>(R.Wd), G.getEdgeKindName(Kind)));
+}
+
 template <EdgeKind_aarch32 Kind> bool checkOpcode(const ThumbRelocation &R) {
   uint16_t Hi = R.Hi & FixupInfo<Kind>::OpcodeMask.Hi;
   uint16_t Lo = R.Lo & FixupInfo<Kind>::OpcodeMask.Lo;
   return Hi == FixupInfo<Kind>::Opcode.Hi && Lo == FixupInfo<Kind>::Opcode.Lo;
 }
 
+template <EdgeKind_aarch32 Kind> bool checkOpcode(const ArmRelocation &R) {
+  uint32_t Wd = R.Wd & FixupInfo<Kind>::OpcodeMask;
+  return Wd == FixupInfo<Kind>::Opcode;
+}
+
 template <EdgeKind_aarch32 Kind>
 bool checkRegister(const ThumbRelocation &R, HalfWords Reg) {
   uint16_t Hi = R.Hi & FixupInfo<Kind>::RegMask.Hi;
   uint16_t Lo = R.Lo & FixupInfo<Kind>::RegMask.Lo;
   return Hi == Reg.Hi && Lo == Reg.Lo;
 }
 
 template <EdgeKind_aarch32 Kind>
+bool checkRegister(const ArmRelocation &R, uint32_t Reg) {
+  uint32_t Wd = R.Wd & FixupInfo<Kind>::RegMask;
+  return Wd == Reg;
+}
+
+template <EdgeKind_aarch32 Kind>
 void writeRegister(WritableThumbRelocation &R, HalfWords Reg) {
   static constexpr HalfWords Mask = FixupInfo<Kind>::RegMask;
   assert((Mask.Hi & Reg.Hi) == Reg.Hi && (Mask.Lo & Reg.Lo) == Reg.Lo &&
          "Value bits exceed bit range of given mask");
   R.Hi = (R.Hi & ~Mask.Hi) | Reg.Hi;
   R.Lo = (R.Lo & ~Mask.Lo) | Reg.Lo;
 }
 
 template <EdgeKind_aarch32 Kind>
+void writeRegister(WritableArmRelocation &R, uint32_t Reg) {
+  static constexpr uint32_t Mask = FixupInfo<Kind>::RegMask;
+  assert((Mask & Reg) == Reg && "Value bits exceed bit range of given mask");
+  R.Wd = (R.Wd & ~Mask) | Reg;
+}
+
+template <EdgeKind_aarch32 Kind>
 void writeImmediate(WritableThumbRelocation &R, HalfWords Imm) {
   static constexpr HalfWords Mask = FixupInfo<Kind>::ImmMask;
   assert((Mask.Hi & Imm.Hi) == Imm.Hi && (Mask.Lo & Imm.Lo) == Imm.Lo &&
          "Value bits exceed bit range of given mask");
   R.Hi = (R.Hi & ~Mask.Hi) | Imm.Hi;
   R.Lo = (R.Lo & ~Mask.Lo) | Imm.Lo;
 }
 
+template <EdgeKind_aarch32 Kind>
+void writeImmediate(WritableArmRelocation &R, uint32_t Imm) {
+  static constexpr uint32_t Mask = FixupInfo<Kind>::ImmMask;
+  assert((Mask & Imm) == Imm && "Value bits exceed bit range of given mask");
+  R.Wd = (R.Wd & ~Mask) | Imm;
+}
+
 Expected<int64_t> readAddendData(LinkGraph &G, Block &B, const Edge &E) {
   support::endianness Endian = G.getEndianness();
   assert(Endian != support::native && "Declare as little or big explicitly");
 
   Edge::Kind Kind = E.getKind();
   const char *BlockWorkingMem = B.getContent().data();
   const char *FixupPtr = BlockWorkingMem + E.getOffset();
 
   switch (Kind) {
   case Data_Delta32:
   case Data_Pointer32:
     return SignExtend64<32>(support::endian::read32(FixupPtr, Endian));
   default:
     return make_error<JITLinkError>(
         "In graph " + G.getName() + ", section " + B.getSection().getName() +
         " can not read implicit addend for aarch32 edge kind " +
         G.getEdgeKindName(E.getKind()));
   }
 }
 
 Expected<int64_t> readAddendArm(LinkGraph &G, Block &B, const Edge &E) {
+  ArmRelocation R(B.getContent().data() + E.getOffset());
   Edge::Kind Kind = E.getKind();
 
   switch (Kind) {
   case Arm_Call:
-    return make_error<JITLinkError>(
-        "Addend extraction for relocation type not yet implemented: " +
-        StringRef(G.getEdgeKindName(Kind)));
+    if (!checkOpcode<Arm_Call>(R))
+      return makeUnexpectedOpcodeError(G, R, Kind);
+    return decodeImmBA1BlA1BlxA2(R.Wd);
+
   default:
     return make_error<JITLinkError>(
         "In graph " + G.getName() + ", section " + B.getSection().getName() +
         " can not read implicit addend for aarch32 edge kind " +
         G.getEdgeKindName(E.getKind()));
   }
 }
 
else
       endian::write32<big>(FixupPtr, Imm);
   };
 
   Edge::Kind Kind = E.getKind();
   uint64_t FixupAddress = (B.getAddress() + E.getOffset()).getValue();
   int64_t Addend = E.getAddend();
   Symbol &TargetSymbol = E.getTarget();
   uint64_t TargetAddress = TargetSymbol.getAddress().getValue();
-  assert(!hasTargetFlags(TargetSymbol, ThumbSymbol));
 
   // Regular data relocations have size 4, alignment 1 and write the full 32-bit
   // result to the place; no need for overflow checking. There are three
   // exceptions: R_ARM_ABS8, R_ARM_ABS16, R_ARM_PREL31
   switch (Kind) {
   case Data_Delta32: {
     int64_t Value = TargetAddress - FixupAddress + Addend;
     if (!isInt<32>(Value))
default:
     return make_error<JITLinkError>(
         "In graph " + G.getName() + ", section " + B.getSection().getName() +
         " encountered unfixable aarch32 edge kind " +
         G.getEdgeKindName(E.getKind()));
   }
 }
 
 Error applyFixupArm(LinkGraph &G, Block &B, const Edge &E) {
+  WritableArmRelocation R(B.getAlreadyMutableContent().data() + E.getOffset());
   Edge::Kind Kind = E.getKind();
+  uint64_t FixupAddress = (B.getAddress() + E.getOffset()).getValue();
+  int64_t Addend = E.getAddend();
+  Symbol &TargetSymbol = E.getTarget();
+  uint64_t TargetAddress = TargetSymbol.getAddress().getValue();
+  if (hasTargetFlags(TargetSymbol, ThumbSymbol))
+    TargetAddress |= 0x01;
 
   switch (Kind) {
-  case Arm_Call:
-    return make_error<JITLinkError>(
-        "Fix-up for relocation type not yet implemented: " +
+  case Arm_Call: {
+    if (!checkOpcode<Arm_Call>(R))
+      return makeUnexpectedOpcodeError(G, R, Kind);
+
+    if ((R.Wd & FixupInfo<Arm_Call>::CondMask) !=
+        FixupInfo<Arm_Call>::Unconditional)
+      return make_error<JITLinkError>("Relocation expects an unconditional "
+                                      "BL/BLX branch instruction: " +
                                       StringRef(G.getEdgeKindName(Kind)));
+
+    int64_t Value = TargetAddress - FixupAddress + Addend;
+
+    // The call instruction itself is Arm. The call destination can either be
+    // Thumb or Arm. We use BL to stay in Arm and BLX to change to Thumb.
+    bool TargetIsThumb = hasTargetFlags(TargetSymbol, ThumbSymbol);
+    bool InstrIsBlx = (~R.Wd & FixupInfo<Arm_Call>::BitBlx) == 0;
+    if (TargetIsThumb != InstrIsBlx) {
+      if (LLVM_LIKELY(TargetIsThumb)) {
+        // Change opcode BL -> BLX and fix range value
+        R.Wd = R.Wd | FixupInfo<Arm_Call>::BitBlx;
+        R.Wd = R.Wd & ~FixupInfo<Arm_Call>::BitH;
+        // Set Thumb bit
+        Value |= 0x01;
+      } else {
+        // Change opcode BLX -> BL
+        R.Wd = R.Wd & ~FixupInfo<Arm_Call>::BitBlx;
+      }
+    }
+
+    if (!isInt<26>(Value))
+      return makeTargetOutOfRangeError(G, B, E);
+    writeImmediate<Arm_Call>(R, encodeImmBA1BlA1BlxA2(Value));
+
+    return Error::success();
+  }
+
   default:
     return make_error<JITLinkError>(
         "In graph " + G.getName() + ", section " + B.getSection().getName() +
         " encountered unfixable aarch32 edge kind " +
         G.getEdgeKindName(E.getKind()));
   }
 }
 

llvm/test/ExecutionEngine/JITLink/AArch32/ELF_static_arm_reloc.s

+# RUN: llvm-mc -triple=armv7-linux-gnueabi -arm-add-build-attributes -filetype=obj -o %t.o %s
+# RUN: llvm-objdump -r %t.o | FileCheck --check-prefix=CHECK-TYPE %s
+# RUN: llvm-objdump --disassemble %t.o | FileCheck --check-prefix=CHECK-INSTR %s
+# RUN: llvm-jitlink -noexec -slab-address 0x76ff0000 -slab-allocate 10Kb \
+# RUN:              -slab-page-size 4096 -show-entry-es -check %s %t.o
+
+
+  .text
+  .syntax unified
+
+# CHECK-TYPE: {{[0-9a-f]+}} R_ARM_CALL call_target
+# CHECK-INSTR:  00000000 <call_site>:
+# CHECK-INSTR:         0: ebfffffe     bl      0x0 <call_site>
+# CHECK-INSTR:  00000004 <call_target>:
+# CHECK-INSTR:         4: e12fff1e     bx      lr
+# ARM branch offset is 8, because it accounts for an additional prefetch
+# instruction that increments PC even though it is implicit
+# jitlink-check: decode_operand(call_site, 0) = call_target - (call_site + 8)
+  .globl  call_site
+  .type call_site,%function
+  .p2align  2
+call_site:
+  bl  call_target
+  .size call_site,  .-call_site
+
+  .globl  call_target
+  .type call_target,%function
+  .p2align  2
+call_target:
+  bx  lr
+  .size call_target,  .-call_target
+
+# Empty main function for jitlink to be happy
+  .globl  main
+  .type main,%function
+  .p2align  2
+main:
+  bx  lr
+  .size main, .-main

llvm/unittests/ExecutionEngine/JITLink/AArch32Tests.cpp

void patch(HalfWords Value, HalfWords Mask) {
     Hi = (Hi & ~Mask.Hi) | Value.Hi;
     Lo = (Lo & ~Mask.Lo) | Value.Lo;
   }
 
   uint16_t Hi; // First halfword
   uint16_t Lo; // Second halfword
 };
 
+struct MutableWord {
+  MutableWord(uint32_t Preset) : Wd(Preset) {}
+
+  void patch(uint32_t Value, uint32_t Mask) { Wd = (Wd & ~Mask) | Value; }
+
+  uint32_t Wd;
+};
 namespace llvm {
 namespace jitlink {
 
 Expected<aarch32::EdgeKind_aarch32> getJITLinkEdgeKind(uint32_t ELFType);
 Expected<uint32_t> getELFRelocationType(Edge::Kind Kind);
 
 } // namespace jitlink
 } // namespace llvm

 }
 
 namespace llvm {
 namespace jitlink {
 namespace aarch32 {
 
 HalfWords encodeImmBT4BlT1BlxT2(int64_t Value);
 HalfWords encodeImmBT4BlT1BlxT2_J1J2(int64_t Value);
+uint32_t encodeImmBA1BlA1BlxA2(int64_t Value);
 HalfWords encodeImmMovtT1MovwT3(uint16_t Value);
 HalfWords encodeRegMovtT1MovwT3(int64_t Value);
 
 int64_t decodeImmBT4BlT1BlxT2(uint32_t Hi, uint32_t Lo);
 int64_t decodeImmBT4BlT1BlxT2_J1J2(uint32_t Hi, uint32_t Lo);
+int64_t decodeImmBA1BlA1BlxA2(int64_t Value);
 uint16_t decodeImmMovtT1MovwT3(uint32_t Hi, uint32_t Lo);
 int64_t decodeRegMovtT1MovwT3(uint32_t Hi, uint32_t Lo);
 
 } // namespace aarch32
 } // namespace jitlink
 } // namespace llvm
 
 // Big-endian for v7 and v8 (and v6 unless in legacy backwards compatible mode
for (MutableHalfWords Mem : MemPresets) {
     EXPECT_NE(EncodeDecode(-2097153, Mem), -2097153); // First underflow
 
     EXPECT_TRUE(UnaffectedBits.Hi == (Mem.Hi & ~ImmMask.Hi) &&
                 UnaffectedBits.Lo == (Mem.Lo & ~ImmMask.Lo))
         << "Diff outside immediate field";
   }
 }
 
+/// 26-bit branch with link
+TEST(AArch32_Relocations, Arm_Call_Bare) {
+  static_assert(isInt<26>(33554430), "Max value");
+  static_assert(isInt<26>(-33554432), "Min value");
+  static_assert(!isInt<26>(33554432), "First overflow");
+  static_assert(!isInt<26>(-33554434), "First underflow");
+
+  constexpr uint32_t ImmMask = FixupInfo<Arm_Call>::ImmMask;
+
+  static std::array<uint32_t, 3> MemPresets{
+      0xfeeffff7, // common
+      0x00000000, // zeros
+      0xffffffff, // ones
+  };
+
+  auto EncodeDecode = [](int64_t In, MutableWord &Mem) {
+    Mem.patch(encodeImmBA1BlA1BlxA2(In), ImmMask);
+    return decodeImmBA1BlA1BlxA2(Mem.Wd);
+  };
+
+  for (MutableWord Mem : MemPresets) {
+    MutableWord UnaffectedBits(Mem.Wd & ~ImmMask);
+
+    EXPECT_EQ(EncodeDecode(0, Mem), 0);                 // Zero value
+    EXPECT_EQ(EncodeDecode(0x40, Mem), 0x40);           // Common value
+    EXPECT_EQ(EncodeDecode(33554428, Mem), 33554428);   // Maximum value
+    EXPECT_EQ(EncodeDecode(-33554432, Mem), -33554432); // Minimum value
+    EXPECT_NE(EncodeDecode(33554434, Mem), 33554434);   // First overflow
+    EXPECT_NE(EncodeDecode(-33554434, Mem), -33554434); // First underflow
+
+    EXPECT_TRUE(UnaffectedBits.Wd == (Mem.Wd & ~ImmMask))
+        << "Diff outside immediate field";
+  }
+}
+
 /// Write immediate value to the top halfword of the destination register
 TEST(AArch32_Relocations, Thumb_MovtAbs) {
   static_assert(isUInt<16>(65535), "Max value");
   static_assert(!isUInt<16>(65536), "First overflow");
 
   constexpr HalfWords ImmMask = FixupInfo<Thumb_MovtAbs>::ImmMask;
   constexpr HalfWords RegMask = FixupInfo<Thumb_MovtAbs>::RegMask;