[RISCV] Fix rlist grammar for cm.push, cm.popret, cm.popretz and cm.pop in RISCV zcmp Extension

[imkiva]

Summary

The register list in the arg string is declared as {$rlist}. This patch removes the wrapping curly brackets because of the following:

• Curly brackets are the syntax for variant selection, e.g. given X = {v0 | v1}, the result after CodeGenInstruction::FlattenAsmStringVariants should be X[AsmVariantNo].
• ARM also supports the register list, and they do not use the bracket wrapper.
• Parse of curly brackets are handled by RISCVAsmParser::parseReglist, the brackets in the td file do not correspond to asm syntax. Thus no testcase is affected.

So the curly brackets here are redundant and will become dangerous if RISCV needs more asm parser variants (took me several hours to figure out some wired assertion failures in a downstream fork)

[imkiva]

rebased main

[Jim]

No testcase changed? At least llvm/test/MC/RISCV/rv32zcmp-valid.s.

[jrtc27]

In D157472#4572004, @Jim wrote:

No testcase changed? At least llvm/test/MC/RISCV/rv32zcmp-valid.s.

RISCVAsmParser etc handle the curly braces already; these curly braces did not correspond to the assembly syntax's.

[imkiva]

In D157472#4572004, @Jim wrote:

No testcase changed? At least llvm/test/MC/RISCV/rv32zcmp-valid.s.

Thanks for pointing this out. I edited the description to clarify according to @jrtc27.

[imkiva]

Hi, is this patch being reviewed?

[craig.topper]

LGTM

[imkiva]

Sorry to bother again... I just received an email that says 'Flang :: Driver/underscoring.f90' is failing on a ppc64le-flang-rhel-clang buildbot, and I am on the blame list.
I am confused and want to know if this failure is really linked to this patch. Is there any action that I should take?

[wangpc]

In D157472#4585722, @imkiva wrote:

Sorry to bother again... I just received an email that says 'Flang :: Driver/underscoring.f90' is failing on a ppc64le-flang-rhel-clang buildbot, and I am on the blame list.
I am confused and want to know if this failure is really linked to this patch. Is there any action that I should take?

You can just ignore it if it's definitely not related to your patch. :-)

llvm/lib/Target/RISCV/RISCVInstrInfoZc.td

 class RVZcArith_r<bits<5> funct5, string OpcodeStr> :
   RVInst16CU<0b100111, funct5, 0b01, (outs GPRC:$rd_wb), (ins GPRC:$rd),
              OpcodeStr, "$rd"> {
   let Constraints = "$rd = $rd_wb";
 }
 
 class RVInstZcCPPP<bits<5> funct5, string opcodestr>
     : RVInst16<(outs), (ins rlist:$rlist, spimm:$spimm),
-               opcodestr, "{$rlist}, $spimm", [], InstFormatOther> {
+               opcodestr, "$rlist, $spimm", [], InstFormatOther> {
   bits<4> rlist;
   bits<16> spimm;
 
   let Inst{1-0} = 0b10;
   let Inst{3-2} = spimm{5-4};
   let Inst{7-4} = rlist;
   let Inst{12-8} = funct5;
   let Inst{15-13} = 0b101;