[PEI] Switch to backwards frame index elimination by default

[foad]

Summary

Also rename the flag from supportsBackwardScavenger to
eliminateFrameIndicesBackwards to reflect what it actually does.

X86 is the only target still using forwards frame index elimination.
This will not block removing support for forwards register scavenging,
because X86 does not use the register scavenger.

llvm/include/llvm/CodeGen/TargetRegisterInfo.h

virtual bool saveScavengerRegister(MachineBasicBlock &MBB,
                                      Register Reg) const {
     return false;
   }
 
   /// Process frame indices in reverse block order. This changes the behavior of
   /// the RegScavenger passed to eliminateFrameIndex. If this is true targets
   /// should scavengeRegisterBackwards in eliminateFrameIndex. New targets
   /// should prefer reverse scavenging behavior.
-  virtual bool supportsBackwardScavenger() const { return false; }
+  /// TODO: Remove this when all targets return true.
+  virtual bool eliminateFrameIndicesBackwards() const { return true; }
 
   /// This method must be overriden to eliminate abstract frame indices from
   /// instructions which may use them. The instruction referenced by the
   /// iterator contains an MO_FrameIndex operand which must be eliminated by
   /// this method. This method may modify or replace the specified instruction,
   /// as long as it keeps the iterator pointing at the finished product.
   /// SPAdj is the SP adjustment due to call frame setup instruction.
   /// FIOperandNum is the FI operand number.

llvm/lib/CodeGen/PrologEpilogInserter.cpp

bool PEI::runOnMachineFunction(MachineFunction &MF) {
   // Replace all MO_FrameIndex operands with physical register references
   // and actual offsets.
   if (TFI->needsFrameIndexResolution(MF)) {
     // Allow the target to determine this after knowing the frame size.
     FrameIndexEliminationScavenging =
         (RS && !FrameIndexVirtualScavenging) ||
         TRI->requiresFrameIndexReplacementScavenging(MF);
 
-    if (TRI->supportsBackwardScavenger())
+    if (TRI->eliminateFrameIndicesBackwards())
       replaceFrameIndicesBackward(MF);
     else
       replaceFrameIndices(MF);
   }
 
   // If register scavenging is needed, as we've enabled doing it as a
   // post-pass, scavenge the virtual registers that frame index elimination
   // inserted.

llvm/lib/Target/AMDGPU/SIRegisterInfo.h

bool restoreSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS,
                    SlotIndexes *Indexes = nullptr, LiveIntervals *LIS = nullptr,
                    bool OnlyToVGPR = false,
                    bool SpillToPhysVGPRLane = false) const;
 
   bool spillEmergencySGPR(MachineBasicBlock::iterator MI,
                           MachineBasicBlock &RestoreMBB, Register SGPR,
                           RegScavenger *RS) const;
 
-  bool supportsBackwardScavenger() const override {
-    return true;
-  }
-
   bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
                            unsigned FIOperandNum,
                            RegScavenger *RS) const override;
 
   bool eliminateSGPRToVGPRSpillFrameIndex(
       MachineBasicBlock::iterator MI, int FI, RegScavenger *RS,
       SlotIndexes *Indexes = nullptr, LiveIntervals *LIS = nullptr,
       bool SpillToPhysVGPRLane = false) const;

llvm/lib/Target/ARC/ARCRegisterInfo.h

public:
   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
 
   BitVector getReservedRegs(const MachineFunction &MF) const override;
 
   bool requiresRegisterScavenging(const MachineFunction &MF) const override;
 
   bool useFPForScavengingIndex(const MachineFunction &MF) const override;
 
-  bool supportsBackwardScavenger() const override { return true; }
-
   bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
                            unsigned FIOperandNum,
                            RegScavenger *RS = nullptr) const override;
 
   const uint32_t *getCallPreservedMask(const MachineFunction &MF,
                                        CallingConv::ID CC) const override;
 
   // Debug information queries.

llvm/lib/Target/ARM/ARMBaseRegisterInfo.h

emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
                     Register PredReg = Register(),
                     unsigned MIFlags = MachineInstr::NoFlags) const;
 
   /// Code Generation virtual methods...
   bool requiresRegisterScavenging(const MachineFunction &MF) const override;
 
   bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
 
-  bool supportsBackwardScavenger() const override { return true; }
-
   bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
 
   bool eliminateFrameIndex(MachineBasicBlock::iterator II,
                            int SPAdj, unsigned FIOperandNum,
                            RegScavenger *RS = nullptr) const override;
 
   /// SrcRC and DstRC will be morphed into NewRC if this returns true
   bool shouldCoalesce(MachineInstr *MI,

llvm/lib/Target/Lanai/LanaiRegisterInfo.h

struct LanaiRegisterInfo : public LanaiGenRegisterInfo {
   // Code Generation virtual methods.
   const uint16_t *
   getCalleeSavedRegs(const MachineFunction *MF = nullptr) const override;
 
   BitVector getReservedRegs(const MachineFunction &MF) const override;
 
   bool requiresRegisterScavenging(const MachineFunction &MF) const override;
 
-  bool supportsBackwardScavenger() const override { return true; }
-
   bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
                            unsigned FIOperandNum,
                            RegScavenger *RS = nullptr) const override;
 
   // Debug information queries.
   unsigned getRARegister() const;
   Register getFrameRegister(const MachineFunction &MF) const override;
   Register getBaseRegister() const;
   bool hasBasePointer(const MachineFunction &MF) const;
 
   int getDwarfRegNum(unsigned RegNum, bool IsEH) const;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_LANAI_LANAIREGISTERINFO_H

llvm/lib/Target/Mips/MipsRegisterInfo.h

public:
   bool canRealignStack(const MachineFunction &MF) const override;
 
   /// Debug information queries.
   Register getFrameRegister(const MachineFunction &MF) const override;
 
   /// Return GPR register class.
   virtual const TargetRegisterClass *intRegClass(unsigned Size) const = 0;
 
-  bool supportsBackwardScavenger() const override { return true; }
-
 private:
   virtual void eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo,
                            int FrameIndex, uint64_t StackSize,
                            int64_t SPOffset) const = 0;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_MIPS_MIPSREGISTERINFO_H

llvm/lib/Target/PowerPC/PPCRegisterInfo.h

public:
 
   /// We require the register scavenger.
   bool requiresRegisterScavenging(const MachineFunction &MF) const override {
     return true;
   }
 
   bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
 
-  bool supportsBackwardScavenger() const override { return true; }
-
   bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
 
   void lowerDynamicAlloc(MachineBasicBlock::iterator II) const;
   void lowerDynamicAreaOffset(MachineBasicBlock::iterator II) const;
   void prepareDynamicAlloca(MachineBasicBlock::iterator II,
                             Register &NegSizeReg, bool &KillNegSizeReg,
                             Register &FramePointer) const;
   void lowerPrepareProbedAlloca(MachineBasicBlock::iterator II) const;

llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.h

public:
 
   // Code Generation virtual methods.
   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
   BitVector getReservedRegs(const MachineFunction &MF) const override;
   bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
                            unsigned FIOperandNum,
                            RegScavenger *RS = nullptr) const override;
 
-  bool supportsBackwardScavenger() const override { return true; }
-
   // Debug information queries.
   Register getFrameRegister(const MachineFunction &MF) const override;
 
   const TargetRegisterClass *
   getPointerRegClass(const MachineFunction &MF,
                      unsigned Kind = 0) const override;
   // This does not apply to wasm.
   const uint32_t *getNoPreservedMask() const override { return nullptr; }
 };
 
 } // end namespace llvm
 
 #endif

llvm/lib/Target/X86/X86RegisterInfo.h

public:
   void eliminateFrameIndex(MachineBasicBlock::iterator II,
                            unsigned FIOperandNum, Register BaseReg,
                            int FIOffset) const;
 
   bool eliminateFrameIndex(MachineBasicBlock::iterator MI,
                            int SPAdj, unsigned FIOperandNum,
                            RegScavenger *RS = nullptr) const override;
 
+  /// Process frame indices in forwards block order because
+  /// X86InstrInfo::getSPAdjust relies on it when searching for the
+  /// ADJCALLSTACKUP pseudo following a call.
+  /// TODO: Fix this and return true like all other targets.
+  bool eliminateFrameIndicesBackwards() const override { return false; }
+
   /// findDeadCallerSavedReg - Return a caller-saved register that isn't live
   /// when it reaches the "return" instruction. We can then pop a stack object
   /// to this register without worry about clobbering it.
   unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
                                   MachineBasicBlock::iterator &MBBI) const;
 
   // Debug information queries.
   Register getFrameRegister(const MachineFunction &MF) const override;

llvm/lib/Target/XCore/XCoreRegisterInfo.h

public:
   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
 
   BitVector getReservedRegs(const MachineFunction &MF) const override;
 
   bool requiresRegisterScavenging(const MachineFunction &MF) const override;
 
   bool useFPForScavengingIndex(const MachineFunction &MF) const override;
 
-  bool supportsBackwardScavenger() const override { return true; }
-
   bool eliminateFrameIndex(MachineBasicBlock::iterator II,
                            int SPAdj, unsigned FIOperandNum,
                            RegScavenger *RS = nullptr) const override;
 
   // Debug information queries.
   Register getFrameRegister(const MachineFunction &MF) const override;
 
   //! Return whether to emit frame moves
   static bool needsFrameMoves(const MachineFunction &MF);
 };
 
 } // end namespace llvm
 
 #endif