[GlobalISel] Handle sequences of trunc(sext/zext/anyext...) in artifact combiner

[dzhidzhoev]

Summary

trunc(sext/zext/anyext... x) -> x pattern is handled in artifact combiner to avoid extra copy instructions in https://reviews.llvm.org/D156831.

[jroelofs]

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

330

ISTM this should do m_GAnyExt so we also get coverage for trunc(zext x) -> x.

334

[arsenm]

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

240

Can we start moving all of this into ArtifactValueFinder instead of incrementally finding every permutation of casts?

[dzhidzhoev]

Addressed @jroelofs and @arsenm comments.
Now we find sequences of trunc/sext/anyext/zext instructions, starting with trunc(...),
and replace the destination of trunc with the source of nested instructions if
the destination and "nested" source types are matching.

[jroelofs]

LGTM

[aemerson]

Some more comments, otherwise LGTM with some nice codegen improvements.

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

330

Can just use Register here since it auto doesn't buy much.

758–764

Can invert this condition to early-exit if StartBit + Size > SrcSize

[dzhidzhoev]

Addressed @aemerson comments.

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

bool tryCombineTrunc(MachineInstr &MI,
                        GISelObserverWrapper &Observer) {
     using namespace llvm::MIPatternMatch;
     assert(MI.getOpcode() == TargetOpcode::G_TRUNC);
 
     Builder.setInstr(MI);
     Register DstReg = MI.getOperand(0).getReg();
     Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg());
 
     // Try to fold trunc(g_constant) when the smaller constant type is legal.
     auto *SrcMI = MRI.getVRegDef(SrcReg);
     if (SrcMI->getOpcode() == TargetOpcode::G_CONSTANT) {
       const LLT DstTy = MRI.getType(DstReg);
       if (isInstLegal({TargetOpcode::G_CONSTANT, {DstTy}})) {
         auto &CstVal = SrcMI->getOperand(1);
         Builder.buildConstant(
             DstReg, CstVal.getCImm()->getValue().trunc(DstTy.getSizeInBits()));
         UpdatedDefs.push_back(DstReg);
if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) {
       LLVM_DEBUG(dbgs() << ".. Combine G_TRUNC(G_TRUNC): " << MI);
 
       Builder.buildTrunc(DstReg, TruncSrc);
       UpdatedDefs.push_back(DstReg);
       markInstAndDefDead(MI, *MRI.getVRegDef(TruncSrc), DeadInsts);
       return true;
     }
 
+    // trunc(sext x) -> x
+    Register SextSrc;
+    if (mi_match(SrcReg, MRI, m_GSExt(m_Reg(SextSrc)))) {
+      LLT DstTy = MRI.getType(DstReg);
+      LLT SextSrcTy = MRI.getType(SextSrc);
+      if (DstTy == SextSrcTy) {
+        LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;);
+
+        replaceRegOrBuildCopy(DstReg, SextSrc, MRI, Builder, UpdatedDefs, Observer);
+        UpdatedDefs.push_back(DstReg);
+        markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts);
+        return true;
+      }
+    }
+
     return false;
   }
 
   /// Try to fold G_[ASZ]EXT (G_IMPLICIT_DEF).
   bool tryFoldImplicitDef(MachineInstr &MI,
                           SmallVectorImpl<MachineInstr *> &DeadInsts,
                           SmallVectorImpl<Register> &UpdatedDefs) {
     unsigned Opcode = MI.getOpcode();
Register findValueFromDefImpl(Register DefReg, unsigned StartBit,
       case TargetOpcode::G_CONCAT_VECTORS:
         return findValueFromConcat(cast<GConcatVectors>(*Def), StartBit, Size);
       case TargetOpcode::G_UNMERGE_VALUES: {
         unsigned DefStartBit = 0;
         unsigned DefSize = MRI.getType(DefReg).getSizeInBits();
         for (const auto &MO : Def->defs()) {
           if (MO.getReg() == DefReg)
             break;
           DefStartBit += DefSize;
         }
         Register SrcReg = Def->getOperand(Def->getNumOperands() - 1).getReg();
         Register SrcOriginReg =
             findValueFromDefImpl(SrcReg, StartBit + DefStartBit, Size);
         if (SrcOriginReg)
           return SrcOriginReg;
         // Failed to find a further value. If the StartBit and Size perfectly
         // covered the requested DefReg, return that since it's better than
         // nothing.
         if (StartBit == 0 && Size == DefSize)
           return DefReg;
         return CurrentBest;
       }
       case TargetOpcode::G_BUILD_VECTOR:

llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-trunc.mir

bb.0:
     ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
     ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[DEF]](s64)
     ; CHECK-NEXT: $vgpr0 = COPY [[TRUNC]](s32)
     %0:_(s64) = G_IMPLICIT_DEF
     %1:_(s48) = G_TRUNC %0
     %2:_(s32) = G_TRUNC %1
     $vgpr0 = COPY %2
 ...
+
+---
+name: trunc_sext
+
+body: |
+  bb.0:
+    ; Test that trunc(sext) is replaced with sext source.
+    ; CHECK-LABEL: name: trunc_sext
+    ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+    ; CHECK-NEXT: $vgpr0 = COPY [[DEF]](s32)
+    %0:_(s32) = G_IMPLICIT_DEF
+    %1:_(s64) = G_SEXT %0
+    %2:_(s32) = G_TRUNC %1
+    $vgpr0 = COPY %2
+...