Revert "[AArch64] Merge LDRSWpre-LD[U]RSW pair into LDPSWpre"

[alexfh]

Summary

This reverts commit b0093e13fcfdd4eea5bbd7ae57d3d1b82f4135c3 due to a miscompile
under MSan. See https://reviews.llvm.org/D152407#4533478 for more details.

[alexfh]

Premerge checks on debian seem to be OK (TIMEOUT: MLIR :: Examples/standalone/test.toy (80447 of 82620) is unlikely to be related).

[dmgreen]

Thanks for reverting. We should make sure that happens on the branch too.

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

bool AArch64InstrInfo::hasUnscaledLdStOffset(unsigned Opc) {
   case AArch64::LDURDi:
   case AArch64::LDRDpre:
   case AArch64::LDURQi:
   case AArch64::LDRQpre:
   case AArch64::LDURWi:
   case AArch64::LDRWpre:
   case AArch64::LDURXi:
   case AArch64::LDRXpre:
-  case AArch64::LDRSWpre:
   case AArch64::LDURSWi:
   case AArch64::LDURHHi:
   case AArch64::LDURBBi:
   case AArch64::LDURSBWi:
   case AArch64::LDURSHWi:
     return true;
   }
 }
bool AArch64InstrInfo::isPairableLdStInst(const MachineInstr &MI) {
   case AArch64::LDRDpre:
   case AArch64::LDURQi:
   case AArch64::LDRQpre:
   case AArch64::LDURWi:
   case AArch64::LDRWpre:
   case AArch64::LDURXi:
   case AArch64::LDRXpre:
   case AArch64::LDURSWi:
-  case AArch64::LDRSWpre:
     return true;
   }
 }
 
 unsigned AArch64InstrInfo::convertToFlagSettingOpc(unsigned Opc) {
   switch (Opc) {
   default:
     llvm_unreachable("Opcode has no flag setting equivalent!");
bool AArch64InstrInfo::isCandidateToMergeOrPair(const MachineInstr &MI) const {
   bool IsImmPreLdSt = IsPreLdSt && MI.getOperand(3).isImm();
 
   if (!MI.getOperand(2).isImm() && !IsImmPreLdSt)
     return false;
 
   // Can't merge/pair if the instruction modifies the base register.
   // e.g., ldr x0, [x0]
   // This case will never occur with an FI base.
-  // However, if the instruction is an LDR<S,D,Q,W,X,SW>pre or
-  // STR<S,D,Q,W,X>pre, it can be merged.
+  // However, if the instruction is an LDR/STR<S,D,Q,W,X>pre, it can be merged.
   // For example:
   //   ldr q0, [x11, #32]!
   //   ldr q1, [x11, #16]
   //   to
   //   ldp q0, q1, [x11, #32]!
   if (MI.getOperand(1).isReg() && !IsPreLdSt) {
     Register BaseReg = MI.getOperand(1).getReg();
     const TargetRegisterInfo *TRI = &getRegisterInfo();
int AArch64InstrInfo::getMemScale(unsigned Opc) {
   case AArch64::STRHHui:
   case AArch64::STURHHi:
     return 2;
   case AArch64::LDRSui:
   case AArch64::LDURSi:
   case AArch64::LDRSpre:
   case AArch64::LDRSWui:
   case AArch64::LDURSWi:
-  case AArch64::LDRSWpre:
   case AArch64::LDRWpre:
   case AArch64::LDRWui:
   case AArch64::LDURWi:
   case AArch64::STRSui:
   case AArch64::STURSi:
   case AArch64::STRSpre:
   case AArch64::STRWui:
   case AArch64::STURWi:

 }
 
 bool AArch64InstrInfo::isPreLd(const MachineInstr &MI) {
   switch (MI.getOpcode()) {
   default:
     return false;
   case AArch64::LDRWpre:
   case AArch64::LDRXpre:
-  case AArch64::LDRSWpre:
   case AArch64::LDRSpre:
   case AArch64::LDRDpre:
   case AArch64::LDRQpre:
     return true;
   }
 }
 
 bool AArch64InstrInfo::isPreSt(const MachineInstr &MI) {

llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

static unsigned getMatchingNonSExtOpcode(unsigned Opc,
   case AArch64::LDRSui:
   case AArch64::LDURSi:
   case AArch64::LDRSpre:
     return Opc;
   case AArch64::LDRSWui:
     return AArch64::LDRWui;
   case AArch64::LDURSWi:
     return AArch64::LDURWi;
-  case AArch64::LDRSWpre:
-    return AArch64::LDRWpre;
   }
 }
 
 static unsigned getMatchingWideOpcode(unsigned Opc) {
   switch (Opc) {
   default:
     llvm_unreachable("Opcode has no wide equivalent!");
   case AArch64::STRBBui:
static unsigned getMatchingPairOpcode(unsigned Opc) {
   case AArch64::LDRXui:
   case AArch64::LDURXi:
     return AArch64::LDPXi;
   case AArch64::LDRXpre:
     return AArch64::LDPXpre;
   case AArch64::LDRSWui:
   case AArch64::LDURSWi:
     return AArch64::LDPSWi;
-  case AArch64::LDRSWpre:
-    return AArch64::LDPSWpre;
   }
 }
 
 static unsigned isMatchingStore(MachineInstr &LoadInst,
                                 MachineInstr &StoreInst) {
   unsigned LdOpc = LoadInst.getOpcode();
   unsigned StOpc = StoreInst.getOpcode();
   switch (LdOpc) {
static bool isPreLdStPairCandidate(MachineInstr &FirstMI, MachineInstr &MI) {
   case AArch64::LDRDpre:
     return (OpcB == AArch64::LDRDui) || (OpcB == AArch64::LDURDi);
   case AArch64::LDRQpre:
     return (OpcB == AArch64::LDRQui) || (OpcB == AArch64::LDURQi);
   case AArch64::LDRWpre:
     return (OpcB == AArch64::LDRWui) || (OpcB == AArch64::LDURWi);
   case AArch64::LDRXpre:
     return (OpcB == AArch64::LDRXui) || (OpcB == AArch64::LDURXi);
-  case AArch64::LDRSWpre:
-    return (OpcB == AArch64::LDRSWui) || (OpcB == AArch64::LDURSWi);
   }
 }
 
 // Returns the scale and offset range of pre/post indexed variants of MI.
 static void getPrePostIndexedMemOpInfo(const MachineInstr &MI, int &Scale,
                                        int &MinOffset, int &MaxOffset) {
   bool IsPaired = AArch64InstrInfo::isPairedLdSt(MI);
   bool IsTagStore = isTagStore(MI);
if (!PairIsValidLdStrOpc)
     return false;
 
   // FIXME: We don't support merging narrow stores with mixed scaled/unscaled
   // offsets.
   if (isNarrowStore(OpcA) || isNarrowStore(OpcB))
     return false;
 
   // The STR<S,D,Q,W,X>pre - STR<S,D,Q,W,X>ui and
-  // LDR<S,D,Q,W,X,SW>pre-LDR<S,D,Q,W,X,SW>ui
+  // LDR<S,D,Q,W,X>pre-LDR<S,D,Q,W,X>ui
   // are candidate pairs that can be merged.
   if (isPreLdStPairCandidate(FirstMI, MI))
     return true;
 
   // Try to match an unscaled load/store with a scaled load/store.
   return TII->hasUnscaledLdStOffset(OpcA) != TII->hasUnscaledLdStOffset(OpcB) &&
          getMatchingPairOpcode(OpcA) == getMatchingPairOpcode(OpcB);
 

llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir

bb.0:
     renamable $s1 = LDRSui renamable $x1, 1 :: (load (s32))
     STRSui killed renamable $s0, renamable $x1, 0 :: (store (s32))
     STRSui killed renamable $s1, renamable $x1, 1 :: (store (s32))
     RET undef $lr
 ...
 
 
 ---
-name:            21-ldrswpre-ldrswui-merge
+name:            21-ldrswpre-ldrswui-no-merge
 tracksRegLiveness: true
 liveins:
   - { reg: '$x0' }
   - { reg: '$x1' }
   - { reg: '$x2' }
 machineFunctionInfo:
   hasRedZone:      false
 body:             |
   bb.0:
     liveins: $x0, $x1, $x2
-    ; CHECK-LABEL: name: 21-ldrswpre-ldrswui-merge
+    ; CHECK-LABEL: name: 21-ldrswpre-ldrswui-no-merge
     ; CHECK: liveins: $x0, $x1, $x2
-    ; CHECK: early-clobber $x1, renamable $x0, renamable $x2 = LDPSWpre renamable $x1, 10 :: (load (s32))
+    ; CHECK: early-clobber renamable $x1, renamable $x0 = LDRSWpre renamable $x1, 40, implicit $w1 :: (load (s32))
+    ; CHECK: renamable $x2 = LDRSWui renamable $x1, 1 :: (load (s32))
     ; CHECK: STPXi renamable $x0, renamable $x2, renamable $x1, 0 :: (store (s64))
     ; CHECK: RET undef $lr
     early-clobber renamable $x1, renamable $x0 = LDRSWpre killed renamable $x1, 40 :: (load (s32))
     renamable $x2 = LDRSWui renamable $x1, 1 :: (load (s32))
     STRXui killed renamable $x0, renamable $x1, 0 :: (store (s64))
     STRXui killed renamable $x2, renamable $x1, 1 :: (store (s64))
     RET undef $lr
 ...
 
 
 ---
-name:            22-ldrswpre-ldurswi-merge
+name:            22-ldrswpre-ldurswi-no-merge
 tracksRegLiveness: true
 liveins:
   - { reg: '$x0' }
   - { reg: '$x1' }
   - { reg: '$x2' }
 machineFunctionInfo:
   hasRedZone:      false
 body:             |
   bb.0:
     liveins: $x0, $x1, $x2
-    ; CHECK-LABEL: name: 22-ldrswpre-ldurswi-merge
+    ; CHECK-LABEL: name: 22-ldrswpre-ldurswi-no-merge
     ; CHECK: liveins: $x0, $x1, $x2
-    ; CHECK: early-clobber $x1, renamable $x0, renamable $x2 = LDPSWpre renamable $x1, 10 :: (load (s32))
+    ; CHECK: early-clobber renamable $x1, renamable $x0 = LDRSWpre renamable $x1, 40, implicit $w1 :: (load (s32))
+    ; CHECK: renamable $x2 = LDURSWi renamable $x1, 4 :: (load (s32))
     ; CHECK: STPXi renamable $x0, renamable $x2, renamable $x1, 0 :: (store (s64))
     ; CHECK: RET undef $lr
     early-clobber renamable $x1, renamable $x0 = LDRSWpre killed renamable $x1, 40 :: (load (s32))
     renamable $x2 = LDURSWi renamable $x1, 4 :: (load (s32))
     STRXui killed renamable $x0, renamable $x1, 0 :: (store (s64))
     STRXui killed renamable $x2, renamable $x1, 1 :: (store (s64))
     RET undef $lr
 ...