[RISCV] Add isAllocatable=0 to VCSR register class.

[craig.topper]

Summary

This avoids creating an unnecessary register pressure set.

[asb]

LGTM.

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

 def VXRM   : RISCVReg<0, "vxrm">;
 let isConstant = true in
 def VLENB  : RISCVReg<0, "vlenb">,
              DwarfRegNum<[!add(4096, SysRegVLENB.Encoding)]>;
 
 def VCSR : RegisterClass<"RISCV", [XLenVT], 32,
                           (add VTYPE, VL, VLENB)> {
   let RegInfos = XLenRI;
+  let isAllocatable = 0;
 }
 
 
 foreach m = [1, 2, 4] in {
   foreach n = NFList<m>.L in {
     def "VN" # n # "M" # m # "NoV0": RegisterTuples<
                                        SubRegSet<n, m>.L,
                                        VRegList<[], 0, n, m, false>.L>;