[Clang][SVE] Permit specific predicate-as-counter registers in inline assembly

[david-arm]

Summary

This patch adds the predicate-as-counter registers pn0-pn15 to the
list of supported registers used when writing inline assembly.

Tests added to

clang/test/CodeGen/aarch64-sve-inline-asm.c

[MattDevereau]

clang/test/CodeGen/aarch64-sve-inline-asm.c

20

I think it would be better to keep this test similar to test_sve_asm in that it tests both ends of the range of predicate registers and also tests it can be used as an operand to other valid instructions. Right now it feels like the bare minimum.

[sdesmalen]

clang/test/CodeGen/aarch64-sve-inline-asm.c

6

Could you also add a RUN line that compiles this to asm, just to make sure that LLVM accepts the inline asm syntax? There don't need to be any checks for the output.
This then probably also requires a REQUIRES: aarch64-registered-target.

21

x2 seems unused. Did you forget to assign it and to add some CHECK lines for it?

[david-arm]

• Addressed review comments on tests

clang/lib/Basic/Targets/AArch64.cpp

const char *const AArch64TargetInfo::GCCRegNames[] = {
 
     // SVE vector registers
     "z0",  "z1",  "z2",  "z3",  "z4",  "z5",  "z6",  "z7",  "z8",  "z9",  "z10",
     "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21",
     "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31",
 
     // SVE predicate registers
     "p0",  "p1",  "p2",  "p3",  "p4",  "p5",  "p6",  "p7",  "p8",  "p9",  "p10",
-    "p11", "p12", "p13", "p14", "p15"
+    "p11", "p12", "p13", "p14", "p15",
+
+    // SVE predicate-as-counter registers
+    "pn0",  "pn1",  "pn2",  "pn3",  "pn4",  "pn5",  "pn6",  "pn7",  "pn8",
+    "pn9",  "pn10", "pn11", "pn12", "pn13", "pn14", "pn15"
 };
 
 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const {
   return llvm::ArrayRef(GCCRegNames);
 }
 
 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
     {{"w31"}, "wsp"},

clang/test/CodeGen/aarch64-sve-inline-asm.c

-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2p1 \
+// RUN:   -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2p1 \
+// RUN:   -S -o /dev/null
 
 void test_sve_asm(void) {
   asm volatile(
       "ptrue p0.d\n"
       "ptrue p15.d\n"
       "add z0.d, p0/m, z0.d, z0.d\n"
       "add z31.d, p0/m, z31.d, z31.d\n"
       :
       :
       : "z0", "z31", "p0", "p15");
+  // CHECK-LABEL: @test_sve_asm
   // CHECK: "~{z0},~{z31},~{p0},~{p15}"
 }
+
+void test_sve2p1_asm(void) {
+  asm("pfalse pn0.b\n"
+      "ptrue pn8.d\n"
+      "ptrue pn15.b\n"
+      "pext p3.b, pn8[1]\n"
+      ::: "pn0", "pn8", "pn15", "p3");
+  // CHECK-LABEL: @test_sve2p1_asm
+  // CHECK: "~{pn0},~{pn8},~{pn15},~{p3}"
+}