[RISCV] Add subclasses of Sched to simplify code

[wangpc]

Summary

We add some subclasses of Sched to reduce code which cast string
to SchedWrite/SchedRead.

Besides, we add ReadVMask iff pseudo is masked. And this is the
reason why this patch isn't a NFC since we add it for all pseudos
before.

ReadMergeOp will be added in D155654.

[wangpc]

Remove defvars.

[michaelmaitland]

I'm a fan of this change! I support updating the rest of the Scheds like this.

[wangpc]

• Rebase.
• Rewrite all.

[wangpc]

• Move subclasses of Sched to RISCVInstrInfoV.td.
• Double check.

[michaelmaitland]

Thanks for these changes, they clean up this file a bunch!

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

101 ↗

(On Diff #543483)

Can we add docstrings for these functions since they will be used by many different classes?

101 ↗

(On Diff #543483)

These classes are only used in RISCVInstrVPseudos.td. Do they belong in that file?

111 ↗

(On Diff #543483)

I don't know the case convention for TableGen, but it looks like we're mixing camel and pascal case here (and we also use underscores in other places too). Is there a reason for mixing case conventions here?

[wangpc]

• Add doc.
• Rewrite MC Scheds.

[wangpc]

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

101 ↗

(On Diff #543483)

Now they are used. :-)

111 ↗

(On Diff #543483)

Fixed.
Just my convention:

• pascal case for classes, multiclasses, fields.
• camel case for iterators, arguments, defvars, subroutines, the return value of subroutines.

Usually, I don't use underscores or mix the cases. But sometimes I will in order to match existed code (some of them are inherited from target independent TableGen infrastructures).
We can do some cleanups in the future to keep the style consistent once we reach an agreement.

[wangpc]

Add MC Sched classed for load/store.

[michaelmaitland]

LGTM.

[wangpc]

Fix copy/paste error.

[wangpc]

Fix copy/paste error.

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

let VLMul = MInfo.value, SEW=sew in {
     def suffix : VPseudoBinaryNoMaskTU<RetClass, Op1Class, Op2Class,
                                        Constraint>;
     def suffix # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class,
                                                    Constraint>,
                            RISCVMaskedPseudo<MaskIdx=3>;
   }
 }
 
+class SchedBinary<string write, string read0, string read1,
+                  string mx, int sew = 0>: Sched<[]> {
+  defvar Write = !cast<SchedWrite>(!if(sew,
+                                       write # "_" # mx # "_E" # sew,
+                                       write # "_" # mx));
+  defvar Read0 = !cast<SchedRead>(!if(sew,
+                                      read0 # "_" # mx # "_E" # sew,
+                                      read0 # "_" # mx));
+  defvar Read1 = !cast<SchedRead>(!if(sew,
+                                      read1 # "_" # mx # "_E" # sew,
+                                      read1 # "_" # mx));
+  defvar SchedRWList = [Write, Read0, Read1];
+  defvar SchedRWListMasked = [Write, Read0, Read1, ReadVMask];
+  defvar IsMasked = !ne(!find(NAME, "_MASK"), -1);
+  let SchedRW = !if(IsMasked, SchedRWListMasked, SchedRWList);
+}
+
+class SchedBinaryVV<string write, string read0, string read1,
+                    string mx, int sew = 0>:
+                  SchedBinary<write, read0, read1, mx, sew>;
+
+class SchedBinaryVX<string write, string read0, string read1,
+                    string mx, int sew = 0>:
+                  SchedBinary<write, read0, read1, mx, sew>;
+
+class SchedBinaryVI<string write, string read0, 
+                    string mx, int sew = 0>: Sched<[]> {
+  defvar Write = !cast<SchedWrite>(!if(sew,
+                                       write # "_" # mx # "_E" # sew,
+                                       write # "_" # mx));
+  defvar Read0 = !cast<SchedRead>(!if(sew,
+                                      read0 # "_" # mx # "_E" # sew,
+                                      read0 # "_" # mx));
+  defvar SchedRWList = [Write, Read0];
+  defvar SchedRWListMasked = [Write, Read0, ReadVMask];
+  defvar IsMasked = !find(NAME, "_MASK");
+  let SchedRW = !if(IsMasked, SchedRWListMasked, SchedRWList);
+}
+
 multiclass VPseudoBinaryRoundingMode<VReg RetClass,
                                      VReg Op1Class,
                                      DAGOperand Op2Class,
                                      LMULInfo MInfo,
                                      string Constraint = "",
                                      int sew = 0,
                                      int UsesVXRM = 1> {
   let VLMul = MInfo.value, SEW=sew in {
foreach sew = EEWList in {
       defvar dataEMULOctuple = m.octuple;
       // emul = lmul * eew / sew
       defvar idxEMULOctuple = !srl(!mul(dataEMULOctuple, eew), !logtwo(sew));
       if !and(!ge(idxEMULOctuple, 1), !le(idxEMULOctuple, 64)) then {
         defvar emulMX = octuple_to_str<idxEMULOctuple>.ret;
         defvar emul = !cast<LMULInfo>("V_" # emulMX);
         defvar sews = SchedSEWSet<mx>.val;
         foreach e = sews in {
-          defvar WriteVRGatherVV_MX_E = !cast<SchedWrite>("WriteVRGatherVV_" # mx # "_E" # e);
-          defvar ReadVRGatherVV_data_MX_E = !cast<SchedRead>("ReadVRGatherVV_data_" # mx # "_E" # e);
-          defvar ReadVRGatherVV_index_MX_E = !cast<SchedRead>("ReadVRGatherVV_index_" # mx # "_E" # e);
           defm _VV : VPseudoBinaryEmul<m.vrclass, m.vrclass, emul.vrclass, m, emul, Constraint, e>,
-                     Sched<[WriteVRGatherVV_MX_E, ReadVRGatherVV_data_MX_E, ReadVRGatherVV_index_MX_E]>;
+                     SchedBinaryVV<"WriteVRGatherVV", "ReadVRGatherVV_data", "ReadVRGatherVV_index", mx, e>;
         }
       }
     }
   }
 }
 
 multiclass VPseudoBinaryV_VX<LMULInfo m, string Constraint = "", int sew = 0> {
   defm "_VX" : VPseudoBinary<m.vrclass, m.vrclass, GPR, m, Constraint, sew>;
multiclass VPseudoBinaryV_VF_RM<LMULInfo m, FPR_Info f, string Constraint = "", int sew = 0> {
   defm "_V" # f.FX : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass,
                                                f.fprclass, m, Constraint, sew,
                                                UsesVXRM=0>;
 }
 
 multiclass VPseudoVSLD1_VF<string Constraint = ""> {
   foreach f = FPList in {
     foreach m = f.MxList in {
-      defvar mx = m.MX;
-      defvar WriteVFSlide1F_MX = !cast<SchedWrite>("WriteVFSlide1F_" # mx);
-      defvar ReadVFSlideV_MX = !cast<SchedRead>("ReadVFSlideV_" # mx);
-      defvar ReadVFSlideF_MX = !cast<SchedRead>("ReadVFSlideF_" # mx);
-
       defm "_V" # f.FX :
         VPseudoBinary<m.vrclass, m.vrclass, f.fprclass, m, Constraint>,
-        Sched<[WriteVFSlide1F_MX, ReadVFSlideV_MX, ReadVFSlideF_MX, ReadVMask]>;
+        SchedBinaryVV<"WriteVFSlide1F", "ReadVFSlideV", "ReadVFSlideF", m.MX>;
     }
   }
 }
 
 multiclass VPseudoBinaryV_VI<Operand ImmType = simm5, LMULInfo m, string Constraint = ""> {
   defm _VI : VPseudoBinary<m.vrclass, m.vrclass, ImmType, m, Constraint>;
 }
 

 multiclass VPseudoBinaryM_VI<LMULInfo m> {
   defm _VI : VPseudoBinaryM<VR, m.vrclass, simm5, m,
                             !if(!ge(m.octuple, 16), "@earlyclobber $rd", "")>;
 }
 
 multiclass VPseudoVGTR_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
   foreach m = MxList in {
     defvar mx = m.MX;
-    defvar WriteVRGatherVX_MX = !cast<SchedWrite>("WriteVRGatherVX_" # mx);
-    defvar WriteVRGatherVI_MX = !cast<SchedWrite>("WriteVRGatherVI_" # mx);
-    defvar ReadVRGatherVX_data_MX = !cast<SchedRead>("ReadVRGatherVX_data_" # mx);
-    defvar ReadVRGatherVX_index_MX = !cast<SchedRead>("ReadVRGatherVX_index_" # mx);
-    defvar ReadVRGatherVI_data_MX = !cast<SchedRead>("ReadVRGatherVI_data_" # mx);
-
     defm "" : VPseudoBinaryV_VX<m, Constraint>,
-              Sched<[WriteVRGatherVX_MX, ReadVRGatherVX_data_MX,
-                     ReadVRGatherVX_index_MX, ReadVMask]>;
+              SchedBinaryVX<"WriteVRGatherVX", "ReadVRGatherVX_data",
+                            "ReadVRGatherVX_index", mx>;
     defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
-              Sched<[WriteVRGatherVI_MX, ReadVRGatherVI_data_MX, ReadVMask]>;
+              SchedBinaryVI<"WriteVRGatherVI", "ReadVRGatherVI_data", mx>;
 
     defvar sews = SchedSEWSet<mx>.val;
     foreach e = sews in {
-      defvar WriteVRGatherVV_MX_E = !cast<SchedWrite>("WriteVRGatherVV_" # mx # "_E" # e);
-      defvar ReadVRGatherVV_data_MX_E = !cast<SchedRead>("ReadVRGatherVV_data_" # mx # "_E" # e);
-      defvar ReadVRGatherVV_index_MX_E = !cast<SchedRead>("ReadVRGatherVV_index_" # mx # "_E" # e);
       defm "" : VPseudoBinaryV_VV<m, Constraint, e>,
-                Sched<[WriteVRGatherVV_MX_E, ReadVRGatherVV_data_MX_E,
-                       ReadVRGatherVV_index_MX_E, ReadVMask]>;
+                SchedBinaryVV<"WriteVRGatherVV", "ReadVRGatherVV_data",
+                              "ReadVRGatherVV_index", mx, e>;
     }
   }
 }
 
 multiclass VPseudoVSALU_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
   foreach m = MxList in {
     defvar mx = m.MX;
     defvar WriteVSALUV_MX = !cast<SchedWrite>("WriteVSALUV_" # mx);
     defvar WriteVSALUX_MX = !cast<SchedWrite>("WriteVSALUX_" # mx);
     defvar WriteVSALUI_MX = !cast<SchedWrite>("WriteVSALUI_" # mx);
     defvar ReadVSALUV_MX = !cast<SchedRead>("ReadVSALUV_" # mx);
     defvar ReadVSALUX_MX = !cast<SchedRead>("ReadVSALUX_" # mx);
 
     defm "" : VPseudoBinaryV_VV<m, Constraint>,
-              Sched<[WriteVSALUV_MX, ReadVSALUV_MX, ReadVSALUV_MX, ReadVMask]>;
+              SchedBinaryVV<"WriteVSALUV", "ReadVSALUV", "ReadVSALUX", mx>;
     defm "" : VPseudoBinaryV_VX<m, Constraint>,
-              Sched<[WriteVSALUX_MX, ReadVSALUV_MX, ReadVSALUX_MX, ReadVMask]>;
+              SchedBinaryVX<"WriteVSALUX", "ReadVSALUV", "ReadVSALUX", mx>;
     defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
-              Sched<[WriteVSALUI_MX, ReadVSALUV_MX, ReadVMask]>;
+              SchedBinaryVI<"WriteVSALUI", "ReadVSALUV", mx>;
   }
 }
 
 
 multiclass VPseudoVSHT_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
   foreach m = MxList in {
     defvar mx = m.MX;
     defvar WriteVShiftV_MX = !cast<SchedWrite>("WriteVShiftV_" # mx);