[RISCV] Add subclasses of Sched to simplify code

[wangpc]

Summary

We add some subclasses of Sched to reduce code which cast string
to SchedWrite/SchedRead.

Besides, we add ReadVMask iff pseudo is masked. And this is the
reason why this patch isn't a NFC since we add it for all pseudos
before.

ReadMergeOp will be added in D155654.

[wangpc]

Remove defvars.

[michaelmaitland]

I'm a fan of this change! I support updating the rest of the Scheds like this.

[wangpc]

• Rebase.
• Rewrite all.

[wangpc]

• Move subclasses of Sched to RISCVInstrInfoV.td.
• Double check.

[michaelmaitland]

Thanks for these changes, they clean up this file a bunch!

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

101

Can we add docstrings for these functions since they will be used by many different classes?

101

These classes are only used in RISCVInstrVPseudos.td. Do they belong in that file?

111

I don't know the case convention for TableGen, but it looks like we're mixing camel and pascal case here (and we also use underscores in other places too). Is there a reason for mixing case conventions here?

[wangpc]

• Add doc.
• Rewrite MC Scheds.

[wangpc]

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

101

Now they are used. :-)

111

Fixed.
Just my convention:

• pascal case for classes, multiclasses, fields.
• camel case for iterators, arguments, defvars, subroutines, the return value of subroutines.

Usually, I don't use underscores or mix the cases. But sometimes I will in order to match existed code (some of them are inherited from target independent TableGen infrastructures).
We can do some cleanups in the future to keep the style consistent once we reach an agreement.

[wangpc]

Add MC Sched classed for load/store.

[michaelmaitland]

LGTM.

[wangpc]

Fix copy/paste error.

[wangpc]

Fix copy/paste error.

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

 
 def simm5_plus1_nonzero : ImmLeaf<XLenVT,
   [{return Imm != 0 && ((isInt<5>(Imm) && Imm != -16) || Imm == 16);}]>;
 
 //===----------------------------------------------------------------------===//
 // Scheduling definitions.
 //===----------------------------------------------------------------------===//
 
-class VMVRSched<int n> : Sched<[
-  !cast<SchedReadWrite>("WriteVMov" #n #"V"),
-  !cast<SchedReadWrite>("ReadVMov" #n #"V")
-]>;
-
-class VLESched<string lmul = "WorstCase"> : Sched<[
-  !cast<SchedReadWrite>("WriteVLDE_" #lmul),
-  ReadVLDX, ReadVMask
-]>;
-
-class VSESched<string lmul = "WorstCase"> : Sched<[
-  !cast<SchedReadWrite>("WriteVSTE_" #lmul),
-  !cast<SchedReadWrite>("ReadVSTEV_" #lmul),
-  ReadVSTX, ReadVMask
-]>;
-
-class VLSSched<int eew, string emul = "WorstCase"> : Sched<[
-  !cast<SchedReadWrite>("WriteVLDS" #eew #"_" #emul),
-  ReadVLDX, ReadVLDSX, ReadVMask
-]>;
-
-class VSSSched<int eew, string emul = "WorstCase"> : Sched<[
-  !cast<SchedReadWrite>("WriteVSTS" #eew #"_" #emul),
-  !cast<SchedReadWrite>("ReadVSTS" #eew #"V_" #emul),
-  ReadVSTX, ReadVSTSX, ReadVMask
-]>;
-
-class VLXSched<int dataEEW, string isOrdered,
-               string dataEMUL = "WorstCase",
-               string idxEMUL = "WorstCase"> : Sched<[
-  !cast<SchedReadWrite>("WriteVLD" #isOrdered #"X" #dataEEW #"_" #dataEMUL),
-  ReadVLDX,
-  !cast<SchedReadWrite>("ReadVLD" #isOrdered #"XV_" #idxEMUL), ReadVMask
-]>;
-
-class VSXSched<int dataEEW, string isOrdered,
-               string dataEMUL = "WorstCase",
-               string idxEMUL = "WorstCase"> : Sched<[
-  !cast<SchedReadWrite>("WriteVST" #isOrdered #"X" #dataEEW #"_" #dataEMUL),
-  !cast<SchedReadWrite>("ReadVST" #isOrdered #"X" #dataEEW #"_" #dataEMUL),
-  ReadVSTX, !cast<SchedReadWrite>("ReadVST" #isOrdered #"XV_" #idxEMUL), ReadVMask
-]>;
-
-class VLFSched<string lmul = "WorstCase"> : Sched<[
-  !cast<SchedReadWrite>("WriteVLDFF_" #lmul),
-  ReadVLDX, ReadVMask
-]>;
+// Common class of scheduling definitions.
+// `ReadVMask` will be appended if instruction is masked.
+// Operands:
+//   `writes`       SchedWrites that are listed for each explicit def operand
+//                  in order.
+//   `reads`        SchedReads that are listed for each explicit use operand.
+//   `forceMasked`  Forced to be masked (e.g. Add-with-Carry Instructions).
+class SchedCommon<list<SchedWrite> writes, list<SchedRead> reads,
+                  bit forceMasked = 0>: Sched<[]> {
+  defvar isMasked = !ne(!find(NAME, "_MASK"), -1);
+  defvar needReadVMask = !or(forceMasked, isMasked);
+  let SchedRW = !listconcat(writes, reads,
+                            !if(needReadVMask, [ReadVMask], []));
+}
+
+// Common class of scheduling definitions for n-ary instructions.
+// The scheudling resources are relevant to LMUL and may be relevant to SEW.
+class SchedNary<string write, list<string> reads,
+                string mx, int sew = 0, bit forceMasked = 0>:
+  SchedCommon<[!cast<SchedWrite>(
+                 !if(sew, write # "_" # mx # "_E" # sew,
+                          write # "_" # mx))],
+              !foreach(read, reads,
+                !cast<SchedRead>(
+                  !if(sew, read # "_" # mx # "_E" # sew,
+                           read # "_" # mx))),
+              forceMasked>;
+
+// Classes with postfix "MC" are only used in MC layer.
+// For these classes, we assume that they are with the worst case costs and
+// `ReadVMask` is always needed (with some exceptions).
+
+// For instructions with no operand.
+class SchedNullary<string write, string mx, int sew = 0, bit forceMasked = 0>:
+  SchedNary<write, [], mx, sew, forceMasked>;
+class SchedNullaryMC<string write, bit forceMasked = 1>:
+  SchedNullary<write, "WorstCase", forceMasked=forceMasked>;
+
+// For instructions with one operand.
+class SchedUnary<string write, string read0, string mx, int sew = 0,
+                 bit forceMasked = 0>:
+  SchedNary<write, [read0], mx, sew, forceMasked>;
+class SchedUnaryMC<string write, string read0, bit forceMasked = 1>:
+  SchedUnary<write, read0, "WorstCase", forceMasked=forceMasked>;
+
+// For instructions with two operands.
+class SchedBinary<string write, string read0, string read1,
+                  string mx, int sew = 0, bit forceMasked = 0>:
+  SchedNary<write, [read0, read1], mx, sew, forceMasked>;
+class SchedBinaryMC<string write, string read0, string read1,
+                    bit forceMasked = 1>:
+  SchedBinary<write, read0, read1, "WorstCase", forceMasked=forceMasked>;
+
+// For instructions with three operands.
+class SchedTernary<string write, string read0, string read1, string read2,
+                   string mx, int sew = 0, bit forceMasked = 0>:
+  SchedNary<write, [read0, read1, read2], mx, sew, forceMasked>;
+
+// For reduction instructions.
+class SchedReduction<string write, string read, string mx, int sew>:
+  SchedCommon<[!cast<SchedWrite>(write # "_" # mx # "_E" # sew)],
+              !listsplat(!cast<SchedRead>(read), 3)>;
+class SchedReductionMC<string write, string readV, string readV0>:
+  SchedCommon<[!cast<SchedWrite>(write # "_WorstCase")],
+              [!cast<SchedRead>(readV), !cast<SchedRead>(readV0)],
+              forceMasked=1>;
+
+// Whole Vector Register Move
+class VMVRSched<int n> : SchedCommon<
+  [!cast<SchedWrite>("WriteVMov" #n #"V")],
+  [!cast<SchedRead>("ReadVMov" #n #"V")]
+>;
+
+// Vector Unit-Stride Loads and Stores
+class VLESched<string lmul, bit forceMasked = 0> : SchedCommon<
+  [!cast<SchedWrite>("WriteVLDE_" #lmul)],
+  [ReadVLDX], forceMasked
+>;
+class VLESchedMC : VLESched<"WorstCase", forceMasked=1>;
+
+class VSESched<string lmul, bit forceMasked = 0> : SchedCommon<
+  [!cast<SchedWrite>("WriteVSTE_" #lmul)],
+  [!cast<SchedRead>("ReadVSTEV_" #lmul), ReadVSTX], forceMasked
+>;
+class VSESchedMC : VSESched<"WorstCase", forceMasked=1>;
+
+// Vector Strided Loads and Stores
+class VLSSched<int eew, string emul, bit forceMasked = 0> : SchedCommon<
+  [!cast<SchedWrite>("WriteVLDS" #eew #"_" #emul)],
+  [ReadVLDX, ReadVLDSX], forceMasked
+>;
+class VLSSchedMC<int eew> : VLSSched<eew, "WorstCase", forceMasked=1>;
+
+class VSSSched<int eew, string emul, bit forceMasked = 0> : SchedCommon<
+  [!cast<SchedWrite>("WriteVSTS" #eew #"_" #emul)],
+  [!cast<SchedRead>("ReadVSTS" #eew #"V_" #emul), ReadVSTX, ReadVSTSX],
+  forceMasked
+>;
+class VSSSchedMC<int eew> : VSSSched<eew, "WorstCase", forceMasked=1>;
+
+// Vector Indexed Loads and Stores
+class VLXSched<int dataEEW, string isOrdered, string dataEMUL, string idxEMUL,
+               bit forceMasked = 0> : SchedCommon<
+  [!cast<SchedWrite>("WriteVLD" #isOrdered #"X" #dataEEW #"_" #dataEMUL)],
+  [ReadVLDX, !cast<SchedRead>("ReadVLD" #isOrdered #"XV_" #idxEMUL)],
+  forceMasked
+>;
+class VLXSchedMC<int dataEEW, string isOrdered>:
+  VLXSched<dataEEW, isOrdered, "WorstCase", "WorstCase", forceMasked=1>;
+
+class VSXSched<int dataEEW, string isOrdered, string dataEMUL, string idxEMUL,
+               bit forceMasked = 0> : SchedCommon<
+  [!cast<SchedWrite>("WriteVST" #isOrdered #"X" #dataEEW #"_" #dataEMUL)],
+  [!cast<SchedRead>("ReadVST" #isOrdered #"X" #dataEEW #"_" #dataEMUL),
+   ReadVSTX, !cast<SchedRead>("ReadVST" #isOrdered #"XV_" #idxEMUL)],
+  forceMasked
+>;
+class VSXSchedMC<int dataEEW, string isOrdered>:
+  VSXSched<dataEEW, isOrdered, "WorstCase", "WorstCase", forceMasked=1>;
+
+// Unit-stride Fault-Only-First Loads
+class VLFSched<string lmul, bit forceMasked = 0> : SchedCommon<
+  [!cast<SchedWrite>("WriteVLDFF_" #lmul)],
+  [ReadVLDX], forceMasked
+>;
+class VLFSchedMC: VLFSched<"WorstCase", forceMasked=1>;
 
 // Unit-Stride Segment Loads and Stores
-class VLSEGSched<int nf, int eew, string emul = "WorstCase"> : Sched<[
-  !cast<SchedReadWrite>("WriteVLSEG" #nf #"e" #eew #"_" #emul),
-  ReadVLDX, ReadVMask
-]>;
-class VSSEGSched<int nf, int eew, string emul = "WorstCase"> : Sched<[
-  !cast<SchedReadWrite>("WriteVSSEG" #nf #"e" #eew #"_" #emul),
-  !cast<SchedReadWrite>("ReadVSTEV_" #emul),
-  ReadVSTX, ReadVMask
-]>;
-class VLSEGFFSched<int nf, int eew, string emul = "WorstCase"> : Sched<[
-  !cast<SchedReadWrite>("WriteVLSEGFF" #nf #"e" #eew #"_" #emul),
-  ReadVLDX, ReadVMask
-]>;
+class VLSEGSched<int nf, int eew, string emul, bit forceMasked = 0> : SchedCommon<
+  [!cast<SchedWrite>("WriteVLSEG" #nf #"e" #eew #"_" #emul)],
+  [ReadVLDX], forceMasked
+>;
+class VLSEGSchedMC<int nf, int eew> : VLSEGSched<nf, eew, "WorstCase",
+                                                 forceMasked=1>;
+
+class VSSEGSched<int nf, int eew, string emul, bit forceMasked = 0> : SchedCommon<
+  [!cast<SchedWrite>("WriteVSSEG" #nf #"e" #eew #"_" #emul)],
+  [!cast<SchedRead>("ReadVSTEV_" #emul), ReadVSTX], forceMasked
+>;
+class VSSEGSchedMC<int nf, int eew> : VSSEGSched<nf, eew, "WorstCase",
+                                                 forceMasked=1>;
+
+class VLSEGFFSched<int nf, int eew, string emul, bit forceMasked = 0> : SchedCommon<
+  [!cast<SchedWrite>("WriteVLSEGFF" #nf #"e" #eew #"_" #emul)],
+  [ReadVLDX], forceMasked
+>;
+class VLSEGFFSchedMC<int nf, int eew> : VLSEGFFSched<nf, eew, "WorstCase",
+                                                     forceMasked=1>;
+
 // Strided Segment Loads and Stores
-class VLSSEGSched<int nf, int eew, string emul = "WorstCase"> : Sched<[
-  !cast<SchedReadWrite>("WriteVLSSEG" #nf #"e" #eew #"_" #emul),
-  ReadVLDX, ReadVLDSX, ReadVMask
-]>;
-class VSSSEGSched<int nf, int eew, string emul = "WorstCase"> : Sched<[
-  !cast<SchedReadWrite>("WriteVSSSEG" #nf #"e" #eew #"_" #emul),
-  !cast<SchedReadWrite>("ReadVSTS" #eew #"V_" #emul),
-  ReadVSTX, ReadVSTSX, ReadVMask
-]>;
+class VLSSEGSched<int nf, int eew, string emul, bit forceMasked = 0> : SchedCommon<
+  [!cast<SchedWrite>("WriteVLSSEG" #nf #"e" #eew #"_" #emul)],
+  [ReadVLDX, ReadVLDSX], forceMasked
+>;
+class VLSSEGSchedMC<int nf, int eew> : VLSSEGSched<nf, eew, "WorstCase",
+                                                   forceMasked=1>;
+
+class VSSSEGSched<int nf, int eew, string emul, bit forceMasked = 0> : SchedCommon<
+  [!cast<SchedWrite>("WriteVSSSEG" #nf #"e" #eew #"_" #emul)],
+  [!cast<SchedRead>("ReadVSTS" #eew #"V_" #emul),
+   ReadVSTX, ReadVSTSX], forceMasked
+>;
+class VSSSEGSchedMC<int nf, int eew> : VSSSEGSched<nf, eew, "WorstCase",
+                                                   forceMasked=1>;
+
 // Indexed Segment Loads and Stores
-class VLXSEGSched<int nf, int eew, string isOrdered, string emul = "WorstCase"> : Sched<[
-  !cast<SchedReadWrite>("WriteVL" #isOrdered #"XSEG" #nf #"e" #eew #"_" #emul),
-  ReadVLDX, !cast<SchedReadWrite>("ReadVLD" #isOrdered #"XV_" #emul), ReadVMask
-]>;
-class VSXSEGSched<int nf, int eew, string isOrdered, string emul = "WorstCase"> : Sched<[
-  !cast<SchedReadWrite>("WriteVS" #isOrdered #"XSEG" #nf #"e" #eew #"_" #emul),
-  !cast<SchedReadWrite>("ReadVST" #isOrdered #"X" #eew #"_" #emul),
-  ReadVSTX, !cast<SchedReadWrite>("ReadVST" #isOrdered #"XV_" #emul), ReadVMask
-]>;
+class VLXSEGSched<int nf, int eew, string isOrdered, string emul,
+                  bit forceMasked = 0> : SchedCommon<
+  [!cast<SchedWrite>("WriteVL" #isOrdered #"XSEG" #nf #"e" #eew #"_" #emul)],
+  [ReadVLDX, !cast<SchedRead>("ReadVLD" #isOrdered #"XV_" #emul)],
+  forceMasked
+>;
+class VLXSEGSchedMC<int nf, int eew, string isOrdered>:
+  VLXSEGSched<nf, eew, isOrdered, "WorstCase", forceMasked=1>;
+
+class VSXSEGSched<int nf, int eew, string isOrdered, string emul,
+                  bit forceMasked = 0> : SchedCommon<
+  [!cast<SchedWrite>("WriteVS" #isOrdered #"XSEG" #nf #"e" #eew #"_" #emul)],
+  [!cast<SchedRead>("ReadVST" #isOrdered #"X" #eew #"_" #emul),
+   ReadVSTX, !cast<SchedRead>("ReadVST" #isOrdered #"XV_" #emul)],
+  forceMasked
+>;
+class VSXSEGSchedMC<int nf, int eew, string isOrdered>:
+  VSXSEGSched<nf, eew, isOrdered, "WorstCase", forceMasked=1>;
 
 //===----------------------------------------------------------------------===//
 // Instruction class templates
 //===----------------------------------------------------------------------===//
 
 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
 // unit-stride load vd, (rs1), vm
 class VUnitStrideLoad<RISCVWidth width, string opcodestr>

 //===----------------------------------------------------------------------===//
 
 multiclass VIndexLoadStore<list<int> EEWList> {
   foreach n = EEWList in {
     defvar w = !cast<RISCVWidth>("LSWidth" # n);
 
     def VLUXEI # n # _V :
       VIndexedLoad<MOPLDIndexedUnord, w, "vluxei" # n # ".v">,
-      VLXSched<n, "U">;
+      VLXSchedMC<n, "U">;
     def VLOXEI # n # _V :
       VIndexedLoad<MOPLDIndexedOrder, w, "vloxei" # n # ".v">,
-      VLXSched<n, "O">;
+      VLXSchedMC<n, "O">;
 
     def VSUXEI # n # _V :
       VIndexedStore<MOPSTIndexedUnord, w, "vsuxei" # n # ".v">,
-      VSXSched<n, "U">;
+      VSXSchedMC<n, "U">;
     def VSOXEI # n # _V :
       VIndexedStore<MOPSTIndexedOrder, w, "vsoxei" # n # ".v">,
-      VSXSched<n, "O">;
+      VSXSchedMC<n, "O">;
   }
 }
 
 multiclass VALU_IV_V<string opcodestr, bits<6> funct6> {
   def V  : VALUVV<funct6, OPIVV, opcodestr # ".vv">,
-           Sched<[WriteVIALUV_WorstCase, ReadVIALUV_WorstCase,
-                  ReadVIALUV_WorstCase, ReadVMask]>;
+           SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">;
 }
 
 multiclass VALU_IV_X<string opcodestr, bits<6> funct6> {
   def X  : VALUVX<funct6, OPIVX, opcodestr # ".vx">,
-           Sched<[WriteVIALUX_WorstCase, ReadVIALUV_WorstCase,
-                  ReadVIALUX_WorstCase, ReadVMask]>;
+           SchedBinaryMC<"WriteVIALUX", "ReadVIALUV", "ReadVIALUX">;
 }
 
 multiclass VALU_IV_I<string opcodestr, bits<6> funct6> {
   def I  : VALUVI<funct6, opcodestr # ".vi", simm5>,
-           Sched<[WriteVIALUI_WorstCase, ReadVIALUV_WorstCase,
-                  ReadVMask]>;
+           SchedUnaryMC<"WriteVIALUI", "ReadVIALUV">;
 }
 
 multiclass VALU_IV_V_X_I<string opcodestr, bits<6> funct6>
     : VALU_IV_V<opcodestr, funct6>,
       VALU_IV_X<opcodestr, funct6>,
       VALU_IV_I<opcodestr, funct6>;
 
 multiclass VALU_IV_V_X<string opcodestr, bits<6> funct6>
     : VALU_IV_V<opcodestr, funct6>,
       VALU_IV_X<opcodestr, funct6>;
 
 multiclass VALU_IV_X_I<string opcodestr, bits<6> funct6>
     : VALU_IV_X<opcodestr, funct6>,
       VALU_IV_I<opcodestr, funct6>;
 
 multiclass VALU_MV_V_X<string opcodestr, bits<6> funct6, string vw> {
   def V  : VALUVV<funct6, OPMVV, opcodestr # "." # vw # "v">,
-           Sched<[WriteVIWALUV_WorstCase, ReadVIWALUV_WorstCase,
-                  ReadVIWALUV_WorstCase, ReadVMask]>;
+           SchedBinaryMC<"WriteVIWALUV", "ReadVIWALUV", "ReadVIWALUV">;
   def X  : VALUVX<funct6, OPMVX, opcodestr # "." # vw # "x">,
-           Sched<[WriteVIWALUX_WorstCase, ReadVIWALUV_WorstCase,
-                  ReadVIWALUX_WorstCase, ReadVMask]>;
+           SchedBinaryMC<"WriteVIWALUX", "ReadVIWALUV", "ReadVIWALUX">;
 }
 
 multiclass VMAC_MV_V_X<string opcodestr, bits<6> funct6> {
   def V : VALUrVV<funct6, OPMVV, opcodestr # ".vv">,
-          Sched<[WriteVIMulAddV_WorstCase, ReadVIMulAddV_WorstCase,
-                 ReadVIMulAddV_WorstCase, ReadVMask]>;
+          SchedBinaryMC<"WriteVIMulAddV", "ReadVIMulAddV", "ReadVIMulAddV">;
   def X : VALUrVX<funct6, OPMVX, opcodestr # ".vx">,
-          Sched<[WriteVIMulAddX_WorstCase, ReadVIMulAddV_WorstCase,
-                 ReadVIMulAddX_WorstCase, ReadVMask]>;
+          SchedBinaryMC<"WriteVIMulAddX", "ReadVIMulAddV", "ReadVIMulAddX">;
 }
 
 multiclass VWMAC_MV_X<string opcodestr, bits<6> funct6> {
   def X : VALUrVX<funct6, OPMVX, opcodestr # ".vx">,
-          Sched<[WriteVIWMulAddX_WorstCase, ReadVIWMulAddV_WorstCase,
-                 ReadVIWMulAddX_WorstCase, ReadVMask]>;
+          SchedBinaryMC<"WriteVIWMulAddX", "ReadVIWMulAddV", "ReadVIWMulAddX">;
 }
 
 multiclass VWMAC_MV_V_X<string opcodestr, bits<6> funct6>
    : VWMAC_MV_X<opcodestr, funct6> {
   def V : VALUrVV<funct6, OPMVV, opcodestr # ".vv">,
-          Sched<[WriteVIWMulAddV_WorstCase, ReadVIWMulAddV_WorstCase,
-                 ReadVIWMulAddV_WorstCase, ReadVMask]>;
+          SchedBinaryMC<"WriteVIWMulAddV", "ReadVIWMulAddV", "ReadVIWMulAddV">;
 }
 
 multiclass VALU_MV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
   def "" : VALUVs2<funct6, vs1, OPMVV, opcodestr>,
-           Sched<[WriteVExtV_WorstCase, ReadVExtV_WorstCase, ReadVMask]>;
+           SchedUnaryMC<"WriteVExtV", "ReadVExtV">;
 }
 
 multiclass VMRG_IV_V_X_I<string opcodestr, bits<6> funct6> {
   def VM : VALUmVV<funct6, OPIVV, opcodestr # ".vvm">,
-           Sched<[WriteVIMergeV_WorstCase, ReadVIMergeV_WorstCase,
-                  ReadVIMergeV_WorstCase, ReadVMask]>;
+           SchedBinaryMC<"WriteVIMergeV", "ReadVIMergeV", "ReadVIMergeV">;
   def XM : VALUmVX<funct6, OPIVX, opcodestr # ".vxm">,
-           Sched<[WriteVIMergeX_WorstCase, ReadVIMergeV_WorstCase,
-                  ReadVIMergeX_WorstCase, ReadVMask]>;
+           SchedBinaryMC<"WriteVIMergeX", "ReadVIMergeV", "ReadVIMergeX">;
   def IM : VALUmVI<funct6, opcodestr # ".vim">,
-           Sched<[WriteVIMergeI_WorstCase, ReadVIMergeV_WorstCase,
-                  ReadVMask]>;
+           SchedUnaryMC<"WriteVIMergeI", "ReadVIMergeV">;
 }
 
 multiclass VALUm_IV_V_X<string opcodestr, bits<6> funct6> {
   def VM : VALUmVV<funct6, OPIVV, opcodestr # ".vvm">,
-           Sched<[WriteVICALUV_WorstCase, ReadVICALUV_WorstCase,
-                  ReadVICALUV_WorstCase, ReadVMask]>;
+           SchedBinaryMC<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV">;
   def XM : VALUmVX<funct6, OPIVX, opcodestr # ".vxm">,
-           Sched<[WriteVICALUX_WorstCase, ReadVICALUV_WorstCase,
-                  ReadVICALUX_WorstCase, ReadVMask]>;
+           SchedBinaryMC<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX">;
 }
 
 multiclass VALUm_IV_V_X_I<string opcodestr, bits<6> funct6>
     : VALUm_IV_V_X<opcodestr, funct6> {
   def IM : VALUmVI<funct6, opcodestr # ".vim">,
-           Sched<[WriteVICALUI_WorstCase, ReadVICALUV_WorstCase,
-                  ReadVMask]>;
+           SchedUnaryMC<"WriteVICALUI", "ReadVICALUV">;
 }
 
 multiclass VALUNoVm_IV_V_X<string opcodestr, bits<6> funct6> {
   def V : VALUVVNoVm<funct6, OPIVV, opcodestr # ".vv">,
-          Sched<[WriteVICALUV_WorstCase, ReadVICALUV_WorstCase,
-                 ReadVICALUV_WorstCase]>;
+          SchedBinaryMC<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV",
+                        forceMasked=0>;
   def X : VALUVXNoVm<funct6, OPIVX, opcodestr # ".vx">,
-          Sched<[WriteVICALUX_WorstCase, ReadVICALUV_WorstCase,
-                 ReadVICALUX_WorstCase]>;
+          SchedBinaryMC<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX",
+                        forceMasked=0>;
 }
 
 multiclass VALUNoVm_IV_V_X_I<string opcodestr, bits<6> funct6>
    : VALUNoVm_IV_V_X<opcodestr, funct6> {
   def I : VALUVINoVm<funct6, opcodestr # ".vi", simm5>,
-          Sched<[WriteVICALUI_WorstCase, ReadVICALUV_WorstCase]>;
+          SchedUnaryMC<"WriteVICALUI", "ReadVICALUV", forceMasked=0>;
 }
 
 multiclass VALU_FV_F<string opcodestr, bits<6> funct6> {
   def F : VALUVF<funct6, OPFVF, opcodestr # ".vf">,
-          Sched<[WriteVFALUF_WorstCase, ReadVFALUV_WorstCase,
-                 ReadVFALUF_WorstCase, ReadVMask]>;
+          SchedBinaryMC<"WriteVFALUF", "ReadVFALUV", "ReadVFALUF">;
 }
 
 multiclass VALU_FV_V_F<string opcodestr, bits<6> funct6>
     : VALU_FV_F<opcodestr, funct6> {
   def V : VALUVV<funct6, OPFVV, opcodestr # ".vv">,
-          Sched<[WriteVFALUV_WorstCase, ReadVFALUV_WorstCase,
-                 ReadVFALUV_WorstCase, ReadVMask]>;
+          SchedBinaryMC<"WriteVFALUV", "ReadVFALUV", "ReadVFALUV">;
 }
 
 multiclass VWALU_FV_V_F<string opcodestr, bits<6> funct6, string vw> {
   def V : VALUVV<funct6, OPFVV, opcodestr # "." # vw # "v">,
-          Sched<[WriteVFWALUV_WorstCase, ReadVFWALUV_WorstCase,
-                 ReadVFWALUV_WorstCase, ReadVMask]>;
+          SchedBinaryMC<"WriteVFWALUV", "ReadVFWALUV", "ReadVFWALUV">;
   def F : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f">,
-          Sched<[WriteVFWALUF_WorstCase, ReadVFWALUV_WorstCase,
-                 ReadVFWALUF_WorstCase, ReadVMask]>;
+          SchedBinaryMC<"WriteVFWALUF", "ReadVFWALUV", "ReadVFWALUF">;
 }
 
 multiclass VMUL_FV_V_F<string opcodestr, bits<6> funct6> {
   def V : VALUVV<funct6, OPFVV, opcodestr # ".vv">,
-          Sched<[WriteVFMulV_WorstCase, ReadVFMulV_WorstCase,
-                 ReadVFMulV_WorstCase, ReadVMask]>;
+          SchedBinaryMC<"WriteVFMulV", "ReadVFMulV", "ReadVFMulV">;
   def F : VALUVF<funct6, OPFVF, opcodestr # ".vf">,
-          Sched<[WriteVFMulF_WorstCase, ReadVFMulV_WorstCase,
-                 ReadVFMulF_WorstCase, ReadVMask]>;
+          SchedBinaryMC<"WriteVFMulF", "ReadVFMulV", "ReadVFMulF">;
 }
 
 multiclass VDIV_FV_F<string opcodestr, bits<6> funct6> {
   def F : VALUVF<funct6, OPFVF, opcodestr # ".vf">,
-          Sched<[WriteVFDivF_WorstCase, ReadVFDivV_WorstCase,
-                 ReadVFDivF_WorstCase, ReadVMask]>;
+          SchedBinaryMC<"WriteVFDivF", "ReadVFDivV", "ReadVFDivF">;
 }
 
 multiclass VDIV_FV_V_F<string opcodestr, bits<6> funct6>
     : VDIV_FV_F<opcodestr, funct6> {
   def V : VALUVV<funct6, OPFVV, opcodestr # ".vv">,
-          Sched<[WriteVFDivV_WorstCase, ReadVFDivV_WorstCase,
-                 ReadVFDivV_WorstCase, ReadVMask]>;
+          SchedBinaryMC<"WriteVFDivV", "ReadVFDivV", "ReadVFDivV">;
 }
 
 multiclass VWMUL_FV_V_F<string opcodestr, bits<6> funct6> {
   def V : VALUVV<funct6, OPFVV, opcodestr # ".vv">,
-          Sched<[WriteVFWMulV_WorstCase, ReadVFWMulV_WorstCase,
-                 ReadVFWMulV_WorstCase, ReadVMask]>;
+          SchedBinaryMC<"WriteVFWMulV", "ReadVFWMulV", "ReadVFWMulV">;
   def F : VALUVF<funct6, OPFVF, opcodestr # ".vf">,
-          Sched<[WriteVFWMulF_WorstCase, ReadVFWMulV_WorstCase,
-                 ReadVFWMulF_WorstCase, ReadVMask]>;
+          SchedBinaryMC<"WriteVFWMulF", "ReadVFWMulV", "ReadVFWMulF">;
 }
 
 multiclass VMAC_FV_V_F<string opcodestr, bits<6> funct6> {
   def V : VALUrVV<funct6, OPFVV, opcodestr # ".vv">,
-          Sched<[WriteVFMulAddV_WorstCase, ReadVFMulAddV_WorstCase,
-                 ReadVFMulAddV_WorstCase, ReadVMask]>;
+          SchedBinaryMC<"WriteVFMulAddV", "ReadVFMulAddV", "ReadVFMulAddV">;
   def F : VALUrVF<funct6, OPFVF, opcodestr # ".vf">,
-          Sched<[WriteVFMulAddF_WorstCase, ReadVFMulAddV_WorstCase,
-                 ReadVFMulAddF_WorstCase, ReadVMask]>;
+          SchedBinaryMC<"WriteVFMulAddF", "ReadVFMulAddV", "ReadVFMulAddF">;
 }
 
 multiclass VWMAC_FV_V_F<string opcodestr, bits<6> funct6> {
   def V : VALUrVV<funct6, OPFVV, opcodestr # ".vv">,
-          Sched<[WriteVFWMulAddV_WorstCase, ReadVFWMulAddV_WorstCase,
-                 ReadVFWMulAddV_WorstCase, ReadVMask]>;
+          SchedBinaryMC<"WriteVFWMulAddV", "ReadVFWMulAddV", "ReadVFWMulAddV">;
   def F : VALUrVF<funct6, OPFVF, opcodestr # ".vf">,
-          Sched<[WriteVFWMulAddF_WorstCase, ReadVFWMulAddV_WorstCase,
-                 ReadVFWMulAddF_WorstCase, ReadVMask]>;
+          SchedBinaryMC<"WriteVFWMulAddF", "ReadVFWMulAddV", "ReadVFWMulAddF">;
 }
 
 multiclass VSQR_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
   def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>,
-           Sched<[WriteVFSqrtV_WorstCase, ReadVFSqrtV_WorstCase,
-                  ReadVMask]>;
+           SchedUnaryMC<"WriteVFSqrtV", "ReadVFSqrtV">;
 }
 
 multiclass VRCP_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
   def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>,
-           Sched<[WriteVFRecpV_WorstCase, ReadVFRecpV_WorstCase,
-                  ReadVMask]>;
+           SchedUnaryMC<"WriteVFRecpV", "ReadVFRecpV">;
 }
 
 multiclass VMINMAX_FV_V_F<string opcodestr, bits<6> funct6> {
   def V : VALUVV<funct6, OPFVV, opcodestr # ".vv">,
-          Sched<[WriteVFMinMaxV_WorstCase, ReadVFMinMaxV_WorstCase,
-                 ReadVFMinMaxV_WorstCase, ReadVMask]>;
+          SchedBinaryMC<"WriteVFMinMaxV", "ReadVFMinMaxV", "ReadVFMinMaxV">;
   def F : VALUVF<funct6, OPFVF, opcodestr # ".vf">,
-          Sched<[WriteVFMinMaxF_WorstCase, ReadVFMinMaxV_WorstCase,
-                 ReadVFMinMaxF_WorstCase, ReadVMask]>;
+          SchedBinaryMC<"WriteVFMinMaxF", "ReadVFMinMaxV", "ReadVFMinMaxF">;
 }
 
 multiclass VCMP_FV_F<string opcodestr, bits<6> funct6> {
   def F : VALUVF<funct6, OPFVF, opcodestr # ".vf">,
-          Sched<[WriteVFCmpF_WorstCase, ReadVFCmpV_WorstCase,
-                 ReadVFCmpF_WorstCase, ReadVMask]>;
+          SchedBinaryMC<"WriteVFCmpF", "ReadVFCmpV", "ReadVFCmpF">;
 }
 
 multiclass VCMP_FV_V_F<string opcodestr, bits<6> funct6>
     : VCMP_FV_F<opcodestr, funct6> {
   def V : VALUVV<funct6, OPFVV, opcodestr # ".vv">,
-          Sched<[WriteVFCmpV_WorstCase, ReadVFCmpV_WorstCase,
-                 ReadVFCmpV_WorstCase, ReadVMask]>;
+          SchedBinaryMC<"WriteVFCmpV", "ReadVFCmpV", "ReadVFCmpV">;
 }
 
 multiclass VSGNJ_FV_V_F<string opcodestr, bits<6> funct6> {
   def V : VALUVV<funct6, OPFVV, opcodestr # ".vv">,
-          Sched<[WriteVFSgnjV_WorstCase, ReadVFSgnjV_WorstCase,
-                 ReadVFSgnjV_WorstCase, ReadVMask]>;
+          SchedBinaryMC<"WriteVFSgnjV", "ReadVFSgnjV", "ReadVFSgnjV">;
   def F : VALUVF<funct6, OPFVF, opcodestr # ".vf">,
-          Sched<[WriteVFSgnjF_WorstCase, ReadVFSgnjV_WorstCase,
-                 ReadVFSgnjF_WorstCase, ReadVMask]>;
+          SchedBinaryMC<"WriteVFSgnjF", "ReadVFSgnjV", "ReadVFSgnjF">;
 }
 
 multiclass VCLS_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
   def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>,
-           Sched<[WriteVFClassV_WorstCase, ReadVFClassV_WorstCase,
-                  ReadVMask]>;
+           SchedUnaryMC<"WriteVFClassV", "ReadVFClassV">;
 }
 
 multiclass VCVTF_IV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
   def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>,
-           Sched<[WriteVFCvtIToFV_WorstCase, ReadVFCvtIToFV_WorstCase,
-                  ReadVMask]>;
+           SchedUnaryMC<"WriteVFCvtIToFV", "ReadVFCvtIToFV">;
 }
 
 multiclass VCVTI_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
   def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>,
-           Sched<[WriteVFCvtFToIV_WorstCase, ReadVFCvtFToIV_WorstCase,
-                  ReadVMask]>;
+           SchedUnaryMC<"WriteVFCvtFToIV", "ReadVFCvtFToIV">;
 }
 
 multiclass VWCVTF_IV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
   def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>,
-           Sched<[WriteVFWCvtIToFV_WorstCase, ReadVFWCvtIToFV_WorstCase,
-                  ReadVMask]>;
+           SchedUnaryMC<"WriteVFWCvtIToFV", "ReadVFWCvtIToFV">;
 }
 
 multiclass VWCVTI_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
   def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>,
-           Sched<[WriteVFWCvtFToIV_WorstCase, ReadVFWCvtFToIV_WorstCase,
-                  ReadVMask]>;
+           SchedUnaryMC<"WriteVFWCvtFToIV", "ReadVFWCvtFToIV">;
 }
 
 multiclass VWCVTF_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
   def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>,
-           Sched<[WriteVFWCvtFToFV_WorstCase, ReadVFWCvtFToFV_WorstCase,
-                  ReadVMask]>;
+           SchedUnaryMC<"WriteVFWCvtFToFV", "ReadVFWCvtFToFV">;
 }
 
 multiclass VNCVTF_IV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
   def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>,
-           Sched<[WriteVFNCvtIToFV_WorstCase, ReadVFNCvtIToFV_WorstCase,
-                  ReadVMask]>;
+           SchedUnaryMC<"WriteVFNCvtIToFV", "ReadVFNCvtIToFV">;
 }
 
 multiclass VNCVTI_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
   def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>,
-           Sched<[WriteVFNCvtFToIV_WorstCase, ReadVFNCvtFToIV_WorstCase,
-                  ReadVMask]>;
+           SchedUnaryMC<"WriteVFNCvtFToIV", "ReadVFNCvtFToIV">;
 }
 
 multiclass VNCVTF_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
   def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>,
-           Sched<[WriteVFNCvtFToFV_WorstCase, ReadVFNCvtFToFV_WorstCase,
-                  ReadVMask]>;
+           SchedUnaryMC<"WriteVFNCvtFToFV", "ReadVFNCvtFToFV">;
 }
 
 multiclass VRED_MV_V<string opcodestr, bits<6> funct6> {
   def _VS : VALUVV<funct6, OPMVV, opcodestr # ".vs">,
-            Sched<[WriteVIRedV_From_WorstCase, ReadVIRedV, ReadVIRedV0,
-                   ReadVMask]>;
+            SchedReductionMC<"WriteVIRedV_From", "ReadVIRedV", "ReadVIRedV0">;
 }
 
 multiclass VREDMINMAX_MV_V<string opcodestr, bits<6> funct6> {
   def _VS : VALUVV<funct6, OPMVV, opcodestr # ".vs">,
-            Sched<[WriteVIRedMinMaxV_From_WorstCase, ReadVIRedV, ReadVIRedV0,
-                   ReadVMask]>;
+            SchedReductionMC<"WriteVIRedMinMaxV_From", "ReadVIRedV", "ReadVIRedV0">;
 }
 
 multiclass VWRED_IV_V<string opcodestr, bits<6> funct6> {
   def _VS : VALUVV<funct6, OPIVV, opcodestr # ".vs">,
-            Sched<[WriteVIWRedV_From_WorstCase, ReadVIWRedV, ReadVIWRedV0,
-                   ReadVMask]>;
+            SchedReductionMC<"WriteVIWRedV_From", "ReadVIWRedV", "ReadVIWRedV0">;
 }
 
 multiclass VRED_FV_V<string opcodestr, bits<6> funct6> {
   def _VS : VALUVV<funct6, OPFVV, opcodestr # ".vs">,
-            Sched<[WriteVFRedV_From_WorstCase, ReadVFRedV, ReadVFRedV0,
-                   ReadVMask]>;
+            SchedReductionMC<"WriteVFRedV_From", "ReadVFRedV", "ReadVFRedV0">;
 }
 
 multiclass VREDMINMAX_FV_V<string opcodestr, bits<6> funct6> {
   def _VS : VALUVV<funct6, OPFVV, opcodestr # ".vs">,
-            Sched<[WriteVFRedMinMaxV_From_WorstCase, ReadVFRedV, ReadVFRedV0,
-                   ReadVMask]>;
+            SchedReductionMC<"WriteVFRedMinMaxV_From", "ReadVFRedV", "ReadVFRedV0">;
 }
 
 multiclass VREDO_FV_V<string opcodestr, bits<6> funct6> {
   def _VS : VALUVV<funct6, OPFVV, opcodestr # ".vs">,
-            Sched<[WriteVFRedOV_From_WorstCase, ReadVFRedOV, ReadVFRedOV0,
-                   ReadVMask]>;
+            SchedReductionMC<"WriteVFRedOV_From", "ReadVFRedOV", "ReadVFRedOV0">;
 }
 
 multiclass VWRED_FV_V<string opcodestr, bits<6> funct6> {
   def _VS : VALUVV<funct6, OPFVV, opcodestr # ".vs">,
-            Sched<[WriteVFWRedV_From_WorstCase, ReadVFWRedV, ReadVFWRedV0,
-                   ReadVMask]>;
+            SchedReductionMC<"WriteVFWRedV_From", "ReadVFWRedV", "ReadVFWRedV0">;
 }
 
 multiclass VWREDO_FV_V<string opcodestr, bits<6> funct6> {
   def _VS : VALUVV<funct6, OPFVV, opcodestr # ".vs">,
-            Sched<[WriteVFWRedOV_From_WorstCase, ReadVFWRedOV, ReadVFWRedOV0,
-                   ReadVMask]>;
+            SchedReductionMC<"WriteVFWRedOV_From", "ReadVFWRedOV", "ReadVFWRedOV0">;
 }
 
 multiclass VMALU_MV_Mask<string opcodestr, bits<6> funct6, string vm = "v"> {
   def M : VALUVVNoVm<funct6, OPMVV, opcodestr #"." #vm #"m">,
-          Sched<[WriteVMALUV_WorstCase, ReadVMALUV_WorstCase,
-                 ReadVMALUV_WorstCase]>;
+          SchedBinaryMC<"WriteVMALUV", "ReadVMALUV", "ReadVMALUV",
+                        forceMasked=0>;
 }
 
 multiclass VMSFS_MV_V<string opcodestr, bits<6> funct6, bits<5> vs1> {
   def "" : VALUVs2<funct6, vs1, OPMVV, opcodestr>,
-           Sched<[WriteVMSFSV_WorstCase, ReadVMSFSV_WorstCase, ReadVMask]>;
+           SchedUnaryMC<"WriteVMSFSV", "ReadVMSFSV">;
 }
 
 multiclass VMIOT_MV_V<string opcodestr, bits<6> funct6, bits<5> vs1> {
   def "" : VALUVs2<funct6, vs1, OPMVV, opcodestr>,
-           Sched<[WriteVMIotV_WorstCase, ReadVMIotV_WorstCase, ReadVMask]>;
+           SchedUnaryMC<"WriteVMIotV", "ReadVMIotV">;
 }
 
 multiclass VSHT_IV_V_X_I<string opcodestr, bits<6> funct6> {
   def V  : VALUVV<funct6, OPIVV, opcodestr # ".vv">,
-           Sched<[WriteVShiftV_WorstCase, ReadVShiftV_WorstCase,
-                  ReadVShiftV_WorstCase, ReadVMask]>;
+           SchedBinaryMC<"WriteVShiftV", "ReadVShiftV", "ReadVShiftV">;
   def X  : VALUVX<funct6, OPIVX, opcodestr # ".vx">,
-           Sched<[WriteVShiftX_WorstCase, ReadVShiftV_WorstCase,
-                  ReadVShiftX_WorstCase, ReadVMask]>;
+           SchedBinaryMC<"WriteVShiftX", "ReadVShiftV", "ReadVShiftX">;
   def I  : VALUVI<funct6, opcodestr # ".vi", uimm5>,
-           Sched<[WriteVShiftI_WorstCase, ReadVShiftV_WorstCase,
-                  ReadVMask]>;
+           SchedUnaryMC<"WriteVShiftI", "ReadVShiftV">;
 }
 
 multiclass VNSHT_IV_V_X_I<string opcodestr, bits<6> funct6> {
   def V  : VALUVV<funct6, OPIVV, opcodestr # ".wv">,
-           Sched<[WriteVNShiftV_WorstCase, ReadVNShiftV_WorstCase,
-                  ReadVNShiftV_WorstCase, ReadVMask]>;
+           SchedBinaryMC<"WriteVNShiftV", "ReadVNShiftV", "ReadVNShiftV">;
   def X  : VALUVX<funct6, OPIVX, opcodestr # ".wx">,
-           Sched<[WriteVNShiftX_WorstCase, ReadVNShiftV_WorstCase,
-                  ReadVNShiftX_WorstCase, ReadVMask]>;
+           SchedBinaryMC<"WriteVNShiftX", "ReadVNShiftV", "ReadVNShiftX">;
   def I  : VALUVI<funct6, opcodestr # ".wi", uimm5>,
-           Sched<[WriteVNShiftI_WorstCase, ReadVNShiftV_WorstCase,
-                  ReadVMask]>;
+           SchedUnaryMC<"WriteVNShiftI", "ReadVNShiftV">;
 }
 
 multiclass VMINMAX_IV_V_X<string opcodestr, bits<6> funct6> {
   def V  : VALUVV<funct6, OPIVV, opcodestr # ".vv">,
-           Sched<[WriteVIMinMaxV_WorstCase, ReadVIMinMaxV_WorstCase,
-                  ReadVIMinMaxV_WorstCase, ReadVMask]>;
+           SchedBinaryMC<"WriteVIMinMaxV", "ReadVIMinMaxV", "ReadVIMinMaxV">;
   def X  : VALUVX<funct6, OPIVX, opcodestr # ".vx">,
-           Sched<[WriteVIMinMaxX_WorstCase, ReadVIMinMaxV_WorstCase,
-                  ReadVIMinMaxX_WorstCase, ReadVMask]>;
+           SchedBinaryMC<"WriteVIMinMaxX", "ReadVIMinMaxV", "ReadVIMinMaxX">;
 }
 
 multiclass VCMP_IV_V<string opcodestr, bits<6> funct6> {
   def V  : VALUVV<funct6, OPIVV, opcodestr # ".vv">,
-           Sched<[WriteVICmpV_WorstCase, ReadVICmpV_WorstCase,
-                  ReadVICmpV_WorstCase, ReadVMask]>;
+           SchedBinaryMC<"WriteVICmpV", "ReadVICmpV", "ReadVICmpV">;
 }
 
 multiclass VCMP_IV_X<string opcodestr, bits<6> funct6> {
   def X  : VALUVX<funct6, OPIVX, opcodestr # ".vx">,
-           Sched<[WriteVICmpX_WorstCase, ReadVICmpV_WorstCase,
-                  ReadVICmpX_WorstCase, ReadVMask]>;
+           SchedBinaryMC<"WriteVICmpX", "ReadVICmpV", "ReadVICmpX">;
 }
 
 multiclass VCMP_IV_I<string opcodestr, bits<6> funct6> {
   def I  : VALUVI<funct6, opcodestr # ".vi", simm5>,
-           Sched<[WriteVICmpI_WorstCase, ReadVICmpV_WorstCase,
-                  ReadVMask]>;
+           SchedUnaryMC<"WriteVICmpI", "ReadVICmpV">;
 }
 
 multiclass VCMP_IV_V_X_I<string opcodestr, bits<6> funct6>
     : VCMP_IV_V<opcodestr, funct6>,
       VCMP_IV_X<opcodestr, funct6>,
       VCMP_IV_I<opcodestr, funct6>;
 
 multiclass VCMP_IV_X_I<string opcodestr, bits<6> funct6>
     : VCMP_IV_X<opcodestr, funct6>,
       VCMP_IV_I<opcodestr, funct6>;
 
 multiclass VCMP_IV_V_X<string opcodestr, bits<6> funct6>
     : VCMP_IV_V<opcodestr, funct6>,
       VCMP_IV_X<opcodestr, funct6>;
 
 multiclass VMUL_MV_V_X<string opcodestr, bits<6> funct6> {
   def V  : VALUVV<funct6, OPMVV, opcodestr # ".vv">,
-           Sched<[WriteVIMulV_WorstCase, ReadVIMulV_WorstCase,
-                  ReadVIMulV_WorstCase, ReadVMask]>;
+           SchedBinaryMC<"WriteVIMulV", "ReadVIMulV", "ReadVIMulV">;
   def X  : VALUVX<funct6, OPMVX, opcodestr # ".vx">,
-           Sched<[WriteVIMulX_WorstCase, ReadVIMulV_WorstCase,
-                  ReadVIMulX_WorstCase, ReadVMask]>;
+           SchedBinaryMC<"WriteVIMulX", "ReadVIMulV", "ReadVIMulX">;
 }
 
 multiclass VWMUL_MV_V_X<string opcodestr, bits<6> funct6> {
   def V  : VALUVV<funct6, OPMVV, opcodestr # ".vv">,
-           Sched<[WriteVIWMulV_WorstCase, ReadVIWMulV_WorstCase,
-                  ReadVIWMulV_WorstCase, ReadVMask]>;
+           SchedBinaryMC<"WriteVIWMulV", "ReadVIWMulV", "ReadVIWMulV">;
   def X  : VALUVX<funct6, OPMVX, opcodestr # ".vx">,
-           Sched<[WriteVIWMulX_WorstCase, ReadVIWMulV_WorstCase,
-                  ReadVIWMulX_WorstCase, ReadVMask]>;
+           SchedBinaryMC<"WriteVIWMulX", "ReadVIWMulV", "ReadVIWMulX">;
 }
 
 multiclass VDIV_MV_V_X<string opcodestr, bits<6> funct6> {
   def V  : VALUVV<funct6, OPMVV, opcodestr # ".vv">,
-           Sched<[WriteVIDivV_WorstCase, ReadVIDivV_WorstCase,
-                  ReadVIDivV_WorstCase, ReadVMask]>;
+           SchedBinaryMC<"WriteVIDivV", "ReadVIDivV", "ReadVIDivV">;
   def X  : VALUVX<funct6, OPMVX, opcodestr # ".vx">,
-           Sched<[WriteVIDivX_WorstCase, ReadVIDivV_WorstCase,
-                  ReadVIDivX_WorstCase, ReadVMask]>;
+           SchedBinaryMC<"WriteVIDivX", "ReadVIDivV", "ReadVIDivX">;
 }
 
 multiclass VSALU_IV_V_X<string opcodestr, bits<6> funct6> {
   def V  : VALUVV<funct6, OPIVV, opcodestr # ".vv">,
-           Sched<[WriteVSALUV_WorstCase, ReadVSALUV_WorstCase,
-                  ReadVSALUV_WorstCase, ReadVMask]>;
+           SchedBinaryMC<"WriteVSALUV", "ReadVSALUV", "ReadVSALUV">;
   def X  : VALUVX<funct6, OPIVX, opcodestr # ".vx">,
-           Sched<[WriteVSALUX_WorstCase, ReadVSALUV_WorstCase,
-                  ReadVSALUX_WorstCase, ReadVMask]>;
+           SchedBinaryMC<"WriteVSALUX", "ReadVSALUV", "ReadVSALUX">;
 }
 
 multiclass VSALU_IV_V_X_I<string opcodestr, bits<6> funct6>
     : VSALU_IV_V_X<opcodestr, funct6> {
   def I  : VALUVI<funct6, opcodestr # ".vi", simm5>,
-           Sched<[WriteVSALUI_WorstCase, ReadVSALUV_WorstCase,
-                  ReadVMask]>;
+           SchedUnaryMC<"WriteVSALUI", "ReadVSALUV">;
 }
 
 multiclass VAALU_MV_V_X<string opcodestr, bits<6> funct6> {
   def V  : VALUVV<funct6, OPMVV, opcodestr # ".vv">,
-           Sched<[WriteVAALUV_WorstCase, ReadVAALUV_WorstCase,
-                  ReadVAALUV_WorstCase, ReadVMask]>;
+           SchedBinaryMC<"WriteVAALUV", "ReadVAALUV", "ReadVAALUV">;
   def X  : VALUVX<funct6, OPMVX, opcodestr # ".vx">,
-           Sched<[WriteVAALUX_WorstCase, ReadVAALUV_WorstCase,
-                  ReadVAALUX_WorstCase, ReadVMask]>;
+           SchedBinaryMC<"WriteVAALUX", "ReadVAALUV", "ReadVAALUX">;
 }
 
 multiclass VSMUL_IV_V_X<string opcodestr, bits<6> funct6> {
   def V  : VALUVV<funct6, OPIVV, opcodestr # ".vv">,
-           Sched<[WriteVSMulV_WorstCase, ReadVSMulV_WorstCase,
-                  ReadVSMulV_WorstCase, ReadVMask]>;
+           SchedBinaryMC<"WriteVSMulV", "ReadVSMulV", "ReadVSMulV">;
   def X  : VALUVX<funct6, OPIVX, opcodestr # ".vx">,
-           Sched<[WriteVSMulX_WorstCase, ReadVSMulV_WorstCase,
-                  ReadVSMulX_WorstCase, ReadVMask]>;
+           SchedBinaryMC<"WriteVSMulX", "ReadVSMulV", "ReadVSMulX">;
 }
 
 multiclass VSSHF_IV_V_X_I<string opcodestr, bits<6> funct6> {
   def V  : VALUVV<funct6, OPIVV, opcodestr # ".vv">,
-           Sched<[WriteVSShiftV_WorstCase, ReadVSShiftV_WorstCase,
-                  ReadVSShiftV_WorstCase, ReadVMask]>;
+           SchedBinaryMC<"WriteVSShiftV", "ReadVSShiftV", "ReadVSShiftV">;
   def X  : VALUVX<funct6, OPIVX, opcodestr # ".vx">,
-           Sched<[WriteVSShiftX_WorstCase, ReadVSShiftV_WorstCase,
-                  ReadVSShiftX_WorstCase, ReadVMask]>;
+           SchedBinaryMC<"WriteVSShiftX", "ReadVSShiftV", "ReadVSShiftX">;
   def I  : VALUVI<funct6, opcodestr # ".vi", uimm5>,
-           Sched<[WriteVSShiftI_WorstCase, ReadVSShiftV_WorstCase,
-                  ReadVMask]>;
+           SchedUnaryMC<"WriteVSShiftI", "ReadVSShiftV">;
 }
 
 multiclass VNCLP_IV_V_X_I<string opcodestr, bits<6> funct6> {
   def V  : VALUVV<funct6, OPIVV, opcodestr # ".wv">,
-           Sched<[WriteVNClipV_WorstCase, ReadVNClipV_WorstCase,
-                  ReadVNClipV_WorstCase, ReadVMask]>;
+           SchedBinaryMC<"WriteVNClipV", "ReadVNClipV", "ReadVNClipV">;
   def X  : VALUVX<funct6, OPIVX, opcodestr # ".wx">,
-           Sched<[WriteVNClipX_WorstCase, ReadVNClipV_WorstCase,
-                  ReadVNClipX_WorstCase, ReadVMask]>;
+           SchedBinaryMC<"WriteVNClipX", "ReadVNClipV", "ReadVNClipX">;
   def I  : VALUVI<funct6, opcodestr # ".wi", uimm5>,
-           Sched<[WriteVNClipI_WorstCase, ReadVNClipV_WorstCase,
-                  ReadVMask]>;
+           SchedUnaryMC<"WriteVNClipI", "ReadVNClipV">;
 }
 
 multiclass VSLD_IV_X_I<string opcodestr, bits<6> funct6> {
   def X  : VALUVX<funct6, OPIVX, opcodestr # ".vx">,
-           Sched<[WriteVISlideX_WorstCase, ReadVISlideV_WorstCase,
-                  ReadVISlideX_WorstCase, ReadVMask]>;
+           SchedBinaryMC<"WriteVISlideX", "ReadVISlideV", "ReadVISlideX">;
   def I  : VALUVI<funct6, opcodestr # ".vi", uimm5>,
-           Sched<[WriteVISlideI_WorstCase, ReadVISlideV_WorstCase,
-                  ReadVMask]>;
+           SchedUnaryMC<"WriteVISlideI", "ReadVISlideV">;
 }
 
 multiclass VSLD1_MV_X<string opcodestr, bits<6> funct6> {
   def X  : VALUVX<funct6, OPMVX, opcodestr # ".vx">,
-           Sched<[WriteVISlide1X_WorstCase, ReadVISlideV_WorstCase,
-                  ReadVISlideX_WorstCase, ReadVMask]>;
+           SchedBinaryMC<"WriteVISlide1X", "ReadVISlideV", "ReadVISlideX">;
 }
 
 multiclass VSLD1_FV_F<string opcodestr, bits<6> funct6> {
   def F : VALUVF<funct6, OPFVF, opcodestr # ".vf">,
-          Sched<[WriteVFSlide1F_WorstCase, ReadVFSlideV_WorstCase,
-                 ReadVFSlideF_WorstCase, ReadVMask]>;
+          SchedBinaryMC<"WriteVFSlide1F", "ReadVFSlideV", "ReadVFSlideF">;
 }
 
 multiclass VGTR_IV_V_X_I<string opcodestr, bits<6> funct6> {
   def V  : VALUVV<funct6, OPIVV, opcodestr # ".vv">,
-           Sched<[WriteVRGatherVV_WorstCase, ReadVRGatherVV_data_WorstCase,
-                  ReadVRGatherVV_index_WorstCase, ReadVMask]>;
+           SchedBinaryMC<"WriteVRGatherVV", "ReadVRGatherVV_data",
+                         "ReadVRGatherVV_index">;
   def X  : VALUVX<funct6, OPIVX, opcodestr # ".vx">,
-           Sched<[WriteVRGatherVX_WorstCase, ReadVRGatherVX_data_WorstCase,
-                  ReadVRGatherVX_index_WorstCase, ReadVMask]>;
+           SchedBinaryMC<"WriteVRGatherVX", "ReadVRGatherVX_data",
+                         "ReadVRGatherVX_index">;
   def I  : VALUVI<funct6, opcodestr # ".vi", uimm5>,
-           Sched<[WriteVRGatherVI_WorstCase, ReadVRGatherVI_data_WorstCase,
-                  ReadVMask]>;
+           SchedUnaryMC<"WriteVRGatherVI", "ReadVRGatherVI_data">;
 }
 
 multiclass VCPR_MV_Mask<string opcodestr, bits<6> funct6, string vm = "v"> {
   def M  : VALUVVNoVm<funct6, OPMVV, opcodestr # "." # vm # "m">,
-           Sched<[WriteVCompressV_WorstCase, ReadVCompressV_WorstCase,
-                  ReadVCompressV_WorstCase]>;
+           SchedBinaryMC<"WriteVCompressV", "ReadVCompressV", "ReadVCompressV">;
 }
 
 multiclass VWholeLoadN<bits<3> nf, string opcodestr, RegisterClass VRC> {
   foreach l = [8, 16, 32] in {
     defvar w = !cast<RISCVWidth>("LSWidth" # l);
     defvar s = !cast<SchedWrite>("WriteVLD" # !add(nf, 1) # "R");
 
     def E # l # _V : VWholeLoad<nf, w, opcodestr # "e" # l # ".v", VRC>,

 def VSETVL : RVInstSetVL<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
                          "vsetvl", "$rd, $rs1, $rs2">,
                           Sched<[WriteVSETVL, ReadVSETVL, ReadVSETVL]>;
 } // hasSideEffects = 1, mayLoad = 0, mayStore = 0
 foreach eew = [8, 16, 32] in {
   defvar w = !cast<RISCVWidth>("LSWidth" # eew);
 
   // Vector Unit-Stride Instructions
-  def VLE#eew#_V : VUnitStrideLoad<w, "vle"#eew#".v">, VLESched;
-  def VSE#eew#_V  : VUnitStrideStore<w,  "vse"#eew#".v">, VSESched;
+  def VLE#eew#_V : VUnitStrideLoad<w, "vle"#eew#".v">, VLESchedMC;
+  def VSE#eew#_V  : VUnitStrideStore<w,  "vse"#eew#".v">, VSESchedMC;
 
   // Vector Unit-Stride Fault-only-First Loads
-  def VLE#eew#FF_V : VUnitStrideLoadFF<w,  "vle"#eew#"ff.v">, VLFSched;
+  def VLE#eew#FF_V : VUnitStrideLoadFF<w,  "vle"#eew#"ff.v">, VLFSchedMC;
 
   // Vector Strided Instructions
-  def VLSE#eew#_V  : VStridedLoad<w,  "vlse"#eew#".v">, VLSSched<eew>;
-  def VSSE#eew#_V  : VStridedStore<w,  "vsse"#eew#".v">, VSSSched<eew>;
+  def VLSE#eew#_V  : VStridedLoad<w,  "vlse"#eew#".v">, VLSSchedMC<eew>;
+  def VSSE#eew#_V  : VStridedStore<w,  "vsse"#eew#".v">, VSSSchedMC<eew>;
 }
 
 defm "" : VIndexLoadStore<[8, 16, 32]>;
 } // Predicates = [HasVInstructions]
 
 let Predicates = [HasVInstructions] in {
 def VLM_V : VUnitStrideLoadMask<"vlm.v">,
              Sched<[WriteVLDM_WorstCase, ReadVLDX]>;

 def : InstAlias<"vl2r.v $vd, (${rs1})", (VL2RE8_V VRM2:$vd, GPR:$rs1)>;
 def : InstAlias<"vl4r.v $vd, (${rs1})", (VL4RE8_V VRM4:$vd, GPR:$rs1)>;
 def : InstAlias<"vl8r.v $vd, (${rs1})", (VL8RE8_V VRM8:$vd, GPR:$rs1)>;
 } // Predicates = [HasVInstructions]
 
 let Predicates = [HasVInstructionsI64] in {
 // Vector Unit-Stride Instructions
 def VLE64_V : VUnitStrideLoad<LSWidth64, "vle64.v">,
-              VLESched;
+              VLESchedMC;
 
 def VLE64FF_V : VUnitStrideLoadFF<LSWidth64, "vle64ff.v">,
-                VLFSched;
+                VLFSchedMC;
 
 def VSE64_V : VUnitStrideStore<LSWidth64, "vse64.v">,
-              VSESched;
+              VSESchedMC;
 // Vector Strided Instructions
 def VLSE64_V : VStridedLoad<LSWidth64, "vlse64.v">,
-               VLSSched<32>;
+               VLSSchedMC<32>;
 
 def VSSE64_V : VStridedStore<LSWidth64, "vsse64.v">,
-               VSSSched<64>;
+               VSSSchedMC<64>;
 
 defm VL1R: VWholeLoadEEW64<0, "vl1r", VR, WriteVLD1R>;
 defm VL2R: VWholeLoadEEW64<1, "vl2r", VRM2, WriteVLD2R>;
 defm VL4R: VWholeLoadEEW64<3, "vl4r", VRM4, WriteVLD4R>;
 defm VL8R: VWholeLoadEEW64<7, "vl8r", VRM8, WriteVLD8R>;
 } // Predicates = [HasVInstructionsI64]
 let Predicates = [IsRV64, HasVInstructionsI64] in {
   // Vector Indexed Instructions

 defm VMERGE_V : VMRG_IV_V_X_I<"vmerge", 0b010111>;
 
 // Vector Integer Move Instructions
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, vs2 = 0, vm = 1,
     RVVConstraint = NoConstraint  in {
 // op vd, vs1
 def VMV_V_V : RVInstVV<0b010111, OPIVV, (outs VR:$vd),
                        (ins VR:$vs1), "vmv.v.v", "$vd, $vs1">,
-              Sched<[WriteVIMovV_WorstCase, ReadVIMovV_WorstCase]>;
+              SchedUnaryMC<"WriteVIMovV", "ReadVIMovV", forceMasked=0>;
 // op vd, rs1
 def VMV_V_X : RVInstVX<0b010111, OPIVX, (outs VR:$vd),
                        (ins GPR:$rs1), "vmv.v.x", "$vd, $rs1">,
-              Sched<[WriteVIMovX_WorstCase, ReadVIMovX_WorstCase]>;
+              SchedUnaryMC<"WriteVIMovX", "ReadVIMovX", forceMasked=0>;
 // op vd, imm
 def VMV_V_I : RVInstIVI<0b010111, (outs VR:$vd),
                        (ins simm5:$imm), "vmv.v.i", "$vd, $imm">,
-              Sched<[WriteVIMovI_WorstCase]>;
+              SchedNullaryMC<"WriteVIMovI", forceMasked=0>;
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0
 
 // Vector Fixed-Point Arithmetic Instructions
 defm VSADDU_V : VSALU_IV_V_X_I<"vsaddu", 0b100000>;
 defm VSADD_V : VSALU_IV_V_X_I<"vsadd", 0b100001>;
 defm VSSUBU_V : VSALU_IV_V_X<"vssubu", 0b100010>;
 defm VSSUB_V : VSALU_IV_V_X<"vssub", 0b100011>;
 

 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
 
 // Vector Floating-Point Merge Instruction
 let vm = 0 in
 def VFMERGE_VFM : RVInstVX<0b010111, OPFVF, (outs VR:$vd),
                            (ins VR:$vs2, FPR32:$rs1, VMV0:$v0),
                            "vfmerge.vfm", "$vd, $vs2, $rs1, v0">,
-                  Sched<[WriteVFMergeV_WorstCase, ReadVFMergeV_WorstCase,
-                         ReadVFMergeF_WorstCase, ReadVMask]>;
+                  SchedBinaryMC<"WriteVFMergeV", "ReadVFMergeV", "ReadVFMergeF">;
 
 // Vector Floating-Point Move Instruction
 let RVVConstraint = NoConstraint in
 let vm = 1, vs2 = 0 in
 def VFMV_V_F : RVInstVX<0b010111, OPFVF, (outs VR:$vd),
                        (ins FPR32:$rs1), "vfmv.v.f", "$vd, $rs1">,
-               Sched<[WriteVFMovV_WorstCase, ReadVFMovF_WorstCase]>;
+               SchedUnaryMC<"WriteVFMovV", "ReadVFMovF", forceMasked=0>;
 
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0
 
 // Single-Width Floating-Point/Integer Type-Convert Instructions
 let mayRaiseFPException = true in {
 let Uses = [FRM] in {
 defm VFCVT_XU_F_V : VCVTI_FV_VS2<"vfcvt.xu.f.v", 0b010010, 0b00000>;
 defm VFCVT_X_F_V : VCVTI_FV_VS2<"vfcvt.x.f.v", 0b010010, 0b00001>;

 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0,
     RVVConstraint = NoConstraint  in {
 
 // Vector mask population count vcpop
 def VCPOP_M : RVInstV<0b010000, 0b10000, OPMVV, (outs GPR:$vd),
                       (ins VR:$vs2, VMaskOp:$vm),
                       "vcpop.m", "$vd, $vs2$vm">,
-              Sched<[WriteVMPopV_WorstCase, ReadVMPopV_WorstCase,
-                     ReadVMask]>;
+              SchedUnaryMC<"WriteVMPopV", "ReadVMPopV">;
 
 // vfirst find-first-set mask bit
 def VFIRST_M : RVInstV<0b010000, 0b10001, OPMVV, (outs GPR:$vd),
                        (ins VR:$vs2, VMaskOp:$vm),
                        "vfirst.m", "$vd, $vs2$vm">,
-              Sched<[WriteVMFFSV_WorstCase, ReadVMFFSV_WorstCase,
-                     ReadVMask]>;
+              SchedUnaryMC<"WriteVMFFSV", "ReadVMFFSV">;
 
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0
 
 def : InstAlias<"vpopc.m $vd, $vs2$vm",
                 (VCPOP_M GPR:$vd, VR:$vs2, VMaskOp:$vm), 0>;
 
 let Constraints = "@earlyclobber $vd", RVVConstraint = Iota in {
 

 } // Constraints = "@earlyclobber $vd", RVVConstraint = Iota
 
 // Vector Element Index Instruction
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
 
 let vs2 = 0 in
 def VID_V : RVInstV<0b010100, 0b10001, OPMVV, (outs VR:$vd),
                     (ins VMaskOp:$vm), "vid.v", "$vd$vm">,
-            Sched<[WriteVMIdxV_WorstCase, ReadVMask]>;
+            SchedNullaryMC<"WriteVMIdxV">;
 
 // Integer Scalar Move Instructions
 let vm = 1, RVVConstraint = NoConstraint in {
 def VMV_X_S : RVInstV<0b010000, 0b00000, OPMVV, (outs GPR:$vd),
                       (ins VR:$vs2), "vmv.x.s", "$vd, $vs2">,
               Sched<[WriteVIMovVX, ReadVIMovVX]>;
 let Constraints = "$vd = $vd_wb" in
 def VMV_S_X : RVInstV2<0b010000, 0b00000, OPMVX, (outs VR:$vd_wb),

 defm VFSLIDE1DOWN_V : VSLD1_FV_F<"vfslide1down", 0b001111>;
 } // Predicates = [HasVInstructionsAnyF]
 
 let Predicates = [HasVInstructions] in {
 // Vector Register Gather Instruction
 let Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather in {
 defm VRGATHER_V : VGTR_IV_V_X_I<"vrgather", 0b001100>;
 def VRGATHEREI16_VV : VALUVV<0b001110, OPIVV, "vrgatherei16.vv">,
-                      Sched<[WriteVRGatherVV_WorstCase, ReadVRGatherVV_data_WorstCase,
-                             ReadVRGatherVV_index_WorstCase]>;
+                      SchedBinaryMC<"WriteVRGatherVV", "ReadVRGatherVV_data",
+                                    "ReadVRGatherVV_index">;
 } // Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather
 
 // Vector Compress Instruction
 let Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress in {
 defm VCOMPRESS_V : VCPR_MV_Mask<"vcompress", 0b010111>;
 } // Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isMoveReg = 1,

 
 let Predicates = [HasVInstructions] in {
   foreach nf=2-8 in {
     foreach eew = [8, 16, 32] in {
       defvar w = !cast<RISCVWidth>("LSWidth"#eew);
 
       def VLSEG#nf#E#eew#_V :
         VUnitStrideSegmentLoad<!add(nf, -1), w, "vlseg"#nf#"e"#eew#".v">,
-        VLSEGSched<nf, eew>;
+        VLSEGSchedMC<nf, eew>;
       def VLSEG#nf#E#eew#FF_V :
         VUnitStrideSegmentLoadFF<!add(nf, -1), w, "vlseg"#nf#"e"#eew#"ff.v">,
-        VLSEGFFSched<nf, eew>;
+        VLSEGFFSchedMC<nf, eew>;
       def VSSEG#nf#E#eew#_V :
         VUnitStrideSegmentStore<!add(nf, -1), w, "vsseg"#nf#"e"#eew#".v">,
-        VSSEGSched<nf, eew>;
+        VSSEGSchedMC<nf, eew>;
       // Vector Strided Instructions
       def VLSSEG#nf#E#eew#_V :
         VStridedSegmentLoad<!add(nf, -1), w, "vlsseg"#nf#"e"#eew#".v">,
-        VLSSEGSched<nf, eew>;
+        VLSSEGSchedMC<nf, eew>;
       def VSSSEG#nf#E#eew#_V :
         VStridedSegmentStore<!add(nf, -1), w, "vssseg"#nf#"e"#eew#".v">,
-        VSSSEGSched<nf, eew>;
+        VSSSEGSchedMC<nf, eew>;
 
       // Vector Indexed Instructions
       def VLUXSEG#nf#EI#eew#_V :
         VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedUnord, w,
                             "vluxseg"#nf#"ei"#eew#".v">,
-        VLXSEGSched<nf, eew, "U">;
+        VLXSEGSchedMC<nf, eew, "U">;
       def VLOXSEG#nf#EI#eew#_V :
         VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedOrder, w,
                             "vloxseg"#nf#"ei"#eew#".v">,
-        VLXSEGSched<nf, eew, "O">;
+        VLXSEGSchedMC<nf, eew, "O">;
       def VSUXSEG#nf#EI#eew#_V :
         VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedUnord, w,
                              "vsuxseg"#nf#"ei"#eew#".v">,
-        VSXSEGSched<nf, eew, "U">;
+        VSXSEGSchedMC<nf, eew, "U">;
       def VSOXSEG#nf#EI#eew#_V :
         VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder, w,
                              "vsoxseg"#nf#"ei"#eew#".v">,
-        VSXSEGSched<nf, eew, "O">;
+        VSXSEGSchedMC<nf, eew, "O">;
     }
   }
 } // Predicates = [HasVInstructions]
 
 let Predicates = [HasVInstructionsI64] in {
   foreach nf=2-8 in {
     // Vector Unit-strided Segment Instructions
     def VLSEG#nf#E64_V :
       VUnitStrideSegmentLoad<!add(nf, -1), LSWidth64, "vlseg"#nf#"e64.v">,
-      VLSEGSched<nf, 64>;
+      VLSEGSchedMC<nf, 64>;
     def VLSEG#nf#E64FF_V :
       VUnitStrideSegmentLoadFF<!add(nf, -1), LSWidth64, "vlseg"#nf#"e64ff.v">,
-      VLSEGFFSched<nf, 64>;
+      VLSEGFFSchedMC<nf, 64>;
     def VSSEG#nf#E64_V :
       VUnitStrideSegmentStore<!add(nf, -1), LSWidth64, "vsseg"#nf#"e64.v">,
-      VSSEGSched<nf, 64>;
+      VSSEGSchedMC<nf, 64>;
 
     // Vector Strided Segment Instructions
     def VLSSEG#nf#E64_V :
       VStridedSegmentLoad<!add(nf, -1), LSWidth64, "vlsseg"#nf#"e64.v">,
-      VLSSEGSched<nf, 64>;
+      VLSSEGSchedMC<nf, 64>;
     def VSSSEG#nf#E64_V :
       VStridedSegmentStore<!add(nf, -1), LSWidth64, "vssseg"#nf#"e64.v">,
-      VSSSEGSched<nf, 64>;
+      VSSSEGSchedMC<nf, 64>;
   }
 } // Predicates = [HasVInstructionsI64]
 let Predicates = [HasVInstructionsI64, IsRV64] in {
   foreach nf = 2 - 8 in {
     // Vector Indexed Segment Instructions
     def VLUXSEG #nf #EI64_V
         : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedUnord, LSWidth64,
                               "vluxseg" #nf #"ei64.v">,
-          VLXSEGSched<nf, 64, "U">;
+          VLXSEGSchedMC<nf, 64, "U">;
     def VLOXSEG #nf #EI64_V
         : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedOrder, LSWidth64,
                               "vloxseg" #nf #"ei64.v">,
-          VLXSEGSched<nf, 64, "O">;
+          VLXSEGSchedMC<nf, 64, "O">;
     def VSUXSEG #nf #EI64_V
         : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedUnord, LSWidth64,
                                "vsuxseg" #nf #"ei64.v">,
-          VSXSEGSched<nf, 64, "U">;
+          VSXSEGSchedMC<nf, 64, "U">;
     def VSOXSEG #nf #EI64_V
         : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder, LSWidth64,
                                "vsoxseg" #nf #"ei64.v">,
-          VSXSEGSched<nf, 64, "O">;
+          VSXSEGSchedMC<nf, 64, "O">;
   }
 } // Predicates = [HasVInstructionsI64, IsRV64]
 
 include "RISCVInstrInfoVPseudos.td"

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

foreach dataEEW = EEWList in {
       }
     }
   }
 }
 
 multiclass VPseudoVPOP_M {
   foreach mti = AllMasks in {
     defvar mx = mti.LMul.MX;
-    defvar WriteVMPopV_MX = !cast<SchedWrite>("WriteVMPopV_" # mx);
-    defvar ReadVMPopV_MX = !cast<SchedRead>("ReadVMPopV_" # mx);
     let VLMul = mti.LMul.value in {
       def "_M_" # mti.BX : VPseudoUnaryNoMaskGPROut,
-                           Sched<[WriteVMPopV_MX, ReadVMPopV_MX, ReadVMPopV_MX]>;
+                           SchedBinary<"WriteVMPopV", "ReadVMPopV", "ReadVMPopV", mx>;
       def "_M_" # mti.BX # "_MASK" : VPseudoUnaryMaskGPROut,
-                                     Sched<[WriteVMPopV_MX, ReadVMPopV_MX, ReadVMPopV_MX]>;
+                                     SchedBinary<"WriteVMPopV", "ReadVMPopV", "ReadVMPopV", mx>;
     }
   }
 }
 
 multiclass VPseudoV1ST_M {
   foreach mti = AllMasks in {
     defvar mx = mti.LMul.MX;
-    defvar WriteVMFFSV_MX = !cast<SchedWrite>("WriteVMFFSV_" # mx);
-    defvar ReadVMFFSV_MX = !cast<SchedRead>("ReadVMFFSV_" # mx);
     let VLMul = mti.LMul.value in {
       def "_M_" # mti.BX : VPseudoUnaryNoMaskGPROut,
-                           Sched<[WriteVMFFSV_MX, ReadVMFFSV_MX, ReadVMFFSV_MX]>;
+                           SchedBinary<"WriteVMFFSV", "ReadVMFFSV", "ReadVMFFSV", mx>;
       def "_M_" # mti.BX # "_MASK" : VPseudoUnaryMaskGPROut,
-                                     Sched<[WriteVMFFSV_MX, ReadVMFFSV_MX, ReadVMFFSV_MX]>;
+                                     SchedBinary<"WriteVMFFSV", "ReadVMFFSV", "ReadVMFFSV", mx>;
     }
   }
 }
 
 multiclass VPseudoVSFS_M {
   defvar constraint = "@earlyclobber $rd";
   foreach mti = AllMasks in {
     defvar mx = mti.LMul.MX;
-    defvar WriteVMSFSV_MX = !cast<SchedWrite>("WriteVMSFSV_" # mx);
-    defvar ReadVMSFSV_MX = !cast<SchedRead>("ReadVMSFSV_" # mx);
     let VLMul = mti.LMul.value in {
       def "_M_" # mti.BX : VPseudoUnaryNoMask<VR, VR, constraint>,
-                           Sched<[WriteVMSFSV_MX, ReadVMSFSV_MX, ReadVMask]>;
+                           SchedUnary<"WriteVMSFSV", "ReadVMSFSV", mx>;
       def "_M_" # mti.BX # "_MASK" : VPseudoUnaryMask<VR, VR, constraint>,
-                                     Sched<[WriteVMSFSV_MX, ReadVMSFSV_MX, ReadVMask]>;
+                                     SchedUnary<"WriteVMSFSV", "ReadVMSFSV", mx>;
     }
   }
 }
 
 multiclass VPseudoVID_V {
   foreach m = MxList in {
     defvar mx = m.MX;
-    defvar WriteVMIdxV_MX = !cast<SchedWrite>("WriteVMIdxV_" # mx);
-    defvar ReadVMIdxV_MX = !cast<SchedRead>("ReadVMIdxV_" # mx);
-
     let VLMul = m.value in {
-      def "_V_" # m.MX : VPseudoNullaryNoMask<m.vrclass>,
-                         Sched<[WriteVMIdxV_MX, ReadVMask]>;
-      def "_V_" # m.MX # "_MASK" : VPseudoNullaryMask<m.vrclass>,
+      def "_V_" # mx : VPseudoNullaryNoMask<m.vrclass>,
+                         SchedNullary<"WriteVMIdxV", mx>;
+      def "_V_" # mx # "_MASK" : VPseudoNullaryMask<m.vrclass>,
                                    RISCVMaskedPseudo<MaskIdx=1>,
-                                   Sched<[WriteVMIdxV_MX, ReadVMask]>;
+                                   SchedNullary<"WriteVMIdxV", mx>;
     }
   }
 }
 
 multiclass VPseudoNullaryPseudoM <string BaseInst> {
   foreach mti = AllMasks in {
-    defvar mx = mti.LMul.MX;
-    defvar WriteVMALUV_MX = !cast<SchedWrite>("WriteVMALUV_" # mx);
-    defvar ReadVMALUV_MX = !cast<SchedRead>("ReadVMALUV_" # mx);
-
     let VLMul = mti.LMul.value in {
       def "_M_" # mti.BX : VPseudoNullaryPseudoM<BaseInst # "_MM">,
-        Sched<[WriteVMALUV_MX, ReadVMALUV_MX, ReadVMALUV_MX]>;
+        SchedBinary<"WriteVMALUV", "ReadVMALUV", "ReadVMALUV", mti.LMul.MX>;
     }
   }
 }
 
 multiclass VPseudoVIOT_M {
   defvar constraint = "@earlyclobber $rd";
   foreach m = MxList in {
     defvar mx = m.MX;
-    defvar WriteVMIotV_MX = !cast<SchedWrite>("WriteVMIotV_" # mx);
-    defvar ReadVMIotV_MX = !cast<SchedRead>("ReadVMIotV_" # mx);
     let VLMul = m.value in {
-      def "_" # m.MX : VPseudoUnaryNoMask<m.vrclass, VR, constraint>,
-                       Sched<[WriteVMIotV_MX, ReadVMIotV_MX, ReadVMask]>;
-      def "_" # m.MX # "_MASK" : VPseudoUnaryMask<m.vrclass, VR, constraint>,
+      def "_" # mx : VPseudoUnaryNoMask<m.vrclass, VR, constraint>,
+                       SchedUnary<"WriteVMIotV", "ReadVMIotV", mx>;
+      def "_" # mx # "_MASK" : VPseudoUnaryMask<m.vrclass, VR, constraint>,
                                  RISCVMaskedPseudo<MaskIdx=2>,
-                                 Sched<[WriteVMIotV_MX, ReadVMIotV_MX, ReadVMask]>;
+                                 SchedUnary<"WriteVMIotV", "ReadVMIotV", mx>;
     }
   }
 }
 
 multiclass VPseudoVCPR_V {
   foreach m = MxList in {
     defvar mx = m.MX;
     defvar sews = SchedSEWSet<mx>.val;
     let VLMul = m.value in
       foreach e = sews in {
         defvar suffix = "_" # m.MX # "_E" # e;
-        defvar WriteVCompressV_MX_E = !cast<SchedWrite>("WriteVCompressV" # suffix);
-        defvar ReadVCompressV_MX_E = !cast<SchedRead>("ReadVCompressV" # suffix);
-
         let SEW = e in
         def _VM # suffix : VPseudoUnaryAnyMask<m.vrclass, m.vrclass>,
-                           Sched<[WriteVCompressV_MX_E, ReadVCompressV_MX_E, ReadVCompressV_MX_E]>;
+                           SchedBinary<"WriteVCompressV", "ReadVCompressV", "ReadVCompressV",
+                                       mx, e>;
       }
   }
 }
 
 multiclass VPseudoBinary<VReg RetClass,
                          VReg Op1Class,
                          DAGOperand Op2Class,
                          LMULInfo MInfo,
foreach sew = EEWList in {
       defvar dataEMULOctuple = m.octuple;
       // emul = lmul * eew / sew
       defvar idxEMULOctuple = !srl(!mul(dataEMULOctuple, eew), !logtwo(sew));
       if !and(!ge(idxEMULOctuple, 1), !le(idxEMULOctuple, 64)) then {
         defvar emulMX = octuple_to_str<idxEMULOctuple>.ret;
         defvar emul = !cast<LMULInfo>("V_" # emulMX);
         defvar sews = SchedSEWSet<mx>.val;
         foreach e = sews in {
-          defvar WriteVRGatherVV_MX_E = !cast<SchedWrite>("WriteVRGatherVV_" # mx # "_E" # e);
-          defvar ReadVRGatherVV_data_MX_E = !cast<SchedRead>("ReadVRGatherVV_data_" # mx # "_E" # e);
-          defvar ReadVRGatherVV_index_MX_E = !cast<SchedRead>("ReadVRGatherVV_index_" # mx # "_E" # e);
           defm _VV : VPseudoBinaryEmul<m.vrclass, m.vrclass, emul.vrclass, m, emul, Constraint, e>,
-                     Sched<[WriteVRGatherVV_MX_E, ReadVRGatherVV_data_MX_E, ReadVRGatherVV_index_MX_E]>;
+                     SchedBinary<"WriteVRGatherVV", "ReadVRGatherVV_data", "ReadVRGatherVV_index",
+                                 mx, e>;
         }
       }
     }
   }
 }
 
 multiclass VPseudoBinaryV_VX<LMULInfo m, string Constraint = "", int sew = 0> {
   defm "_VX" : VPseudoBinary<m.vrclass, m.vrclass, GPR, m, Constraint, sew>;
 }
 
 multiclass VPseudoBinaryV_VX_RM<LMULInfo m, string Constraint = ""> {
   defm "_VX" : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass, GPR, m, Constraint>;
 }
 
 multiclass VPseudoVSLD1_VX<string Constraint = ""> {
   foreach m = MxList in {
-    defvar mx = m.MX;
-    defvar WriteVISlide1X_MX = !cast<SchedWrite>("WriteVISlide1X_" # mx);
-    defvar ReadVISlideV_MX = !cast<SchedRead>("ReadVISlideV_" # mx);
-    defvar ReadVISlideX_MX = !cast<SchedRead>("ReadVISlideX_" # mx);
-
     defm "_VX" : VPseudoBinary<m.vrclass, m.vrclass, GPR, m, Constraint>,
-                 Sched<[WriteVISlide1X_MX, ReadVISlideV_MX, ReadVISlideX_MX, ReadVMask]>;
+                 SchedBinary<"WriteVISlide1X", "ReadVISlideV", "ReadVISlideX", m.MX>;
   }
 }
 
 multiclass VPseudoBinaryV_VF<LMULInfo m, FPR_Info f, string Constraint = "", int sew = 0> {
   defm "_V" # f.FX : VPseudoBinary<m.vrclass, m.vrclass,
                                    f.fprclass, m, Constraint, sew>;
 }
 
 multiclass VPseudoBinaryV_VF_RM<LMULInfo m, FPR_Info f, string Constraint = "", int sew = 0> {
   defm "_V" # f.FX : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass,
                                                f.fprclass, m, Constraint, sew,
                                                UsesVXRM=0>;
 }
 
 multiclass VPseudoVSLD1_VF<string Constraint = ""> {
   foreach f = FPList in {
     foreach m = f.MxList in {
-      defvar mx = m.MX;
-      defvar WriteVFSlide1F_MX = !cast<SchedWrite>("WriteVFSlide1F_" # mx);
-      defvar ReadVFSlideV_MX = !cast<SchedRead>("ReadVFSlideV_" # mx);
-      defvar ReadVFSlideF_MX = !cast<SchedRead>("ReadVFSlideF_" # mx);
-
       defm "_V" # f.FX :
         VPseudoBinary<m.vrclass, m.vrclass, f.fprclass, m, Constraint>,
-        Sched<[WriteVFSlide1F_MX, ReadVFSlideV_MX, ReadVFSlideF_MX, ReadVMask]>;
+        SchedBinary<"WriteVFSlide1F", "ReadVFSlideV", "ReadVFSlideF", m.MX>;
     }
   }
 }
 
 multiclass VPseudoBinaryV_VI<Operand ImmType = simm5, LMULInfo m, string Constraint = ""> {
   defm _VI : VPseudoBinary<m.vrclass, m.vrclass, ImmType, m, Constraint>;
 }
 
 multiclass VPseudoBinaryV_VI_RM<Operand ImmType = simm5, LMULInfo m, string Constraint = ""> {
   defm _VI : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass, ImmType, m, Constraint>;
 }
 
 multiclass VPseudoVALU_MM {
   foreach m = MxList in {
     defvar mx = m.MX;
-    defvar WriteVMALUV_MX = !cast<SchedWrite>("WriteVMALUV_" # mx);
-    defvar ReadVMALUV_MX = !cast<SchedRead>("ReadVMALUV_" # mx);
-
     let VLMul = m.value in {
       def "_MM_" # mx : VPseudoBinaryNoMask<VR, VR, VR, "">,
-                          Sched<[WriteVMALUV_MX, ReadVMALUV_MX, ReadVMALUV_MX]>;
+                          SchedBinary<"WriteVMALUV", "ReadVMALUV", "ReadVMALUV", mx>;
     }
   }
 }
 
 // We use earlyclobber here due to
 // * The destination EEW is smaller than the source EEW and the overlap is
 //   in the lowest-numbered part of the source register group is legal.
 //   Otherwise, it is illegal.
def "_VXM" # "_" # m.MX:
     VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
                              m.vrclass, GPR, m, 1, "">;
 }
 
 multiclass VPseudoVMRG_FM {
   foreach f = FPList in {
     foreach m = f.MxList in {
       defvar mx = m.MX;
-      defvar WriteVFMergeV_MX = !cast<SchedWrite>("WriteVFMergeV_" # mx);
-      defvar ReadVFMergeV_MX = !cast<SchedRead>("ReadVFMergeV_" # mx);
-      defvar ReadVFMergeF_MX = !cast<SchedRead>("ReadVFMergeF_" # mx);
-
       def "_V" # f.FX # "M_" # mx:
         VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
                                  m.vrclass, f.fprclass, m, CarryIn=1, Constraint="">,
-        Sched<[WriteVFMergeV_MX, ReadVFMergeV_MX, ReadVFMergeF_MX, ReadVMask]>;
+        SchedBinary<"WriteVFMergeV", "ReadVFMergeV", "ReadVFMergeF", mx, forceMasked=1>;
     }
   }
 }
 
 multiclass VPseudoBinaryV_IM<LMULInfo m, bit CarryOut = 0, bit CarryIn = 1,
                              string Constraint = ""> {
   def "_VI" # !if(CarryIn, "M", "") # "_" # m.MX :
     VPseudoBinaryCarryIn<!if(CarryOut, VR,
                          !if(!and(CarryIn, !not(CarryOut)),
                              GetVRegNoV0<m.vrclass>.R, m.vrclass)),
                          m.vrclass, simm5, m, CarryIn, Constraint>;
 }
 
 multiclass VPseudoTiedBinaryV_IM<LMULInfo m> {
   def "_VIM" # "_" # m.MX:
     VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
                              m.vrclass, simm5, m, 1, "">;
 }
 
 multiclass VPseudoUnaryVMV_V_X_I {
   foreach m = MxList in {
     let VLMul = m.value in {
       defvar mx = m.MX;
-      defvar WriteVIMovV_MX = !cast<SchedWrite>("WriteVIMovV_" # mx);
-      defvar WriteVIMovX_MX = !cast<SchedWrite>("WriteVIMovX_" # mx);
-      defvar WriteVIMovI_MX = !cast<SchedWrite>("WriteVIMovI_" # mx);
-      defvar ReadVIMovV_MX = !cast<SchedRead>("ReadVIMovV_" # mx);
-      defvar ReadVIMovX_MX = !cast<SchedRead>("ReadVIMovX_" # mx);
-
       let VLMul = m.value in {
         def "_V_" # mx : VPseudoUnaryNoMask<m.vrclass, m.vrclass>,
-                           Sched<[WriteVIMovV_MX, ReadVIMovV_MX]>;
+                         SchedUnary<"WriteVIMovV", "ReadVIMovV", mx>;
         def "_X_" # mx : VPseudoUnaryNoMask<m.vrclass, GPR>,
-                           Sched<[WriteVIMovX_MX, ReadVIMovX_MX]>;
+                         SchedUnary<"WriteVIMovX", "ReadVIMovX", mx>;
         def "_I_" # mx : VPseudoUnaryNoMask<m.vrclass, simm5>,
-                           Sched<[WriteVIMovI_MX]>;
+                         SchedNullary<"WriteVIMovI", mx>;
       }
     }
   }
 }
 
 multiclass VPseudoVMV_F {
   foreach f = FPList in {
     foreach m = f.MxList in {
       defvar mx = m.MX;
-      defvar WriteVFMovV_MX = !cast<SchedWrite>("WriteVFMovV_" # mx);
-      defvar ReadVFMovF_MX = !cast<SchedRead>("ReadVFMovF_" # mx);
-
       let VLMul = m.value in {
         def "_" # f.FX # "_" # mx :
           VPseudoUnaryNoMask<m.vrclass, f.fprclass>,
-          Sched<[WriteVFMovV_MX, ReadVFMovF_MX]>;
+          SchedUnary<"WriteVFMovV", "ReadVFMovF", mx>;
       }
     }
   }
 }
 
 multiclass VPseudoVCLS_V {
   foreach m = MxListF in {
     defvar mx = m.MX;
-    defvar WriteVFClassV_MX = !cast<SchedWrite>("WriteVFClassV_" # mx);
-    defvar ReadVFClassV_MX = !cast<SchedRead>("ReadVFClassV_" # mx);
-
     let VLMul = m.value in {
       def "_V_" # mx : VPseudoUnaryNoMask<m.vrclass, m.vrclass>,
-                       Sched<[WriteVFClassV_MX, ReadVFClassV_MX, ReadVMask]>;
+                       SchedUnary<"WriteVFClassV", "ReadVFClassV", mx>;
       def "_V_" # mx # "_MASK" : VPseudoUnaryMask<m.vrclass, m.vrclass>,
                                  RISCVMaskedPseudo<MaskIdx=2>,
-                                 Sched<[WriteVFClassV_MX, ReadVFClassV_MX, ReadVMask]>;
+                                 SchedUnary<"WriteVFClassV", "ReadVFClassV", mx>;
     }
   }
 }
 
 multiclass VPseudoVSQR_V_RM {
   foreach m = MxListF in {
     defvar mx = m.MX;
     defvar sews = SchedSEWSet<m.MX, isF=1>.val;
 
     let VLMul = m.value in
       foreach e = sews in {
         defvar suffix = "_" # mx # "_E" # e;
-        defvar WriteVFSqrtV_MX_E = !cast<SchedWrite>("WriteVFSqrtV" # suffix);
-        defvar ReadVFSqrtV_MX_E = !cast<SchedRead>("ReadVFSqrtV" # suffix);
-
         let SEW = e in {
           def "_V" # suffix : VPseudoUnaryNoMaskRoundingMode<m.vrclass, m.vrclass>,
-                              Sched<[WriteVFSqrtV_MX_E, ReadVFSqrtV_MX_E,
-                                     ReadVMask]>;
+                              SchedUnary<"WriteVFSqrtV", "ReadVFSqrtV", mx, e>;
           def "_V" # suffix # "_MASK" : VPseudoUnaryMaskRoundingMode<m.vrclass, m.vrclass>,
                                         RISCVMaskedPseudo<MaskIdx=2>,
-                                        Sched<[WriteVFSqrtV_MX_E, ReadVFSqrtV_MX_E,
-                                               ReadVMask]>;
+                                        SchedUnary<"WriteVFSqrtV", "ReadVFSqrtV", mx, e>;
         }
       }
   }
 }
 
 multiclass VPseudoVRCP_V {
   foreach m = MxListF in {
     defvar mx = m.MX;
-    defvar WriteVFRecpV_MX = !cast<SchedWrite>("WriteVFRecpV_" # mx);
-    defvar ReadVFRecpV_MX = !cast<SchedRead>("ReadVFRecpV_" # mx);
-
     let VLMul = m.value in {
       def "_V_" # mx : VPseudoUnaryNoMask<m.vrclass, m.vrclass>,
-                         Sched<[WriteVFRecpV_MX, ReadVFRecpV_MX, ReadVMask]>;
+                         SchedUnary<"WriteVFRecpV", "ReadVFRecpV", mx>;
       def "_V_" # mx # "_MASK" : VPseudoUnaryMask<m.vrclass, m.vrclass>,
                                  RISCVMaskedPseudo<MaskIdx=2>,
-                                 Sched<[WriteVFRecpV_MX, ReadVFRecpV_MX, ReadVMask]>;
+                                 SchedUnary<"WriteVFRecpV", "ReadVFRecpV", mx>;
     }
   }
 }
 
 multiclass VPseudoVRCP_V_RM {
   foreach m = MxListF in {
     defvar mx = m.MX;
-    defvar WriteVFRecpV_MX = !cast<SchedWrite>("WriteVFRecpV_" # mx);
-    defvar ReadVFRecpV_MX = !cast<SchedRead>("ReadVFRecpV_" # mx);
-
     let VLMul = m.value in {
       def "_V_" # mx : VPseudoUnaryNoMaskRoundingMode<m.vrclass, m.vrclass>,
-                         Sched<[WriteVFRecpV_MX, ReadVFRecpV_MX, ReadVMask]>;
+                         SchedUnary<"WriteVFRecpV", "ReadVFRecpV", mx>;
       def "_V_" # mx # "_MASK" : VPseudoUnaryMaskRoundingMode<m.vrclass, m.vrclass>,
                                  RISCVMaskedPseudo<MaskIdx=2>,
-                                 Sched<[WriteVFRecpV_MX, ReadVFRecpV_MX, ReadVMask]>;
+                                 SchedUnary<"WriteVFRecpV", "ReadVFRecpV", mx>;
     }
   }
 }
 
 multiclass PseudoVEXT_VF2 {
   defvar constraints = "@earlyclobber $rd";
   foreach m = MxListVF2 in {
     defvar mx = m.MX;
-    defvar WriteVExtV_MX = !cast<SchedWrite>("WriteVExtV_" # mx);
-    defvar ReadVExtV_MX = !cast<SchedRead>("ReadVExtV_" # mx);
-
     let VLMul = m.value in {
       def "_" # mx : VPseudoUnaryNoMask<m.vrclass, m.f2vrclass, constraints>,
-                     Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
+                     SchedUnary<"WriteVExtV", "ReadVExtV", mx>;
       def "_" # mx # "_MASK" :
         VPseudoUnaryMask<m.vrclass, m.f2vrclass, constraints>,
         RISCVMaskedPseudo<MaskIdx=2>,
-        Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
+        SchedUnary<"WriteVExtV", "ReadVExtV", mx>;
     }
   }
 }
 
 multiclass PseudoVEXT_VF4 {
   defvar constraints = "@earlyclobber $rd";
   foreach m = MxListVF4 in {
     defvar mx = m.MX;
-    defvar WriteVExtV_MX = !cast<SchedWrite>("WriteVExtV_" # mx);
-    defvar ReadVExtV_MX = !cast<SchedRead>("ReadVExtV_" # mx);
-
     let VLMul = m.value in {
       def "_" # mx : VPseudoUnaryNoMask<m.vrclass, m.f4vrclass, constraints>,
-                     Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
+                     SchedUnary<"WriteVExtV", "ReadVExtV", mx>;
       def "_" # mx # "_MASK" :
         VPseudoUnaryMask<m.vrclass, m.f4vrclass, constraints>,
         RISCVMaskedPseudo<MaskIdx=2>,
-        Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
+        SchedUnary<"WriteVExtV", "ReadVExtV", mx>;
     }
   }
 }
 
 multiclass PseudoVEXT_VF8 {
   defvar constraints = "@earlyclobber $rd";
   foreach m = MxListVF8 in {
     defvar mx = m.MX;
-    defvar WriteVExtV_MX = !cast<SchedWrite>("WriteVExtV_" # mx);
-    defvar ReadVExtV_MX = !cast<SchedRead>("ReadVExtV_" # mx);
-
     let VLMul = m.value in {
       def "_" # mx : VPseudoUnaryNoMask<m.vrclass, m.f8vrclass, constraints>,
-                     Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
+                     SchedUnary<"WriteVExtV", "ReadVExtV", mx>;
       def "_" # mx # "_MASK" :
         VPseudoUnaryMask<m.vrclass, m.f8vrclass, constraints>,
         RISCVMaskedPseudo<MaskIdx=2>,
-        Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
+        SchedUnary<"WriteVExtV", "ReadVExtV", mx>;
     }
   }
 }
 
 // The destination EEW is 1 since "For the purposes of register group overlap
 // constraints, mask elements have EEW=1."
 // The source EEW is 8, 16, 32, or 64.
 // When the destination EEW is different from source EEW, we need to use

 multiclass VPseudoBinaryM_VI<LMULInfo m> {
   defm _VI : VPseudoBinaryM<VR, m.vrclass, simm5, m,
                             !if(!ge(m.octuple, 16), "@earlyclobber $rd", "")>;
 }
 
 multiclass VPseudoVGTR_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
   foreach m = MxList in {
     defvar mx = m.MX;
-    defvar WriteVRGatherVX_MX = !cast<SchedWrite>("WriteVRGatherVX_" # mx);
-    defvar WriteVRGatherVI_MX = !cast<SchedWrite>("WriteVRGatherVI_" # mx);
-    defvar ReadVRGatherVX_data_MX = !cast<SchedRead>("ReadVRGatherVX_data_" # mx);
-    defvar ReadVRGatherVX_index_MX = !cast<SchedRead>("ReadVRGatherVX_index_" # mx);
-    defvar ReadVRGatherVI_data_MX = !cast<SchedRead>("ReadVRGatherVI_data_" # mx);
-
     defm "" : VPseudoBinaryV_VX<m, Constraint>,
-              Sched<[WriteVRGatherVX_MX, ReadVRGatherVX_data_MX,
-                     ReadVRGatherVX_index_MX, ReadVMask]>;
+              SchedBinary<"WriteVRGatherVX", "ReadVRGatherVX_data",
+                          "ReadVRGatherVX_index", mx>;
     defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
-              Sched<[WriteVRGatherVI_MX, ReadVRGatherVI_data_MX, ReadVMask]>;
+              SchedUnary<"WriteVRGatherVI", "ReadVRGatherVI_data", mx>;
 
     defvar sews = SchedSEWSet<mx>.val;
     foreach e = sews in {
-      defvar WriteVRGatherVV_MX_E = !cast<SchedWrite>("WriteVRGatherVV_" # mx # "_E" # e);
-      defvar ReadVRGatherVV_data_MX_E = !cast<SchedRead>("ReadVRGatherVV_data_" # mx # "_E" # e);
-      defvar ReadVRGatherVV_index_MX_E = !cast<SchedRead>("ReadVRGatherVV_index_" # mx # "_E" # e);
       defm "" : VPseudoBinaryV_VV<m, Constraint, e>,
-                Sched<[WriteVRGatherVV_MX_E, ReadVRGatherVV_data_MX_E,
-                       ReadVRGatherVV_index_MX_E, ReadVMask]>;
+                SchedBinary<"WriteVRGatherVV", "ReadVRGatherVV_data",
+                              "ReadVRGatherVV_index", mx, e>;
     }
   }
 }
 
 multiclass VPseudoVSALU_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
   foreach m = MxList in {
     defvar mx = m.MX;
-    defvar WriteVSALUV_MX = !cast<SchedWrite>("WriteVSALUV_" # mx);
-    defvar WriteVSALUX_MX = !cast<SchedWrite>("WriteVSALUX_" # mx);
-    defvar WriteVSALUI_MX = !cast<SchedWrite>("WriteVSALUI_" # mx);
-    defvar ReadVSALUV_MX = !cast<SchedRead>("ReadVSALUV_" # mx);
-    defvar ReadVSALUX_MX = !cast<SchedRead>("ReadVSALUX_" # mx);
-
     defm "" : VPseudoBinaryV_VV<m, Constraint>,
-              Sched<[WriteVSALUV_MX, ReadVSALUV_MX, ReadVSALUV_MX, ReadVMask]>;
+              SchedBinary<"WriteVSALUV", "ReadVSALUV", "ReadVSALUX", mx>;
     defm "" : VPseudoBinaryV_VX<m, Constraint>,
-              Sched<[WriteVSALUX_MX, ReadVSALUV_MX, ReadVSALUX_MX, ReadVMask]>;
+              SchedBinary<"WriteVSALUX", "ReadVSALUV", "ReadVSALUX", mx>;
     defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
-              Sched<[WriteVSALUI_MX, ReadVSALUV_MX, ReadVMask]>;
+              SchedUnary<"WriteVSALUI", "ReadVSALUV", mx>;
   }
 }
 
 
 multiclass VPseudoVSHT_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
   foreach m = MxList in {
     defvar mx = m.MX;
-    defvar WriteVShiftV_MX = !cast<SchedWrite>("WriteVShiftV_" # mx);
-    defvar WriteVShiftX_MX = !cast<SchedWrite>("WriteVShiftX_" # mx);
-    defvar WriteVShiftI_MX = !cast<SchedWrite>("WriteVShiftI_" # mx);
-    defvar ReadVShiftV_MX = !cast<SchedRead>("ReadVShiftV_" # mx);
-    defvar ReadVShiftX_MX = !cast<SchedRead>("ReadVShiftX_" # mx);
-
     defm "" : VPseudoBinaryV_VV<m, Constraint>,
-              Sched<[WriteVShiftV_MX, ReadVShiftV_MX, ReadVShiftV_MX, ReadVMask]>;
+              SchedBinary<"WriteVShiftV", "ReadVShiftV", "ReadVShiftV", mx>;
     defm "" : VPseudoBinaryV_VX<m, Constraint>,
-              Sched<[WriteVShiftX_MX, ReadVShiftV_MX, ReadVShiftX_MX, ReadVMask]>;
+              SchedBinary<"WriteVShiftX", "ReadVShiftV", "ReadVShiftX", mx>;
     defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
-              Sched<[WriteVShiftI_MX, ReadVShiftV_MX, ReadVMask]>;
+              SchedUnary<"WriteVShiftI", "ReadVShiftV", mx>;
   }
 }
 
 multiclass VPseudoVSSHT_VV_VX_VI_RM<Operand ImmType = simm5, string Constraint = ""> {
   foreach m = MxList in {
     defvar mx = m.MX;
-    defvar WriteVSShiftV_MX = !cast<SchedWrite>("WriteVSShiftV_" # mx);
-    defvar WriteVSShiftX_MX = !cast<SchedWrite>("WriteVSShiftX_" # mx);
-    defvar WriteVSShiftI_MX = !cast<SchedWrite>("WriteVSShiftI_" # mx);
-    defvar ReadVSShiftV_MX = !cast<SchedRead>("ReadVSShiftV_" # mx);
-    defvar ReadVSShiftX_MX = !cast<SchedRead>("ReadVSShiftX_" # mx);
-
     defm "" : VPseudoBinaryV_VV_RM<m, Constraint>,
-              Sched<[WriteVSShiftV_MX, ReadVSShiftV_MX, ReadVSShiftV_MX, ReadVMask]>;
+              SchedBinary<"WriteVSShiftV", "ReadVSShiftV", "ReadVSShiftV", mx>;
     defm "" : VPseudoBinaryV_VX_RM<m, Constraint>,
-              Sched<[WriteVSShiftX_MX, ReadVSShiftV_MX, ReadVSShiftX_MX, ReadVMask]>;
+              SchedBinary<"WriteVSShiftX", "ReadVSShiftV", "ReadVSShiftX", mx>;
     defm "" : VPseudoBinaryV_VI_RM<ImmType, m, Constraint>,
-              Sched<[WriteVSShiftI_MX, ReadVSShiftV_MX, ReadVMask]>;
+              SchedUnary<"WriteVSShiftI", "ReadVSShiftV", mx>;
   }
 }
 
 multiclass VPseudoVALU_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
   foreach m = MxList in {
     defvar mx = m.MX;
-    defvar WriteVIALUV_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
-    defvar WriteVIALUX_MX = !cast<SchedWrite>("WriteVIALUX_" # mx);
-    defvar WriteVIALUI_MX = !cast<SchedWrite>("WriteVIALUI_" # mx);
-    defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
-    defvar ReadVIALUX_MX = !cast<SchedRead>("ReadVIALUX_" # mx);
-
     defm "" : VPseudoBinaryV_VV<m, Constraint>,
-            Sched<[WriteVIALUV_MX, ReadVIALUV_MX, ReadVIALUV_MX, ReadVMask]>;
+            SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", mx>;
     defm "" : VPseudoBinaryV_VX<m, Constraint>,
-            Sched<[WriteVIALUX_MX, ReadVIALUV_MX, ReadVIALUX_MX, ReadVMask]>;
+            SchedBinary<"WriteVIALUX", "ReadVIALUV", "ReadVIALUX", mx>;
     defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
-            Sched<[WriteVIALUI_MX, ReadVIALUV_MX, ReadVMask]>;
+            SchedUnary<"WriteVIALUI", "ReadVIALUV", mx>;
   }
 }
 
 multiclass VPseudoVSALU_VV_VX {
   foreach m = MxList in {
     defvar mx = m.MX;
-    defvar WriteVSALUV_MX = !cast<SchedWrite>("WriteVSALUV_" # mx);
-    defvar WriteVSALUX_MX = !cast<SchedWrite>("WriteVSALUX_" # mx);
-    defvar ReadVSALUV_MX = !cast<SchedRead>("ReadVSALUV_" # mx);
-    defvar ReadVSALUX_MX = !cast<SchedRead>("ReadVSALUX_" # mx);
-
     defm "" : VPseudoBinaryV_VV<m>,
-              Sched<[WriteVSALUV_MX, ReadVSALUV_MX, ReadVSALUV_MX, ReadVMask]>;
+              SchedBinary<"WriteVSALUV", "ReadVSALUV", "ReadVSALUV", mx>;
     defm "" : VPseudoBinaryV_VX<m>,
-              Sched<[WriteVSALUX_MX, ReadVSALUV_MX, ReadVSALUX_MX, ReadVMask]>;
+              SchedBinary<"WriteVSALUX", "ReadVSALUV", "ReadVSALUX", mx>;
   }
 }
 
 multiclass VPseudoVSMUL_VV_VX_RM {
   foreach m = MxList in {
     defvar mx = m.MX;
-    defvar WriteVSMulV_MX = !cast<SchedWrite>("WriteVSMulV_" # mx);
-    defvar WriteVSMulX_MX = !cast<SchedWrite>("WriteVSMulX_" # mx);
-    defvar ReadVSMulV_MX = !cast<SchedRead>("ReadVSMulV_" # mx);
-    defvar ReadVSMulX_MX = !cast<SchedRead>("ReadVSMulX_" # mx);
-
     defm "" : VPseudoBinaryV_VV_RM<m>,
-              Sched<[WriteVSMulV_MX, ReadVSMulV_MX, ReadVSMulV_MX, ReadVMask]>;
+              SchedBinary<"WriteVSMulV", "ReadVSMulV", "ReadVSMulV", mx>;
     defm "" : VPseudoBinaryV_VX_RM<m>,
-              Sched<[WriteVSMulX_MX, ReadVSMulV_MX, ReadVSMulX_MX, ReadVMask]>;
+              SchedBinary<"WriteVSMulX", "ReadVSMulV", "ReadVSMulX", mx>;
   }
 }
 
 multiclass VPseudoVAALU_VV_VX_RM {
   foreach m = MxList in {
     defvar mx = m.MX;
-    defvar WriteVAALUV_MX = !cast<SchedWrite>("WriteVAALUV_" # mx);
-    defvar WriteVAALUX_MX = !cast<SchedWrite>("WriteVAALUX_" # mx);
-    defvar ReadVAALUV_MX = !cast<SchedRead>("ReadVAALUV_" # mx);
-    defvar ReadVAALUX_MX = !cast<SchedRead>("ReadVAALUX_" # mx);
-
     defm "" : VPseudoBinaryV_VV_RM<m>,
-              Sched<[WriteVAALUV_MX, ReadVAALUV_MX, ReadVAALUV_MX, ReadVMask]>;
+              SchedBinary<"WriteVAALUV", "ReadVAALUV", "ReadVAALUV", mx>;
     defm "" : VPseudoBinaryV_VX_RM<m>,
-              Sched<[WriteVAALUX_MX, ReadVAALUV_MX, ReadVAALUX_MX, ReadVMask]>;
+              SchedBinary<"WriteVAALUX", "ReadVAALUV", "ReadVAALUX", mx>;
   }
 }
 
 multiclass VPseudoVMINMAX_VV_VX {
   foreach m = MxList in {
     defvar mx = m.MX;
-    defvar WriteVIMinMaxV_MX = !cast<SchedWrite>("WriteVIMinMaxV_" # mx);
-    defvar WriteVIMinMaxX_MX = !cast<SchedWrite>("WriteVIMinMaxX_" # mx);
-    defvar ReadVIMinMaxV_MX = !cast<SchedRead>("ReadVIMinMaxV_" # mx);
-    defvar ReadVIMinMaxX_MX = !cast<SchedRead>("ReadVIMinMaxX_" # mx);
-
     defm "" : VPseudoBinaryV_VV<m>,
-              Sched<[WriteVIMinMaxV_MX, ReadVIMinMaxV_MX, ReadVIMinMaxV_MX, ReadVMask]>;
+              SchedBinary<"WriteVIMinMaxV", "ReadVIMinMaxV", "ReadVIMinMaxV", mx>;
     defm "" : VPseudoBinaryV_VX<m>,
-              Sched<[WriteVIMinMaxX_MX, ReadVIMinMaxV_MX, ReadVIMinMaxX_MX, ReadVMask]>;
+              SchedBinary<"WriteVIMinMaxX", "ReadVIMinMaxV", "ReadVIMinMaxX", mx>;
   }
 }
 
 multiclass VPseudoVMUL_VV_VX {
   foreach m = MxList in {
     defvar mx = m.MX;
-    defvar WriteVIMulV_MX = !cast<SchedWrite>("WriteVIMulV_" # mx);
-    defvar WriteVIMulX_MX = !cast<SchedWrite>("WriteVIMulX_" # mx);
-    defvar ReadVIMulV_MX = !cast<SchedRead>("ReadVIMulV_" # mx);
-    defvar ReadVIMulX_MX = !cast<SchedRead>("ReadVIMulX_" # mx);
-
     defm "" : VPseudoBinaryV_VV<m>,
-              Sched<[WriteVIMulV_MX, ReadVIMulV_MX, ReadVIMulV_MX, ReadVMask]>;
+              SchedBinary<"WriteVIMulV", "ReadVIMulV", "ReadVIMulV", mx>;
     defm "" : VPseudoBinaryV_VX<m>,
-              Sched<[WriteVIMulX_MX, ReadVIMulV_MX, ReadVIMulX_MX, ReadVMask]>;
+              SchedBinary<"WriteVIMulX", "ReadVIMulV", "ReadVIMulX", mx>;
   }
 }
 
 multiclass VPseudoVDIV_VV_VX {
   foreach m = MxList in {
     defvar mx = m.MX;
     defvar sews = SchedSEWSet<mx>.val;
     foreach e = sews in {
-      defvar WriteVIDivV_MX_E = !cast<SchedWrite>("WriteVIDivV_" # mx # "_E" # e);
-      defvar WriteVIDivX_MX_E = !cast<SchedWrite>("WriteVIDivX_" # mx # "_E" # e);
-      defvar ReadVIDivV_MX_E = !cast<SchedRead>("ReadVIDivV_" # mx # "_E" # e);
-      defvar ReadVIDivX_MX_E = !cast<SchedRead>("ReadVIDivX_" # mx # "_E" # e);
-
       defm "" : VPseudoBinaryV_VV<m, "", e>,
-                Sched<[WriteVIDivV_MX_E, ReadVIDivV_MX_E, ReadVIDivV_MX_E, ReadVMask]>;
+                SchedBinary<"WriteVIDivV", "ReadVIDivV", "ReadVIDivV", mx, e>;
       defm "" : VPseudoBinaryV_VX<m, "", e>,
-                Sched<[WriteVIDivX_MX_E, ReadVIDivV_MX_E, ReadVIDivX_MX_E, ReadVMask]>;
+                SchedBinary<"WriteVIDivX", "ReadVIDivV", "ReadVIDivX", mx, e>;
     }
   }
 }
 
 multiclass VPseudoVFMUL_VV_VF_RM {
   foreach m = MxListF in {
-    defvar mx = m.MX;
-    defvar WriteVFMulV_MX = !cast<SchedWrite>("WriteVFMulV_" # mx);
-    defvar ReadVFMulV_MX = !cast<SchedRead>("ReadVFMulV_" # mx);
-
     defm "" : VPseudoBinaryFV_VV_RM<m>,
-              Sched<[WriteVFMulV_MX, ReadVFMulV_MX, ReadVFMulV_MX, ReadVMask]>;
+              SchedBinary<"WriteVFMulV", "ReadVFMulV", "ReadVFMulV", m.MX>;
   }
 
   foreach f = FPList in {
     foreach m = f.MxList in {
-      defvar mx = m.MX;
-      defvar WriteVFMulF_MX = !cast<SchedWrite>("WriteVFMulF_" # mx);
-      defvar ReadVFMulV_MX = !cast<SchedRead>("ReadVFMulV_" # mx);
-      defvar ReadVFMulF_MX = !cast<SchedRead>("ReadVFMulF_" # mx);
-
       defm "" : VPseudoBinaryV_VF_RM<m, f>,
-                Sched<[WriteVFMulF_MX, ReadVFMulV_MX, ReadVFMulF_MX, ReadVMask]>;
+                SchedBinary<"WriteVFMulF", "ReadVFMulV", "ReadVFMulF", m.MX>;
     }
   }
 }
 
 multiclass VPseudoVFDIV_VV_VF_RM {
   foreach m = MxListF in {
     defvar mx = m.MX;
     defvar sews = SchedSEWSet<mx, isF=1>.val;
     foreach e = sews in {
-      defvar WriteVFDivV_MX_E = !cast<SchedWrite>("WriteVFDivV_" # mx # "_E" # e);
-      defvar ReadVFDivV_MX_E = !cast<SchedRead>("ReadVFDivV_" # mx # "_E" # e);
-
       defm "" : VPseudoBinaryFV_VV_RM<m, "", e>,
-                Sched<[WriteVFDivV_MX_E, ReadVFDivV_MX_E, ReadVFDivV_MX_E, ReadVMask]>;
+                SchedBinary<"WriteVFDivV", "ReadVFDivV", "ReadVFDivV", mx, e>;
     }
   }
 
   foreach f = FPList in {
     foreach m = f.MxList in {
-      defvar mx = m.MX;
-      defvar WriteVFDivF_MX_E = !cast<SchedWrite>("WriteVFDivF_" # mx # "_E" # f.SEW);
-      defvar ReadVFDivV_MX_E = !cast<SchedRead>("ReadVFDivV_" # mx # "_E" # f.SEW);
-      defvar ReadVFDivF_MX_E = !cast<SchedRead>("ReadVFDivF_" # mx # "_E" # f.SEW);
-
       defm "" : VPseudoBinaryV_VF_RM<m, f, "", f.SEW>,
-                Sched<[WriteVFDivF_MX_E, ReadVFDivV_MX_E, ReadVFDivF_MX_E, ReadVMask]>;
+                SchedBinary<"WriteVFDivF", "ReadVFDivV", "ReadVFDivF", m.MX, f.SEW>;
     }
   }
 }
 
 multiclass VPseudoVFRDIV_VF_RM {
   foreach f = FPList in {
     foreach m = f.MxList in {
-      defvar mx = m.MX;
-      defvar WriteVFDivF_MX_E = !cast<SchedWrite>("WriteVFDivF_" # mx # "_E" # f.SEW);
-      defvar ReadVFDivV_MX_E = !cast<SchedRead>("ReadVFDivV_" # mx # "_E" # f.SEW);
-      defvar ReadVFDivF_MX_E = !cast<SchedRead>("ReadVFDivF_" # mx # "_E" # f.SEW);
-
       defm "" : VPseudoBinaryV_VF_RM<m, f, "", f.SEW>,
-                Sched<[WriteVFDivF_MX_E, ReadVFDivV_MX_E, ReadVFDivF_MX_E, ReadVMask]>;
+                SchedBinary<"WriteVFDivF", "ReadVFDivV", "ReadVFDivF", m.MX, f.SEW>;
     }
   }
 }
 
 multiclass VPseudoVALU_VV_VX {
  foreach m = MxList in {
-    defvar mx = m.MX;
-    defvar WriteVIALUV_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
-    defvar WriteVIALUX_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
-    defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
-    defvar ReadVIALUX_MX = !cast<SchedRead>("ReadVIALUX_" # mx);
-
     defm "" : VPseudoBinaryV_VV<m>,
-            Sched<[WriteVIALUV_MX, ReadVIALUV_MX, ReadVIALUV_MX, ReadVMask]>;
+            SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", m.MX>;
     defm "" : VPseudoBinaryV_VX<m>,
-            Sched<[WriteVIALUX_MX, ReadVIALUV_MX, ReadVIALUX_MX, ReadVMask]>;
+            SchedBinary<"WriteVIALUX", "ReadVIALUV", "ReadVIALUX", m.MX>;
   }
 }
 
 multiclass VPseudoVSGNJ_VV_VF {
   foreach m = MxListF in {
-    defvar mx = m.MX;
-    defvar WriteVFSgnjV_MX = !cast<SchedWrite>("WriteVFSgnjV_" # mx);
-    defvar ReadVFSgnjV_MX = !cast<SchedRead>("ReadVFSgnjV_" # mx);
-
     defm "" : VPseudoBinaryFV_VV<m>,
-              Sched<[WriteVFSgnjV_MX, ReadVFSgnjV_MX, ReadVFSgnjV_MX, ReadVMask]>;
+              SchedBinary<"WriteVFSgnjV", "ReadVFSgnjV", "ReadVFSgnjV", m.MX>;
   }
 
   foreach f = FPList in {
     foreach m = f.MxList in {
-      defvar mx = m.MX;
-      defvar WriteVFSgnjF_MX = !cast<SchedWrite>("WriteVFSgnjF_" # mx);
-      defvar ReadVFSgnjV_MX = !cast<SchedRead>("ReadVFSgnjV_" # mx);
-      defvar ReadVFSgnjF_MX = !cast<SchedRead>("ReadVFSgnjF_" # mx);
-
       defm "" : VPseudoBinaryV_VF<m, f>,
-                Sched<[WriteVFSgnjF_MX, ReadVFSgnjV_MX, ReadVFSgnjF_MX, ReadVMask]>;
+                SchedBinary<"WriteVFSgnjF", "ReadVFSgnjV", "ReadVFSgnjF", m.MX>;
     }
   }
 }
 
 multiclass VPseudoVMAX_VV_VF {
   foreach m = MxListF in {
-    defvar mx = m.MX;
-    defvar WriteVFMinMaxV_MX = !cast<SchedWrite>("WriteVFMinMaxV_" # mx);
-    defvar ReadVFMinMaxV_MX = !cast<SchedRead>("ReadVFMinMaxV_" # mx);
-
     defm "" : VPseudoBinaryFV_VV<m>,
-              Sched<[WriteVFMinMaxV_MX, ReadVFMinMaxV_MX, ReadVFMinMaxV_MX, ReadVMask]>;
+              SchedBinary<"WriteVFMinMaxV", "ReadVFMinMaxV", "ReadVFMinMaxV", m.MX>;
   }
 
   foreach f = FPList in {
     foreach m = f.MxList in {
-      defvar mx = m.MX;
-      defvar WriteVFMinMaxF_MX = !cast<SchedWrite>("WriteVFMinMaxF_" # mx);
-      defvar ReadVFMinMaxV_MX = !cast<SchedRead>("ReadVFMinMaxV_" # mx);
-      defvar ReadVFMinMaxF_MX = !cast<SchedRead>("ReadVFMinMaxF_" # mx);
-
       defm "" : VPseudoBinaryV_VF<m, f>,
-                Sched<[WriteVFMinMaxF_MX, ReadVFMinMaxV_MX, ReadVFMinMaxF_MX, ReadVMask]>;
+                SchedBinary<"WriteVFMinMaxF", "ReadVFMinMaxV", "ReadVFMinMaxF", m.MX>;
     }
   }
 }
 
 multiclass VPseudoVALU_VV_VF {
   foreach m = MxListF in {
-    defvar mx = m.MX;
-    defvar WriteVFALUV_MX = !cast<SchedWrite>("WriteVFALUV_" # mx);
-    defvar ReadVFALUV_MX = !cast<SchedRead>("ReadVFALUV_" # mx);
-
     defm "" : VPseudoBinaryFV_VV<m>,
-              Sched<[WriteVFALUV_MX, ReadVFALUV_MX, ReadVFALUV_MX, ReadVMask]>;
+              SchedBinary<"WriteVFALUV", "ReadVFALUV", "ReadVFALUV", m.MX>;
   }
 
   foreach f = FPList in {
     foreach m = f.MxList in {
-      defvar mx = m.MX;
-      defvar WriteVFALUF_MX = !cast<SchedWrite>("WriteVFALUF_" # mx);
-      defvar ReadVFALUV_MX = !cast<SchedRead>("ReadVFALUV_" # mx);
-      defvar ReadVFALUF_MX = !cast<SchedRead>("ReadVFALUF_" # mx);
       defm "" : VPseudoBinaryV_VF<m, f>,
-                Sched<[WriteVFALUF_MX, ReadVFALUV_MX, ReadVFALUF_MX, ReadVMask]>;
+                SchedBinary<"WriteVFALUF", "ReadVFALUV", "ReadVFALUF", m.MX>;
     }
   }
 }
 
 multiclass VPseudoVALU_VV_VF_RM {
   foreach m = MxListF in {
-    defvar mx = m.MX;
-    defvar WriteVFALUV_MX = !cast<SchedWrite>("WriteVFALUV_" # mx);
-    defvar ReadVFALUV_MX = !cast<SchedRead>("ReadVFALUV_" # mx);
-
     defm "" : VPseudoBinaryFV_VV_RM<m>,
-              Sched<[WriteVFALUV_MX, ReadVFALUV_MX, ReadVFALUV_MX, ReadVMask]>;
+              SchedBinary<"WriteVFALUV", "ReadVFALUV", "ReadVFALUV", m.MX>;
   }
 
   foreach f = FPList in {
     foreach m = f.MxList in {
-      defvar mx = m.MX;
-      defvar WriteVFALUF_MX = !cast<SchedWrite>("WriteVFALUF_" # mx);
-      defvar ReadVFALUV_MX = !cast<SchedRead>("ReadVFALUV_" # mx);
-      defvar ReadVFALUF_MX = !cast<SchedRead>("ReadVFALUF_" # mx);
       defm "" : VPseudoBinaryV_VF_RM<m, f>,
-                Sched<[WriteVFALUF_MX, ReadVFALUV_MX, ReadVFALUF_MX, ReadVMask]>;
+                SchedBinary<"WriteVFALUF", "ReadVFALUV", "ReadVFALUF", m.MX>;
     }
   }
 }
 
 multiclass VPseudoVALU_VF {
   foreach f = FPList in {
     foreach m = f.MxList in {
-      defvar mx = m.MX;
-      defvar WriteVFALUF_MX = !cast<SchedWrite>("WriteVFALUF_" # mx);
-      defvar ReadVFALUV_MX = !cast<SchedRead>("ReadVFALUV_" # mx);
-      defvar ReadVFALUF_MX = !cast<SchedRead>("ReadVFALUF_" # mx);
-
       defm "" : VPseudoBinaryV_VF<m, f>,
-                Sched<[WriteVFALUF_MX, ReadVFALUV_MX, ReadVFALUF_MX, ReadVMask]>;
+                SchedBinary<"WriteVFALUF", "ReadVFALUV", "ReadVFALUF", m.MX>;
     }
   }
 }
 
 multiclass VPseudoVALU_VF_RM {
   foreach f = FPList in {
     foreach m = f.MxList in {
-      defvar mx = m.MX;
-      defvar WriteVFALUF_MX = !cast<SchedWrite>("WriteVFALUF_" # mx);
-      defvar ReadVFALUV_MX = !cast<SchedRead>("ReadVFALUV_" # mx);
-      defvar ReadVFALUF_MX = !cast<SchedRead>("ReadVFALUF_" # mx);
-
       defm "" : VPseudoBinaryV_VF_RM<m, f>,
-                Sched<[WriteVFALUF_MX, ReadVFALUV_MX, ReadVFALUF_MX, ReadVMask]>;
+                SchedBinary<"WriteVFALUF", "ReadVFALUV", "ReadVFALUF", m.MX>;
     }
   }
 }
 
 multiclass VPseudoVALU_VX_VI<Operand ImmType = simm5> {
   foreach m = MxList in {
     defvar mx = m.MX;
-    defvar WriteVIALUX_MX = !cast<SchedWrite>("WriteVIALUX_" # mx);
-    defvar WriteVIALUI_MX = !cast<SchedWrite>("WriteVIALUI_" # mx);
-    defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
-    defvar ReadVIALUX_MX = !cast<SchedRead>("ReadVIALUX_" # mx);
-
     defm "" : VPseudoBinaryV_VX<m>,
-            Sched<[WriteVIALUX_MX, ReadVIALUV_MX, ReadVIALUX_MX, ReadVMask]>;
+              SchedBinary<"WriteVIALUX", "ReadVIALUV", "ReadVIALUX", mx>;
     defm "" : VPseudoBinaryV_VI<ImmType, m>,
-            Sched<[WriteVIALUI_MX, ReadVIALUV_MX, ReadVMask]>;
+              SchedUnary<"WriteVIALUI", "ReadVIALUV", mx>;
   }
 }
 
 multiclass VPseudoVWALU_VV_VX {
   foreach m = MxListW in {
     defvar mx = m.MX;
-    defvar WriteVIWALUV_MX = !cast<SchedWrite>("WriteVIWALUV_" # mx);
-    defvar WriteVIWALUX_MX = !cast<SchedWrite>("WriteVIWALUX_" # mx);
-    defvar ReadVIWALUV_MX = !cast<SchedRead>("ReadVIWALUV_" # mx);
-    defvar ReadVIWALUX_MX = !cast<SchedRead>("ReadVIWALUX_" # mx);
-
     defm "" : VPseudoBinaryW_VV<m>,
-            Sched<[WriteVIWALUV_MX, ReadVIWALUV_MX, ReadVIWALUV_MX, ReadVMask]>;
+              SchedBinary<"WriteVIWALUV", "ReadVIWALUV", "ReadVIWALUV", mx>;
     defm "" : VPseudoBinaryW_VX<m>,
-            Sched<[WriteVIWALUX_MX, ReadVIWALUV_MX, ReadVIWALUX_MX, ReadVMask]>;
+              SchedBinary<"WriteVIWALUX", "ReadVIWALUV", "ReadVIWALUX", mx>;
   }
 }
 
 multiclass VPseudoVWMUL_VV_VX {
   foreach m = MxListW in {
     defvar mx = m.MX;
-    defvar WriteVIWMulV_MX = !cast<SchedWrite>("WriteVIWMulV_" # mx);
-    defvar WriteVIWMulX_MX = !cast<SchedWrite>("WriteVIWMulX_" # mx);
-    defvar ReadVIWMulV_MX = !cast<SchedRead>("ReadVIWMulV_" # mx);
-    defvar ReadVIWMulX_MX = !cast<SchedRead>("ReadVIWMulX_" # mx);
-
     defm "" : VPseudoBinaryW_VV<m>,
-              Sched<[WriteVIWMulV_MX, ReadVIWMulV_MX, ReadVIWMulV_MX, ReadVMask]>;
+              SchedBinary<"WriteVIWMulV", "ReadVIWMulV", "ReadVIWMulV", mx>;
     defm "" : VPseudoBinaryW_VX<m>,
-              Sched<[WriteVIWMulX_MX, ReadVIWMulV_MX, ReadVIWMulX_MX, ReadVMask]>;
+              SchedBinary<"WriteVIWMulX", "ReadVIWMulV", "ReadVIWMulX", mx>;
   }
 }
 
 multiclass VPseudoVWMUL_VV_VF_RM {
   foreach m = MxListFW in {
-    defvar mx = m.MX;
-    defvar WriteVFWMulV_MX = !cast<SchedWrite>("WriteVFWMulV_" # mx);
-    defvar ReadVFWMulV_MX = !cast<SchedRead>("ReadVFWMulV_" # mx);
-
     defm "" : VPseudoBinaryW_VV_RM<m>,
-              Sched<[WriteVFWMulV_MX, ReadVFWMulV_MX, ReadVFWMulV_MX, ReadVMask]>;
+              SchedBinary<"WriteVFWMulV", "ReadVFWMulV", "ReadVFWMulV", m.MX>;
   }
 
   foreach f = FPListW in {
     foreach m = f.MxListFW in {
-      defvar mx = m.MX;
-      defvar WriteVFWMulF_MX = !cast<SchedWrite>("WriteVFWMulF_" # mx);
-      defvar ReadVFWMulV_MX = !cast<SchedRead>("ReadVFWMulV_" # mx);
-      defvar ReadVFWMulF_MX = !cast<SchedRead>("ReadVFWMulF_" # mx);
-
       defm "" : VPseudoBinaryW_VF_RM<m, f>,
-                Sched<[WriteVFWMulF_MX, ReadVFWMulV_MX, ReadVFWMulF_MX, ReadVMask]>;
+                SchedBinary<"WriteVFWMulF", "ReadVFWMulV", "ReadVFWMulF", m.MX>;
     }
   }
 }
 
 multiclass VPseudoVWALU_WV_WX {
   foreach m = MxListW in {
     defvar mx = m.MX;
-    defvar WriteVIWALUV_MX = !cast<SchedWrite>("WriteVIWALUV_" # mx);
-    defvar WriteVIWALUX_MX = !cast<SchedWrite>("WriteVIWALUX_" # mx);
-    defvar ReadVIWALUV_MX = !cast<SchedRead>("ReadVIWALUV_" # mx);
-    defvar ReadVIWALUX_MX = !cast<SchedRead>("ReadVIWALUX_" # mx);
-
     defm "" : VPseudoBinaryW_WV<m>,
-              Sched<[WriteVIWALUV_MX, ReadVIWALUV_MX, ReadVIWALUV_MX, ReadVMask]>;
+              SchedBinary<"WriteVIWALUV", "ReadVIWALUV", "ReadVIWALUV", mx>;
     defm "" : VPseudoBinaryW_WX<m>,
-              Sched<[WriteVIWALUX_MX, ReadVIWALUV_MX, ReadVIWALUX_MX, ReadVMask]>;
+              SchedBinary<"WriteVIWALUX", "ReadVIWALUV", "ReadVIWALUX", mx>;
   }
 }
 
 multiclass VPseudoVFWALU_VV_VF_RM {
   foreach m = MxListFW in {
-    defvar mx = m.MX;
-    defvar WriteVFWALUV_MX = !cast<SchedWrite>("WriteVFWALUV_" # mx);
-    defvar ReadVFWALUV_MX = !cast<SchedRead>("ReadVFWALUV_" # mx);
-
     defm "" : VPseudoBinaryW_VV_RM<m>,
-              Sched<[WriteVFWALUV_MX, ReadVFWALUV_MX, ReadVFWALUV_MX, ReadVMask]>;
+              SchedBinary<"WriteVFWALUV", "ReadVFWALUV", "ReadVFWALUV", m.MX>;
   }
 
   foreach f = FPListW in {
     foreach m = f.MxListFW in {
-      defvar mx = m.MX;
-      defvar WriteVFWALUF_MX = !cast<SchedWrite>("WriteVFWALUF_" # mx);
-      defvar ReadVFWALUV_MX = !cast<SchedRead>("ReadVFWALUV_" # mx);
-      defvar ReadVFWALUF_MX = !cast<SchedRead>("ReadVFWALUF_" # mx);
-
       defm "" : VPseudoBinaryW_VF_RM<m, f>,
-                Sched<[WriteVFWALUF_MX, ReadVFWALUV_MX, ReadVFWALUF_MX, ReadVMask]>;
+                SchedBinary<"WriteVFWALUF", "ReadVFWALUV", "ReadVFWALUF", m.MX>;
     }
   }
 }
 
 multiclass VPseudoVFWALU_WV_WF_RM {
   foreach m = MxListFW in {
-    defvar mx = m.MX;
-    defvar WriteVFWALUV_MX = !cast<SchedWrite>("WriteVFWALUV_" # mx);
-    defvar ReadVFWALUV_MX = !cast<SchedRead>("ReadVFWALUV_" # mx);
-
     defm "" : VPseudoBinaryW_WV_RM<m>,
-              Sched<[WriteVFWALUV_MX, ReadVFWALUV_MX, ReadVFWALUV_MX, ReadVMask]>;
+              SchedBinary<"WriteVFWALUV", "ReadVFWALUV", "ReadVFWALUV", m.MX>;
   }
   foreach f = FPListW in {
     foreach m = f.MxListFW in {
-      defvar mx = m.MX;
-      defvar WriteVFWALUF_MX = !cast<SchedWrite>("WriteVFWALUF_" # mx);
-      defvar ReadVFWALUV_MX = !cast<SchedRead>("ReadVFWALUV_" # mx);
-      defvar ReadVFWALUF_MX = !cast<SchedRead>("ReadVFWALUF_" # mx);
-
       defm "" : VPseudoBinaryW_WF_RM<m, f>,
-                Sched<[WriteVFWALUF_MX, ReadVFWALUV_MX, ReadVFWALUF_MX, ReadVMask]>;
+                SchedBinary<"WriteVFWALUF", "ReadVFWALUV", "ReadVFWALUF", m.MX>;
     }
   }
 }
 
 multiclass VPseudoVMRG_VM_XM_IM {
   foreach m = MxList in {
     defvar mx = m.MX;
-    defvar WriteVIMergeV_MX = !cast<SchedWrite>("WriteVIMergeV_" # mx);
-    defvar WriteVIMergeX_MX = !cast<SchedWrite>("WriteVIMergeX_" # mx);
-    defvar WriteVIMergeI_MX = !cast<SchedWrite>("WriteVIMergeI_" # mx);
-    defvar ReadVIMergeV_MX = !cast<SchedRead>("ReadVIMergeV_" # mx);
-    defvar ReadVIMergeX_MX = !cast<SchedRead>("ReadVIMergeX_" # mx);
-
     def "_VVM" # "_" # m.MX:
       VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
                                m.vrclass, m.vrclass, m, 1, "">,
-      Sched<[WriteVIMergeV_MX, ReadVIMergeV_MX, ReadVIMergeV_MX, ReadVMask]>;
+      SchedBinary<"WriteVIMergeV", "ReadVIMergeV", "ReadVIMergeV", mx>;
     def "_VXM" # "_" # m.MX:
       VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
                                m.vrclass, GPR, m, 1, "">,
-      Sched<[WriteVIMergeX_MX, ReadVIMergeV_MX, ReadVIMergeX_MX, ReadVMask]>;
+      SchedBinary<"WriteVIMergeX", "ReadVIMergeV", "ReadVIMergeX", mx>;
     def "_VIM" # "_" # m.MX:
       VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
                                m.vrclass, simm5, m, 1, "">,
-      Sched<[WriteVIMergeI_MX, ReadVIMergeV_MX, ReadVMask]>;
+      SchedUnary<"WriteVIMergeI", "ReadVIMergeV", mx>;
   }
 }
 
 multiclass VPseudoVCALU_VM_XM_IM {
   foreach m = MxList in {
     defvar mx = m.MX;
-    defvar WriteVICALUV_MX = !cast<SchedWrite>("WriteVICALUV_" # mx);
-    defvar WriteVICALUX_MX = !cast<SchedWrite>("WriteVICALUX_" # mx);
-    defvar WriteVICALUI_MX = !cast<SchedWrite>("WriteVICALUI_" # mx);
-    defvar ReadVICALUV_MX = !cast<SchedRead>("ReadVICALUV_" # mx);
-    defvar ReadVICALUX_MX = !cast<SchedRead>("ReadVICALUX_" # mx);
-
     defm "" : VPseudoTiedBinaryV_VM<m>,
-              Sched<[WriteVICALUV_MX, ReadVICALUV_MX, ReadVICALUV_MX, ReadVMask]>;
+              SchedBinary<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV", mx>;
     defm "" : VPseudoTiedBinaryV_XM<m>,
-              Sched<[WriteVICALUX_MX, ReadVICALUV_MX, ReadVICALUX_MX, ReadVMask]>;
+              SchedBinary<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX", mx>;
     defm "" : VPseudoTiedBinaryV_IM<m>,
-              Sched<[WriteVICALUI_MX, ReadVICALUV_MX, ReadVMask]>;
+              SchedUnary<"WriteVICALUI", "ReadVICALUV", mx>;
   }
 }
 
 multiclass VPseudoVCALU_VM_XM {
   foreach m = MxList in {
     defvar mx = m.MX;
-    defvar WriteVICALUV_MX = !cast<SchedWrite>("WriteVICALUV_" # mx);
-    defvar WriteVICALUX_MX = !cast<SchedWrite>("WriteVICALUX_" # mx);
-    defvar ReadVICALUV_MX = !cast<SchedRead>("ReadVICALUV_" # mx);
-    defvar ReadVICALUX_MX = !cast<SchedRead>("ReadVICALUX_" # mx);
-
     defm "" : VPseudoTiedBinaryV_VM<m>,
-              Sched<[WriteVICALUV_MX, ReadVICALUV_MX, ReadVICALUV_MX, ReadVMask]>;
+              SchedBinary<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV", mx>;
     defm "" : VPseudoTiedBinaryV_XM<m>,
-              Sched<[WriteVICALUX_MX, ReadVICALUV_MX, ReadVICALUX_MX, ReadVMask]>;
+              SchedBinary<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX", mx>;
   }
 }
 
 multiclass VPseudoVCALUM_VM_XM_IM<string Constraint> {
   foreach m = MxList in {
     defvar mx = m.MX;
-    defvar WriteVICALUV_MX = !cast<SchedWrite>("WriteVICALUV_" # mx);
-    defvar WriteVICALUX_MX = !cast<SchedWrite>("WriteVICALUX_" # mx);
-    defvar WriteVICALUI_MX = !cast<SchedWrite>("WriteVICALUI_" # mx);
-    defvar ReadVICALUV_MX = !cast<SchedRead>("ReadVICALUV_" # mx);
-    defvar ReadVICALUX_MX = !cast<SchedRead>("ReadVICALUX_" # mx);
-
     defm "" : VPseudoBinaryV_VM<m, CarryOut=1, CarryIn=1, Constraint=Constraint>,
-              Sched<[WriteVICALUV_MX, ReadVICALUV_MX, ReadVICALUV_MX, ReadVMask]>;
+              SchedBinary<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV", mx, forceMasked=1>;
     defm "" : VPseudoBinaryV_XM<m, CarryOut=1, CarryIn=1, Constraint=Constraint>,
-              Sched<[WriteVICALUX_MX, ReadVICALUV_MX, ReadVICALUX_MX, ReadVMask]>;
+              SchedBinary<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX", mx, forceMasked=1>;
     defm "" : VPseudoBinaryV_IM<m, CarryOut=1, CarryIn=1, Constraint=Constraint>,
-              Sched<[WriteVICALUI_MX, ReadVICALUV_MX, ReadVMask]>;
+              SchedUnary<"WriteVICALUI", "ReadVICALUV", mx, forceMasked=1>;
   }
 }
 
 multiclass VPseudoVCALUM_VM_XM<string Constraint> {
   foreach m = MxList in {
     defvar mx = m.MX;
-    defvar WriteVICALUV_MX = !cast<SchedWrite>("WriteVICALUV_" # mx);
-    defvar WriteVICALUX_MX = !cast<SchedWrite>("WriteVICALUX_" # mx);
-    defvar ReadVICALUV_MX = !cast<SchedRead>("ReadVICALUV_" # mx);
-    defvar ReadVICALUX_MX = !cast<SchedRead>("ReadVICALUX_" # mx);
-
     defm "" : VPseudoBinaryV_VM<m, CarryOut=1, CarryIn=1, Constraint=Constraint>,
-              Sched<[WriteVICALUV_MX, ReadVICALUV_MX, ReadVICALUV_MX, ReadVMask]>;
+              SchedBinary<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV", mx, forceMasked=1>;
     defm "" : VPseudoBinaryV_XM<m, CarryOut=1, CarryIn=1, Constraint=Constraint>,
-              Sched<[WriteVICALUX_MX, ReadVICALUV_MX, ReadVICALUX_MX, ReadVMask]>;
+              SchedBinary<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX", mx, forceMasked=1>;
   }
 }
 
 multiclass VPseudoVCALUM_V_X_I<string Constraint> {
   foreach m = MxList in {
     defvar mx = m.MX;
-    defvar WriteVICALUV_MX = !cast<SchedWrite>("WriteVICALUV_" # mx);
-    defvar WriteVICALUX_MX = !cast<SchedWrite>("WriteVICALUX_" # mx);
-    defvar WriteVICALUI_MX = !cast<SchedWrite>("WriteVICALUI_" # mx);
-    defvar ReadVICALUV_MX = !cast<SchedRead>("ReadVICALUV_" # mx);
-    defvar ReadVICALUX_MX = !cast<SchedRead>("ReadVICALUX_" # mx);
-
     defm "" : VPseudoBinaryV_VM<m, CarryOut=1, CarryIn=0, Constraint=Constraint>,
-              Sched<[WriteVICALUV_MX, ReadVICALUV_MX, ReadVICALUV_MX]>;
+              SchedBinary<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV", mx>;
     defm "" : VPseudoBinaryV_XM<m, CarryOut=1, CarryIn=0, Constraint=Constraint>,
-              Sched<[WriteVICALUX_MX, ReadVICALUV_MX, ReadVICALUX_MX]>;
+              SchedBinary<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX", mx>;
     defm "" : VPseudoBinaryV_IM<m, CarryOut=1, CarryIn=0, Constraint=Constraint>,
-              Sched<[WriteVICALUI_MX, ReadVICALUV_MX]>;
+              SchedUnary<"WriteVICALUI", "ReadVICALUV", mx>;
   }
 }
 
 multiclass VPseudoVCALUM_V_X<string Constraint> {
   foreach m = MxList in {
     defvar mx = m.MX;
-    defvar WriteVICALUV_MX = !cast<SchedWrite>("WriteVICALUV_" # mx);
-    defvar WriteVICALUX_MX = !cast<SchedWrite>("WriteVICALUX_" # mx);
-    defvar ReadVICALUV_MX = !cast<SchedRead>("ReadVICALUV_" # mx);
-    defvar ReadVICALUX_MX = !cast<SchedRead>("ReadVICALUX_" # mx);
-
     defm "" : VPseudoBinaryV_VM<m, CarryOut=1, CarryIn=0, Constraint=Constraint>,
-              Sched<[WriteVICALUV_MX, ReadVICALUV_MX, ReadVICALUV_MX]>;
+              SchedBinary<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV", mx>;
     defm "" : VPseudoBinaryV_XM<m, CarryOut=1, CarryIn=0, Constraint=Constraint>,
-              Sched<[WriteVICALUX_MX, ReadVICALUV_MX, ReadVICALUX_MX]>;
+              SchedBinary<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX", mx>;
   }
 }
 
 multiclass VPseudoVNCLP_WV_WX_WI_RM {
   foreach m = MxListW in {
     defvar mx = m.MX;
-    defvar WriteVNClipV_MX = !cast<SchedWrite>("WriteVNClipV_" # mx);
-    defvar WriteVNClipX_MX = !cast<SchedWrite>("WriteVNClipX_" # mx);
-    defvar WriteVNClipI_MX = !cast<SchedWrite>("WriteVNClipI_" # mx);
-    defvar ReadVNClipV_MX = !cast<SchedRead>("ReadVNClipV_" # mx);
-    defvar ReadVNClipX_MX = !cast<SchedRead>("ReadVNClipX_" # mx);
-
     defm "" : VPseudoBinaryV_WV_RM<m>,
-              Sched<[WriteVNClipV_MX, ReadVNClipV_MX, ReadVNClipV_MX, ReadVMask]>;
+              SchedBinary<"WriteVNClipV", "ReadVNClipV", "ReadVNClipV", mx>;
     defm "" : VPseudoBinaryV_WX_RM<m>,
-              Sched<[WriteVNClipX_MX, ReadVNClipV_MX, ReadVNClipX_MX, ReadVMask]>;
+              SchedBinary<"WriteVNClipX", "ReadVNClipV", "ReadVNClipX", mx>;
     defm "" : VPseudoBinaryV_WI_RM<m>,
-              Sched<[WriteVNClipI_MX, ReadVNClipV_MX, ReadVMask]>;
+              SchedUnary<"WriteVNClipI", "ReadVNClipV", mx>;
   }
 }
 
 multiclass VPseudoVNSHT_WV_WX_WI {
   foreach m = MxListW in {
     defvar mx = m.MX;
-    defvar WriteVNShiftV_MX = !cast<SchedWrite>("WriteVNShiftV_" # mx);
-    defvar WriteVNShiftX_MX = !cast<SchedWrite>("WriteVNShiftX_" # mx);
-    defvar WriteVNShiftI_MX = !cast<SchedWrite>("WriteVNShiftI_" # mx);
-    defvar ReadVNShiftV_MX = !cast<SchedRead>("ReadVNShiftV_" # mx);
-    defvar ReadVNShiftX_MX = !cast<SchedRead>("ReadVNShiftX_" # mx);
-
     defm "" : VPseudoBinaryV_WV<m>,
-              Sched<[WriteVNShiftV_MX, ReadVNShiftV_MX, ReadVNShiftV_MX, ReadVMask]>;
+              SchedBinary<"WriteVNShiftV", "ReadVNShiftV", "ReadVNShiftV", mx>;
     defm "" : VPseudoBinaryV_WX<m>,
-              Sched<[WriteVNShiftX_MX, ReadVNShiftV_MX, ReadVNShiftX_MX, ReadVMask]>;
+              SchedBinary<"WriteVNShiftX", "ReadVNShiftV", "ReadVNShiftX", mx>;
     defm "" : VPseudoBinaryV_WI<m>,
-              Sched<[WriteVNShiftI_MX, ReadVNShiftV_MX, ReadVMask]>;
+              SchedUnary<"WriteVNShiftI", "ReadVNShiftV", mx>;
   }
 }
 
 multiclass VPseudoTernaryWithTailPolicy<VReg RetClass,
                                           RegisterClass Op1Class,
                                           DAGOperand Op2Class,
                                           LMULInfo MInfo,
                                           int sew,

 
 multiclass VPseudoVSLDV_VI<Operand ImmType = simm5, LMULInfo m, string Constraint = ""> {
   defm _VI : VPseudoVSLDVWithPolicy<m.vrclass, m.vrclass, ImmType, m, Constraint>;
 }
 
 multiclass VPseudoVMAC_VV_VX_AAXA<string Constraint = ""> {
   foreach m = MxList in {
     defvar mx = m.MX;
-    defvar WriteVIMulAddV_MX = !cast<SchedWrite>("WriteVIMulAddV_" # mx);
-    defvar WriteVIMulAddX_MX = !cast<SchedWrite>("WriteVIMulAddX_" # mx);
-    defvar ReadVIMulAddV_MX = !cast<SchedRead>("ReadVIMulAddV_" # mx);
-    defvar ReadVIMulAddX_MX = !cast<SchedRead>("ReadVIMulAddX_" # mx);
-
     defm "" : VPseudoTernaryV_VV_AAXA<m, Constraint>,
-              Sched<[WriteVIMulAddV_MX, ReadVIMulAddV_MX, ReadVIMulAddV_MX,
-                     ReadVIMulAddV_MX, ReadVMask]>;
+              SchedTernary<"WriteVIMulAddV", "ReadVIMulAddV", "ReadVIMulAddV",
+                           "ReadVIMulAddV", mx>;
     defm "" : VPseudoTernaryV_VX_AAXA<m, Constraint>,
-              Sched<[WriteVIMulAddX_MX, ReadVIMulAddV_MX, ReadVIMulAddV_MX,
-                     ReadVIMulAddX_MX, ReadVMask]>;
+              SchedTernary<"WriteVIMulAddX", "ReadVIMulAddV", "ReadVIMulAddV",
+                           "ReadVIMulAddX", mx>;
   }
 }
 
 multiclass VPseudoVMAC_VV_VF_AAXA<string Constraint = ""> {
   foreach m = MxListF in {
-    defvar mx = m.MX;
-    defvar WriteVFMulAddV_MX = !cast<SchedWrite>("WriteVFMulAddV_" # mx);
-    defvar ReadVFMulAddV_MX = !cast<SchedRead>("ReadVFMulAddV_" # mx);
-
     defm "" : VPseudoTernaryV_VV_AAXA<m, Constraint>,
-              Sched<[WriteVFMulAddV_MX, ReadVFMulAddV_MX, ReadVFMulAddV_MX, ReadVFMulAddV_MX, ReadVMask]>;
+              SchedTernary<"WriteVFMulAddV", "ReadVFMulAddV", "ReadVFMulAddV",
+                           "ReadVFMulAddV", m.MX>;
   }
 
   foreach f = FPList in {
     foreach m = f.MxList in {
-      defvar mx = m.MX;
-      defvar WriteVFMulAddF_MX = !cast<SchedWrite>("WriteVFMulAddF_" # mx);
-      defvar ReadVFMulAddV_MX = !cast<SchedRead>("ReadVFMulAddV_" # mx);
-      defvar ReadVFMulAddF_MX = !cast<SchedRead>("ReadVFMulAddF_" # mx);
-
       defm "" : VPseudoTernaryV_VF_AAXA<m, f, Constraint>,
-                Sched<[WriteVFMulAddF_MX, ReadVFMulAddV_MX, ReadVFMulAddV_MX, ReadVFMulAddF_MX, ReadVMask]>;
+                SchedTernary<"WriteVFMulAddF", "ReadVFMulAddV", "ReadVFMulAddV",
+                             "ReadVFMulAddF", m.MX>;
     }
   }
 }
 
 multiclass VPseudoVMAC_VV_VF_AAXA_RM<string Constraint = ""> {
   foreach m = MxListF in {
-    defvar mx = m.MX;
-    defvar WriteVFMulAddV_MX = !cast<SchedWrite>("WriteVFMulAddV_" # mx);
-    defvar ReadVFMulAddV_MX = !cast<SchedRead>("ReadVFMulAddV_" # mx);
-
     defm "" : VPseudoTernaryV_VV_AAXA_RM<m, Constraint>,
-              Sched<[WriteVFMulAddV_MX, ReadVFMulAddV_MX, ReadVFMulAddV_MX, ReadVFMulAddV_MX, ReadVMask]>;
+              SchedTernary<"WriteVFMulAddV", "ReadVFMulAddV", "ReadVFMulAddV",
+                           "ReadVFMulAddV", m.MX>;
   }
 
   foreach f = FPList in {
     foreach m = f.MxList in {
-      defvar mx = m.MX;
-      defvar WriteVFMulAddF_MX = !cast<SchedWrite>("WriteVFMulAddF_" # mx);
-      defvar ReadVFMulAddV_MX = !cast<SchedRead>("ReadVFMulAddV_" # mx);
-      defvar ReadVFMulAddF_MX = !cast<SchedRead>("ReadVFMulAddF_" # mx);
-
       defm "" : VPseudoTernaryV_VF_AAXA_RM<m, f, Constraint>,
-                Sched<[WriteVFMulAddF_MX, ReadVFMulAddV_MX, ReadVFMulAddV_MX, ReadVFMulAddF_MX, ReadVMask]>;
+                SchedTernary<"WriteVFMulAddF", "ReadVFMulAddV", "ReadVFMulAddV",
+                             "ReadVFMulAddF", m.MX>;
     }
   }
 }
 
 multiclass VPseudoVSLD_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
   foreach m = MxList in {
     defvar mx = m.MX;
-    defvar WriteVISlideX_MX = !cast<SchedWrite>("WriteVISlideX_" # mx);
-    defvar WriteVISlideI_MX = !cast<SchedWrite>("WriteVISlideI_" # mx);
-    defvar ReadVISlideV_MX = !cast<SchedRead>("ReadVISlideV_" # mx);
-    defvar ReadVISlideX_MX = !cast<SchedRead>("ReadVISlideX_" # mx);
-
     defm "" : VPseudoVSLDV_VX<m, Constraint>,
-              Sched<[WriteVISlideX_MX, ReadVISlideV_MX, ReadVISlideV_MX,
-                     ReadVISlideX_MX, ReadVMask]>;
+              SchedTernary<"WriteVISlideX", "ReadVISlideV", "ReadVISlideV",
+                           "ReadVISlideX", mx>;
     defm "" : VPseudoVSLDV_VI<ImmType, m, Constraint>,
-              Sched<[WriteVISlideI_MX, ReadVISlideV_MX, ReadVISlideV_MX, ReadVMask]>;
+              SchedBinary<"WriteVISlideI", "ReadVISlideV", "ReadVISlideV", mx>;
   }
 }
 
 multiclass VPseudoVWMAC_VV_VX {
   foreach m = MxListW in {
     defvar mx = m.MX;
-    defvar WriteVIWMulAddV_MX = !cast<SchedWrite>("WriteVIWMulAddV_" # mx);
-    defvar WriteVIWMulAddX_MX = !cast<SchedWrite>("WriteVIWMulAddX_" # mx);
-    defvar ReadVIWMulAddV_MX = !cast<SchedRead>("ReadVIWMulAddV_" # mx);
-    defvar ReadVIWMulAddX_MX = !cast<SchedRead>("ReadVIWMulAddX_" # mx);
-
     defm "" : VPseudoTernaryW_VV<m>,
-              Sched<[WriteVIWMulAddV_MX, ReadVIWMulAddV_MX, ReadVIWMulAddV_MX,
-                     ReadVIWMulAddV_MX, ReadVMask]>;
+              SchedTernary<"WriteVIWMulAddV", "ReadVIWMulAddV", "ReadVIWMulAddV",
+                           "ReadVIWMulAddV", mx>;
     defm "" : VPseudoTernaryW_VX<m>,
-              Sched<[WriteVIWMulAddX_MX, ReadVIWMulAddV_MX, ReadVIWMulAddV_MX,
-                     ReadVIWMulAddX_MX, ReadVMask]>;
+              SchedTernary<"WriteVIWMulAddX", "ReadVIWMulAddV", "ReadVIWMulAddV",
+                           "ReadVIWMulAddX", mx>;
   }
 }
 
 multiclass VPseudoVWMAC_VX {
   foreach m = MxListW in {
-    defvar mx = m.MX;
-    defvar WriteVIWMulAddX_MX = !cast<SchedWrite>("WriteVIWMulAddX_" # mx);
-    defvar ReadVIWMulAddV_MX= !cast<SchedRead>("ReadVIWMulAddV_" # mx);
-    defvar ReadVIWMulAddX_MX = !cast<SchedRead>("ReadVIWMulAddX_" # mx);
-
     defm "" : VPseudoTernaryW_VX<m>,
-              Sched<[WriteVIWMulAddX_MX, ReadVIWMulAddV_MX, ReadVIWMulAddV_MX,
-                     ReadVIWMulAddX_MX, ReadVMask]>;
+              SchedTernary<"WriteVIWMulAddX", "ReadVIWMulAddV", "ReadVIWMulAddV",
+                           "ReadVIWMulAddX", m.MX>;
   }
 }
 
 multiclass VPseudoVWMAC_VV_VF_RM {
   foreach m = MxListFW in {
-    defvar mx = m.MX;
-    defvar WriteVFWMulAddV_MX = !cast<SchedWrite>("WriteVFWMulAddV_" # mx);
-    defvar ReadVFWMulAddV_MX = !cast<SchedRead>("ReadVFWMulAddV_" # mx);
-
     defm "" : VPseudoTernaryW_VV_RM<m>,
-              Sched<[WriteVFWMulAddV_MX, ReadVFWMulAddV_MX,
-                     ReadVFWMulAddV_MX, ReadVFWMulAddV_MX, ReadVMask]>;
+              SchedTernary<"WriteVFWMulAddV", "ReadVFWMulAddV",
+                           "ReadVFWMulAddV", "ReadVFWMulAddV", m.MX>;
   }
 
   foreach f = FPListW in {
     foreach m = f.MxListFW in {
-      defvar mx = m.MX;
-      defvar WriteVFWMulAddF_MX = !cast<SchedWrite>("WriteVFWMulAddF_" # mx);
-      defvar ReadVFWMulAddV_MX = !cast<SchedRead>("ReadVFWMulAddV_" # mx);
-      defvar ReadVFWMulAddF_MX = !cast<SchedRead>("ReadVFWMulAddF_" # mx);
-
       defm "" : VPseudoTernaryW_VF_RM<m, f>,
-                Sched<[WriteVFWMulAddF_MX, ReadVFWMulAddV_MX,
-                       ReadVFWMulAddV_MX, ReadVFWMulAddF_MX, ReadVMask]>;
+                SchedTernary<"WriteVFWMulAddF", "ReadVFWMulAddV",
+                             "ReadVFWMulAddV", "ReadVFWMulAddF", m.MX>;
     }
   }
 }
 
 multiclass VPseudoVCMPM_VV_VX_VI {
   foreach m = MxList in {
     defvar mx = m.MX;
-    defvar WriteVICmpV_MX = !cast<SchedWrite>("WriteVICmpV_" # mx);
-    defvar WriteVICmpX_MX = !cast<SchedWrite>("WriteVICmpX_" # mx);
-    defvar WriteVICmpI_MX = !cast<SchedWrite>("WriteVICmpI_" # mx);
-    defvar ReadVICmpV_MX = !cast<SchedRead>("ReadVICmpV_" # mx);
-    defvar ReadVICmpX_MX = !cast<SchedRead>("ReadVICmpX_" # mx);
-
     defm "" : VPseudoBinaryM_VV<m>,
-              Sched<[WriteVICmpV_MX, ReadVICmpV_MX, ReadVICmpV_MX, ReadVMask]>;
+              SchedBinary<"WriteVICmpV", "ReadVICmpV", "ReadVICmpV", mx>;
     defm "" : VPseudoBinaryM_VX<m>,
-              Sched<[WriteVICmpX_MX, ReadVICmpV_MX, ReadVICmpX_MX, ReadVMask]>;
+              SchedBinary<"WriteVICmpX", "ReadVICmpV", "ReadVICmpX", mx>;
     defm "" : VPseudoBinaryM_VI<m>,
-              Sched<[WriteVICmpI_MX, ReadVICmpV_MX, ReadVMask]>;
+              SchedUnary<"WriteVICmpI", "ReadVICmpV", mx>;
   }
 }
 
 multiclass VPseudoVCMPM_VV_VX {
   foreach m = MxList in {
     defvar mx = m.MX;
-    defvar WriteVICmpV_MX = !cast<SchedWrite>("WriteVICmpV_" # mx);
-    defvar WriteVICmpX_MX = !cast<SchedWrite>("WriteVICmpX_" # mx);
-    defvar ReadVICmpV_MX = !cast<SchedRead>("ReadVICmpV_" # mx);
-    defvar ReadVICmpX_MX = !cast<SchedRead>("ReadVICmpX_" # mx);
-
     defm "" : VPseudoBinaryM_VV<m>,
-              Sched<[WriteVICmpV_MX, ReadVICmpV_MX, ReadVICmpV_MX, ReadVMask]>;
+              SchedBinary<"WriteVICmpV", "ReadVICmpV", "ReadVICmpV", mx>;
     defm "" : VPseudoBinaryM_VX<m>,
-              Sched<[WriteVICmpX_MX, ReadVICmpV_MX, ReadVICmpX_MX, ReadVMask]>;
+              SchedBinary<"WriteVICmpX", "ReadVICmpV", "ReadVICmpX", mx>;
   }
 }
 
 multiclass VPseudoVCMPM_VV_VF {
   foreach m = MxListF in {
-    defvar mx = m.MX;
-    defvar WriteVFCmpV_MX = !cast<SchedWrite>("WriteVFCmpV_" # mx);
-    defvar ReadVFCmpV_MX = !cast<SchedRead>("ReadVFCmpV_" # mx);
-
     defm "" : VPseudoBinaryM_VV<m>,
-              Sched<[WriteVFCmpV_MX, ReadVFCmpV_MX, ReadVFCmpV_MX, ReadVMask]>;
+              SchedBinary<"WriteVFCmpV", "ReadVFCmpV", "ReadVFCmpV", m.MX>;
   }
 
   foreach f = FPList in {
     foreach m = f.MxList in {
-      defvar mx = m.MX;
-      defvar WriteVFCmpF_MX = !cast<SchedWrite>("WriteVFCmpF_" # mx);
-      defvar ReadVFCmpV_MX = !cast<SchedRead>("ReadVFCmpV_" # mx);
-      defvar ReadVFCmpF_MX = !cast<SchedRead>("ReadVFCmpF_" # mx);
-
       defm "" : VPseudoBinaryM_VF<m, f>,
-                Sched<[WriteVFCmpF_MX, ReadVFCmpV_MX, ReadVFCmpF_MX, ReadVMask]>;
+                SchedBinary<"WriteVFCmpF", "ReadVFCmpV", "ReadVFCmpF", m.MX>;
     }
   }
 }
 
 multiclass VPseudoVCMPM_VF {
   foreach f = FPList in {
     foreach m = f.MxList in {
-      defvar mx = m.MX;
-      defvar WriteVFCmpF_MX = !cast<SchedWrite>("WriteVFCmpF_" # mx);
-      defvar ReadVFCmpV_MX = !cast<SchedRead>("ReadVFCmpV_" # mx);
-      defvar ReadVFCmpF_MX = !cast<SchedRead>("ReadVFCmpF_" # mx);
-
       defm "" : VPseudoBinaryM_VF<m, f>,
-                Sched<[WriteVFCmpF_MX, ReadVFCmpV_MX, ReadVFCmpF_MX, ReadVMask]>;
+                SchedBinary<"WriteVFCmpF", "ReadVFCmpV", "ReadVFCmpF", m.MX>;
     }
   }
 }
 
 multiclass VPseudoVCMPM_VX_VI {
   foreach m = MxList in {
     defvar mx = m.MX;
-    defvar WriteVICmpX_MX = !cast<SchedWrite>("WriteVICmpX_" # mx);
-    defvar WriteVICmpI_MX = !cast<SchedWrite>("WriteVICmpI_" # mx);
-    defvar ReadVICmpV_MX = !cast<SchedRead>("ReadVICmpV_" # mx);
-    defvar ReadVICmpX_MX = !cast<SchedRead>("ReadVICmpX_" # mx);
-
     defm "" : VPseudoBinaryM_VX<m>,
-              Sched<[WriteVICmpX_MX, ReadVICmpV_MX, ReadVICmpX_MX, ReadVMask]>;
+              SchedBinary<"WriteVICmpX", "ReadVICmpV", "ReadVICmpX", mx>;
     defm "" : VPseudoBinaryM_VI<m>,
-              Sched<[WriteVICmpI_MX, ReadVICmpV_MX, ReadVMask]>;
+              SchedUnary<"WriteVICmpI", "ReadVICmpV", mx>;
   }
 }
 
 multiclass VPseudoVRED_VS {
   foreach m = MxList in {
     defvar mx = m.MX;
     foreach e = SchedSEWSet<mx>.val in {
-      defvar WriteVIRedV_From_MX_E = !cast<SchedWrite>("WriteVIRedV_From_" # mx # "_E" # e);
       defm _VS : VPseudoTernaryWithTailPolicy<V_M1.vrclass, m.vrclass, V_M1.vrclass, m, e>,
-                 Sched<[WriteVIRedV_From_MX_E, ReadVIRedV, ReadVIRedV, ReadVIRedV,
-                        ReadVMask]>;
+                 SchedReduction<"WriteVIRedV_From", "ReadVIRedV", mx, e>;
     }
   }
 }
 
 multiclass VPseudoVREDMINMAX_VS {
   foreach m = MxList in {
     defvar mx = m.MX;
     foreach e = SchedSEWSet<mx>.val in {
-      defvar WriteVIRedMinMaxV_From_MX_E = !cast<SchedWrite>("WriteVIRedMinMaxV_From_" # mx # "_E" # e);
       defm _VS : VPseudoTernaryWithTailPolicy<V_M1.vrclass, m.vrclass, V_M1.vrclass, m, e>,
-                 Sched<[WriteVIRedMinMaxV_From_MX_E, ReadVIRedV, ReadVIRedV,
-                        ReadVIRedV, ReadVMask]>;
+                 SchedReduction<"WriteVIRedMinMaxV_From", "ReadVIRedV", mx, e>;
     }
   }
 }
 
 multiclass VPseudoVWRED_VS {
   foreach m = MxListWRed in {
     defvar mx = m.MX;
     foreach e = SchedSEWSet<mx, isWidening=1>.val in {
-      defvar WriteVIWRedV_From_MX_E = !cast<SchedWrite>("WriteVIWRedV_From_" # mx # "_E" # e);
       defm _VS : VPseudoTernaryWithTailPolicy<V_M1.vrclass, m.vrclass, V_M1.vrclass, m, e>,
-                 Sched<[WriteVIWRedV_From_MX_E, ReadVIWRedV, ReadVIWRedV,
-                        ReadVIWRedV, ReadVMask]>;
+                 SchedReduction<"WriteVIWRedV_From", "ReadVIWRedV", mx, e>;
     }
   }
 }
 
 multiclass VPseudoVFRED_VS_RM {
   foreach m = MxListF in {
     defvar mx = m.MX;
     foreach e = SchedSEWSet<mx, isF=1>.val in {
-      defvar WriteVFRedV_From_MX_E = !cast<SchedWrite>("WriteVFRedV_From_" # mx # "_E" # e);
       defm _VS
           : VPseudoTernaryWithTailPolicyRoundingMode<V_M1.vrclass, m.vrclass, 
                                                      V_M1.vrclass, m, e>,
-                 Sched<[WriteVFRedV_From_MX_E, ReadVFRedV, ReadVFRedV, ReadVFRedV,
-                        ReadVMask]>;
+            SchedReduction<"WriteVFRedV_From", "ReadVFRedV", mx, e>;
     }
   }
 }
 
 multiclass VPseudoVFREDMINMAX_VS {
   foreach m = MxListF in {
     defvar mx = m.MX;
     foreach e = SchedSEWSet<mx, isF=1>.val in {
-      defvar WriteVFRedMinMaxV_From_MX_E = !cast<SchedWrite>("WriteVFRedMinMaxV_From_" # mx # "_E" # e);
       defm _VS : VPseudoTernaryWithTailPolicy<V_M1.vrclass, m.vrclass, V_M1.vrclass, m, e>,
-                 Sched<[WriteVFRedMinMaxV_From_MX_E, ReadVFRedV, ReadVFRedV, ReadVFRedV,
-                        ReadVMask]>;
+                 SchedReduction<"WriteVFRedMinMaxV_From", "ReadVFRedV", mx, e>;
     }
   }
 }
 
 multiclass VPseudoVFREDO_VS_RM {
   foreach m = MxListF in {
     defvar mx = m.MX;
     foreach e = SchedSEWSet<mx, isF=1>.val in {
-      defvar WriteVFRedOV_From_MX_E = !cast<SchedWrite>("WriteVFRedOV_From_" # mx # "_E" # e);
       defm _VS : VPseudoTernaryWithTailPolicyRoundingMode<V_M1.vrclass, m.vrclass,
                                                           V_M1.vrclass, m, e>,
-                 Sched<[WriteVFRedOV_From_MX_E, ReadVFRedOV, ReadVFRedOV,
-                        ReadVFRedOV, ReadVMask]>;
+                 SchedReduction<"WriteVFRedOV_From", "ReadVFRedOV", mx, e>;
     }
   }
 }
 
 multiclass VPseudoVFWRED_VS_RM {
   foreach m = MxListFWRed in {
     defvar mx = m.MX;
     foreach e = SchedSEWSet<mx, isF=1, isWidening=1>.val in {
-      defvar WriteVFWRedV_From_MX_E = !cast<SchedWrite>("WriteVFWRedV_From_" # mx # "_E" # e);
       defm _VS
           : VPseudoTernaryWithTailPolicyRoundingMode<V_M1.vrclass, m.vrclass,
                                                      V_M1.vrclass, m, e>,
-                 Sched<[WriteVFWRedV_From_MX_E, ReadVFWRedV, ReadVFWRedV,
-                        ReadVFWRedV, ReadVMask]>;
+            SchedReduction<"WriteVFWRedV_From", "ReadVFWRedV", mx, e>;
     }
   }
 }
 
 multiclass VPseudoConversion<VReg RetClass,
                              VReg Op1Class,
                              LMULInfo MInfo,
                              string Constraint = ""> {
multiclass VPseudoConversionNoExcept<VReg RetClass,
                                      string Constraint = ""> {
   let VLMul = MInfo.value in {
     def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMask_NoExcept<RetClass, Op1Class, Constraint>;
   }
 }
 
 multiclass VPseudoVCVTI_V {
   foreach m = MxListF in {
-    defvar mx = m.MX;
-    defvar WriteVFCvtFToIV_MX = !cast<SchedWrite>("WriteVFCvtFToIV_" # mx);
-    defvar ReadVFCvtFToIV_MX = !cast<SchedRead>("ReadVFCvtFToIV_" # mx);
-
     defm _V : VPseudoConversion<m.vrclass, m.vrclass, m>,
-              Sched<[WriteVFCvtFToIV_MX, ReadVFCvtFToIV_MX, ReadVMask]>;
+              SchedUnary<"WriteVFCvtFToIV", "ReadVFCvtFToIV", m.MX>;
   }
 }
 
 multiclass VPseudoVCVTI_V_RM {
   foreach m = MxListF in {
-    defvar mx = m.MX;
-    defvar WriteVFCvtFToIV_MX = !cast<SchedWrite>("WriteVFCvtFToIV_" # mx);
-    defvar ReadVFCvtFToIV_MX = !cast<SchedRead>("ReadVFCvtFToIV_" # mx);
-
     defm _V : VPseudoConversionRoundingMode<m.vrclass, m.vrclass, m>,
-              Sched<[WriteVFCvtFToIV_MX, ReadVFCvtFToIV_MX, ReadVMask]>;
+              SchedUnary<"WriteVFCvtFToIV", "ReadVFCvtFToIV", m.MX>;
   }
 }
 
 multiclass VPseudoVCVTI_RM_V {
   foreach m = MxListF in {
-    defvar mx = m.MX;
-    defvar WriteVFCvtFToIV_MX = !cast<SchedWrite>("WriteVFCvtFToIV_" # mx);
-    defvar ReadVFCvtFToIV_MX = !cast<SchedRead>("ReadVFCvtFToIV_" # mx);
-
     defm _V : VPseudoConversionRM<m.vrclass, m.vrclass, m>,
-              Sched<[WriteVFCvtFToIV_MX, ReadVFCvtFToIV_MX, ReadVMask]>;
+              SchedUnary<"WriteVFCvtFToIV", "ReadVFCvtFToIV", m.MX>;
   }
 }
 
 multiclass VPseudoVFROUND_NOEXCEPT_V {
   foreach m = MxListF in {
-    defvar mx = m.MX;
-    defvar WriteVFCvtFToIV_MX = !cast<SchedWrite>("WriteVFCvtFToIV_" # mx);
-    defvar ReadVFCvtFToIV_MX = !cast<SchedRead>("ReadVFCvtFToIV_" # mx);
-
     defm _V : VPseudoConversionNoExcept<m.vrclass, m.vrclass, m>,
-              Sched<[WriteVFCvtFToIV_MX, ReadVFCvtFToIV_MX, ReadVMask]>;
+              SchedUnary<"WriteVFCvtFToIV", "ReadVFCvtFToIV", m.MX>;
   }
 }
 
 multiclass VPseudoVCVTF_V_RM {
   foreach m = MxListF in {
-    defvar mx = m.MX;
-    defvar WriteVFCvtIToFV_MX = !cast<SchedWrite>("WriteVFCvtIToFV_" # mx);
-    defvar ReadVFCvtIToFV_MX = !cast<SchedRead>("ReadVFCvtIToFV_" # mx);
-
     defm _V : VPseudoConversionRoundingMode<m.vrclass, m.vrclass, m>,
-              Sched<[WriteVFCvtIToFV_MX, ReadVFCvtIToFV_MX, ReadVMask]>;
+              SchedUnary<"WriteVFCvtIToFV", "ReadVFCvtIToFV", m.MX>;
   }
 }
 
 multiclass VPseudoVCVTF_RM_V {
   foreach m = MxListF in {
-    defvar mx = m.MX;
-    defvar WriteVFCvtIToFV_MX = !cast<SchedWrite>("WriteVFCvtIToFV_" # mx);
-    defvar ReadVFCvtIToFV_MX = !cast<SchedRead>("ReadVFCvtIToFV_" # mx);
-
     defm _V : VPseudoConversionRM<m.vrclass, m.vrclass, m>,
-              Sched<[WriteVFCvtIToFV_MX, ReadVFCvtIToFV_MX, ReadVMask]>;
+              SchedUnary<"WriteVFCvtIToFV", "ReadVFCvtIToFV", m.MX>;
   }
 }
 
 multiclass VPseudoVWCVTI_V {
   defvar constraint = "@earlyclobber $rd";
   foreach m = MxListFW in {
-    defvar mx = m.MX;
-    defvar WriteVFWCvtFToIV_MX = !cast<SchedWrite>("WriteVFWCvtFToIV_" # mx);
-    defvar ReadVFWCvtFToIV_MX = !cast<SchedRead>("ReadVFWCvtFToIV_" # mx);
-
     defm _V : VPseudoConversion<m.wvrclass, m.vrclass, m, constraint>,
-              Sched<[WriteVFWCvtFToIV_MX, ReadVFWCvtFToIV_MX, ReadVMask]>;
+              SchedUnary<"WriteVFWCvtFToIV", "ReadVFWCvtFToIV", m.MX>;
   }
 }
 
 multiclass VPseudoVWCVTI_V_RM {
   defvar constraint = "@earlyclobber $rd";
   foreach m = MxListFW in {
-    defvar mx = m.MX;
-    defvar WriteVFWCvtFToIV_MX = !cast<SchedWrite>("WriteVFWCvtFToIV_" # mx);
-    defvar ReadVFWCvtFToIV_MX = !cast<SchedRead>("ReadVFWCvtFToIV_" # mx);
-
     defm _V : VPseudoConversionRoundingMode<m.wvrclass, m.vrclass, m, constraint>,
-              Sched<[WriteVFWCvtFToIV_MX, ReadVFWCvtFToIV_MX, ReadVMask]>;
+              SchedUnary<"WriteVFWCvtFToIV", "ReadVFWCvtFToIV", m.MX>;
   }
 }
 
 multiclass VPseudoVWCVTI_RM_V {
   defvar constraint = "@earlyclobber $rd";
   foreach m = MxListFW in {
-    defvar mx = m.MX;
-    defvar WriteVFWCvtFToIV_MX = !cast<SchedWrite>("WriteVFWCvtFToIV_" # mx);
-    defvar ReadVFWCvtFToIV_MX = !cast<SchedRead>("ReadVFWCvtFToIV_" # mx);
-
     defm _V : VPseudoConversionRM<m.wvrclass, m.vrclass, m, constraint>,
-              Sched<[WriteVFWCvtFToIV_MX, ReadVFWCvtFToIV_MX, ReadVMask]>;
+              SchedUnary<"WriteVFWCvtFToIV", "ReadVFWCvtFToIV", m.MX>;
   }
 }
 
 multiclass VPseudoVWCVTF_V {
   defvar constraint = "@earlyclobber $rd";
   foreach m = MxListW in {
-    defvar mx = m.MX;
-    defvar WriteVFWCvtIToFV_MX = !cast<SchedWrite>("WriteVFWCvtIToFV_" # mx);
-    defvar ReadVFWCvtIToFV_MX = !cast<SchedRead>("ReadVFWCvtIToFV_" # mx);
-
     defm _V : VPseudoConversion<m.wvrclass, m.vrclass, m, constraint>,
-              Sched<[WriteVFWCvtIToFV_MX, ReadVFWCvtIToFV_MX, ReadVMask]>;
+              SchedUnary<"WriteVFWCvtIToFV", "ReadVFWCvtIToFV", m.MX>;
   }
 }
 
 multiclass VPseudoVWCVTD_V {
   defvar constraint = "@earlyclobber $rd";
   foreach m = MxListFW in {
-    defvar mx = m.MX;
-    defvar WriteVFWCvtFToFV_MX = !cast<SchedWrite>("WriteVFWCvtFToFV_" # mx);
-    defvar ReadVFWCvtFToFV_MX = !cast<SchedRead>("ReadVFWCvtFToFV_" # mx);
-
     defm _V : VPseudoConversion<m.wvrclass, m.vrclass, m, constraint>,
-              Sched<[WriteVFWCvtFToFV_MX, ReadVFWCvtFToFV_MX, ReadVMask]>;
+              SchedUnary<"WriteVFWCvtFToFV", "ReadVFWCvtFToFV", m.MX>;
   }
 }
 
 multiclass VPseudoVNCVTI_W {
   defvar constraint = "@earlyclobber $rd";
   foreach m = MxListW in {
-    defvar mx = m.MX;
-    defvar WriteVFNCvtFToIV_MX = !cast<SchedWrite>("WriteVFNCvtFToIV_" # mx);
-    defvar ReadVFNCvtFToIV_MX = !cast<SchedRead>("ReadVFNCvtFToIV_" # mx);
-
     defm _W : VPseudoConversion<m.vrclass, m.wvrclass, m, constraint>,
-              Sched<[WriteVFNCvtFToIV_MX, ReadVFNCvtFToIV_MX, ReadVMask]>;
+              SchedUnary<"WriteVFNCvtFToIV", "ReadVFNCvtFToIV", m.MX>;
   }
 }
 
 multiclass VPseudoVNCVTI_W_RM {
   defvar constraint = "@earlyclobber $rd";
   foreach m = MxListW in {
-    defvar mx = m.MX;
-    defvar WriteVFNCvtFToIV_MX = !cast<SchedWrite>("WriteVFNCvtFToIV_" # mx);
-    defvar ReadVFNCvtFToIV_MX = !cast<SchedRead>("ReadVFNCvtFToIV_" # mx);
-
     defm _W : VPseudoConversionRoundingMode<m.vrclass, m.wvrclass, m, constraint>,
-              Sched<[WriteVFNCvtFToIV_MX, ReadVFNCvtFToIV_MX, ReadVMask]>;
+              SchedUnary<"WriteVFNCvtFToIV", "ReadVFNCvtFToIV", m.MX>;
   }
 }
 
 multiclass VPseudoVNCVTI_RM_W {
   defvar constraint = "@earlyclobber $rd";
   foreach m = MxListW in {
-    defvar mx = m.MX;
-    defvar WriteVFNCvtFToIV_MX = !cast<SchedWrite>("WriteVFNCvtFToIV_" # mx);
-    defvar ReadVFNCvtFToIV_MX = !cast<SchedRead>("ReadVFNCvtFToIV_" # mx);
-
     defm _W : VPseudoConversionRM<m.vrclass, m.wvrclass, m, constraint>,
-              Sched<[WriteVFNCvtFToIV_MX, ReadVFNCvtFToIV_MX, ReadVMask]>;
+              SchedUnary<"WriteVFNCvtFToIV", "ReadVFNCvtFToIV", m.MX>;
   }
 }
 
 multiclass VPseudoVNCVTF_W_RM {
   defvar constraint = "@earlyclobber $rd";
   foreach m = MxListFW in {
-    defvar mx = m.MX;
-    defvar WriteVFNCvtIToFV_MX = !cast<SchedWrite>("WriteVFNCvtIToFV_" # mx);
-    defvar ReadVFNCvtIToFV_MX = !cast<SchedRead>("ReadVFNCvtIToFV_" # mx);
-
     defm _W : VPseudoConversionRoundingMode<m.vrclass, m.wvrclass, m, constraint>,
-              Sched<[WriteVFNCvtIToFV_MX, ReadVFNCvtIToFV_MX, ReadVMask]>;
+              SchedUnary<"WriteVFNCvtIToFV", "ReadVFNCvtIToFV", m.MX>;
   }
 }
 
 multiclass VPseudoVNCVTF_RM_W {
   defvar constraint = "@earlyclobber $rd";
   foreach m = MxListFW in {
-    defvar mx = m.MX;
-    defvar WriteVFNCvtIToFV_MX = !cast<SchedWrite>("WriteVFNCvtIToFV_" # mx);
-    defvar ReadVFNCvtIToFV_MX = !cast<SchedRead>("ReadVFNCvtIToFV_" # mx);
-
     defm _W : VPseudoConversionRM<m.vrclass, m.wvrclass, m, constraint>,
-              Sched<[WriteVFNCvtIToFV_MX, ReadVFNCvtIToFV_MX, ReadVMask]>;
+              SchedUnary<"WriteVFNCvtIToFV", "ReadVFNCvtIToFV", m.MX>;
   }
 }
 
 multiclass VPseudoVNCVTD_W {
   defvar constraint = "@earlyclobber $rd";
   foreach m = MxListFW in {
-    defvar mx = m.MX;
-    defvar WriteVFNCvtFToFV_MX = !cast<SchedWrite>("WriteVFNCvtFToFV_" # mx);
-    defvar ReadVFNCvtFToFV_MX = !cast<SchedRead>("ReadVFNCvtFToFV_" # mx);
-
     defm _W : VPseudoConversion<m.vrclass, m.wvrclass, m, constraint>,
-              Sched<[WriteVFNCvtFToFV_MX, ReadVFNCvtFToFV_MX, ReadVMask]>;
+              SchedUnary<"WriteVFNCvtFToFV", "ReadVFNCvtFToFV", m.MX>;
   }
 }
 
 multiclass VPseudoVNCVTD_W_RM {
   defvar constraint = "@earlyclobber $rd";
   foreach m = MxListFW in {
-    defvar mx = m.MX;
-    defvar WriteVFNCvtFToFV_MX = !cast<SchedWrite>("WriteVFNCvtFToFV_" # mx);
-    defvar ReadVFNCvtFToFV_MX = !cast<SchedRead>("ReadVFNCvtFToFV_" # mx);
-
     defm _W : VPseudoConversionRoundingMode<m.vrclass, m.wvrclass, m, constraint>,
-              Sched<[WriteVFNCvtFToFV_MX, ReadVFNCvtFToFV_MX, ReadVMask]>;
+              SchedUnary<"WriteVFNCvtFToFV", "ReadVFNCvtFToFV", m.MX>;
   }
 }
 
 multiclass VPseudoUSSegLoad {
   foreach eew = EEWList in {
     foreach lmul = MxSet<eew>.m in {
       defvar LInfo = lmul.MX;
       let VLMul = lmul.value, SEW=eew in {