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Differential D155927

[RISCV] Add tests for vnsrl.vx where shift amount is truncated
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Authored by luke on Jul 21 2023, 2:25 AM.

Details

Reviewers
craig.topper
4vtomat
reames
Commits
rG7c652feb95d7: [RISCV] Add tests for vnsrl.vx where shift amount is truncated

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Event Timeline

luke created this revision.Jul 21 2023, 2:25 AM
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Herald added subscribers: jobnoorman, asb, pmatos and 27 others. · View Herald Transcript
luke requested review of this revision.Jul 21 2023, 2:25 AM
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luke added a child revision: D155928: [RISCV] Add patterns for vnsrl.vx where shift amount is truncated.Jul 21 2023, 2:32 AM
Harbormaster completed remote builds in B247148: Diff 542825.Jul 21 2023, 6:23 AM
craig.topper accepted this revision.Jul 24 2023, 1:21 PM

LGTM

This revision is now accepted and ready to land.Jul 24 2023, 1:21 PM
Closed by commit rG7c652feb95d7: [RISCV] Add tests for vnsrl.vx where shift amount is truncated (authored by luke). · Explain WhyJul 26 2023, 12:26 PM
This revision was automatically updated to reflect the committed changes.
luke added a commit: rG7c652feb95d7: [RISCV] Add tests for vnsrl.vx where shift amount is truncated.

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
rvv/
78 lines

Diff 544472

llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -target-abi=ilp32 \ ; RUN: llc -mtriple=riscv32 -mattr=+v -target-abi=ilp32 \
; RUN: -verify-machineinstrs < %s | FileCheck %s ; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV32 %s
; RUN: llc -mtriple=riscv64 -mattr=+v -target-abi=lp64 \ ; RUN: llc -mtriple=riscv64 -mattr=+v -target-abi=lp64 \
; RUN: -verify-machineinstrs < %s | FileCheck %s ; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV64 %s
define <vscale x 1 x i32> @vnsrl_wx_i64_nxv1i32(<vscale x 1 x i64> %va, i64 %b) { define <vscale x 1 x i32> @vnsrl_wx_i64_nxv1i32(<vscale x 1 x i64> %va, i64 %b) {
; CHECK-LABEL: vnsrl_wx_i64_nxv1i32: ; CHECK-LABEL: vnsrl_wx_i64_nxv1i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
; CHECK-NEXT: vnsrl.wx v8, v8, a0 ; CHECK-NEXT: vnsrl.wx v8, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0 %head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
▲ Show 20 Lines • Show All 613 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 15, i32 0 %head = insertelement <vscale x 8 x i32> poison, i32 15, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vb = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64> %vb = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
%x = lshr <vscale x 8 x i64> %va, %vb %x = lshr <vscale x 8 x i64> %va, %vb
%y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32> %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
ret <vscale x 8 x i32> %y ret <vscale x 8 x i32> %y
} }
define <vscale x 1 x i16> @vnsrl_wx_i64_nxv1i16(<vscale x 1 x i32> %va, i64 %b) {
; RV32-LABEL: vnsrl_wx_i64_nxv1i16:
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vnsrl.wi v9, v9, 0
; RV32-NEXT: vsrl.vv v8, v8, v9
; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; RV32-NEXT: vnsrl.wi v8, v8, 0
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vnsrl_wx_i64_nxv1i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; RV64-NEXT: vnsrl.wi v9, v9, 0
; RV64-NEXT: vsrl.vv v8, v8, v9
; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; RV64-NEXT: vnsrl.wi v8, v8, 0
; RV64-NEXT: ret
%head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
%vb = trunc <vscale x 1 x i64> %splat to <vscale x 1 x i32>
%x = lshr <vscale x 1 x i32> %va, %vb
%y = trunc <vscale x 1 x i32> %x to <vscale x 1 x i16>
ret <vscale x 1 x i16> %y
}
define <vscale x 1 x i8> @vnsrl_wx_i64_nxv1i8(<vscale x 1 x i16> %va, i64 %b) {
; RV32-LABEL: vnsrl_wx_i64_nxv1i8:
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vnsrl.wi v9, v9, 0
; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; RV32-NEXT: vnsrl.wi v9, v9, 0
; RV32-NEXT: vsrl.vv v8, v8, v9
; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
; RV32-NEXT: vnsrl.wi v8, v8, 0
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vnsrl_wx_i64_nxv1i8:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; RV64-NEXT: vnsrl.wi v9, v9, 0
; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; RV64-NEXT: vnsrl.wi v9, v9, 0
; RV64-NEXT: vsrl.vv v8, v8, v9
; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
; RV64-NEXT: vnsrl.wi v8, v8, 0
; RV64-NEXT: ret
%head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
%vb = trunc <vscale x 1 x i64> %splat to <vscale x 1 x i16>
%x = lshr <vscale x 1 x i16> %va, %vb
%y = trunc <vscale x 1 x i16> %x to <vscale x 1 x i8>
ret <vscale x 1 x i8> %y
}