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Differential D155772

[RISCV][GlobalISel] Legalize bitshift instructions for narrow types
ClosedPublic

Authored by nitinjohnraj on Jul 19 2023, 7:44 PM.

Details

Reviewers
craig.topper
arsenm
Commits
rG649e1d1b9de9: [RISCV][GlobalISel] Legalize bitshift instructions for narrow types
Summary

Legalize G_SHL, G_ASHR and G_LSHR for types narrower and upto (and including) XLen: (i7, i8,
i16 and i32) for rv32 and (i8, i15, i16, i32 and i64) for rv64. This requires
adding some rules to handle G_ANYEXT, G_ZEXT and G_SEXT.

Diff Detail

Event Timeline

nitinjohnraj created this revision.Jul 19 2023, 7:44 PM
Herald added a project: Restricted Project. · View Herald TranscriptJul 19 2023, 7:44 PM
Herald added subscribers: jobnoorman, luke, VincentWu and 28 others. · View Herald Transcript
nitinjohnraj requested review of this revision.Jul 19 2023, 7:44 PM
Herald added a project: Restricted Project. · View Herald TranscriptJul 19 2023, 7:44 PM
Herald added subscribers: llvm-commits, wangpc, eopXD and 2 others. · View Herald Transcript
Harbormaster completed remote builds in B246743: Diff 542282.Jul 19 2023, 9:29 PM
arsenm added inline comments.Jul 20 2023, 4:04 PM
llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
38

Do you actually need to permit anything besides XLenVT? I would hope if all of these were illegal the artifact combiner would eliminate all the casts in your examples

46

Don't use references with LLT

llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-ashr.mir
4

Need some < 8 bit and odd intermediate sizes too

craig.topper added inline comments.Jul 20 2023, 10:06 PM
llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
38

I had tried to help Nitin with this. I think it wasn't working with just .clampScalar(0, XLenLLT, XLenLLT);. The code here was taken from AArch64 and modified to XLen.

59

This should be 2*XLen. The AArch64 code says 128 here.

tschuett added a subscriber: tschuett.Jul 20 2023, 10:34 PM
tschuett added inline comments.
llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
34

You claim: " types narrower and upto XLen". But you clamp to XLenLLT?

llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-ashr.mir
22

Input and output are %4?

tschuett added inline comments.Jul 20 2023, 10:52 PM
llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
59

X86 did it differently, but it does not support vectors:
https://github.com/llvm/llvm-project/blob/c3648f37d0ed24e5a783d4ead4c34c9f4796b3e3/llvm/lib/Target/X86/X86LegalizerInfo.cpp#L398

tschuett added a comment.Jul 21 2023, 12:41 AM

The builder provides various methods to help you to legalize operations.

nitinjohnraj updated this revision to Diff 544553.Jul 26 2023, 4:31 PM
nitinjohnraj marked 2 inline comments as done.

Address comments

Harbormaster completed remote builds in B248400: Diff 544553.Jul 26 2023, 4:32 PM
nitinjohnraj marked 5 inline comments as done.Jul 27 2023, 12:36 PM
nitinjohnraj added inline comments.
llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
34

XLenLLT is the only legal type on RISCV.

llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-ashr.mir
4

This doesn't work with odd-sized types right now, I'll update the description and fix that in a future patch.

I added one test for i1; but in order to pass it, I needed to change the legalization logic for G_{ANY/Z/S}EXT. Specifically, I allowed the SrcSize and DstSize to be as small as 1 for legal instructions. But neither X86 nor AArch64 allows this, so I'm not sure we should be allowing this.

22

Thank you for catching this.

nitinjohnraj added a parent revision: D156383: [RISCV][GlobalISel] Legalize constants, undefined values, extension instructions, and (un)merge instructions for narrow types.Jul 27 2023, 12:36 PM
nitinjohnraj retitled this revision from [RISCV][GlobalISel] Legalize bitshift instructions for narrow types to [RISCV][GlobalISel] Legalize bitshift instructions for narrow types that are a power of 2.
nitinjohnraj marked an inline comment as done.Jul 27 2023, 12:57 PM
nitinjohnraj added inline comments.
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-ashr.mir
4

To clarify, I meant it didn't work will odd types less than 8. I'll add a test for an odd type.

nitinjohnraj marked an inline comment as not done.Jul 27 2023, 1:01 PM
nitinjohnraj added inline comments.
llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
59

This needs to be handled in parent revision.

nitinjohnraj updated this revision to Diff 546171.Aug 1 2023, 12:09 PM

Added rules for G_SEXT_INREG. Now this patch works for non-pow 2 types.

nitinjohnraj retitled this revision from [RISCV][GlobalISel] Legalize bitshift instructions for narrow types that are a power of 2 to [RISCV][GlobalISel] Legalize bitshift instructions for narrow types.Aug 1 2023, 12:11 PM
nitinjohnraj edited the summary of this revision. (Show Details)
nitinjohnraj marked an inline comment as done.

Ping! Is anyone available to review this?

Harbormaster completed remote builds in B249570: Diff 546171.Aug 1 2023, 1:31 PM
craig.topper accepted this revision.Aug 1 2023, 3:57 PM

LGTM

This revision is now accepted and ready to land.Aug 1 2023, 3:57 PM
This revision was landed with ongoing or failed builds.Aug 7 2023, 3:13 PM
Closed by commit rG649e1d1b9de9: [RISCV][GlobalISel] Legalize bitshift instructions for narrow types (authored by nitinjohnraj). · Explain Why
This revision was automatically updated to reflect the committed changes.
nitinjohnraj added a commit: rG649e1d1b9de9: [RISCV][GlobalISel] Legalize bitshift instructions for narrow types.

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
GISel/
8 lines
test/
CodeGen/
RISCV/
GlobalISel/
legalizer/
rv32/
89 lines
92 lines
86 lines
rv64/
112 lines
116 lines
108 lines

Diff 547974

llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

Show All 23 LinesRISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
const LLT XLenLLT = LLT::scalar(XLen); const LLT XLenLLT = LLT::scalar(XLen);
using namespace TargetOpcode; using namespace TargetOpcode;
getActionDefinitionsBuilder({G_ADD, G_SUB, G_AND, G_OR, G_XOR}) getActionDefinitionsBuilder({G_ADD, G_SUB, G_AND, G_OR, G_XOR})
.legalFor({XLenLLT}) .legalFor({XLenLLT})
.clampScalar(0, XLenLLT, XLenLLT); .clampScalar(0, XLenLLT, XLenLLT);
getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL})
.legalFor({{XLenLLT, XLenLLT}})
.widenScalarToNextPow2(0)
tschuettUnsubmitted
Done
ReplyInline Actions

You claim: " types narrower and upto XLen". But you clamp to XLenLLT?

tschuett: You claim: " types narrower and upto XLen". But you clamp to XLenLLT?
nitinjohnrajAuthorUnsubmitted
Done
ReplyInline Actions

XLenLLT is the only legal type on RISCV.

nitinjohnraj: XLenLLT is the only legal type on RISCV.
.clampScalar(1, XLenLLT, XLenLLT)
.clampScalar(0, XLenLLT, XLenLLT);
// Extensions // Extensions
arsenmUnsubmitted
Done
ReplyInline Actions

Do you actually need to permit anything besides XLenVT? I would hope if all of these were illegal the artifact combiner would eliminate all the casts in your examples

arsenm: Do you actually need to permit anything besides XLenVT? I would hope if all of these were…
craig.topperUnsubmitted
Done
ReplyInline Actions

I had tried to help Nitin with this. I think it wasn't working with just .clampScalar(0, XLenLLT, XLenLLT);. The code here was taken from AArch64 and modified to XLen.

craig.topper: I had tried to help Nitin with this. I think it wasn't working with just `.clampScalar(0…
auto ExtLegalFunc = [=](const LegalityQuery &Query) { auto ExtLegalFunc = [=](const LegalityQuery &Query) {
unsigned DstSize = Query.Types[0].getSizeInBits(); unsigned DstSize = Query.Types[0].getSizeInBits();
// Make sure that we have something that will fit in a register, and // Make sure that we have something that will fit in a register, and
// make sure it's a power of 2. // make sure it's a power of 2.
if (DstSize < 8 || DstSize > XLen || !isPowerOf2_32(DstSize)) if (DstSize < 8 || DstSize > XLen || !isPowerOf2_32(DstSize))
return false; return false;
arsenmUnsubmitted
Done
ReplyInline Actions

Don't use references with LLT

arsenm: Don't use references with LLT
const LLT SrcTy = Query.Types[1]; const LLT SrcTy = Query.Types[1];
// Make sure we fit in a register otherwise. Don't bother checking that // Make sure we fit in a register otherwise. Don't bother checking that
// the source type is below 2 * XLen bits. We shouldn't be allowing anything // the source type is below 2 * XLen bits. We shouldn't be allowing anything
// through which is wider than the destination in the first place. // through which is wider than the destination in the first place.
unsigned SrcSize = SrcTy.getSizeInBits(); unsigned SrcSize = SrcTy.getSizeInBits();
if (SrcSize < 8 || !isPowerOf2_32(SrcSize)) if (SrcSize < 8 || !isPowerOf2_32(SrcSize))
return false; return false;
return true; return true;
}; };
getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT}) getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT})
.legalIf(ExtLegalFunc) .legalIf(ExtLegalFunc)
craig.topperUnsubmitted
Not Done
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This should be 2*XLen. The AArch64 code says 128 here.

craig.topper: This should be 2*XLen. The AArch64 code says 128 here.
tschuettUnsubmitted
Done
ReplyInline Actions

X86 did it differently, but it does not support vectors:
https://github.com/llvm/llvm-project/blob/c3648f37d0ed24e5a783d4ead4c34c9f4796b3e3/llvm/lib/Target/X86/X86LegalizerInfo.cpp#L398

tschuett: X86 did it differently, but it does not support vectors: https://github.com/llvm/llvm…
nitinjohnrajAuthorUnsubmitted
Done
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This needs to be handled in parent revision.

nitinjohnraj: This needs to be handled in parent revision.
.clampScalar(0, XLenLLT, XLenLLT); .clampScalar(0, XLenLLT, XLenLLT);
getActionDefinitionsBuilder(G_SEXT_INREG).legalFor({XLenLLT}).lower();
// Merge/Unmerge // Merge/Unmerge
for (unsigned Op : {G_MERGE_VALUES, G_UNMERGE_VALUES}) { for (unsigned Op : {G_MERGE_VALUES, G_UNMERGE_VALUES}) {
unsigned BigTyIdx = Op == G_MERGE_VALUES ? 0 : 1; unsigned BigTyIdx = Op == G_MERGE_VALUES ? 0 : 1;
unsigned LitTyIdx = Op == G_MERGE_VALUES ? 1 : 0; unsigned LitTyIdx = Op == G_MERGE_VALUES ? 1 : 0;
getActionDefinitionsBuilder(Op) getActionDefinitionsBuilder(Op)
.widenScalarToNextPow2(LitTyIdx, XLen) .widenScalarToNextPow2(LitTyIdx, XLen)
.widenScalarToNextPow2(BigTyIdx, XLen) .widenScalarToNextPow2(BigTyIdx, XLen)
.clampScalar(LitTyIdx, XLenLLT, XLenLLT) .clampScalar(LitTyIdx, XLenLLT, XLenLLT)
Show All 10 Lines

llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-ashr.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s
---
arsenmUnsubmitted
Done
ReplyInline Actions

Need some < 8 bit and odd intermediate sizes too

arsenm: Need some < 8 bit and odd intermediate sizes too
nitinjohnrajAuthorUnsubmitted
Done
ReplyInline Actions

This doesn't work with odd-sized types right now, I'll update the description and fix that in a future patch.

I added one test for i1; but in order to pass it, I needed to change the legalization logic for G_{ANY/Z/S}EXT. Specifically, I allowed the SrcSize and DstSize to be as small as 1 for legal instructions. But neither X86 nor AArch64 allows this, so I'm not sure we should be allowing this.

nitinjohnraj: This doesn't work with odd-sized types right now, I'll update the description and fix that in a…
nitinjohnrajAuthorUnsubmitted
Done
ReplyInline Actions

To clarify, I meant it didn't work will odd types less than 8. I'll add a test for an odd type.

nitinjohnraj: To clarify, I meant it didn't work will odd types less than 8. I'll add a test for an odd type.
name: ashr_i7
body: |
bb.0.entry:
; CHECK-LABEL: name: ashr_i7
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 7
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
; CHECK-NEXT: $x10 = COPY [[ASHR]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s7) = G_TRUNC %0(s32)
%3:_(s7) = G_TRUNC %1(s32)
%4:_(s7) = G_ASHR %2, %3
%5:_(s32) = G_ANYEXT %4(s7)
tschuettUnsubmitted
Done
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Input and output are %4?

tschuett: Input and output are %4?
nitinjohnrajAuthorUnsubmitted
Done
ReplyInline Actions

Thank you for catching this.

nitinjohnraj: Thank you for catching this.
$x10 = COPY %5(s32)
PseudoRET implicit $x10
...
---
name: ashr_i8
body: |
bb.0.entry:
; CHECK-LABEL: name: ashr_i8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
; CHECK-NEXT: $x10 = COPY [[ASHR]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s8) = G_TRUNC %0(s32)
%3:_(s8) = G_TRUNC %1(s32)
%4:_(s8) = G_ASHR %2, %3
%5:_(s32) = G_ANYEXT %4(s8)
$x10 = COPY %5(s32)
PseudoRET implicit $x10
...
---
name: ashr_i16
body: |
bb.0.entry:
; CHECK-LABEL: name: ashr_i16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
; CHECK-NEXT: $x10 = COPY [[ASHR]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s16) = G_TRUNC %0(s32)
%3:_(s16) = G_TRUNC %1(s32)
%4:_(s16) = G_ASHR %2, %3
%5:_(s32) = G_ANYEXT %4(s16)
$x10 = COPY %5(s32)
PseudoRET implicit $x10
...
---
name: ashr_i32
body: |
bb.0.entry:
; CHECK-LABEL: name: ashr_i32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[COPY1]](s32)
; CHECK-NEXT: $x10 = COPY [[ASHR]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s32) = G_ASHR %0, %1
$x10 = COPY %2(s32)
PseudoRET implicit $x10
...

llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-lshr.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s
---
name: lshr_i1
body: |
bb.0.entry:
; CHECK-LABEL: name: lshr_i1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s1) = G_TRUNC %0(s32)
%3:_(s1) = G_TRUNC %1(s32)
%4:_(s1) = G_LSHR %2, %3
%5:_(s32) = G_ANYEXT %4(s1)
$x10 = COPY %5(s32)
PseudoRET implicit $x10
...
---
name: lshr_i8
body: |
bb.0.entry:
; CHECK-LABEL: name: lshr_i8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s8) = G_TRUNC %0(s32)
%3:_(s8) = G_TRUNC %1(s32)
%4:_(s8) = G_LSHR %2, %3
%5:_(s32) = G_ANYEXT %4(s8)
$x10 = COPY %5(s32)
PseudoRET implicit $x10
...
---
name: lshr_i16
body: |
bb.0.entry:
; CHECK-LABEL: name: lshr_i16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s16) = G_TRUNC %0(s32)
%3:_(s16) = G_TRUNC %1(s32)
%4:_(s16) = G_LSHR %2, %3
%5:_(s32) = G_ANYEXT %4(s16)
$x10 = COPY %5(s32)
PseudoRET implicit $x10
...
---
name: lshr_i32
body: |
bb.0.entry:
; CHECK-LABEL: name: lshr_i32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY1]](s32)
; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s32) = G_LSHR %0, %1
$x10 = COPY %2(s32)
PseudoRET implicit $x10
...

llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-shl.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s
---
name: shl_i1
body: |
bb.0.entry:
; CHECK-LABEL: name: shl_i1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32)
; CHECK-NEXT: $x10 = COPY [[SHL]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s1) = G_TRUNC %0(s32)
%3:_(s1) = G_TRUNC %1(s32)
%4:_(s1) = G_SHL %2, %3
%5:_(s32) = G_ANYEXT %4(s1)
$x10 = COPY %5(s32)
PseudoRET implicit $x10
...
---
name: shl_i8
body: |
bb.0.entry:
; CHECK-LABEL: name: shl_i8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32)
; CHECK-NEXT: $x10 = COPY [[SHL]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s8) = G_TRUNC %0(s32)
%3:_(s8) = G_TRUNC %1(s32)
%4:_(s8) = G_SHL %2, %3
%5:_(s32) = G_ANYEXT %4(s8)
$x10 = COPY %5(s32)
PseudoRET implicit $x10
...
---
name: shl_i16
body: |
bb.0.entry:
; CHECK-LABEL: name: shl_i16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32)
; CHECK-NEXT: $x10 = COPY [[SHL]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s16) = G_TRUNC %0(s32)
%3:_(s16) = G_TRUNC %1(s32)
%4:_(s16) = G_SHL %2, %3
%5:_(s32) = G_ANYEXT %4(s16)
$x10 = COPY %5(s32)
PseudoRET implicit $x10
...
---
name: shl_i32
body: |
bb.0.entry:
; CHECK-LABEL: name: shl_i32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
; CHECK-NEXT: $x10 = COPY [[SHL]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s32) = G_SHL %0, %1
$x10 = COPY %2(s32)
PseudoRET implicit $x10
...

llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-ashr.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s
---
name: ashr_i8
body: |
bb.0.entry:
; CHECK-LABEL: name: ashr_i8
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 8
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[AND]](s64)
; CHECK-NEXT: $x10 = COPY [[ASHR]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s8) = G_TRUNC %0(s64)
%3:_(s8) = G_TRUNC %1(s64)
%4:_(s8) = G_ASHR %2, %3
%5:_(s64) = G_ANYEXT %4(s8)
$x10 = COPY %5(s64)
PseudoRET implicit $x10
...
---
name: ashr_i15
body: |
bb.0.entry:
; CHECK-LABEL: name: ashr_i1
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32767
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 15
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[AND]](s64)
; CHECK-NEXT: $x10 = COPY [[ASHR]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s15) = G_TRUNC %0(s64)
%3:_(s15) = G_TRUNC %1(s64)
%4:_(s15) = G_ASHR %2, %3
%5:_(s64) = G_ANYEXT %4(s15)
$x10 = COPY %5(s64)
PseudoRET implicit $x10
...
---
name: ashr_i16
body: |
bb.0.entry:
; CHECK-LABEL: name: ashr_i16
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 16
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[AND]](s64)
; CHECK-NEXT: $x10 = COPY [[ASHR]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s16) = G_TRUNC %0(s64)
%3:_(s16) = G_TRUNC %1(s64)
%4:_(s16) = G_ASHR %2, %3
%5:_(s64) = G_ANYEXT %4(s16)
$x10 = COPY %5(s64)
PseudoRET implicit $x10
...
---
name: ashr_i32
body: |
bb.0.entry:
; CHECK-LABEL: name: ashr_i32
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[AND]](s64)
; CHECK-NEXT: $x10 = COPY [[ASHR]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s32) = G_TRUNC %0(s64)
%3:_(s32) = G_TRUNC %1(s64)
%4:_(s32) = G_ASHR %2, %3
%5:_(s64) = G_ANYEXT %4(s32)
$x10 = COPY %5(s64)
PseudoRET implicit $x10
...
---
name: ashr_i64
body: |
bb.0.entry:
; CHECK-LABEL: name: ashr_i64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[COPY1]](s64)
; CHECK-NEXT: $x10 = COPY [[ASHR]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s64) = G_ASHR %0, %1
$x10 = COPY %2(s64)
PseudoRET implicit $x10
...

llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-lshr.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s
---
name: lshr_i1
body: |
bb.0.entry:
; CHECK-LABEL: name: lshr_i1
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]]
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[AND]](s64)
; CHECK-NEXT: $x10 = COPY [[LSHR]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s1) = G_TRUNC %0(s64)
%3:_(s1) = G_TRUNC %1(s64)
%4:_(s1) = G_LSHR %2, %3
%5:_(s64) = G_ANYEXT %4(s1)
$x10 = COPY %5(s64)
PseudoRET implicit $x10
...
---
name: lshr_i8
body: |
bb.0.entry:
; CHECK-LABEL: name: lshr_i8
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]]
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[AND]](s64)
; CHECK-NEXT: $x10 = COPY [[LSHR]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s8) = G_TRUNC %0(s64)
%3:_(s8) = G_TRUNC %1(s64)
%4:_(s8) = G_LSHR %2, %3
%5:_(s64) = G_ANYEXT %4(s8)
$x10 = COPY %5(s64)
PseudoRET implicit $x10
...
---
name: lshr_i16
body: |
bb.0.entry:
; CHECK-LABEL: name: lshr_i16
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]]
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[AND]](s64)
; CHECK-NEXT: $x10 = COPY [[LSHR]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s16) = G_TRUNC %0(s64)
%3:_(s16) = G_TRUNC %1(s64)
%4:_(s16) = G_LSHR %2, %3
%5:_(s64) = G_ANYEXT %4(s16)
$x10 = COPY %5(s64)
PseudoRET implicit $x10
...
---
name: lshr_i32
body: |
bb.0.entry:
; CHECK-LABEL: name: lshr_i32
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]]
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[AND]](s64)
; CHECK-NEXT: $x10 = COPY [[LSHR]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s32) = G_TRUNC %0(s64)
%3:_(s32) = G_TRUNC %1(s64)
%4:_(s32) = G_LSHR %2, %3
%5:_(s64) = G_ANYEXT %4(s32)
$x10 = COPY %5(s64)
PseudoRET implicit $x10
...
---
name: lshr_i64
body: |
bb.0.entry:
; CHECK-LABEL: name: lshr_i64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[COPY1]](s64)
; CHECK-NEXT: $x10 = COPY [[LSHR]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s64) = G_LSHR %0, %1
$x10 = COPY %2(s64)
PseudoRET implicit $x10
...

llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-shl.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s
---
name: shl_i1
body: |
bb.0.entry:
; CHECK-LABEL: name: shl_i1
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s64)
; CHECK-NEXT: $x10 = COPY [[SHL]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s1) = G_TRUNC %0(s64)
%3:_(s1) = G_TRUNC %1(s64)
%4:_(s1) = G_SHL %2, %3
%5:_(s64) = G_ANYEXT %4(s1)
$x10 = COPY %5(s64)
PseudoRET implicit $x10
...
---
name: shl_i8
body: |
bb.0.entry:
; CHECK-LABEL: name: shl_i8
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s64)
; CHECK-NEXT: $x10 = COPY [[SHL]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s8) = G_TRUNC %0(s64)
%3:_(s8) = G_TRUNC %1(s64)
%4:_(s8) = G_SHL %2, %3
%5:_(s64) = G_ANYEXT %4(s8)
$x10 = COPY %5(s64)
PseudoRET implicit $x10
...
---
name: shl_i16
body: |
bb.0.entry:
; CHECK-LABEL: name: shl_i16
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s64)
; CHECK-NEXT: $x10 = COPY [[SHL]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s16) = G_TRUNC %0(s64)
%3:_(s16) = G_TRUNC %1(s64)
%4:_(s16) = G_SHL %2, %3
%5:_(s64) = G_ANYEXT %4(s16)
$x10 = COPY %5(s64)
PseudoRET implicit $x10
...
---
name: shl_i32
body: |
bb.0.entry:
; CHECK-LABEL: name: shl_i32
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s64)
; CHECK-NEXT: $x10 = COPY [[SHL]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s32) = G_TRUNC %0(s64)
%3:_(s32) = G_TRUNC %1(s64)
%4:_(s32) = G_SHL %2, %3
%5:_(s64) = G_ANYEXT %4(s32)
$x10 = COPY %5(s64)
PseudoRET implicit $x10
...
---
name: shl_i64
body: |
bb.0.entry:
; CHECK-LABEL: name: shl_i64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[COPY1]](s64)
; CHECK-NEXT: $x10 = COPY [[SHL]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s64) = G_SHL %0, %1
$x10 = COPY %2(s64)
PseudoRET implicit $x10
...