[RISCV] Split BEXT and BEXTI Write classes. NFC.

[michaelmaitland]

Summary

BEXT and BEXTI may behave differently from other Zbs instructions.
Split the write classes so these differences may be modeled by
scheduler models.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

 def BCLR : ALU_rr<0b0100100, 0b001, "bclr">,
            Sched<[WriteSingleBit, ReadSingleBit, ReadSingleBit]>;
 def BSET : ALU_rr<0b0010100, 0b001, "bset">,
            Sched<[WriteSingleBit, ReadSingleBit, ReadSingleBit]>;
 def BINV : ALU_rr<0b0110100, 0b001, "binv">,
            Sched<[WriteSingleBit, ReadSingleBit, ReadSingleBit]>;
 let IsSignExtendingOpW = 1 in
 def BEXT : ALU_rr<0b0100100, 0b101, "bext">,
-           Sched<[WriteSingleBit, ReadSingleBit, ReadSingleBit]>;
+           Sched<[WriteBEXT, ReadSingleBit, ReadSingleBit]>;
 
 def BCLRI : RVBShift_ri<0b01001, 0b001, OPC_OP_IMM, "bclri">,
             Sched<[WriteSingleBitImm, ReadSingleBitImm]>;
 def BSETI : RVBShift_ri<0b00101, 0b001, OPC_OP_IMM, "bseti">,
             Sched<[WriteSingleBitImm, ReadSingleBitImm]>;
 def BINVI : RVBShift_ri<0b01101, 0b001, OPC_OP_IMM, "binvi">,
             Sched<[WriteSingleBitImm, ReadSingleBitImm]>;
 let IsSignExtendingOpW = 1 in
 def BEXTI : RVBShift_ri<0b01001, 0b101, OPC_OP_IMM, "bexti">,
-            Sched<[WriteSingleBitImm, ReadSingleBitImm]>;
+            Sched<[WriteBEXTI, ReadSingleBitImm]>;
 } // Predicates = [HasStdExtZbs]
 
 // These instructions were named xperm.n and xperm.b in the last version of
 // the draft bit manipulation specification they were included in. However, we
 // use the mnemonics given to them in the ratified Zbkx extension.
 let Predicates = [HasStdExtZbkx] in {
 def XPERM4 : ALU_rr<0b0010100, 0b010, "xperm4">,
              Sched<[WriteXPERM, ReadXPERM, ReadXPERM]>;

llvm/lib/Target/RISCV/RISCVScheduleZb.td

 def WriteCPOP32      : SchedWrite;
 def WriteREV8        : SchedWrite;
 def WriteORCB        : SchedWrite;
 
 // Zbc extension
 def WriteCLMUL       : SchedWrite; // CLMUL/CLMULR/CLMULH
 
 // Zbs extension
-def WriteSingleBit   : SchedWrite; // BCLR/BSET/BINV/BEXT
-def WriteSingleBitImm: SchedWrite; // BCLRI/BSETI/BINVI/BEXTI
+def WriteSingleBit   : SchedWrite; // BCLR/BSET/BINV
+def WriteSingleBitImm: SchedWrite; // BCLRI/BSETI/BINVI
+def WriteBEXT : SchedWrite; // BEXT
+def WriteBEXTI : SchedWrite; // BEXTI
 
 // Zbkb extension
 def WriteBREV8       : SchedWrite; // brev8
 def WritePACK        : SchedWrite; // pack/packh
 def WritePACK32      : SchedWrite; // packw
 def WriteZIP         : SchedWrite; // zip/unzip
 
 // Zbkx extension

 def : ReadAdvance<ReadCLMUL, 0>;
 }
 }
 
 multiclass UnsupportedSchedZbs {
 let Unsupported = true in {
 def : WriteRes<WriteSingleBit, []>;
 def : WriteRes<WriteSingleBitImm, []>;
+def : WriteRes<WriteBEXT, []>;
+def : WriteRes<WriteBEXTI, []>;
 
 def : ReadAdvance<ReadSingleBit, 0>;
 def : ReadAdvance<ReadSingleBitImm, 0>;
 }
 }
 
 multiclass UnsupportedSchedZbkb {
 let Unsupported = true in {