[RISCV] Simplify operand logic in vmerge combine. NFCI

[luke]

Summary

This patch unifies the operands logic by removing the distinction between True being masked or unmasked.
I find this a bit easier to follow, and it makes an upcoming rework of D153351 simpler.

[luke]

Remove unnecessary if statement

[luke]

Rebase on top of D152996 and handle the new rounding mode operand

[reames]

After staring at this for a while last night and not quite being able to convince myself of the correctness, I went through and split out pieces one at a time this morning - mostly as an exercise in establishing all the intermediate lemmas and justifying it to myself. I think I've landed all the major pieces of this. Can you do one last rebase to see if I missed anything you consider important?

p.s. Thank you for posting it. I definitely agree that the overall result is a lot cleaner.

[luke]

Rebased my D155071 branch on top of it, LGTM. Thanks for chunking it up!

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

 // form.
 bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N) {
 
   SDValue Merge = N->getOperand(0);
   SDValue False = N->getOperand(1);
   SDValue True = N->getOperand(2);
   SDValue Mask = N->getOperand(3);
   SDValue VL = N->getOperand(4);
+  // We always have a glue node for the mask at v0
+  assert(cast<RegisterSDNode>(Mask)->getReg() == RISCV::V0);
+  SDValue Glue = N->getOperand(N->getNumOperands() - 1);
+  assert(Glue.getValueType() == MVT::Glue);
 
   // We require that either merge and false are the same, or that merge
   // is undefined.
   if (Merge != False && !isImplicitDef(Merge))
     return false;
 
   assert(True.getResNo() == 0 &&
          "Expect True is the first output of an instruction.");
if (isImplicitDef(Merge))
       return false;
     SDValue MergeOpTrue = True->getOperand(0);
     // Both the vmerge instruction and the True instruction must have the same
     // merge operand.
     if (False != MergeOpTrue)
       return false;
   }
 
-  if (IsMasked) {
-    assert(HasTiedDest && "Expected tied dest");
-    // The vmerge instruction must be TU.
-    if (isImplicitDef(Merge))
-      return false;
-    // The vmerge instruction must have an all 1s mask since we're going to keep
-    // the mask from the True instruction.
-    // FIXME: Support mask agnostic True instruction which would have an
-    // undef merge operand.
-    if (!usesAllOnesMask(N, /* MaskOpIdx */ 3))
-      return false;
-  }
-
   // Skip if True has side effect.
   // TODO: Support vleff and vlsegff.
   if (TII->get(TrueOpc).hasUnmodeledSideEffects())
     return false;
 
-  // The last operand of a masked instruction may be glued.
+  // Get the operands from True. They take the form:
+  // ([merge] ops* [mask] [rm] vl sew [policy] [chain] [glue])
+  //               ^
+  //               TrueVOpStart
   bool HasGlueOp = True->getGluedNode() != nullptr;
-
   // The chain operand may exist either before the glued operands or in the last
   // position.
-  unsigned TrueChainOpIdx = True.getNumOperands() - HasGlueOp - 1;
-  bool HasChainOp =
-      True.getOperand(TrueChainOpIdx).getValueType() == MVT::Other;
+  unsigned TrueChainIdx = True.getNumOperands() - HasGlueOp - 1;
+  bool HasChainOp = True.getOperand(TrueChainIdx).getValueType() == MVT::Other;
+  bool HasVLOp = RISCVII::hasVLOp(TrueTSFlags);
+  bool HasSEWOp = RISCVII::hasSEWOp(TrueTSFlags);
+  bool HasVecPolicyOp = RISCVII::hasVecPolicyOp(TrueTSFlags);
+  bool HasRoundModeOp = RISCVII::hasRoundModeOp(TrueTSFlags);
+  assert(HasVLOp && HasSEWOp);
+
+  unsigned TrueVOpStart = True.getNumOperands() - HasChainOp - HasGlueOp -
+                          HasVecPolicyOp - HasVLOp - HasSEWOp - HasRoundModeOp -
+                          IsMasked;
+
+  unsigned TrueRoundModeIdx = TrueVOpStart + IsMasked;
+  unsigned TrueVLIdx = TrueVOpStart + IsMasked + HasRoundModeOp;
+  SDValue TrueVL = True.getOperand(TrueVLIdx);
+  SDValue TrueSEW = True.getOperand(TrueVLIdx + 1);
 
   if (HasChainOp) {
     // Avoid creating cycles in the DAG. We must ensure that none of the other
     // operands depend on True through it's Chain.
     SmallVector<const SDNode *, 4> LoopWorklist;
     SmallPtrSet<const SDNode *, 16> Visited;
     LoopWorklist.push_back(False.getNode());
     LoopWorklist.push_back(Mask.getNode());
     LoopWorklist.push_back(VL.getNode());
-    if (SDNode *Glued = N->getGluedNode())
-      LoopWorklist.push_back(Glued);
+    LoopWorklist.push_back(Glue.getNode());
     if (SDNode::hasPredecessorHelper(True.getNode(), Visited, LoopWorklist))
       return false;
   }
 
-  // The vector policy operand may be present for masked intrinsics
-  bool HasVecPolicyOp = RISCVII::hasVecPolicyOp(TrueTSFlags);
-  unsigned TrueVLIndex =
-      True.getNumOperands() - HasVecPolicyOp - HasChainOp - HasGlueOp - 2;
-  SDValue TrueVL = True.getOperand(TrueVLIndex);
+  if (IsMasked) {
+    assert(HasTiedDest && "Expected tied dest");
+    // The vmerge instruction must be TU.
+    if (isImplicitDef(Merge))
+      return false;
+    // The vmerge instruction must have an all 1s mask since we're going to keep
+    // the mask from the True instruction.
+    // FIXME: Support mask agnostic True instruction which would have an
+    // undef merge operand.
+    if (!usesAllOnesMask(N, /* MaskOpIdx */ 3))
+      return false;
+
+    Mask = True->getOperand(TrueVOpStart);
+    assert(True->getGluedNode());
+    Glue = True->getOperand(True->getNumOperands() - 1);
+  }
 
   // We need the VLs to be the same. But if True has a VL of VLMAX then we can
   // go ahead and use N's VL because we know it will be smaller, so any tail
   // elements in the result will be from Merge.
   if (TrueVL != VL && !isAllOnesConstant(TrueVL))
     return false;
 
   // If we end up changing the VL or mask of True, then we need to make sure it
assert(MaskedMCID.getOperandConstraint(MaskedMCID.getNumDefs(),
          "Expected instructions with mask have a tied dest.");
 #endif
 
   uint64_t Policy = isImplicitDef(N->getOperand(0)) ?
     RISCVII::TAIL_AGNOSTIC : /*TUMU*/ 0;
   SDValue PolicyOp =
     CurDAG->getTargetConstant(Policy, DL, Subtarget->getXLenVT());
 
+  // The resulting masked pseudo operands will be in the form:
+  // (merge, ops*, mask, [rm], vl, policy, [chain], glue)
   SmallVector<SDValue, 8> Ops;
-  if (IsMasked) {
-    Ops.push_back(False);
-    Ops.append(True->op_begin() + 1, True->op_begin() + TrueVLIndex);
-    Ops.append({VL, /* SEW */ True.getOperand(TrueVLIndex + 1)});
-    Ops.push_back(PolicyOp);
-    Ops.append(True->op_begin() + TrueVLIndex + 3, True->op_end());
-  } else {
-    Ops.push_back(False);
-    if (RISCVII::hasRoundModeOp(TrueTSFlags)) {
-      // For unmasked "VOp" with rounding mode operand, that is interfaces like
-      // (..., rm, vl) or (..., rm, vl, policy).
-      // Its masked version is (..., vm, rm, vl, policy).
-      // Check the rounding mode pseudo nodes under RISCVInstrInfoVPseudos.td
-      SDValue RoundMode = True->getOperand(TrueVLIndex - 1);
-      Ops.append(True->op_begin() + HasTiedDest,
-                 True->op_begin() + TrueVLIndex - 1);
-      Ops.append(
-          {Mask, RoundMode, VL, /* SEW */ True.getOperand(TrueVLIndex + 1)});
-    } else {
-      Ops.append(True->op_begin() + HasTiedDest,
-                 True->op_begin() + TrueVLIndex);
-      Ops.append({Mask, VL, /* SEW */ True.getOperand(TrueVLIndex + 1)});
-    }
-    Ops.push_back(PolicyOp);
 
-    // Result node should have chain operand of True.
-    if (HasChainOp)
-      Ops.push_back(True.getOperand(TrueChainOpIdx));
+  Ops.append(True->op_begin() + HasTiedDest, True->op_begin() + TrueVOpStart);
+
+  Ops.push_back(Mask);
+
+  if (HasRoundModeOp)
+    Ops.push_back(True.getOperand(TrueRoundModeIdx));
+
+  Ops.append({VL, TrueSEW, PolicyOp});
+
+  // True might have a chain, e.g. if it's a load
+    Ops.push_back(True.getOperand(TrueChainIdx));
 
-    if (N->getGluedNode())
-      Ops.push_back(N->getOperand(N->getNumOperands() - 1));
-  }
+  // Add the glue for the CopyToReg of mask->v0.
+  Ops.push_back(Glue);
 
   SDNode *Result =
       CurDAG->getMachineNode(MaskedOpc, DL, True->getVTList(), Ops);
   Result->setFlags(True->getFlags());
 
   // Replace vmerge.vvm node by Result.
   ReplaceUses(SDValue(N, 0), SDValue(Result, 0));