This is an archive of the discontinued LLVM Phabricator instance.

Differential D154929

[RISCV] Move foreach to multiclass defination, NFC.
Needs ReviewPublic

Authored by jacquesguan on Jul 11 2023, 1:17 AM.

Details

Reviewers
craig.topper
asb
luismarques
frasercrmck
Summary

This patch moves some foreach back to the multiclass defination to reduce scope and argument. It also keeps consistent with other definations.

Diff Detail

Event Timeline

jacquesguan created this revision.Jul 11 2023, 1:17 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 11 2023, 1:17 AM
Herald added subscribers: jobnoorman, luke, VincentWu and 25 others. · View Herald Transcript
jacquesguan requested review of this revision.Jul 11 2023, 1:17 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 11 2023, 1:17 AM
Herald added subscribers: llvm-commits, wangpc, eopXD, MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B244368: Diff 538955.Jul 11 2023, 2:32 AM

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
243 lines

Diff 538955

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

Show First 20 Lines • Show All 814 Lines • ▼ Show 20 Lines def : Pat<(fvti.Vector (vop (SplatFPOp fvti.ScalarRegClass:$rs2),
instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK", instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK",
instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_MASK")) instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_MASK"))
fvti.RegClass:$merge, fvti.RegClass:$merge,
fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2, fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2,
(fvti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>; (fvti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>;
} }
} }
multiclass VPatIntegerSetCCVL_VV<VTypeInfo vti, string instruction_name, multiclass VPatIntegerSetCCVL_VV<string instruction_name, CondCode cc> {
CondCode cc> { foreach vti = AllIntegerVectors in
let Predicates = GetVTypePredicates<vti>.Predicates in
def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1),
vti.RegClass:$rs2, cc, vti.RegClass:$rs2, cc,
VR:$merge, VR:$merge,
(vti.Mask V0), (vti.Mask V0),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX#"_MASK") (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX#"_MASK")
VR:$merge, VR:$merge,
vti.RegClass:$rs1, vti.RegClass:$rs1,
vti.RegClass:$rs2, vti.RegClass:$rs2,
(vti.Mask V0), GPR:$vl, vti.Log2SEW)>; (vti.Mask V0), GPR:$vl, vti.Log2SEW)>;
} }
// Inherits from VPatIntegerSetCCVL_VV and adds a pattern with operands swapped. // Inherits from VPatIntegerSetCCVL_VV and adds a pattern with operands swapped.
multiclass VPatIntegerSetCCVL_VV_Swappable<VTypeInfo vti, string instruction_name, multiclass VPatIntegerSetCCVL_VV_Swappable<string instruction_name,
CondCode cc, CondCode invcc> CondCode cc, CondCode invcc>
: VPatIntegerSetCCVL_VV<vti, instruction_name, cc> { : VPatIntegerSetCCVL_VV<instruction_name, cc> {
foreach vti = AllIntegerVectors in
let Predicates = GetVTypePredicates<vti>.Predicates in
def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs2), def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs2),
vti.RegClass:$rs1, invcc, vti.RegClass:$rs1, invcc,
VR:$merge, VR:$merge,
(vti.Mask V0), (vti.Mask V0),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX#"_MASK") (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX#"_MASK")
VR:$merge, vti.RegClass:$rs1, VR:$merge, vti.RegClass:$rs1, vti.RegClass:$rs2,
vti.RegClass:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; (vti.Mask V0), GPR:$vl, vti.Log2SEW)>;
} }
multiclass VPatIntegerSetCCVL_VX_Swappable<VTypeInfo vti, string instruction_name, multiclass VPatIntegerSetCCVL_VX_Swappable<string instruction_name,
CondCode cc, CondCode invcc> { CondCode cc, CondCode invcc> {
foreach vti = AllIntegerVectors in {
defvar instruction_masked = !cast<Instruction>(instruction_name#"_VX_"#vti.LMul.MX#"_MASK"); defvar instruction_masked = !cast<Instruction>(instruction_name#"_VX_"#vti.LMul.MX#"_MASK");
let Predicates = GetVTypePredicates<vti>.Predicates in {
def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1),
(SplatPat (XLenVT GPR:$rs2)), cc, (SplatPat (XLenVT GPR:$rs2)), cc,
VR:$merge, VR:$merge,
(vti.Mask V0), (vti.Mask V0),
VLOpFrag)), VLOpFrag)),
(instruction_masked VR:$merge, vti.RegClass:$rs1, (instruction_masked VR:$merge, vti.RegClass:$rs1, GPR:$rs2,
GPR:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; (vti.Mask V0), GPR:$vl, vti.Log2SEW)>;
def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat (XLenVT GPR:$rs2)), def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat (XLenVT GPR:$rs2)),
(vti.Vector vti.RegClass:$rs1), invcc, (vti.Vector vti.RegClass:$rs1), invcc,
VR:$merge, VR:$merge,
(vti.Mask V0), (vti.Mask V0),
VLOpFrag)), VLOpFrag)),
(instruction_masked VR:$merge, vti.RegClass:$rs1, (instruction_masked VR:$merge, vti.RegClass:$rs1, GPR:$rs2,
GPR:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; (vti.Mask V0), GPR:$vl, vti.Log2SEW)>;
}
}
} }
multiclass VPatIntegerSetCCVL_VI_Swappable<VTypeInfo vti, string instruction_name, multiclass VPatIntegerSetCCVL_VI_Swappable<string instruction_name,
CondCode cc, CondCode invcc> { CondCode cc, CondCode invcc> {
foreach vti = AllIntegerVectors in {
defvar instruction_masked = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX#"_MASK"); defvar instruction_masked = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX#"_MASK");
let Predicates = GetVTypePredicates<vti>.Predicates in {
def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1),
(SplatPat_simm5 simm5:$rs2), cc, (SplatPat_simm5 simm5:$rs2), cc,
VR:$merge, VR:$merge,
(vti.Mask V0), (vti.Mask V0),
VLOpFrag)), VLOpFrag)),
(instruction_masked VR:$merge, vti.RegClass:$rs1, (instruction_masked VR:$merge, vti.RegClass:$rs1,
XLenVT:$rs2, (vti.Mask V0), GPR:$vl, XLenVT:$rs2, (vti.Mask V0), GPR:$vl,
vti.Log2SEW)>; vti.Log2SEW)>;
// FIXME: Can do some canonicalization to remove these patterns. // FIXME: Can do some canonicalization to remove these patterns.
def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat_simm5 simm5:$rs2), def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat_simm5 simm5:$rs2),
(vti.Vector vti.RegClass:$rs1), invcc, (vti.Vector vti.RegClass:$rs1), invcc,
VR:$merge, VR:$merge,
(vti.Mask V0), (vti.Mask V0),
VLOpFrag)), VLOpFrag)),
(instruction_masked VR:$merge, vti.RegClass:$rs1, (instruction_masked VR:$merge, vti.RegClass:$rs1,
simm5:$rs2, (vti.Mask V0), GPR:$vl, simm5:$rs2, (vti.Mask V0), GPR:$vl,
vti.Log2SEW)>; vti.Log2SEW)>;
} }
}
}
multiclass VPatIntegerSetCCVL_VIPlus1_Swappable<VTypeInfo vti, multiclass VPatIntegerSetCCVL_VIPlus1_Swappable<string instruction_name,
string instruction_name,
CondCode cc, CondCode invcc, CondCode cc, CondCode invcc,
ComplexPattern splatpat_kind> { ComplexPattern splatpat_kind> {
foreach vti = AllIntegerVectors in {
defvar instruction_masked = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX#"_MASK"); defvar instruction_masked = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX#"_MASK");
let Predicates = GetVTypePredicates<vti>.Predicates in {
def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1),
(splatpat_kind simm5:$rs2), cc, (splatpat_kind simm5:$rs2), cc,
VR:$merge, VR:$merge,
(vti.Mask V0), (vti.Mask V0),
VLOpFrag)), VLOpFrag)),
(instruction_masked VR:$merge, vti.RegClass:$rs1, (instruction_masked VR:$merge, vti.RegClass:$rs1,
(DecImm simm5:$rs2), (vti.Mask V0), GPR:$vl, (DecImm simm5:$rs2), (vti.Mask V0), GPR:$vl,
vti.Log2SEW)>; vti.Log2SEW)>;
// FIXME: Can do some canonicalization to remove these patterns. // FIXME: Can do some canonicalization to remove these patterns.
def : Pat<(vti.Mask (riscv_setcc_vl (splatpat_kind simm5:$rs2), def : Pat<(vti.Mask (riscv_setcc_vl (splatpat_kind simm5:$rs2),
(vti.Vector vti.RegClass:$rs1), invcc, (vti.Vector vti.RegClass:$rs1), invcc,
VR:$merge, VR:$merge,
(vti.Mask V0), (vti.Mask V0),
VLOpFrag)), VLOpFrag)),
(instruction_masked VR:$merge, vti.RegClass:$rs1, (instruction_masked VR:$merge, vti.RegClass:$rs1,
(DecImm simm5:$rs2), (vti.Mask V0), GPR:$vl, (DecImm simm5:$rs2), (vti.Mask V0), GPR:$vl,
vti.Log2SEW)>; vti.Log2SEW)>;
} }
}
}
multiclass VPatFPSetCCVL_VV_VF_FV<SDPatternOperator vop, CondCode cc, multiclass VPatFPSetCCVL_VV_VF_FV<SDPatternOperator vop, CondCode cc,
string inst_name, string inst_name,
string swapped_op_inst_name> { string swapped_op_inst_name> {
foreach fvti = AllFloatVectors in { foreach fvti = AllFloatVectors in {
let Predicates = GetVTypePredicates<fvti>.Predicates in { let Predicates = GetVTypePredicates<fvti>.Predicates in {
def : Pat<(fvti.Mask (vop (fvti.Vector fvti.RegClass:$rs1), def : Pat<(fvti.Mask (vop (fvti.Vector fvti.RegClass:$rs1),
fvti.RegClass:$rs2, fvti.RegClass:$rs2,
▲ Show 20 Lines • Show All 724 Lines • ▼ Show 20 Lines def : Pat<(vti.Vector (riscv_trunc_vector_vl (wti.Vector wti.RegClass:$rs1),
(vti.Mask V0), (vti.Mask V0),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>("PseudoVNSRL_WI_"#vti.LMul.MX#"_MASK") (!cast<Instruction>("PseudoVNSRL_WI_"#vti.LMul.MX#"_MASK")
(vti.Vector (IMPLICIT_DEF)), wti.RegClass:$rs1, 0, (vti.Vector (IMPLICIT_DEF)), wti.RegClass:$rs1, 0,
(vti.Mask V0), GPR:$vl, vti.Log2SEW, TA_MA)>; (vti.Mask V0), GPR:$vl, vti.Log2SEW, TA_MA)>;
} }
// 11.8. Vector Integer Comparison Instructions // 11.8. Vector Integer Comparison Instructions
foreach vti = AllIntegerVectors in { defm : VPatIntegerSetCCVL_VV<"PseudoVMSEQ", SETEQ>;
let Predicates = GetVTypePredicates<vti>.Predicates in { defm : VPatIntegerSetCCVL_VV<"PseudoVMSNE", SETNE>;
defm : VPatIntegerSetCCVL_VV<vti, "PseudoVMSEQ", SETEQ>;
defm : VPatIntegerSetCCVL_VV<vti, "PseudoVMSNE", SETNE>; defm : VPatIntegerSetCCVL_VV_Swappable<"PseudoVMSLT", SETLT, SETGT>;
defm : VPatIntegerSetCCVL_VV_Swappable<"PseudoVMSLTU", SETULT, SETUGT>;
defm : VPatIntegerSetCCVL_VV_Swappable<"PseudoVMSLE", SETLE, SETGE>;
defm : VPatIntegerSetCCVL_VV_Swappable<"PseudoVMSLEU", SETULE, SETUGE>;
defm : VPatIntegerSetCCVL_VX_Swappable<"PseudoVMSEQ", SETEQ, SETEQ>;
defm : VPatIntegerSetCCVL_VX_Swappable<"PseudoVMSNE", SETNE, SETNE>;
defm : VPatIntegerSetCCVL_VX_Swappable<"PseudoVMSLT", SETLT, SETGT>;
defm : VPatIntegerSetCCVL_VX_Swappable<"PseudoVMSLTU", SETULT, SETUGT>;
defm : VPatIntegerSetCCVL_VX_Swappable<"PseudoVMSLE", SETLE, SETGE>;
defm : VPatIntegerSetCCVL_VX_Swappable<"PseudoVMSLEU", SETULE, SETUGE>;
defm : VPatIntegerSetCCVL_VX_Swappable<"PseudoVMSGT", SETGT, SETLT>;
defm : VPatIntegerSetCCVL_VX_Swappable<"PseudoVMSGTU", SETUGT, SETULT>;
defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLT", SETLT, SETGT>;
defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>;
defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>;
defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>;
defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSEQ", SETEQ, SETEQ>;
defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSNE", SETNE, SETNE>;
defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLT", SETLT, SETGT>;
defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>;
defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>;
defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>;
defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGT", SETGT, SETLT>;
defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>;
// There is no VMSGE(U)_VX instruction // There is no VMSGE(U)_VX instruction
defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSEQ", SETEQ, SETEQ>; defm : VPatIntegerSetCCVL_VI_Swappable<"PseudoVMSEQ", SETEQ, SETEQ>;
defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSNE", SETNE, SETNE>; defm : VPatIntegerSetCCVL_VI_Swappable<"PseudoVMSNE", SETNE, SETNE>;
defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>; defm : VPatIntegerSetCCVL_VI_Swappable<"PseudoVMSLE", SETLE, SETGE>;
defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>; defm : VPatIntegerSetCCVL_VI_Swappable<"PseudoVMSLEU", SETULE, SETUGE>;
defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGT", SETGT, SETLT>; defm : VPatIntegerSetCCVL_VI_Swappable<"PseudoVMSGT", SETGT, SETLT>;
defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>; defm : VPatIntegerSetCCVL_VI_Swappable<"PseudoVMSGTU", SETUGT, SETULT>;
defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSLE", SETLT, SETGT, defm : VPatIntegerSetCCVL_VIPlus1_Swappable<"PseudoVMSLE", SETLT, SETGT,
SplatPat_simm5_plus1>; SplatPat_simm5_plus1>;
defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSLEU", SETULT, SETUGT, defm : VPatIntegerSetCCVL_VIPlus1_Swappable<"PseudoVMSLEU", SETULT, SETUGT,
SplatPat_simm5_plus1_nonzero>; SplatPat_simm5_plus1_nonzero>;
defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSGT", SETGE, SETLE, defm : VPatIntegerSetCCVL_VIPlus1_Swappable<"PseudoVMSGT", SETGE, SETLE,
SplatPat_simm5_plus1>; SplatPat_simm5_plus1>;
defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSGTU", SETUGE, SETULE, defm : VPatIntegerSetCCVL_VIPlus1_Swappable<"PseudoVMSGTU", SETUGE, SETULE,
SplatPat_simm5_plus1_nonzero>; SplatPat_simm5_plus1_nonzero>;
}
} // foreach vti = AllIntegerVectors
// 11.9. Vector Integer Min/Max Instructions // 11.9. Vector Integer Min/Max Instructions
defm : VPatBinaryVL_VV_VX<riscv_umin_vl, "PseudoVMINU">; defm : VPatBinaryVL_VV_VX<riscv_umin_vl, "PseudoVMINU">;
defm : VPatBinaryVL_VV_VX<riscv_smin_vl, "PseudoVMIN">; defm : VPatBinaryVL_VV_VX<riscv_smin_vl, "PseudoVMIN">;
defm : VPatBinaryVL_VV_VX<riscv_umax_vl, "PseudoVMAXU">; defm : VPatBinaryVL_VV_VX<riscv_umax_vl, "PseudoVMAXU">;
defm : VPatBinaryVL_VV_VX<riscv_smax_vl, "PseudoVMAX">; defm : VPatBinaryVL_VV_VX<riscv_smax_vl, "PseudoVMAX">;
// 11.10. Vector Single-Width Integer Multiply Instructions // 11.10. Vector Single-Width Integer Multiply Instructions
▲ Show 20 Lines • Show All 788 Lines • Show Last 20 Lines