Add the scheduling model for Neoverse V1.
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Cool! Is there a code snippet where llvm-mca can show the differences between the N* and V*?
llvm/test/tools/llvm-mca/AArch64/Neoverse/512tvb-sve-instructions.s | ||
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3–4 | Nit: V1 model? |
Looks like another good addition. Thanks for working on this.
llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td | ||
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30 | Does it help to add SVE2 too? | |
59 | J is invented to model the instructions that set flags, that have a throughput of 3? | |
472 | These are mostly ALU instructions. | |
llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-neon-instructions.s | ||
23 | The Neoverse-V2 version of this file has some extra instructions like addv's, aes and some dup instructions, among others. |
llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td | ||
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30 | The Neoverse V1 does not support Armv9. | |
59 | Correct, gleaned from similar AArch32 instructions. | |
llvm/test/tools/llvm-mca/AArch64/Neoverse/512tvb-sve-instructions.s | ||
3–4 | Perhaps it deserves a more comprehensive test case than just a single instruction. | |
llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-neon-instructions.s | ||
23 | It has many more instructions, but SVE2 ones. I'll add more coverage here. |
llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td | ||
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30 | Yep, that's my point (If I understand what you are saying). It doesn't have SVE2, only SVE1. And doesn't have SME and MTE too. Hence adding it to the list of unsupported features could help cut down on the number of unsupported instructions that it thinks are missing. | |
llvm/test/tools/llvm-mca/AArch64/Neoverse/512tvb-sve-instructions.s | ||
3–4 | Sounds like the comment still needs updating. | |
llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-neon-instructions.s | ||
23 | Thanks - And what about the extra Neon instructions? |
llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-neon-instructions.s | ||
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23 | There were only a handfull of Neon instructions missing that were added here. |
llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td | ||
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950 | This is only used in regexes, so likely doesn't need to change. Is NeoverseMULIdiomPred being added because the V1 uses WriteIM64 and that is used for mulhi too? They both have overrides for SMULHrr/UMULHrr, so I'm not sure this will do anything over using IsReg3ZeroPred directly. Otherwise it looks like IsReg3ZeroPred is now unused, if you did have a reason to stick with NeoverseMULIdiomPred. | |
llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-neon-instructions.s | ||
23 | I still see differences between diff llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-neon-instructions.s llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-neon-instructions.s It would be good to make sure that we are not missing coverage of some of the neon instructions. |
llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td | ||
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950 | In V1, multiply high has its own SchedWriteRes. NeoverseMULIdiomPred does use the predicate CheckIsReg3Zero, on which IsReg3ZeroPred is based on. |
Does it help to add SVE2 too?