[RISCV] Split __builtin_riscv_brev8 into _32 and _64 builtin.

[craig.topper]

Summary

Allow _32 builtin on RV64 since it only brev8+sext.w.

Part of an effort to remove 'long' to mean XLen from the builtin
interface.

Matches the proposal here https://github.com/riscv-non-isa/riscv-c-api-doc/pull/44

[asb]

LGTM.

clang/include/clang/Basic/BuiltinsRISCV.def

 TARGET_BUILTIN(__builtin_riscv_clmulh, "LiLiLi", "nc", "zbc|zbkc")
 TARGET_BUILTIN(__builtin_riscv_clmulr, "LiLiLi", "nc", "zbc")
 
 // Zbkx
 TARGET_BUILTIN(__builtin_riscv_xperm4, "LiLiLi", "nc", "zbkx")
 TARGET_BUILTIN(__builtin_riscv_xperm8, "LiLiLi", "nc", "zbkx")
 
 // Zbkb extension
-TARGET_BUILTIN(__builtin_riscv_brev8, "LiLi", "nc", "zbkb")
+TARGET_BUILTIN(__builtin_riscv_brev8_32, "ii", "nc", "zbkb")
+TARGET_BUILTIN(__builtin_riscv_brev8_64, "WiWi", "nc", "zbkb,64bit")
 TARGET_BUILTIN(__builtin_riscv_zip_32, "ZiZi", "nc", "zbkb,32bit")
 TARGET_BUILTIN(__builtin_riscv_unzip_32, "ZiZi", "nc", "zbkb,32bit")
 
 // Zknd extension
 TARGET_BUILTIN(__builtin_riscv_aes32dsi_32, "ZiZiZiIUi", "nc", "zknd,32bit")
 TARGET_BUILTIN(__builtin_riscv_aes32dsmi_32, "ZiZiZiIUi", "nc", "zknd,32bit")
 TARGET_BUILTIN(__builtin_riscv_aes64ds_64, "WiWiWi", "nc", "zknd,64bit")
 TARGET_BUILTIN(__builtin_riscv_aes64dsm_64, "WiWiWi", "nc", "zknd,64bit")

clang/lib/CodeGen/CGBuiltin.cpp

 //===---- CGBuiltin.cpp - Emit LLVM Code for builtins ---------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
   case RISCV::BI__builtin_riscv_clz_64:
   case RISCV::BI__builtin_riscv_ctz_32:
   case RISCV::BI__builtin_riscv_ctz_64:
   case RISCV::BI__builtin_riscv_clmul:
   case RISCV::BI__builtin_riscv_clmulh:
   case RISCV::BI__builtin_riscv_clmulr:
   case RISCV::BI__builtin_riscv_xperm4:
   case RISCV::BI__builtin_riscv_xperm8:
-  case RISCV::BI__builtin_riscv_brev8:
+  case RISCV::BI__builtin_riscv_brev8_32:
+  case RISCV::BI__builtin_riscv_brev8_64:
   case RISCV::BI__builtin_riscv_zip_32:
   case RISCV::BI__builtin_riscv_unzip_32: {
     switch (BuiltinID) {
     default: llvm_unreachable("unexpected builtin ID");
     // Zbb
     case RISCV::BI__builtin_riscv_orc_b_32:
     case RISCV::BI__builtin_riscv_orc_b_64:
       ID = Intrinsic::riscv_orc_b;
case RISCV::BI__builtin_riscv_unzip_32: {
     case RISCV::BI__builtin_riscv_xperm8:
       ID = Intrinsic::riscv_xperm8;
       break;
     case RISCV::BI__builtin_riscv_xperm4:
       ID = Intrinsic::riscv_xperm4;
       break;
 
     // Zbkb
-    case RISCV::BI__builtin_riscv_brev8:
+    case RISCV::BI__builtin_riscv_brev8_32:
+    case RISCV::BI__builtin_riscv_brev8_64:
       ID = Intrinsic::riscv_brev8;
       break;
     case RISCV::BI__builtin_riscv_zip_32:
       ID = Intrinsic::riscv_zip;
       break;
     case RISCV::BI__builtin_riscv_unzip_32:
       ID = Intrinsic::riscv_unzip;
       break;

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c

 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // RUN: %clang_cc1 -triple riscv32 -target-feature +zbkb -emit-llvm %s -o - \
 // RUN:     | FileCheck %s  -check-prefix=RV32ZBKB
 
 // RV32ZBKB-LABEL: @brev8(
 // RV32ZBKB-NEXT:  entry:
 // RV32ZBKB-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
 // RV32ZBKB-NEXT:    store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
 // RV32ZBKB-NEXT:    [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
 // RV32ZBKB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.brev8.i32(i32 [[TMP0]])
 // RV32ZBKB-NEXT:    ret i32 [[TMP1]]
 //
-long brev8(long rs1)
+int brev8(int rs1)
 {
-  return __builtin_riscv_brev8(rs1);
+  return __builtin_riscv_brev8_32(rs1);
 }
 
 // RV32ZBKB-LABEL: @zip(
 // RV32ZBKB-NEXT:  entry:
 // RV32ZBKB-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
 // RV32ZBKB-NEXT:    store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
 // RV32ZBKB-NEXT:    [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
 // RV32ZBKB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.zip.i32(i32 [[TMP0]])

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c

 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // RUN: %clang_cc1 -triple riscv64 -target-feature +zbkb -emit-llvm %s -o - \
 // RUN:     | FileCheck %s  -check-prefix=RV64ZBKB
 
-// RV64ZBKB-LABEL: @brev8(
+// RV64ZBKB-LABEL: @brev8_32(
+// RV64ZBKB-NEXT:  entry:
+// RV64ZBKB-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBKB-NEXT:    store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
+// RV64ZBKB-NEXT:    [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
+// RV64ZBKB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.brev8.i32(i32 [[TMP0]])
+// RV64ZBKB-NEXT:    ret i32 [[TMP1]]
+//
+int brev8_32(int rs1)
+{
+  return __builtin_riscv_brev8_32(rs1);
+}
+
+// RV64ZBKB-LABEL: @brev8_64(
 // RV64ZBKB-NEXT:  entry:
 // RV64ZBKB-NEXT:    [[RS1_ADDR:%.*]] = alloca i64, align 8
 // RV64ZBKB-NEXT:    store i64 [[RS1:%.*]], ptr [[RS1_ADDR]], align 8
 // RV64ZBKB-NEXT:    [[TMP0:%.*]] = load i64, ptr [[RS1_ADDR]], align 8
 // RV64ZBKB-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.brev8.i64(i64 [[TMP0]])
 // RV64ZBKB-NEXT:    ret i64 [[TMP1]]
 //
-long brev8(long rs1)
+long brev8_64(long rs1)
 {
-  return __builtin_riscv_brev8(rs1);
+  return __builtin_riscv_brev8_64(rs1);
 }