[X86] Preserve volatile ATOMIC_LOAD_OR nodes

[n-omer]

Summary

Fixes #63692.

In reference to volatile memory accesses, the langref says (https://llvm.org/docs/LangRef.html#volatile-memory-accesses):

the backend should never split or merge target-legal volatile load/store instructions.

Which was not being upheld.

[n-omer]

Add test.

[RKSimon]

Please can you pre-commit the test with current (trunk) codegen and then rebase the patch to show the codegen diff?

[n-omer]

Rebase.

[pengfei]

This comment was removed by pengfei.

[pengfei]

LGTM.

llvm/lib/Target/X86/X86ISelLowering.cpp

if (N->hasAnyUseOfValue(0)) {
     return N;
   }
 
   // Specialized lowering for the canonical form of an idemptotent atomicrmw.
   // The core idea here is that since the memory location isn't actually
   // changing, all we need is a lowering for the *ordering* impacts of the
   // atomicrmw.  As such, we can chose a different operation and memory
   // location to minimize impact on other code.
-  if (Opc == ISD::ATOMIC_LOAD_OR && isNullConstant(RHS)) {
+  // The above holds unless the node is marked volatile in which
+  // case it needs to be preserved according to the langref.
+  if (Opc == ISD::ATOMIC_LOAD_OR && isNullConstant(RHS) && !AN->isVolatile()) {
     // On X86, the only ordering which actually requires an instruction is
     // seq_cst which isn't SingleThread, everything just needs to be preserved
     // during codegen and then dropped. Note that we expect (but don't assume),
     // that orderings other than seq_cst and acq_rel have been canonicalized to
     // a store or load.
     if (AN->getSuccessOrdering() == AtomicOrdering::SequentiallyConsistent &&
         AN->getSyncScopeID() == SyncScope::System) {
       // Prefer a locked operation against a stack location to minimize cache

llvm/test/CodeGen/X86/pr63692.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
 ; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
 
 define void @prefault(ptr noundef %range_start, ptr noundef readnone %range_end) {
 ; CHECK-LABEL: prefault:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpq %rsi, %rdi
 ; CHECK-NEXT:    jae .LBB0_3
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  .LBB0_1: # %while.body
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    #MEMBARRIER
+; CHECK-NEXT:    lock orb $0, (%rdi)
 ; CHECK-NEXT:    addq $4096, %rdi # imm = 0x1000
 ; CHECK-NEXT:    cmpq %rsi, %rdi
 ; CHECK-NEXT:    jb .LBB0_1
 ; CHECK-NEXT:  .LBB0_3: # %while.end
 ; CHECK-NEXT:    retq
 entry:
   %cmp3 = icmp ult ptr %range_start, %range_end
   br i1 %cmp3, label %while.body, label %while.end