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Differential D154572

[RISCV] Use 'long' in aes64 Zknd/Zkne builtin tests. NFC
ClosedPublic

Authored by craig.topper on Jul 6 2023, 12:10 AM.

Details

Reviewers
asb
VincentWu
kito-cheng
Commits
rGac03e3f51c27: [RISCV] Use 'long' in aes64 Zknd/Zkne builtin tests. NFC
Summary

This matches the data type of the intrinsics. This case be seen
from the removal of sext and trunc instructions from the IR.

Diff Detail

Event Timeline

craig.topper created this revision.Jul 6 2023, 12:10 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 6 2023, 12:10 AM
Herald added subscribers: jobnoorman, luke, vkmr and 24 others. · View Herald Transcript
craig.topper requested review of this revision.Jul 6 2023, 12:10 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 6 2023, 12:10 AM
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craig.topper retitled this revision from [RISCV] Use 'long' in aes64 Zknd/Zkne builtin tests. to [RISCV] Use 'long' in aes64 Zknd/Zkne builtin tests. NFC.Jul 6 2023, 12:10 AM
Harbormaster completed remote builds in B243391: Diff 537608.Jul 6 2023, 12:38 AM
kito-cheng accepted this revision.Jul 6 2023, 1:05 AM

LGTM

This revision is now accepted and ready to land.Jul 6 2023, 1:05 AM
This revision was landed with ongoing or failed builds.Jul 6 2023, 1:14 AM
Closed by commit rGac03e3f51c27: [RISCV] Use 'long' in aes64 Zknd/Zkne builtin tests. NFC (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rGac03e3f51c27: [RISCV] Use 'long' in aes64 Zknd/Zkne builtin tests. NFC.

Revision Contents

PathSize
clang/
test/
CodeGen/
RISCV/
rvk-intrinsics/
35 lines
56 lines
42 lines

Diff 537619

clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple riscv64 -target-feature +zknd -emit-llvm %s -o - \ // RUN: %clang_cc1 -triple riscv64 -target-feature +zknd -emit-llvm %s -o - \
// RUN: | FileCheck %s -check-prefix=RV64ZKND-ZKNE // RUN: | FileCheck %s -check-prefix=RV64ZKND-ZKNE
// RUN: %clang_cc1 -triple riscv64 -target-feature +zkne -emit-llvm %s -o - \ // RUN: %clang_cc1 -triple riscv64 -target-feature +zkne -emit-llvm %s -o - \
// RUN: | FileCheck %s -check-prefix=RV64ZKND-ZKNE // RUN: | FileCheck %s -check-prefix=RV64ZKND-ZKNE
// RV64ZKND-ZKNE-LABEL: @aes64ks1i( // RV64ZKND-ZKNE-LABEL: @aes64ks1i(
// RV64ZKND-ZKNE-NEXT: entry: // RV64ZKND-ZKNE-NEXT: entry:
// RV64ZKND-ZKNE-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4 // RV64ZKND-ZKNE-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
// RV64ZKND-ZKNE-NEXT: store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4 // RV64ZKND-ZKNE-NEXT: store i64 [[RS1:%.*]], ptr [[RS1_ADDR]], align 8
// RV64ZKND-ZKNE-NEXT: [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4 // RV64ZKND-ZKNE-NEXT: [[TMP0:%.*]] = load i64, ptr [[RS1_ADDR]], align 8
// RV64ZKND-ZKNE-NEXT: [[CONV:%.*]] = sext i32 [[TMP0]] to i64 // RV64ZKND-ZKNE-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.aes64ks1i(i64 [[TMP0]], i32 0)
// RV64ZKND-ZKNE-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.aes64ks1i(i64 [[CONV]], i32 0) // RV64ZKND-ZKNE-NEXT: ret i64 [[TMP1]]
// RV64ZKND-ZKNE-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
// RV64ZKND-ZKNE-NEXT: ret i32 [[CONV1]]
// //
int aes64ks1i(int rs1) { long aes64ks1i(long rs1) {
return __builtin_riscv_aes64ks1i_64(rs1, 0); return __builtin_riscv_aes64ks1i_64(rs1, 0);
} }
// RV64ZKND-ZKNE-LABEL: @aes64ks2( // RV64ZKND-ZKNE-LABEL: @aes64ks2(
// RV64ZKND-ZKNE-NEXT: entry: // RV64ZKND-ZKNE-NEXT: entry:
// RV64ZKND-ZKNE-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4 // RV64ZKND-ZKNE-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
// RV64ZKND-ZKNE-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4 // RV64ZKND-ZKNE-NEXT: [[RS2_ADDR:%.*]] = alloca i64, align 8
// RV64ZKND-ZKNE-NEXT: store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4 // RV64ZKND-ZKNE-NEXT: store i64 [[RS1:%.*]], ptr [[RS1_ADDR]], align 8
// RV64ZKND-ZKNE-NEXT: store i32 [[RS2:%.*]], ptr [[RS2_ADDR]], align 4 // RV64ZKND-ZKNE-NEXT: store i64 [[RS2:%.*]], ptr [[RS2_ADDR]], align 8
// RV64ZKND-ZKNE-NEXT: [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4 // RV64ZKND-ZKNE-NEXT: [[TMP0:%.*]] = load i64, ptr [[RS1_ADDR]], align 8
// RV64ZKND-ZKNE-NEXT: [[CONV:%.*]] = sext i32 [[TMP0]] to i64 // RV64ZKND-ZKNE-NEXT: [[TMP1:%.*]] = load i64, ptr [[RS2_ADDR]], align 8
// RV64ZKND-ZKNE-NEXT: [[TMP1:%.*]] = load i32, ptr [[RS2_ADDR]], align 4 // RV64ZKND-ZKNE-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.aes64ks2(i64 [[TMP0]], i64 [[TMP1]])
// RV64ZKND-ZKNE-NEXT: [[CONV1:%.*]] = sext i32 [[TMP1]] to i64 // RV64ZKND-ZKNE-NEXT: ret i64 [[TMP2]]
// RV64ZKND-ZKNE-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.aes64ks2(i64 [[CONV]], i64 [[CONV1]])
// RV64ZKND-ZKNE-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
// RV64ZKND-ZKNE-NEXT: ret i32 [[CONV2]]
// //
int aes64ks2(int rs1, int rs2) { long aes64ks2(long rs1, long rs2) {
return __builtin_riscv_aes64ks2_64(rs1, rs2); return __builtin_riscv_aes64ks2_64(rs1, rs2);
} }

clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple riscv64 -target-feature +zknd -emit-llvm %s -o - \ // RUN: %clang_cc1 -triple riscv64 -target-feature +zknd -emit-llvm %s -o - \
// RUN: | FileCheck %s -check-prefix=RV64ZKND // RUN: | FileCheck %s -check-prefix=RV64ZKND
// RV64ZKND-LABEL: @aes64dsm( // RV64ZKND-LABEL: @aes64dsm(
// RV64ZKND-NEXT: entry: // RV64ZKND-NEXT: entry:
// RV64ZKND-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4 // RV64ZKND-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
// RV64ZKND-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4 // RV64ZKND-NEXT: [[RS2_ADDR:%.*]] = alloca i64, align 8
// RV64ZKND-NEXT: store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4 // RV64ZKND-NEXT: store i64 [[RS1:%.*]], ptr [[RS1_ADDR]], align 8
// RV64ZKND-NEXT: store i32 [[RS2:%.*]], ptr [[RS2_ADDR]], align 4 // RV64ZKND-NEXT: store i64 [[RS2:%.*]], ptr [[RS2_ADDR]], align 8
// RV64ZKND-NEXT: [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4 // RV64ZKND-NEXT: [[TMP0:%.*]] = load i64, ptr [[RS1_ADDR]], align 8
// RV64ZKND-NEXT: [[CONV:%.*]] = sext i32 [[TMP0]] to i64 // RV64ZKND-NEXT: [[TMP1:%.*]] = load i64, ptr [[RS2_ADDR]], align 8
// RV64ZKND-NEXT: [[TMP1:%.*]] = load i32, ptr [[RS2_ADDR]], align 4 // RV64ZKND-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.aes64dsm(i64 [[TMP0]], i64 [[TMP1]])
// RV64ZKND-NEXT: [[CONV1:%.*]] = sext i32 [[TMP1]] to i64 // RV64ZKND-NEXT: ret i64 [[TMP2]]
// RV64ZKND-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.aes64dsm(i64 [[CONV]], i64 [[CONV1]])
// RV64ZKND-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
// RV64ZKND-NEXT: ret i32 [[CONV2]]
// //
int aes64dsm(int rs1, int rs2) { long aes64dsm(long rs1, long rs2) {
return __builtin_riscv_aes64dsm_64(rs1, rs2); return __builtin_riscv_aes64dsm_64(rs1, rs2);
} }
// RV64ZKND-LABEL: @aes64ds( // RV64ZKND-LABEL: @aes64ds(
// RV64ZKND-NEXT: entry: // RV64ZKND-NEXT: entry:
// RV64ZKND-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4 // RV64ZKND-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
// RV64ZKND-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4 // RV64ZKND-NEXT: [[RS2_ADDR:%.*]] = alloca i64, align 8
// RV64ZKND-NEXT: store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4 // RV64ZKND-NEXT: store i64 [[RS1:%.*]], ptr [[RS1_ADDR]], align 8
// RV64ZKND-NEXT: store i32 [[RS2:%.*]], ptr [[RS2_ADDR]], align 4 // RV64ZKND-NEXT: store i64 [[RS2:%.*]], ptr [[RS2_ADDR]], align 8
// RV64ZKND-NEXT: [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4 // RV64ZKND-NEXT: [[TMP0:%.*]] = load i64, ptr [[RS1_ADDR]], align 8
// RV64ZKND-NEXT: [[CONV:%.*]] = sext i32 [[TMP0]] to i64 // RV64ZKND-NEXT: [[TMP1:%.*]] = load i64, ptr [[RS2_ADDR]], align 8
// RV64ZKND-NEXT: [[TMP1:%.*]] = load i32, ptr [[RS2_ADDR]], align 4 // RV64ZKND-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.aes64ds(i64 [[TMP0]], i64 [[TMP1]])
// RV64ZKND-NEXT: [[CONV1:%.*]] = sext i32 [[TMP1]] to i64 // RV64ZKND-NEXT: ret i64 [[TMP2]]
// RV64ZKND-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.aes64ds(i64 [[CONV]], i64 [[CONV1]])
// RV64ZKND-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
// RV64ZKND-NEXT: ret i32 [[CONV2]]
// //
int aes64ds(int rs1, int rs2) { long aes64ds(long rs1, long rs2) {
return __builtin_riscv_aes64ds_64(rs1, rs2); return __builtin_riscv_aes64ds_64(rs1, rs2);
} }
// RV64ZKND-LABEL: @aes64im( // RV64ZKND-LABEL: @aes64im(
// RV64ZKND-NEXT: entry: // RV64ZKND-NEXT: entry:
// RV64ZKND-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4 // RV64ZKND-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
// RV64ZKND-NEXT: store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4 // RV64ZKND-NEXT: store i64 [[RS1:%.*]], ptr [[RS1_ADDR]], align 8
// RV64ZKND-NEXT: [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4 // RV64ZKND-NEXT: [[TMP0:%.*]] = load i64, ptr [[RS1_ADDR]], align 8
// RV64ZKND-NEXT: [[CONV:%.*]] = sext i32 [[TMP0]] to i64 // RV64ZKND-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.aes64im(i64 [[TMP0]])
// RV64ZKND-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.aes64im(i64 [[CONV]]) // RV64ZKND-NEXT: ret i64 [[TMP1]]
// RV64ZKND-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
// RV64ZKND-NEXT: ret i32 [[CONV1]]
// //
int aes64im(int rs1) { long aes64im(long rs1) {
return __builtin_riscv_aes64im_64(rs1); return __builtin_riscv_aes64im_64(rs1);
} }

clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple riscv64 -target-feature +zkne -emit-llvm %s -o - \ // RUN: %clang_cc1 -triple riscv64 -target-feature +zkne -emit-llvm %s -o - \
// RUN: | FileCheck %s -check-prefix=RV64ZKNE // RUN: | FileCheck %s -check-prefix=RV64ZKNE
// RV64ZKNE-LABEL: @aes64es( // RV64ZKNE-LABEL: @aes64es(
// RV64ZKNE-NEXT: entry: // RV64ZKNE-NEXT: entry:
// RV64ZKNE-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4 // RV64ZKNE-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
// RV64ZKNE-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4 // RV64ZKNE-NEXT: [[RS2_ADDR:%.*]] = alloca i64, align 8
// RV64ZKNE-NEXT: store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4 // RV64ZKNE-NEXT: store i64 [[RS1:%.*]], ptr [[RS1_ADDR]], align 8
// RV64ZKNE-NEXT: store i32 [[RS2:%.*]], ptr [[RS2_ADDR]], align 4 // RV64ZKNE-NEXT: store i64 [[RS2:%.*]], ptr [[RS2_ADDR]], align 8
// RV64ZKNE-NEXT: [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4 // RV64ZKNE-NEXT: [[TMP0:%.*]] = load i64, ptr [[RS1_ADDR]], align 8
// RV64ZKNE-NEXT: [[CONV:%.*]] = sext i32 [[TMP0]] to i64 // RV64ZKNE-NEXT: [[TMP1:%.*]] = load i64, ptr [[RS2_ADDR]], align 8
// RV64ZKNE-NEXT: [[TMP1:%.*]] = load i32, ptr [[RS2_ADDR]], align 4 // RV64ZKNE-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.aes64es(i64 [[TMP0]], i64 [[TMP1]])
// RV64ZKNE-NEXT: [[CONV1:%.*]] = sext i32 [[TMP1]] to i64 // RV64ZKNE-NEXT: ret i64 [[TMP2]]
// RV64ZKNE-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.aes64es(i64 [[CONV]], i64 [[CONV1]])
// RV64ZKNE-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
// RV64ZKNE-NEXT: ret i32 [[CONV2]]
// //
int aes64es(int rs1, int rs2) { long aes64es(long rs1, long rs2) {
return __builtin_riscv_aes64es_64(rs1, rs2); return __builtin_riscv_aes64es_64(rs1, rs2);
} }
// RV64ZKNE-LABEL: @aes64esm( // RV64ZKNE-LABEL: @aes64esm(
// RV64ZKNE-NEXT: entry: // RV64ZKNE-NEXT: entry:
// RV64ZKNE-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4 // RV64ZKNE-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
// RV64ZKNE-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4 // RV64ZKNE-NEXT: [[RS2_ADDR:%.*]] = alloca i64, align 8
// RV64ZKNE-NEXT: store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4 // RV64ZKNE-NEXT: store i64 [[RS1:%.*]], ptr [[RS1_ADDR]], align 8
// RV64ZKNE-NEXT: store i32 [[RS2:%.*]], ptr [[RS2_ADDR]], align 4 // RV64ZKNE-NEXT: store i64 [[RS2:%.*]], ptr [[RS2_ADDR]], align 8
// RV64ZKNE-NEXT: [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4 // RV64ZKNE-NEXT: [[TMP0:%.*]] = load i64, ptr [[RS1_ADDR]], align 8
// RV64ZKNE-NEXT: [[CONV:%.*]] = sext i32 [[TMP0]] to i64 // RV64ZKNE-NEXT: [[TMP1:%.*]] = load i64, ptr [[RS2_ADDR]], align 8
// RV64ZKNE-NEXT: [[TMP1:%.*]] = load i32, ptr [[RS2_ADDR]], align 4 // RV64ZKNE-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.aes64esm(i64 [[TMP0]], i64 [[TMP1]])
// RV64ZKNE-NEXT: [[CONV1:%.*]] = sext i32 [[TMP1]] to i64 // RV64ZKNE-NEXT: ret i64 [[TMP2]]
// RV64ZKNE-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.aes64esm(i64 [[CONV]], i64 [[CONV1]])
// RV64ZKNE-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
// RV64ZKNE-NEXT: ret i32 [[CONV2]]
// //
int aes64esm(int rs1, int rs2) { long aes64esm(long rs1, long rs2) {
return __builtin_riscv_aes64esm_64(rs1, rs2); return __builtin_riscv_aes64esm_64(rs1, rs2);
} }