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Differential D154488

[PowerPC] Define SchedModel for Power8
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Authored by qiucf on Jul 5 2023, 2:56 AM.

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Reviewers
nemanjai
shchenz
Group Reviewers
Restricted Project
Commits
rGb922a3621116: [PowerPC] Define SchedModel for Power8
Summary

PowerPC subtargets prior to Power9 use the 'legacy' itinerary way to provide scheduling information. This patch re-writes the tablegen file to define the scheduling information in the new SchedModel way. This can bring improvements to some benchmarks.

Diff Detail

Event Timeline

qiucf created this revision.Jul 5 2023, 2:56 AM
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Herald added subscribers: steven.zhang, asbirlea, kbarton, hiraditya. · View Herald Transcript
qiucf requested review of this revision.Jul 5 2023, 2:56 AM
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Harbormaster completed remote builds in B243163: Diff 537275.Jul 5 2023, 4:08 AM
shchenz added a comment.Jul 16 2023, 7:52 PM

Thanks for the big effort.
I think moving from old ProcessorItineraries form to new ProcessorModel form should be correct. Some comments from me. And also please note that there are some failures in the pre-merge checks.

llvm/lib/Target/PowerPC/PPCScheduleP8.td
18

why the MicroOpBufferSize is 60? The pwr8 UM seems showing this value as 32 * 2?

19

We need to comment here why on pwr8 this field is set as 0.

47

minor: _1, _2, _4 does not sound like a good name...

48

Why this unit number for type "2xdouble" is set to 4? Its parent P8_VMX only has 2.

61

Same with the name issue _1, ..._6.

llvm/test/CodeGen/PowerPC/BreakableToken-reduced.ll
244

Seems positive, now we use less CSRs.

llvm/test/CodeGen/PowerPC/P10-stack-alignment.ll
31

low ILP but less registers?

llvm/test/CodeGen/PowerPC/aix32-p8-scalar_vector_conversions.ll
30

lower ILP with less register, I think it is fine only if we get better perf in benchmarks.

llvm/test/CodeGen/PowerPC/atomics-i128.ll
510

negative change, now we have more mr which is not free on pwr8.

llvm/test/CodeGen/PowerPC/atomics-i16-ldst.ll
184

We may need another name for check prefix PREP10? And also double check if prefixes P8 and P9 are still used in this file?

4519

Ah, it show P8 and P9 are not used, we should delete them in the run lines.

llvm/test/CodeGen/PowerPC/atomics-i32-ldst.ll
4779

Ditto

llvm/test/CodeGen/PowerPC/atomics-i8-ldst.ll
4219

Ditto

llvm/test/CodeGen/PowerPC/atomics-regression.ll
456

Aren't the atomic related instructions are barriers to the scheduler? Can you check why there are changes around them? Thanks.

llvm/test/CodeGen/PowerPC/bool-math.ll
120

Weird. Now there is no check for this function?

llvm/test/CodeGen/PowerPC/branch_coalesce.ll
18

lower ILP and less registers

llvm/test/CodeGen/PowerPC/ctrloop-constrained-fp.ll
27

Positive

llvm/test/CodeGen/PowerPC/elf64-byval-cc.ll
35

postive

llvm/test/CodeGen/PowerPC/int128_ldst.ll
1100

Same with above

llvm/test/CodeGen/PowerPC/testComparesi32ltu.ll
37

This looks positive. We had a request to move the lr store instruction be away from mflr

qiucf updated this revision to Diff 543374.Jul 23 2023, 10:08 PM
qiucf marked 5 inline comments as done.
Herald added a subscriber: qcolombet. · View Herald TranscriptJul 23 2023, 10:08 PM
Harbormaster completed remote builds in B247560: Diff 543374.Jul 23 2023, 11:41 PM
shchenz added a comment.Jul 24 2023, 1:16 AM

Please notice the 2 failures on two different bot in the premerge test.

llvm/lib/Target/PowerPC/PPCScheduleP8.td
32

Sorry, this still confuses me. The super is P8_FPU and P8_FPU has 4 execution units which can be executed as 2 way SIMD operation for double. So why we set the ProcResource value to 4 here?

33

Setting P8_VMX as super of "4xSingle" also seems weird. In ISA of pwr8, I think most instructions that handle 4xSingle type are VSX related and from the UM "10.3.2 Instructional Latencies and Throughputs", I saw most of them are using pipeline FPU. So I guess, we should use P8_FPU as Super instead?

llvm/test/CodeGen/PowerPC/atomics-i16-ldst.ll
4517

There are still unused check prefix in the run lines.

llvm/test/CodeGen/PowerPC/atomics-i32-ldst.ll
4777

Please delete the unused check prefixes, so that we won't have this note.

llvm/test/CodeGen/PowerPC/atomics-i8-ldst.ll
4219

Please try to remove this NOTE.

qiucf updated this revision to Diff 543788.Jul 24 2023, 7:27 PM
qiucf marked 10 inline comments as done.
qiucf added inline comments.
llvm/lib/Target/PowerPC/PPCScheduleP8.td
32

Thanks, updated.

33

2.1.3 Speculative Superscalar Inner Core Organization:

  • Two VMX execution units capable of executing simple FX, permute, complex FX, and 4-way SIMD single-precision floating-point operations

I think the reason is before VSX, Altivec already had instructions for 4xSingle vectors and they are implemented within VMX units. So their VSX equivalents uses the same execution units.

48

Its parent P8_FPU has 4 units.

llvm/test/CodeGen/PowerPC/atomics-i16-ldst.ll
184

Like CHECK-NONP10 or CHECK-P8P9? But it actually has the same meaning as CHECK-PREP10.

llvm/test/CodeGen/PowerPC/bool-math.ll
120

Because the test RUN line did not specify -mcpu, so that Linux uses pwr8 while AIX uses pwr7. Fixed.

Harbormaster completed remote builds in B247852: Diff 543788.Jul 24 2023, 7:28 PM
qiucf added inline comments.Jul 25 2023, 1:11 AM
llvm/test/CodeGen/PowerPC/atomics-i128.ll
510

The BB with negative result is quite simple:

SU(0):   %29:gprc = COPY $r3
SU(1):   %34:gprc = LWZ 12, %stack.0
SU(2):   %33:gprc = LWZ 8, %stack.0
SU(3):   %32:gprc = LWZ 4, %stack.0
SU(4):   %31:gprc = LWZ 0, %stack.0
SU(5):   %30:crrc = CMPLWI %29:gprc, 0

The old scheduling model puts SU(5) just after SU(0), so that %29:gprc is assigned with r3. With the new scheduling model, the BB is unchanged after pre-isel scheduling.

I think it's more likely an issue of the scheduler exposed by new model and I'll further look at why regpressure is not respected here. But here I'm curious why the register allocator not assign r3 to %29.

qiucf added inline comments.Jul 25 2023, 1:28 AM
llvm/test/CodeGen/PowerPC/atomics-regression.ll
456

lwsync (SYNC) is treated as global memory barrier. But clrlwi (RLWINM) neither writes nor reads any memory, so scheduling such instruction around SYNC is okay. BTW, the new codegen is the original order.

qiucf added a comment.Jul 27 2023, 7:29 PM

I'd like to give extra comments on some definitions:

2.1.3 Speculative Superscalar Inner Core Organization
Out-of-order issue of up to 10 operations into the following 10 issue ports:
– Two ports to do loads or fixed-point operations.
– Two ports to do stores, fixed-point loads, or fixed-point operations.
– Two fixed-point operations
– Two issue ports shared by two floating-point, two VSX, two VMX, one crypto, and one DFP operations
– One branch operation
– One condition register operation

Sixteen execution units:
– Two symmetric load/store units (LSU), capable of executing stores, fixed-point loads, and simple fixed-point operations
– Two load-only units (LU) also capable of executing simple fixed-point operations
– Two symmetric fixed-point units (FXU)
– Four floating-point units (FPU), implemented as two 2-way SIMD operations for double- and single-precision. Scalar binary floating-point instructions can only use two FPUs.
– Two VMX execution units capable of executing simple FX, permute, complex FX, and 4-way SIMD single-precision floating-point operations
– One Crypto unit
– One decimal floating-point unit (DFU)
– One branch execution unit (BR)
– One condition register logical execution unit (CRL)

So correspondent units and ports are defined. But

  • For ports, we may need to 'combine' them. For example, port group 1, 2, 3 are all acceptable for fixed-point operations. So we need to create a 'parent' group for fixed-point ops and make group 1, 2, 3 all its children. Similar rule applies for fixed-point loads.
  • Some instructions uses 'LSU or FXU', a similar parent-child definition are also needed.

Compared to Power9 model, dispatch rules and pipeline forwarding definition are missing in this patch, because they're vague in Power8 manual.

shchenz added inline comments.Aug 1 2023, 10:32 PM
llvm/lib/Target/PowerPC/PPCScheduleP8.td
12–13

This seems like resources for issue not dispatch?

28

Don't know how do you arrange these instructions. But from the UM: vaddfp pipeline is FPU that should be using P8_FP_4x32 and the execution unit should be P8_FPU?

33

I believe we should use P8_VSX as super of P8_FP_4x32. According to the instructions which uses P8_FP_4x32, all of them are with pipeline FPU that should be for the 4 FPU units.
Or we can create two P8_FP_4x32 resources, one is child of P8_FPU and one is child of P8_VMX. However the child of P8_VMX seems have no use instructions in the "Instruction Latencies and Throughputs" sheet.

89

instruction like STB seems occupies two pipelines LSU and LU while seems here it only occupies LSU pipiline?

qiucf updated this revision to Diff 546332.Aug 1 2023, 11:58 PM
qiucf marked 3 inline comments as done.
  • Rename P8_DISP to P8_ISSUE
  • Add scheduling info for DFP instructions
  • Mark resource usage of 4-way SIMD FP instructions from VMX to FPU
  • Add resource usage of FXU to basic load instructions
llvm/lib/Target/PowerPC/PPCScheduleP8.td
89

It occupies both:

def P8_LS_LU : SchedWriteRes<[P8_LU, P8_LS]>;
Harbormaster completed remote builds in B249683: Diff 546332.Aug 2 2023, 1:21 AM
qiucf added a comment.Aug 30 2023, 1:15 AM

Gentle ping

shchenz added a comment.Aug 30 2023, 10:05 PM

Looks almost good to me. Some other comments related to the instruction definitions.

Please note the two failures in the premerge check on X86 target.

llvm/lib/Target/PowerPC/PPCScheduleP8.td
68

nit: This issue port is not used?

88

should be def P8_LS_FP : SchedWriteRes<[P8_LSU, P8_FPU]>;?

169

For cracked instructions, should we only use one issue port?

171

ADD_rec/SUBF_rec/NEG_rec seems can use both FXU or LSU?

qiucf updated this revision to Diff 555300.Sep 1 2023, 1:34 AM
qiucf marked 3 inline comments as done.
qiucf added inline comments.
llvm/lib/Target/PowerPC/PPCScheduleP8.td
169

I tried modelling cracked instructions, but not got good performance results, which can be future improvement item. I added a TODO note.

171

Thanks, moved to use only FX instead.

Harbormaster completed remote builds in B256208: Diff 555300.Sep 1 2023, 2:20 AM
shchenz added inline comments.Sep 1 2023, 3:48 AM
llvm/lib/Target/PowerPC/PPCScheduleP8.td
210

hmm, this change seems still not accurate, below is from PWR8 UM(17 March 2016)

addi addis add add. subf subf. addic subfic adde addme subfme subfze neg neg. nego
FXU (or LU or LSU for non-dot forms)

add. should be able to use FXU or LU (4 hardware units).

Maybe we need to define a new unit group like P8_FX_LU for this kind of instructions?

I suggest you check other instructions as well compared with the UM.

Thanks very much for the big effort.

qiucf added inline comments.Sep 3 2023, 10:03 PM
llvm/lib/Target/PowerPC/PPCScheduleP8.td
210

Per my understanding, only non-dot forms use LU/LSU?

shchenz added inline comments.Sep 4 2023, 2:06 AM
llvm/lib/Target/PowerPC/PPCScheduleP8.td
210

OK, so we have different understanding about FXU (or LU or LSU for non-dot forms).

Let us use yours for now until we find a clear doc about what units dot form instructions can use.

224

Seems I can not find mflr, is it expected?

244
lswi lswx stswi stswx (unaligned)
LSU,LU
lwarx ldarx
LSU or LU
qiucf updated this revision to Diff 556226.Sep 7 2023, 9:07 PM
  • CRBit instructions are not defined in User Manual, remove
  • Fixed point compare use FX instead of CR
  • Reorder and rename definitions to make it cleaner
  • Mark tw instructions as using P8_FX_NONE
  • Leave TODO note in logical instructions, since the modified codegen is suspicious
Harbormaster completed remote builds in B256836: Diff 556226.Sep 7 2023, 9:08 PM
qiucf added inline comments.Sep 7 2023, 9:14 PM
llvm/lib/Target/PowerPC/PPCScheduleP8.td
244
  • lswi (naturally aligned) uses LSU or LU
  • lswi lswx stswi stswx (unaligned) uses LSU,LU
  • stswi (naturally aligned) uses LSU, LU

We can't differentiate whether it's aligned or not, assume naturally aligned here.

shchenz accepted this revision as: shchenz.Sep 8 2023, 12:04 AM

LGTM. Thanks very much again for the very big effort.

llvm/lib/Target/PowerPC/PPCScheduleP8.td
144

I really like the idea about group the instructions by the pipeline. It will be much easier for later change for this model.

This revision is now accepted and ready to land.Sep 8 2023, 12:04 AM
This revision was landed with ongoing or failed builds.Sep 8 2023, 12:45 AM
Closed by commit rGb922a3621116: [PowerPC] Define SchedModel for Power8 (authored by qiucf). · Explain Why
This revision was automatically updated to reflect the committed changes.
qiucf added a commit: rGb922a3621116: [PowerPC] Define SchedModel for Power8.

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Diff 556234

llvm/lib/Target/PowerPC/PPCScheduleP8.td

//===-- PPCScheduleP8.td - PPC P8 Scheduling Definitions ---*- tablegen -*-===// //===-- PPCScheduleP8.td - PPC P8 Scheduling Definitions ---*- tablegen -*-===//
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file defines the itinerary class data for the POWER8 processor. // This file defines the SchedModel for the POWER8 processor.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Scheduling for the P8 involves tracking two types of resources:
// 1. The dispatch bundle slots
// 2. The functional unit resources
// Dispatch units:
def P8_DU1 : FuncUnit;
def P8_DU2 : FuncUnit;
def P8_DU3 : FuncUnit;
def P8_DU4 : FuncUnit;
def P8_DU5 : FuncUnit;
def P8_DU6 : FuncUnit;
def P8_DU7 : FuncUnit; // Only branch instructions will use DU7,DU8
def P8_DU8 : FuncUnit;
// 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
def P8_LU1 : FuncUnit; // Loads or fixed-point operations 1
def P8_LU2 : FuncUnit; // Loads or fixed-point operations 2
// Load/Store pipelines can handle Stores, fixed-point loads, and simple
// fixed-point operations.
def P8_LSU1 : FuncUnit; // Load/Store pipeline 1
def P8_LSU2 : FuncUnit; // Load/Store pipeline 2
// Fixed Point unit
def P8_FXU1 : FuncUnit; // FX pipeline 1
def P8_FXU2 : FuncUnit; // FX pipeline 2
// The Floating-Point Unit (FPU) and Vector Media Extension (VMX) units
// are combined on P7 and newer into a Vector Scalar Unit (VSU).
// The P8 Instruction latency documents still refers to the unit as the
// FPU, so keep in mind that FPU==VSU.
// In contrast to the P7, the VMX units on P8 are symmetric, so no need to
// split vector integer ops or 128-bit load/store/perms to the specific units.
def P8_FPU1 : FuncUnit; // VS pipeline 1
def P8_FPU2 : FuncUnit; // VS pipeline 2
def P8_CRU : FuncUnit; // CR unit (CR logicals and move-from-SPRs)
def P8_BRU : FuncUnit; // BR unit
def P8Itineraries : ProcessorItineraries<
[P8_DU1, P8_DU2, P8_DU3, P8_DU4, P8_DU5, P8_DU6, P8_DU7, P8_DU8,
P8_LU1, P8_LU2, P8_LSU1, P8_LSU2, P8_FXU1, P8_FXU2,
P8_FPU1, P8_FPU2, P8_CRU, P8_BRU], [], [
InstrItinData<IIC_IntSimple , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2,
P8_LU1, P8_LU2,
P8_LSU1, P8_LSU2]>],
[1, 1, 1]>,
InstrItinData<IIC_IntGeneral , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2, P8_LU1,
P8_LU2, P8_LSU1, P8_LSU2]>],
[1, 1, 1]>,
InstrItinData<IIC_IntISEL, [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2], 0>,
InstrStage<1, [P8_BRU]>],
[1, 1, 1, 1]>,
InstrItinData<IIC_IntCompare , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[1, 1, 1]>,
InstrItinData<IIC_IntDivW , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<15, [P8_FXU1, P8_FXU2]>],
[15, 1, 1]>,
InstrItinData<IIC_IntDivD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<23, [P8_FXU1, P8_FXU2]>],
[23, 1, 1]>,
InstrItinData<IIC_IntMulHW , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[4, 1, 1]>,
InstrItinData<IIC_IntMulHWU , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[4, 1, 1]>,
InstrItinData<IIC_IntMulHD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[4, 1, 1]>,
InstrItinData<IIC_IntMulLI , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[4, 1, 1]>,
InstrItinData<IIC_IntRotate , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[1, 1, 1]>,
InstrItinData<IIC_IntRotateD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[1, 1, 1]>,
InstrItinData<IIC_IntRotateDI , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[1, 1, 1]>,
InstrItinData<IIC_IntShift , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[1, 1, 1]>,
InstrItinData<IIC_IntTrapW , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[1, 1]>,
InstrItinData<IIC_IntTrapD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[1, 1]>,
InstrItinData<IIC_BrB , [InstrStage<1, [P8_DU7, P8_DU8], 0>,
InstrStage<1, [P8_BRU]>],
[3, 1, 1]>,
// FIXME - the Br* groups below are not branch related, so should probably
// be renamed.
// IIC_BrCR consists of the cr* instructions. (crand,crnor,creqv, etc).
// and should be 'First' in dispatch.
InstrItinData<IIC_BrCR , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_CRU]>],
[3, 1, 1]>,
// IIC_BrMCR consists of the mcrf instruction.
InstrItinData<IIC_BrMCR , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_CRU]>],
[3, 1, 1]>,
// IIC_BrMCRX consists of mcrxr (obsolete instruction) and mtcrf, which
// should be first in the dispatch group.
InstrItinData<IIC_BrMCRX , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[3, 1, 1]>,
InstrItinData<IIC_BrMCRX , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[3, 1]>,
InstrItinData<IIC_LdStLoad , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2,
P8_LU1, P8_LU2]>],
[2, 1, 1]>,
InstrItinData<IIC_LdStLoadUpd , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_DU2], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2,
P8_LU1, P8_LU2 ], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[2, 2, 1, 1]>,
// Update-Indexed form loads/stores are no longer first and last in the
// dispatch group. They are simply cracked, so require DU1,DU2.
InstrItinData<IIC_LdStLoadUpdX, [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_DU2], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2,
P8_LU1, P8_LU2], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[3, 3, 1, 1]>,
InstrItinData<IIC_LdStLD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2,
P8_LU1, P8_LU2]>],
[2, 1, 1]>,
InstrItinData<IIC_LdStLDU , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_DU2], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2,
P8_LU1, P8_LU2], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[2, 2, 1, 1]>,
InstrItinData<IIC_LdStLDUX , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_DU2], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2,
P8_LU1, P8_LU2], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[3, 3, 1, 1]>,
InstrItinData<IIC_LdStLFD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_LU1, P8_LU2]>],
[3, 1, 1]>,
InstrItinData<IIC_LdStLVecX , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_LU1, P8_LU2]>],
[3, 1, 1]>,
InstrItinData<IIC_LdStLFDU , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_DU2], 0>,
InstrStage<1, [P8_LU1, P8_LU2], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[3, 3, 1, 1]>,
InstrItinData<IIC_LdStLFDUX , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_DU2], 0>,
InstrStage<1, [P8_LU1, P8_LU2], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[3, 3, 1, 1]>,
InstrItinData<IIC_LdStLHA , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_DU2], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2,
P8_LU1, P8_LU2], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2,
P8_LU1, P8_LU2]>],
[3, 1, 1]>,
InstrItinData<IIC_LdStLHAU , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_DU2], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2,
P8_LU1, P8_LU2], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[4, 4, 1, 1]>,
// first+last in dispatch group.
InstrItinData<IIC_LdStLHAUX , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_DU2], 0>,
InstrStage<1, [P8_DU3], 0>,
InstrStage<1, [P8_DU4], 0>,
InstrStage<1, [P8_DU5], 0>,
InstrStage<1, [P8_DU6], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2,
P8_LU1, P8_LU2], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[4, 4, 1, 1]>,
InstrItinData<IIC_LdStLWA , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_DU2], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2,
P8_LU1, P8_LU2]>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[3, 1, 1]>,
InstrItinData<IIC_LdStLWARX, [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_DU2], 0>,
InstrStage<1, [P8_DU3], 0>,
InstrStage<1, [P8_DU4], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2,
P8_LU1, P8_LU2]>],
[3, 1, 1]>,
// first+last
InstrItinData<IIC_LdStLDARX, [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_DU2], 0>,
InstrStage<1, [P8_DU3], 0>,
InstrStage<1, [P8_DU4], 0>,
InstrStage<1, [P8_DU5], 0>,
InstrStage<1, [P8_DU6], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2,
P8_LU1, P8_LU2]>],
[3, 1, 1]>,
InstrItinData<IIC_LdStLMW , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2,
P8_LU1, P8_LU2]>],
[2, 1, 1]>,
// Stores are dual-issued from the issue queue, so may only take up one
// dispatch slot. The instruction will be broken into two IOPS. The agen
// op is issued to the LSU, and the data op (register fetch) is issued
// to either the LU (GPR store) or the VSU (FPR store).
InstrItinData<IIC_LdStStore , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2]>,
InstrStage<1, [P8_LU1, P8_LU2]>],
[1, 1, 1]>,
InstrItinData<IIC_LdStSTD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_LU1, P8_LU2,
P8_LSU1, P8_LSU2]>]
[1, 1, 1]>,
InstrItinData<IIC_LdStSTU , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_DU2], 0>,
InstrStage<1, [P8_LU1, P8_LU2,
P8_LSU1, P8_LSU2], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[2, 1, 1, 1]>,
// First+last
InstrItinData<IIC_LdStSTUX , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_DU2], 0>,
InstrStage<1, [P8_DU3], 0>,
InstrStage<1, [P8_DU4], 0>,
InstrStage<1, [P8_DU5], 0>,
InstrStage<1, [P8_DU6], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[2, 1, 1, 1]>,
InstrItinData<IIC_LdStSTFD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2], 0>,
InstrStage<1, [P8_FPU1, P8_FPU2]>],
[1, 1, 1]>,
InstrItinData<IIC_LdStSTFDU , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_DU2], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2], 0>,
InstrStage<1, [P8_FPU1, P8_FPU2]>],
[2, 1, 1, 1]>,
InstrItinData<IIC_LdStSTVEBX , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2], 0>,
InstrStage<1, [P8_FPU1, P8_FPU2]>],
[1, 1, 1]>,
InstrItinData<IIC_LdStSTDCX , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_DU2], 0>,
InstrStage<1, [P8_DU3], 0>,
InstrStage<1, [P8_DU4], 0>,
InstrStage<1, [P8_DU5], 0>,
InstrStage<1, [P8_DU6], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2], 0>,
InstrStage<1, [P8_LU1, P8_LU2]>],
[1, 1, 1]>,
InstrItinData<IIC_LdStSTWCX , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_DU2], 0>,
InstrStage<1, [P8_DU3], 0>,
InstrStage<1, [P8_DU4], 0>,
InstrStage<1, [P8_DU5], 0>,
InstrStage<1, [P8_DU6], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2], 0>,
InstrStage<1, [P8_LU1, P8_LU2]>],
[1, 1, 1]>,
InstrItinData<IIC_SprMFCR , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_CRU]>],
[6, 1]>,
InstrItinData<IIC_SprMFCRF , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_CRU]>],
[3, 1]>,
InstrItinData<IIC_SprMTSPR , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[4, 1]>, // mtctr
InstrItinData<IIC_FPGeneral , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FPU1, P8_FPU2]>],
[5, 1, 1]>,
InstrItinData<IIC_FPAddSub , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FPU1, P8_FPU2]>],
[5, 1, 1]>,
InstrItinData<IIC_FPCompare , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FPU1, P8_FPU2]>],
[8, 1, 1]>,
InstrItinData<IIC_FPDivD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FPU1, P8_FPU2]>],
[33, 1, 1]>,
InstrItinData<IIC_FPDivS , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FPU1, P8_FPU2]>],
[27, 1, 1]>,
InstrItinData<IIC_FPSqrtD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FPU1, P8_FPU2]>],
[44, 1, 1]>,
InstrItinData<IIC_FPSqrtS , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FPU1, P8_FPU2]>],
[32, 1, 1]>,
InstrItinData<IIC_FPFused , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FPU1, P8_FPU2]>],
[5, 1, 1, 1]>,
InstrItinData<IIC_FPRes , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FPU1, P8_FPU2]>],
[5, 1, 1]>,
InstrItinData<IIC_VecGeneral , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_FPU1, P8_FPU2]>],
[2, 1, 1]>,
InstrItinData<IIC_VecVSL , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_FPU1, P8_FPU2]>],
[2, 1, 1]>,
InstrItinData<IIC_VecVSR , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_FPU1, P8_FPU2]>],
[2, 1, 1]>,
InstrItinData<IIC_VecFP , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_FPU1, P8_FPU2]>],
[6, 1, 1]>,
InstrItinData<IIC_VecFPCompare, [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_FPU1, P8_FPU2]>],
[6, 1, 1]>,
InstrItinData<IIC_VecFPRound , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_FPU1, P8_FPU2]>],
[6, 1, 1]>,
InstrItinData<IIC_VecComplex , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_FPU1, P8_FPU2]>],
[7, 1, 1]>,
InstrItinData<IIC_VecPerm , [InstrStage<1, [P8_DU1, P8_DU2], 0>,
InstrStage<1, [P8_FPU1, P8_FPU2]>],
[3, 1, 1]>
]>;
// ===---------------------------------------------------------------------===//
// P8 machine model for scheduling and other instruction cost heuristics.
// P8 has an 8 insn dispatch group (6 non-branch, 2 branch) and can issue up
// to 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
def P8Model : SchedMachineModel { def P8Model : SchedMachineModel {
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This seems like resources for issue not dispatch?

shchenz: This seems like resources for issue not dispatch?
let IssueWidth = 8; // up to 8 instructions dispatched per cycle. let IssueWidth = 8;
// up to six non-branch instructions. let LoadLatency = 3;
// up to two branches in a dispatch group.
let LoadLatency = 3; // Optimistic load latency assuming bypass.
// This is overriden by OperandCycles if the
// Itineraries are queried instead.
let MispredictPenalty = 16; let MispredictPenalty = 16;
// Try to make sure we have at least 10 dispatch groups in a loop.
let LoopMicroOpBufferSize = 60; let LoopMicroOpBufferSize = 60;
let MicroOpBufferSize = 64;
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why the MicroOpBufferSize is 60? The pwr8 UM seems showing this value as 32 * 2?

shchenz: why the `MicroOpBufferSize` is 60? The pwr8 UM seems showing this value as 32 * 2?
// TODO: Due to limitation of instruction definitions, non-P8 instructions
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We need to comment here why on pwr8 this field is set as 0.

shchenz: We need to comment here why on pwr8 this field is set as 0.
// are required to be listed here. Change this after it got fixed.
let CompleteModel = 0; let CompleteModel = 0;
let UnsupportedFeatures = [HasSPE, PrefixInstrs, MMA,
PairedVectorMemops, PCRelativeMemops,
IsISA3_0, IsISA3_1, IsISAFuture];
}
let Itineraries = P8Itineraries; let SchedModel = P8Model in {
// Power8 Pipeline Units:
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Don't know how do you arrange these instructions. But from the UM: vaddfp pipeline is FPU that should be using P8_FP_4x32 and the execution unit should be P8_FPU?

shchenz: Don't know how do you arrange these instructions. But from the UM: `vaddfp` pipeline is `FPU`…
def P8_LU_LS_FX : ProcResource<6>;
def P8_LU_LS : ProcResource<4> { let Super = P8_LU_LS_FX; }
def P8_LS : ProcResource<2> { let Super = P8_LU_LS; }
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Sorry, this still confuses me. The super is P8_FPU and P8_FPU has 4 execution units which can be executed as 2 way SIMD operation for double. So why we set the ProcResource value to 4 here?

shchenz: Sorry, this still confuses me. The super is `P8_FPU` and `P8_FPU` has 4 execution units which…
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Thanks, updated.

qiucf: Thanks, updated.
def P8_LU : ProcResource<2> { let Super = P8_LU_LS; }
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Setting P8_VMX as super of "4xSingle" also seems weird. In ISA of pwr8, I think most instructions that handle 4xSingle type are VSX related and from the UM "10.3.2 Instructional Latencies and Throughputs", I saw most of them are using pipeline FPU. So I guess, we should use P8_FPU as Super instead?

shchenz: Setting `P8_VMX` as super of "4xSingle" also seems weird. In ISA of pwr8, I think most…
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2.1.3 Speculative Superscalar Inner Core Organization:

  • Two VMX execution units capable of executing simple FX, permute, complex FX, and 4-way SIMD single-precision floating-point operations

I think the reason is before VSX, Altivec already had instructions for 4xSingle vectors and they are implemented within VMX units. So their VSX equivalents uses the same execution units.

qiucf: > **2.1.3 Speculative Superscalar Inner Core Organization**: > > - Two VMX execution units…
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I believe we should use P8_VSX as super of P8_FP_4x32. According to the instructions which uses P8_FP_4x32, all of them are with pipeline FPU that should be for the 4 FPU units.
Or we can create two P8_FP_4x32 resources, one is child of P8_FPU and one is child of P8_VMX. However the child of P8_VMX seems have no use instructions in the "Instruction Latencies and Throughputs" sheet.

shchenz: I believe we should use `P8_VSX` as super of `P8_FP_4x32`. According to the instructions which…
def P8_FX : ProcResource<2> { let Super = P8_LU_LS_FX; }
def P8_DFU : ProcResource<1>;
def P8_BR : ProcResource<1> { let BufferSize = 16; }
def P8_CY : ProcResource<1>;
def P8_CRL : ProcResource<1>;
def P8_VMX : ProcResource<2>;
def P8_PM : ProcResource<2> {
// This is workaround for scheduler to respect latency of long permute chain.
let BufferSize = 1;
let Super = P8_VMX;
} }
def P8_XS : ProcResource<2> { let Super = P8_VMX; }
def P8_VX : ProcResource<2> { let Super = P8_VMX; }
def P8_FPU : ProcResource<4>;
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minor: _1, _2, _4 does not sound like a good name...

shchenz: minor: _1, _2, _4 does not sound like a good name...
// Units for scalar, 2xDouble and 4xSingle
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Why this unit number for type "2xdouble" is set to 4? Its parent P8_VMX only has 2.

shchenz: Why this unit number for type "2xdouble" is set to 4? Its parent `P8_VMX` only has 2.
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Its parent P8_FPU has 4 units.

qiucf: Its parent `P8_FPU` has 4 units.
def P8_FP_Scal : ProcResource<2> { let Super = P8_FPU; }
def P8_FP_2x64 : ProcResource<2> { let Super = P8_FPU; }
def P8_FP_4x32 : ProcResource<2> { let Super = P8_FPU; }
// Power8 Dispatch Ports:
// Two ports to do loads or fixed-point operations.
// Two ports to do stores, fixed-point loads, or fixed-point operations.
// Two ports for fixed-point operations.
// Two issue ports shared by 2 DFP/2 VSX/2 VMX/1 CY/1 DFP operations.
// One for branch operations.
// One for condition register operations.
// TODO: Model dispatch of cracked instructions.
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Same with the name issue _1, ..._6.

shchenz: Same with the name issue _1, ..._6.
// Six ports in total are available for fixed-point operations.
def P8_PORT_ALLFX : ProcResource<6>;
// Four ports in total are available for fixed-point load operations.
def P8_PORT_FXLD : ProcResource<4> { let Super = P8_PORT_ALLFX; }
// Two ports to do loads or fixed-point operations.
def P8_PORT_LD_FX : ProcResource<2> { let Super = P8_PORT_FXLD; }
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nit: This issue port is not used?

shchenz: nit: This issue port is not used?
// Two ports to do stores, fixed-point loads, or fixed-point operations.
def P8_PORT_ST_FXLD_FX : ProcResource<2> { let Super = P8_PORT_FXLD; }
// Two issue ports shared by two floating-point, two VSX, two VMX, one crypto,
// and one DFP operations.
def P8_PORT_VMX_FP : ProcResource<2>;
// One port for branch operation.
def P8_PORT_BR : ProcResource<1>;
// One port for condition register operation.
def P8_PORT_CR : ProcResource<1>;
def P8_ISSUE_FX : SchedWriteRes<[P8_PORT_ALLFX]>;
def P8_ISSUE_FXLD : SchedWriteRes<[P8_PORT_FXLD]>;
def P8_ISSUE_LD : SchedWriteRes<[P8_PORT_LD_FX]>;
def P8_ISSUE_ST : SchedWriteRes<[P8_PORT_ST_FXLD_FX]>;
def P8_ISSUE_VSX : SchedWriteRes<[P8_PORT_VMX_FP]>;
def P8_ISSUE_BR : SchedWriteRes<[P8_PORT_BR]>;
def P8_ISSUE_CR : SchedWriteRes<[P8_PORT_CR]>;
// Power8 Instruction Latency & Port Groups:
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should be def P8_LS_FP : SchedWriteRes<[P8_LSU, P8_FPU]>;?

shchenz: should be `def P8_LS_FP : SchedWriteRes<[P8_LSU, P8_FPU]>;`?
def P8_LS_LU_NONE : SchedWriteRes<[P8_LU, P8_LS]>;
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instruction like STB seems occupies two pipelines LSU and LU while seems here it only occupies LSU pipiline?

shchenz: instruction like `STB` seems occupies two pipelines `LSU` and `LU` while seems here it only…
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It occupies both:

def P8_LS_LU : SchedWriteRes<[P8_LU, P8_LS]>;
qiucf: It occupies both: ``` def P8_LS_LU : SchedWriteRes<[P8_LU, P8_LS]>; ```
def P8_LS_FP_NONE : SchedWriteRes<[P8_LS, P8_FPU]>;
def P8_LU_or_LS_3C : SchedWriteRes<[P8_LU_LS]> { let Latency = 3; }
def P8_LS_FX_3C : SchedWriteRes<[P8_LS, P8_FX]> { let Latency = 3; }
def P8_LU_or_LS_or_FX_2C : SchedWriteRes<[P8_LU_LS_FX]> { let Latency = 2; }
def P8_LU_or_LS_FX_3C : SchedWriteRes<[P8_LU_LS, P8_FX]> { let Latency = 3; }
def P8_FX_NONE : SchedWriteRes<[P8_FX]>;
def P8_FX_1C : SchedWriteRes<[P8_FX]> { let Latency = 1; }
def P8_FX_2C : SchedWriteRes<[P8_FX]> { let Latency = 2; }
def P8_FX_3C : SchedWriteRes<[P8_FX]> { let Latency = 3; }
def P8_FX_5C : SchedWriteRes<[P8_FX]> { let Latency = 5; }
def P8_FX_10C : SchedWriteRes<[P8_FX]> { let Latency = 10; }
def P8_FX_23C : SchedWriteRes<[P8_FX]> { let Latency = 23; }
def P8_FX_15C : SchedWriteRes<[P8_FX]> { let Latency = 15; }
def P8_FX_41C : SchedWriteRes<[P8_FX]> { let Latency = 41; }
def P8_BR_2C : SchedWriteRes<[P8_BR]> { let Latency = 2; }
def P8_CR_NONE : SchedWriteRes<[P8_CRL]>;
def P8_CR_3C : SchedWriteRes<[P8_CRL]> { let Latency = 3; }
def P8_CR_5C : SchedWriteRes<[P8_CRL]> { let Latency = 5; }
def P8_LU_5C : SchedWriteRes<[P8_LU]> { let Latency = 5; }
def P8_LU_FX_5C : SchedWriteRes<[P8_LU, P8_FX]> { let Latency = 5; }
def P8_LS_FP_FX_2C : SchedWriteRes<[P8_LS, P8_FPU, P8_FX]> { let Latency = 2; }
def P8_LS_FP_FX_3C : SchedWriteRes<[P8_LS, P8_FPU, P8_FX]> { let Latency = 3; }
def P8_LS_3C : SchedWriteRes<[P8_LS]> { let Latency = 3; }
def P8_FP_3C : SchedWriteRes<[P8_FPU]> { let Latency = 3; }
def P8_FP_Scal_6C : SchedWriteRes<[P8_FP_Scal]> { let Latency = 6; }
def P8_FP_4x32_6C : SchedWriteRes<[P8_FP_4x32]> { let Latency = 6; }
def P8_FP_2x64_6C : SchedWriteRes<[P8_FP_2x64]> { let Latency = 6; }
def P8_FP_26C : SchedWriteRes<[P8_FP_Scal]> { let Latency = 26; }
def P8_FP_28C : SchedWriteRes<[P8_FP_4x32]> { let Latency = 28; }
def P8_FP_31C : SchedWriteRes<[P8_FP_Scal]> { let Latency = 31; }
def P8_FP_Scal_32C : SchedWriteRes<[P8_FP_Scal]> { let Latency = 32; }
def P8_FP_2x64_32C : SchedWriteRes<[P8_FP_2x64]> { let Latency = 32; }
def P8_FP_4x32_32C : SchedWriteRes<[P8_FP_4x32]> { let Latency = 32; }
def P8_FP_Scal_43C : SchedWriteRes<[P8_FP_Scal]> { let Latency = 43; }
def P8_FP_2x64_43C : SchedWriteRes<[P8_FP_2x64]> { let Latency = 43; }
def P8_XS_2C : SchedWriteRes<[P8_XS]> { let Latency = 2; }
def P8_PM_2C : SchedWriteRes<[P8_PM]> { let Latency = 2; }
def P8_XS_4C : SchedWriteRes<[P8_XS]> { let Latency = 4; }
def P8_VX_7C : SchedWriteRes<[P8_VX]> { let Latency = 7; }
def P8_XS_9C : SchedWriteRes<[P8_XS]> { let Latency = 9; }
def P8_CY_6C : SchedWriteRes<[P8_CY]> { let Latency = 6; }
def P8_DFU_13C : SchedWriteRes<[P8_DFU]> { let Latency = 13; }
def P8_DFU_15C : SchedWriteRes<[P8_DFU]> { let Latency = 15; }
def P8_DFU_17C : SchedWriteRes<[P8_DFU]> { let Latency = 17; }
def P8_DFU_25C : SchedWriteRes<[P8_DFU]> { let Latency = 25; }
def P8_DFU_32C : SchedWriteRes<[P8_DFU]> { let Latency = 32; }
def P8_DFU_34C : SchedWriteRes<[P8_DFU]> { let Latency = 34; }
def P8_DFU_40C : SchedWriteRes<[P8_DFU]> { let Latency = 40; }
def P8_DFU_90C : SchedWriteRes<[P8_DFU]> { let Latency = 90; }
def P8_DFU_96C : SchedWriteRes<[P8_DFU]> { let Latency = 96; }
def P8_DFU_172C : SchedWriteRes<[P8_DFU]> { let Latency = 172; }
// Direct move instructions
def P8_DM_5C : SchedWriteRes<[]> { let Latency = 5; }
// Instructions of CR pipeline
shchenzUnsubmitted
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I really like the idea about group the instructions by the pipeline. It will be much easier for later change for this model.

shchenz: I really like the idea about group the instructions by the pipeline. It will be much easier for…
def : InstRW<[P8_CR_NONE, P8_ISSUE_CR], (instrs MFCR, MFCR8)>;
def : InstRW<[P8_CR_3C, P8_ISSUE_CR], (instrs MFOCRF, MFOCRF8)>;
def : InstRW<[P8_CR_5C, P8_ISSUE_CR], (instrs MFLR, MFLR8, MFCTR, MFCTR8)>;
// Instructions of CY pipeline
def : InstRW<[P8_CY_6C, P8_ISSUE_VSX], (instrs
VCIPHER, VCIPHERLAST, VNCIPHER, VNCIPHERLAST, VPMSUMB, VPMSUMD, VPMSUMH, VPMSUMW, VSBOX)>;
// Instructions of FPU pipeline
def : InstRW<[P8_FP_26C, P8_ISSUE_VSX], (instrs (instregex "^FDIVS(_rec)?$"), XSDIVSP)>;
def : InstRW<[P8_FP_28C, P8_ISSUE_VSX], (instrs XVDIVSP)>;
def : InstRW<[P8_FP_31C, P8_ISSUE_VSX], (instregex "^FSQRTS(_rec)?$")>;
def : InstRW<[P8_FP_Scal_32C, P8_ISSUE_VSX], (instrs FDIV, FDIV_rec, XSDIVDP)>;
def : InstRW<[P8_FP_2x64_32C, P8_ISSUE_VSX], (instrs XVDIVDP)>;
def : InstRW<[P8_FP_4x32_32C, P8_ISSUE_VSX], (instrs XVSQRTSP)>;
def : InstRW<[P8_FP_Scal_43C, P8_ISSUE_VSX], (instrs FSQRT, FSQRT_rec, XSSQRTDP)>;
def : InstRW<[P8_FP_2x64_43C, P8_ISSUE_VSX], (instrs XVSQRTDP)>;
def : InstRW<[P8_FP_3C, P8_ISSUE_VSX], (instrs
MTFSFI_rec, MTFSF_rec, MTFSFI, MTFSFIb, MTFSF, MTFSFb, MTFSB0, MTFSB1)>;
def : InstRW<[P8_FP_Scal_6C, P8_ISSUE_VSX], (instrs
shchenzUnsubmitted
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For cracked instructions, should we only use one issue port?

shchenz: For cracked instructions, should we only use one issue port?
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I tried modelling cracked instructions, but not got good performance results, which can be future improvement item. I added a TODO note.

qiucf: I tried modelling cracked instructions, but not got good performance results, which can be…
(instregex "^F(N)?M(ADD|SUB)(S)?(_rec)?$"),
(instregex "^XS(N)?M(ADD|SUB)(A|M)(D|S)P$"),
shchenzUnsubmitted
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ADD_rec/SUBF_rec/NEG_rec seems can use both FXU or LSU?

shchenz: ADD_rec/SUBF_rec/NEG_rec seems can use both FXU or LSU?
qiucfAuthorUnsubmitted
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Thanks, moved to use only FX instead.

qiucf: Thanks, moved to use only FX instead.
(instregex "^FC(F|T)I(D|W)(U)?(S|Z)?(_rec)?$"),
(instregex "^(F|XS)(ABS|CPSGN|ADD|MUL|NABS|RE|NEG|SUB|SEL|RSQRTE)(D|S)?(P)?(s)?(_rec)?$"),
(instregex "^FRI(M|N|P|Z)(D|S)(_rec)?$"),
(instregex "^XSCVDP(S|U)X(W|D)S(s)?$"),
(instregex "^XSCV(S|U)XD(D|S)P$"),
(instregex "^XSCV(D|S)P(S|D)P(N)?$"),
(instregex "^XSRDPI(C|M|P|Z)?$"),
FMR, FRSP, FMR_rec, FRSP_rec, XSRSP)>;
def : InstRW<[P8_FP_4x32_6C, P8_ISSUE_VSX], (instrs
(instregex "^XV(N)?M(ADD|SUB)(A|M)SP$"),
(instregex "^VRFI(M|N|P|Z)$"),
XVRSQRTESP, XVSUBSP, VADDFP, VEXPTEFP, VLOGEFP, VMADDFP, VNMSUBFP, VREFP,
VRSQRTEFP, VSUBFP, XVCVSXWSP, XVCVUXWSP, XVMULSP, XVNABSSP, XVNEGSP, XVRESP,
XVCVDPSP, XVCVSXDSP, XVCVUXDSP, XVABSSP, XVADDSP, XVCPSGNSP)>;
def : InstRW<[P8_FP_2x64_6C, P8_ISSUE_VSX], (instrs
(instregex "^XVR(D|S)PI(C|M|P|Z)?$"),
(instregex "^XVCV(S|U)X(D|W)DP$"),
(instregex "^XVCV(D|W|S)P(S|U)X(D|W)S$"),
(instregex "^XV(N)?(M)?(RSQRTE|CPSGN|SUB|ADD|ABS|UL|NEG|RE)(A|M)?DP$"),
XVCVSPDP)>;
// Instructions of FX, LU or LS pipeline
def : InstRW<[P8_FX_NONE, P8_ISSUE_FX], (instrs TDI, TWI, TD, TW, MTCRF, MTCRF8, MTOCRF, MTOCRF8)>;
def : InstRW<[P8_FX_1C, P8_ISSUE_FX], (instregex "^RLWIMI(8)?$")>;
// TODO: Pipeline of logical instructions might be LS or FX
def : InstRW<[P8_FX_2C, P8_ISSUE_FX], (instrs
(instregex "^(N|X)?(EQV|AND|OR)(I)?(S|C)?(8)?(_rec)?$"),
(instregex "^EXTS(B|H|W)(8)?(_32)?(_64)?(_rec)?$"),
(instregex "^RL(D|W)(I)?(NM|C)(L|R)?(8)?(_32)?(_64)?(_rec)?$"),
(instregex "^S(L|R)(A)?(W|D)(I)?(8)?(_rec|_32)?$"),
(instregex "^(ADD|SUBF)(M|Z)?(C|E)?(4|8)?O(_rec)?$"),
(instregex "^(ADD|SUBF)(M|Z)?E(8)?_rec$"),
(instregex "^(ADD|SUBF|NEG)(4|8)?_rec$"),
NOP, ADDG6S, ADDG6S8, ADDZE, ADDZE8, ADDIC_rec, NEGO_rec, ADDC, ADDC8, SUBFC, SUBFC8,
ADDC_rec, ADDC8_rec, SUBFC_rec, SUBFC8_rec, COPY, NEG8O_rec,
RLDIMI, RLDIMI_rec, RLWIMI8_rec, RLWIMI_rec)>;
shchenzUnsubmitted
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hmm, this change seems still not accurate, below is from PWR8 UM(17 March 2016)

addi addis add add. subf subf. addic subfic adde addme subfme subfze neg neg. nego
FXU (or LU or LSU for non-dot forms)

add. should be able to use FXU or LU (4 hardware units).

Maybe we need to define a new unit group like P8_FX_LU for this kind of instructions?

I suggest you check other instructions as well compared with the UM.

Thanks very much for the big effort.

shchenz: hmm, this change seems still not accurate, below is from PWR8 UM(17 March 2016) ``` addi addis…
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Per my understanding, only non-dot forms use LU/LSU?

qiucf: Per my understanding, only non-dot forms use LU/LSU?
shchenzUnsubmitted
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OK, so we have different understanding about FXU (or LU or LSU for non-dot forms).

Let us use yours for now until we find a clear doc about what units dot form instructions can use.

shchenz: OK, so we have different understanding about `FXU (or LU or LSU for non-dot forms)`. Let us…
def : InstRW<[P8_FX_3C], (instregex "^(POP)?CNT(LZ)?(B|W|D)(8)?(_rec)?$")>;
def : InstRW<[P8_FX_5C, P8_ISSUE_FX], (instrs
(instregex "^MUL(H|L)(I|W|D)(8)?(U|O)?(_rec)?$"),
CMPDI,CMPWI,CMPD,CMPW,CMPLDI,CMPLWI,CMPLD,CMPLW,
ISEL, ISEL8, MTLR, MTLR8, MTCTR, MTCTR8, MTCTR8loop, MTCTRloop)>;
def : InstRW<[P8_FX_10C, P8_ISSUE_VSX], (instregex "^MFTB(8)?$")>;
def : InstRW<[P8_FX_15C, P8_ISSUE_FX], (instregex "^DIVW(U)?$")>;
def : InstRW<[P8_FX_23C, P8_ISSUE_FX], (instregex "^DIV(D|WE)(U)?$")>;
def : InstRW<[P8_FX_41C], (instrs
(instregex "^DIV(D|W)(E)?(U)?O(_rec)?$"),
(instregex "^DIV(D|W)(E)?(U)?_rec$"),
shchenzUnsubmitted
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Seems I can not find mflr, is it expected?

shchenz: Seems I can not find `mflr`, is it expected?
DIVDE, DIVDEU)>;
def : InstRW<[P8_LS_3C, P8_ISSUE_FX], (instrs MFSR, MFSRIN)>;
def : InstRW<[P8_LU_5C, P8_ISSUE_LD], (instrs
LFS, LFSX, LFD, LFDX, LFDXTLS, LFDXTLS_, LXVD2X, LXVW4X, LXVDSX, LVEBX, LVEHX, LVEWX,
LVX, LVXL, LXSDX, LFIWAX, LFIWZX, LFSXTLS, LFSXTLS_, LXVB16X, LXVD2X, LXSIWZX,
DFLOADf64, XFLOADf64, LIWZX)>;
def : InstRW<[P8_LS_FX_3C, P8_ISSUE_FXLD], (instrs LQ)>;
def : InstRW<[P8_LU_FX_5C, P8_ISSUE_LD], (instregex "^LF(D|S)U(X)?$")>;
def : InstRW<[P8_LS_FP_NONE, P8_ISSUE_ST], (instrs
STXSDX, STXVD2X, STXVW4X, STFIWX, STFS, STFSX, STFD, STFDX,
STFDEPX, STFDXTLS, STFDXTLS_, STFSXTLS, STFSXTLS_, STXSIWX, STXSSP, STXSSPX)>;
def : InstRW<[P8_LS_FP_FX_2C, P8_ISSUE_ST], (instrs STVEBX, STVEHX, STVEWX, STVX, STVXL)>;
def : InstRW<[P8_LS_FP_FX_3C, P8_ISSUE_ST], (instregex "^STF(D|S)U(X)?$")>;
def : InstRW<[P8_LS_LU_NONE, P8_ISSUE_ST], (instrs
shchenzUnsubmitted
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lswi lswx stswi stswx (unaligned)
LSU,LU
lwarx ldarx
LSU or LU
shchenz: ``` lswi lswx stswi stswx (unaligned) LSU,LU ``` ``` lwarx ldarx LSU or LU ```
qiucfAuthorUnsubmitted
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  • lswi (naturally aligned) uses LSU or LU
  • lswi lswx stswi stswx (unaligned) uses LSU,LU
  • stswi (naturally aligned) uses LSU, LU

We can't differentiate whether it's aligned or not, assume naturally aligned here.

qiucf: - lswi (naturally aligned) uses LSU or LU - lswi lswx stswi stswx (unaligned) uses LSU,LU…
(instregex "^ST(B|H|W|D)(U)?(X)?(8|TLS)?(_)?(32)?$"),
STBCIX, STBCX, STBEPX, STDBRX, STDCIX, STDCX, STHBRX, STHCIX, STHCX, STHEPX,
STMW, STSWI, STWBRX, STWCIX, STWCX, STWEPX)>;
def : InstRW<[P8_LU_or_LS_FX_3C, P8_ISSUE_FXLD],
(instregex "^L(B|H|W|D)(A|Z)?(U)?(X)?(8|TLS)?(_)?(32)?$")>;
def : InstRW<[P8_LU_or_LS_3C, P8_ISSUE_FXLD], (instrs
LBARX, LBARXL, LBEPX, LBZCIX, LDARX, LDARXL, LDBRX, LDCIX, LFDEPX, LHARX, LHARXL, LHBRX, LXSIWAX,
LHBRX8, LHEPX, LHZCIX, LMW, LSWI, LVSL, LVSR, LWARX, LWARXL, LWBRX, LWBRX8, LWEPX, LWZCIX)>;
def : InstRW<[P8_LU_or_LS_or_FX_2C, P8_ISSUE_FX], (instrs
(instregex "^ADDI(C)?(dtprel|tlsgd|toc)?(L)?(ADDR)?(32|8)?$"),
(instregex "^ADDIS(dtprel|tlsgd|toc|gotTprel)?(HA)?(32|8)?$"),
(instregex "^LI(S)?(8)?$"),
(instregex "^ADD(M)?(E)?(4|8)?(TLS)?(_)?$"),
(instregex "^SUBF(M|Z)?(E)?(IC)?(4|8)?$"),
(instregex "^NEG(8)?(O)?$"))>;
// Instructions of PM pipeline
def : InstRW<[P8_PM_2C, P8_ISSUE_VSX], (instrs
(instregex "^VPK(S|U)(H|W|D)(S|U)(M|S)$"),
(instregex "^VUPK(H|L)(P|S)(H|B|W|X)$"),
(instregex "^VSPLT(IS)?(B|H|W)(s)?$"),
(instregex "^(XX|V)MRG(E|O|H|L)(B|H|W)$"),
XXPERMDI, XXPERMDIs, XXSEL, XXSLDWI, XXSLDWIs, XXSPLTW, XXSPLTWs, VPERMXOR,
VPKPX, VPERM, VBPERMQ, VGBBD, VSEL, VSL, VSLDOI, VSLO, VSR, VSRO)>;
def : InstRW<[P8_XS_2C, P8_ISSUE_VSX], (instrs
(instregex "^V(ADD|SUB)(S|U)(B|H|W|D)(M|S)$"),
(instregex "^X(S|V)(MAX|MIN)(D|S)P$"),
(instregex "^V(S)?(R)?(L)?(A)?(B|D|H|W)$"),
(instregex "^VAVG(S|U)(B|H|W)$"),
(instregex "^VM(AX|IN)(S|U)(B|H|W|D)$"),
(instregex "^(XX|V)(L)?(N)?(X)?(AND|OR|EQV)(C)?$"),
(instregex "^(X)?VCMP(EQ|GT|GE|B)(F|S|U)?(B|H|W|D|P|S)(P)?(_rec)?$"),
(instregex "^VCLZ(B|H|W|D)$"),
(instregex "^VPOPCNT(B|H|W)$"),
XXLORf, XXLXORdpz, XXLXORspz, XXLXORz, VEQV, VMAXFP, VMINFP,
VSHASIGMAD, VSHASIGMAW, VSUBCUW, VADDCUW, MFVSCR, MTVSCR)>;
def : InstRW<[P8_XS_4C, P8_ISSUE_VSX], (instrs
(instregex "^V(ADD|SUB)(E)?(C)?UQ(M)?$"),
VPOPCNTD)>;
def : InstRW<[P8_XS_9C, P8_ISSUE_CR], (instrs
(instregex "^(F|XS)CMP(O|U)(D|S)(P)?$"),
(instregex "^(F|XS|XV)T(DIV|SQRT)((D|S)P)?$"))>;
// Instructions of VX pipeline
def : InstRW<[P8_VX_7C, P8_ISSUE_VSX], (instrs
(instregex "^V(M)?SUM(2|4)?(M|S|U)(B|H|W)(M|S)$"),
(instregex "^VMUL(E|O)?(S|U)(B|H|W)(M)?$"),
VMHADDSHS, VMHRADDSHS, VMLADDUHM)>;
// Instructions of BR pipeline
def : InstRW<[P8_BR_2C, P8_ISSUE_BR], (instrs
(instregex "^(g)?B(C)?(C)?(CTR)?(L)?(A)?(R)?(L)?(8)?(_LD|_LWZ)?(always|into_toc|at)?(_RM)?(n)?$"),
(instregex "^BD(N)?Z(L)?(R|A)?(L)?(m|p|8)?$"),
(instregex "^BL(R|A)?(8)?(_NOP)?(_TLS)?(_)?(RM)?$"))>;
// Instructions of DFP pipeline
// DFP operations also use float/vector/crypto issue ports.
def : InstRW<[P8_DFU_13C, P8_ISSUE_VSX], (instrs
(instregex "^DTST(D|S)(C|F|G)(Q)?$"),
(instregex "^D(Q|X)EX(Q)?(_rec)?$"),
(instregex "^D(ADD|SUB|IEX|QUA|RRND|RINTX|RINTN|CTDP|DEDPD|ENBCD)(_rec)?$"),
(instregex "^DSC(L|R)I(_rec)?$"),
BCDADD_rec, BCDSUB_rec, DCMPO, DCMPU, DTSTEX, DQUAI)>;
def : InstRW<[P8_DFU_15C, P8_ISSUE_VSX], (instrs
(instregex "^DRINT(N|X)Q(_rec)?$"),
DCMPOQ, DCMPUQ, DRRNDQ, DRRNDQ_rec, DIEXQ, DIEXQ_rec, DQUAIQ, DQUAIQ_rec,
DTSTEXQ, DDEDPDQ, DDEDPDQ_rec, DENBCDQ, DENBCDQ_rec, DSCLIQ, DSCLIQ_rec,
DSCRIQ, DSCRIQ_rec, DCTQPQ, DCTQPQ_rec)>;
def : InstRW<[P8_DFU_17C, P8_ISSUE_VSX], (instregex "^D(ADD|SUB|QUA)Q(_rec)?$")>;
def : InstRW<[P8_DFU_25C, P8_ISSUE_VSX], (instrs DRSP, DRSP_rec, DCTFIX, DCTFIX_rec)>;
def : InstRW<[P8_DFU_32C, P8_ISSUE_VSX], (instrs DCFFIX, DCFFIX_rec)>;
def : InstRW<[P8_DFU_34C, P8_ISSUE_VSX], (instrs DCFFIXQ, DCFFIXQ_rec)>;
def : InstRW<[P8_DFU_40C, P8_ISSUE_VSX], (instrs DMUL, DMUL_rec)>;
def : InstRW<[P8_DFU_90C, P8_ISSUE_VSX], (instrs DMULQ, DMULQ_rec)>;
def : InstRW<[P8_DFU_96C, P8_ISSUE_VSX], (instrs DDIV, DDIV_rec)>;
def : InstRW<[P8_DFU_172C, P8_ISSUE_VSX], (instrs DDIVQ, DDIVQ_rec)>;
// Direct move instructions
def : InstRW<[P8_DM_5C, P8_ISSUE_VSX], (instrs
MFVRD, MFVSRD, MFVRWZ, MFVSRWZ, MTVRD, MTVSRD, MTVRWA, MTVSRWA, MTVRWZ, MTVSRWZ)>;
}

llvm/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll

llvm/test/CodeGen/PowerPC/BreakableToken-reduced.ll

Show First 20 Lines • Show All 196 Lines • ▼ Show 20 Lines
%"struct.std::_Rb_tree<clang::tooling::Replacement, clang::tooling::Replacement, std::_Identity<clang::tooling::Replacement>, std::less<clang::tooling::Replacement>, std::allocator<clang::tooling::Replacement> >::_Rb_tree_impl" = type { %"struct.std::less.149", %"struct.std::_Rb_tree_node_base", i64 } %"struct.std::_Rb_tree<clang::tooling::Replacement, clang::tooling::Replacement, std::_Identity<clang::tooling::Replacement>, std::less<clang::tooling::Replacement>, std::allocator<clang::tooling::Replacement> >::_Rb_tree_impl" = type { %"struct.std::less.149", %"struct.std::_Rb_tree_node_base", i64 }
%"struct.std::less.149" = type { i8 } %"struct.std::less.149" = type { i8 }
define void @_ZN5clang6format22BreakableStringLiteral11insertBreakEjjSt4pairImjERNS0_17WhitespaceManagerE(ptr nocapture readonly %this, i32 zeroext %LineIndex, i32 zeroext %TailOffset, [2 x i64] %Split.coerce, ptr dereferenceable(1504) %Whitespaces) unnamed_addr #1 align 2 { define void @_ZN5clang6format22BreakableStringLiteral11insertBreakEjjSt4pairImjERNS0_17WhitespaceManagerE(ptr nocapture readonly %this, i32 zeroext %LineIndex, i32 zeroext %TailOffset, [2 x i64] %Split.coerce, ptr dereferenceable(1504) %Whitespaces) unnamed_addr #1 align 2 {
; CHECK-LABEL: _ZN5clang6format22BreakableStringLiteral11insertBreakEjjSt4pairImjERNS0_17WhitespaceManagerE: ; CHECK-LABEL: _ZN5clang6format22BreakableStringLiteral11insertBreakEjjSt4pairImjERNS0_17WhitespaceManagerE:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ld 10, 56(3) ; CHECK-NEXT: ld 10, 56(3)
; CHECK-NEXT: lwz 0, 40(3) ; CHECK-NEXT: lwz 4, 40(3)
; CHECK-NEXT: mr 12, 8 ; CHECK-NEXT: mr 12, 8
; CHECK-NEXT: cmpldi 10, 0 ; CHECK-NEXT: cmpldi 10, 0
; CHECK-NEXT: beq 0, .LBB0_2 ; CHECK-NEXT: beq 0, .LBB0_2
; CHECK-NEXT: # %bb.1: # %if.end.i.i ; CHECK-NEXT: # %bb.1: # %if.end.i.i
; CHECK-NEXT: ld 9, 48(3) ; CHECK-NEXT: ld 9, 48(3)
; CHECK-NEXT: lbz 4, 0(9) ; CHECK-NEXT: lbz 8, 0(9)
; CHECK-NEXT: cmpwi 4, 64 ; CHECK-NEXT: cmpwi 8, 64
; CHECK-NEXT: b .LBB0_3 ; CHECK-NEXT: b .LBB0_3
; CHECK-NEXT: .LBB0_2: # %entry._ZNK4llvm9StringRef10startswithES0_.exit_crit_edge ; CHECK-NEXT: .LBB0_2: # %entry._ZNK4llvm9StringRef10startswithES0_.exit_crit_edge
; CHECK-NEXT: ld 9, 48(3) ; CHECK-NEXT: ld 9, 48(3)
; CHECK-NEXT: crxor 2, 2, 2 ; CHECK-NEXT: crxor 2, 2, 2
; CHECK-NEXT: .LBB0_3: # %_ZNK4llvm9StringRef10startswithES0_.exit ; CHECK-NEXT: .LBB0_3: # %_ZNK4llvm9StringRef10startswithES0_.exit
; CHECK-NEXT: mflr 4 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: .cfi_def_cfa_offset 160 ; CHECK-NEXT: .cfi_def_cfa_offset 144
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: .cfi_offset r28, -32
; CHECK-NEXT: .cfi_offset r29, -24
; CHECK-NEXT: .cfi_offset r30, -16 ; CHECK-NEXT: .cfi_offset r30, -16
; CHECK-NEXT: std 28, -32(1) # 8-byte Folded Spill
; CHECK-NEXT: std 29, -24(1) # 8-byte Folded Spill
; CHECK-NEXT: std 30, -16(1) # 8-byte Folded Spill ; CHECK-NEXT: std 30, -16(1) # 8-byte Folded Spill
; CHECK-NEXT: stdu 1, -160(1) ; CHECK-NEXT: stdu 1, -144(1)
; CHECK-NEXT: std 4, 176(1)
; CHECK-NEXT: li 8, 0 ; CHECK-NEXT: li 8, 0
; CHECK-NEXT: li 11, 1 ; CHECK-NEXT: li 11, 1
; CHECK-NEXT: std 0, 160(1)
; CHECK-NEXT: add 5, 6, 5 ; CHECK-NEXT: add 5, 6, 5
; CHECK-NEXT: iseleq 30, 11, 8 ; CHECK-NEXT: lbz 30, 20(3)
; CHECK-NEXT: clrldi 6, 7, 32
; CHECK-NEXT: iseleq 8, 11, 8
; CHECK-NEXT: ld 11, 64(3) ; CHECK-NEXT: ld 11, 64(3)
; CHECK-NEXT: lbz 29, 20(3)
; CHECK-NEXT: lwz 28, 16(3)
; CHECK-NEXT: add 5, 5, 10 ; CHECK-NEXT: add 5, 5, 10
; CHECK-NEXT: clrldi 5, 5, 32
; CHECK-NEXT: mr 7, 11
; CHECK-NEXT: sub 0, 4, 8
; CHECK-NEXT: ld 4, 8(3) ; CHECK-NEXT: ld 4, 8(3)
; CHECK-NEXT: ld 8, 72(3) ; CHECK-NEXT: ld 8, 72(3)
; CHECK-NEXT: sub 3, 0, 30 ; CHECK-NEXT: lwz 3, 16(3)
; CHECK-NEXT: clrldi 5, 5, 32 ; CHECK-NEXT: std 30, 96(1)
; CHECK-NEXT: li 0, 1 ; CHECK-NEXT: extsw 0, 0
; CHECK-NEXT: clrldi 6, 7, 32 ; CHECK-NEXT: std 3, 112(1)
; CHECK-NEXT: extsw 30, 3 ; CHECK-NEXT: li 3, 1
; CHECK-NEXT: std 0, 120(1)
; CHECK-NEXT: std 3, 104(1)
shchenzUnsubmitted
Done
ReplyInline Actions

Seems positive, now we use less CSRs.

shchenz: Seems positive, now we use less CSRs.
; CHECK-NEXT: mr 3, 12 ; CHECK-NEXT: mr 3, 12
; CHECK-NEXT: mr 7, 11
; CHECK-NEXT: std 0, 104(1)
; CHECK-NEXT: std 28, 112(1)
; CHECK-NEXT: std 29, 96(1)
; CHECK-NEXT: std 30, 120(1)
; CHECK-NEXT: bl _ZN5clang6format17WhitespaceManager24replaceWhitespaceInTokenERKNS0_11FormatTokenEjjN4llvm9StringRefES6_bjji ; CHECK-NEXT: bl _ZN5clang6format17WhitespaceManager24replaceWhitespaceInTokenERKNS0_11FormatTokenEjjN4llvm9StringRefES6_bjji
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi 1, 1, 160 ; CHECK-NEXT: addi 1, 1, 144
; CHECK-NEXT: ld 0, 16(1) ; CHECK-NEXT: ld 0, 16(1)
; CHECK-NEXT: ld 30, -16(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 30, -16(1) # 8-byte Folded Reload
; CHECK-NEXT: ld 29, -24(1) # 8-byte Folded Reload
; CHECK-NEXT: ld 28, -32(1) # 8-byte Folded Reload
; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%Split.coerce.fca.0.extract = extractvalue [2 x i64] %Split.coerce, 0 %Split.coerce.fca.0.extract = extractvalue [2 x i64] %Split.coerce, 0
%Split.coerce.fca.1.extract = extractvalue [2 x i64] %Split.coerce, 1 %Split.coerce.fca.1.extract = extractvalue [2 x i64] %Split.coerce, 1
%StartColumn = getelementptr inbounds %"class.clang::format::BreakableStringLiteral", ptr %this, i64 0, i32 0, i32 1 %StartColumn = getelementptr inbounds %"class.clang::format::BreakableStringLiteral", ptr %this, i64 0, i32 0, i32 1
%0 = load i32, ptr %StartColumn, align 8, !tbaa !2 %0 = load i32, ptr %StartColumn, align 8, !tbaa !2
%Prefix = getelementptr inbounds %"class.clang::format::BreakableStringLiteral", ptr %this, i64 0, i32 0, i32 2 %Prefix = getelementptr inbounds %"class.clang::format::BreakableStringLiteral", ptr %this, i64 0, i32 0, i32 2
▲ Show 20 Lines • Show All 114 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/CSR-fit.ll

llvm/test/CodeGen/PowerPC/CompareEliminationSpillIssue.ll

llvm/test/CodeGen/PowerPC/P10-stack-alignment.ll

Show All 16 Lines
; CHECK-LE-NEXT: mflr r0 ; CHECK-LE-NEXT: mflr r0
; CHECK-LE-NEXT: std r30, -16(r1) ; CHECK-LE-NEXT: std r30, -16(r1)
; CHECK-LE-NEXT: mr r30, r1 ; CHECK-LE-NEXT: mr r30, r1
; CHECK-LE-NEXT: std r0, 16(r1) ; CHECK-LE-NEXT: std r0, 16(r1)
; CHECK-LE-NEXT: clrldi r0, r1, 59 ; CHECK-LE-NEXT: clrldi r0, r1, 59
; CHECK-LE-NEXT: subfic r0, r0, -96 ; CHECK-LE-NEXT: subfic r0, r0, -96
; CHECK-LE-NEXT: stdux r1, r1, r0 ; CHECK-LE-NEXT: stdux r1, r1, r0
; CHECK-LE-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; CHECK-LE-NEXT: addis r3, r2, .LCPI0_0@toc@ha
; CHECK-LE-NEXT: addis r4, r2, .LCPI0_1@toc@ha
; CHECK-LE-NEXT: addi r3, r3, .LCPI0_0@toc@l ; CHECK-LE-NEXT: addi r3, r3, .LCPI0_0@toc@l
; CHECK-LE-NEXT: addi r4, r4, .LCPI0_1@toc@l
; CHECK-LE-NEXT: lxvd2x vs0, 0, r3 ; CHECK-LE-NEXT: lxvd2x vs0, 0, r3
; CHECK-LE-NEXT: lxvd2x vs1, 0, r4 ; CHECK-LE-NEXT: addi r3, r1, 48
; CHECK-LE-NEXT: addi r4, r1, 48 ; CHECK-LE-NEXT: stxvd2x vs0, 0, r3
; CHECK-LE-NEXT: addis r3, r2, .LCPI0_1@toc@ha
; CHECK-LE-NEXT: addi r3, r3, .LCPI0_1@toc@l
; CHECK-LE-NEXT: lxvd2x vs0, 0, r3
shchenzUnsubmitted
Not Done
ReplyInline Actions

low ILP but less registers?

shchenz: low ILP but less registers?
; CHECK-LE-NEXT: addi r3, r1, 32 ; CHECK-LE-NEXT: addi r3, r1, 32
; CHECK-LE-NEXT: stxvd2x vs0, 0, r4 ; CHECK-LE-NEXT: stxvd2x vs0, 0, r3
; CHECK-LE-NEXT: stxvd2x vs1, 0, r3
; CHECK-LE-NEXT: bl test ; CHECK-LE-NEXT: bl test
; CHECK-LE-NEXT: nop ; CHECK-LE-NEXT: nop
; CHECK-LE-NEXT: lwa r3, 32(r1) ; CHECK-LE-NEXT: lwa r3, 32(r1)
; CHECK-LE-NEXT: mr r1, r30 ; CHECK-LE-NEXT: mr r1, r30
; CHECK-LE-NEXT: ld r0, 16(r1) ; CHECK-LE-NEXT: ld r0, 16(r1)
; CHECK-LE-NEXT: ld r30, -16(r1) ; CHECK-LE-NEXT: ld r30, -16(r1)
; CHECK-LE-NEXT: mtlr r0 ; CHECK-LE-NEXT: mtlr r0
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
▲ Show 20 Lines • Show All 111 Lines • ▼ Show 20 Lines
; CHECK-OPT-LABEL: @test_Array( ; CHECK-OPT-LABEL: @test_Array(
; CHECK-OPT-NEXT: entry: ; CHECK-OPT-NEXT: entry:
; CHECK-OPT-NEXT: %Arr2 = alloca [64 x i16], align 2 ; CHECK-OPT-NEXT: %Arr2 = alloca [64 x i16], align 2
; CHECK-OPT: store <16 x i16> [[TMP0:%.*]], ptr [[TMP0:%.*]], align 2 ; CHECK-OPT: store <16 x i16> [[TMP0:%.*]], ptr [[TMP0:%.*]], align 2
; CHECK-LE-LABEL: test_Array: ; CHECK-LE-LABEL: test_Array:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: mflr r0 ; CHECK-LE-NEXT: mflr r0
; CHECK-LE-NEXT: stdu r1, -176(r1) ; CHECK-LE-NEXT: stdu r1, -176(r1)
; CHECK-LE-NEXT: addis r4, r2, Arr1@toc@ha
; CHECK-LE-NEXT: li r3, 0 ; CHECK-LE-NEXT: li r3, 0
; CHECK-LE-NEXT: std r0, 192(r1) ; CHECK-LE-NEXT: addis r4, r2, Arr1@toc@ha
; CHECK-LE-NEXT: li r6, 65 ; CHECK-LE-NEXT: li r6, 65
; CHECK-LE-NEXT: std r0, 192(r1)
; CHECK-LE-NEXT: addi r5, r1, 46 ; CHECK-LE-NEXT: addi r5, r1, 46
; CHECK-LE-NEXT: addi r4, r4, Arr1@toc@l
; CHECK-LE-NEXT: stw r3, 44(r1) ; CHECK-LE-NEXT: stw r3, 44(r1)
; CHECK-LE-NEXT: addi r4, r4, -1 ; CHECK-LE-NEXT: addi r4, r4, Arr1@toc@l
; CHECK-LE-NEXT: mtctr r6 ; CHECK-LE-NEXT: mtctr r6
; CHECK-LE-NEXT: addi r4, r4, -1
; CHECK-LE-NEXT: bdz .LBB2_2 ; CHECK-LE-NEXT: bdz .LBB2_2
; CHECK-LE-NEXT: .p2align 5 ; CHECK-LE-NEXT: .p2align 5
; CHECK-LE-NEXT: .LBB2_1: # %for.body ; CHECK-LE-NEXT: .LBB2_1: # %for.body
; CHECK-LE-NEXT: # ; CHECK-LE-NEXT: #
; CHECK-LE-NEXT: lbz r6, 1(r4) ; CHECK-LE-NEXT: lbz r6, 1(r4)
; CHECK-LE-NEXT: addi r7, r5, 2
; CHECK-LE-NEXT: addi r4, r4, 1 ; CHECK-LE-NEXT: addi r4, r4, 1
; CHECK-LE-NEXT: addi r3, r3, 1 ; CHECK-LE-NEXT: addi r3, r3, 1
; CHECK-LE-NEXT: sth r6, 2(r5) ; CHECK-LE-NEXT: sth r6, 2(r5)
; CHECK-LE-NEXT: mr r5, r7 ; CHECK-LE-NEXT: addi r5, r5, 2
; CHECK-LE-NEXT: bdnz .LBB2_1 ; CHECK-LE-NEXT: bdnz .LBB2_1
; CHECK-LE-NEXT: .LBB2_2: # %for.cond.cleanup ; CHECK-LE-NEXT: .LBB2_2: # %for.cond.cleanup
; CHECK-LE-NEXT: addi r3, r1, 48 ; CHECK-LE-NEXT: addi r3, r1, 48
; CHECK-LE-NEXT: bl test_arr ; CHECK-LE-NEXT: bl test_arr
; CHECK-LE-NEXT: nop ; CHECK-LE-NEXT: nop
; CHECK-LE-NEXT: addi r1, r1, 176 ; CHECK-LE-NEXT: addi r1, r1, 176
; CHECK-LE-NEXT: ld r0, 16(r1) ; CHECK-LE-NEXT: ld r0, 16(r1)
; CHECK-LE-NEXT: mtlr r0 ; CHECK-LE-NEXT: mtlr r0
▲ Show 20 Lines • Show All 80 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll

llvm/test/CodeGen/PowerPC/VSX-XForm-Scalars.ll

llvm/test/CodeGen/PowerPC/aix-dfltabi-rsrvd-reg.ll

llvm/test/CodeGen/PowerPC/aix-vsx-splatimm.ll

llvm/test/CodeGen/PowerPC/aix32-p8-scalar_vector_conversions.ll

Show All 19 Linesentry:
%splat.splat = shufflevector <16 x i8> %splat.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer %splat.splat = shufflevector <16 x i8> %splat.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer
ret <16 x i8> %splat.splat ret <16 x i8> %splat.splat
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define <8 x i16> @builds(i16 zeroext %a) { define <8 x i16> @builds(i16 zeroext %a) {
; CHECK-LABEL: builds: ; CHECK-LABEL: builds:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi 4, 1, -16
; CHECK-NEXT: sth 3, -16(1) ; CHECK-NEXT: sth 3, -16(1)
; CHECK-NEXT: lxvw4x 34, 0, 4 ; CHECK-NEXT: addi 3, 1, -16
; CHECK-NEXT: lxvw4x 34, 0, 3
shchenzUnsubmitted
Not Done
ReplyInline Actions

lower ILP with less register, I think it is fine only if we get better perf in benchmarks.

shchenz: lower ILP with less register, I think it is fine only if we get better perf in benchmarks.
; CHECK-NEXT: vsplth 2, 2, 0 ; CHECK-NEXT: vsplth 2, 2, 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%splat.splatinsert = insertelement <8 x i16> undef, i16 %a, i32 0 %splat.splatinsert = insertelement <8 x i16> undef, i16 %a, i32 0
%splat.splat = shufflevector <8 x i16> %splat.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer %splat.splat = shufflevector <8 x i16> %splat.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer
ret <8 x i16> %splat.splat ret <8 x i16> %splat.splat
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define <4 x i32> @buildi(i32 zeroext %a) { define <4 x i32> @buildi(i32 zeroext %a) {
; CHECK-LABEL: buildi: ; CHECK-LABEL: buildi:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi 4, 1, -16
; CHECK-NEXT: stw 3, -16(1) ; CHECK-NEXT: stw 3, -16(1)
; CHECK-NEXT: lxvw4x 0, 0, 4 ; CHECK-NEXT: addi 3, 1, -16
; CHECK-NEXT: lxvw4x 0, 0, 3
; CHECK-NEXT: xxspltw 34, 0, 0 ; CHECK-NEXT: xxspltw 34, 0, 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%splat.splatinsert = insertelement <4 x i32> undef, i32 %a, i32 0 %splat.splatinsert = insertelement <4 x i32> undef, i32 %a, i32 0
%splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
ret <4 x i32> %splat.splat ret <4 x i32> %splat.splat
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define <2 x i64> @buildl(i64 %a) { define <2 x i64> @buildl(i64 %a) {
; CHECK-LABEL: buildl: ; CHECK-LABEL: buildl:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lwz 5, L..C0(2) # %const.0
; CHECK-NEXT: stw 4, -16(1)
; CHECK-NEXT: stw 3, -32(1) ; CHECK-NEXT: stw 3, -32(1)
; CHECK-NEXT: lwz 3, L..C0(2) # %const.0
; CHECK-NEXT: stw 4, -16(1)
; CHECK-NEXT: lxvw4x 34, 0, 3
; CHECK-NEXT: addi 3, 1, -16 ; CHECK-NEXT: addi 3, 1, -16
; CHECK-NEXT: addi 4, 1, -32
; CHECK-NEXT: lxvw4x 35, 0, 3 ; CHECK-NEXT: lxvw4x 35, 0, 3
; CHECK-NEXT: lxvw4x 36, 0, 4 ; CHECK-NEXT: addi 3, 1, -32
; CHECK-NEXT: lxvw4x 34, 0, 5 ; CHECK-NEXT: lxvw4x 36, 0, 3
; CHECK-NEXT: vperm 2, 4, 3, 2 ; CHECK-NEXT: vperm 2, 4, 3, 2
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%splat.splatinsert = insertelement <2 x i64> undef, i64 %a, i32 0 %splat.splatinsert = insertelement <2 x i64> undef, i64 %a, i32 0
%splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
ret <2 x i64> %splat.splat ret <2 x i64> %splat.splat
} }
▲ Show 20 Lines • Show All 911 Lines • ▼ Show 20 Linesentry:
%vecext = extractelement <2 x i64> %vul, i32 1 %vecext = extractelement <2 x i64> %vul, i32 1
ret i64 %vecext ret i64 %vecext
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @getvelsl(<2 x i64> %vsl, i32 signext %i) { define i64 @getvelsl(<2 x i64> %vsl, i32 signext %i) {
; CHECK-LABEL: getvelsl: ; CHECK-LABEL: getvelsl:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: add 3, 3, 3 ; CHECK-NEXT: add 5, 3, 3
; CHECK-NEXT: addi 4, 1, -16 ; CHECK-NEXT: addi 4, 1, -16
; CHECK-NEXT: addi 5, 3, 1 ; CHECK-NEXT: rlwinm 3, 5, 2, 28, 29
; CHECK-NEXT: addi 5, 5, 1
; CHECK-NEXT: stxvw4x 34, 0, 4 ; CHECK-NEXT: stxvw4x 34, 0, 4
; CHECK-NEXT: rlwinm 3, 3, 2, 28, 29
; CHECK-NEXT: rlwinm 5, 5, 2, 28, 29 ; CHECK-NEXT: rlwinm 5, 5, 2, 28, 29
; CHECK-NEXT: lwzx 3, 4, 3 ; CHECK-NEXT: lwzx 3, 4, 3
; CHECK-NEXT: lwzx 4, 4, 5 ; CHECK-NEXT: lwzx 4, 4, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%vecext = extractelement <2 x i64> %vsl, i32 %i %vecext = extractelement <2 x i64> %vsl, i32 %i
ret i64 %vecext ret i64 %vecext
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @getvelul(<2 x i64> %vul, i32 signext %i) { define i64 @getvelul(<2 x i64> %vul, i32 signext %i) {
; CHECK-LABEL: getvelul: ; CHECK-LABEL: getvelul:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: add 3, 3, 3 ; CHECK-NEXT: add 5, 3, 3
; CHECK-NEXT: addi 4, 1, -16 ; CHECK-NEXT: addi 4, 1, -16
; CHECK-NEXT: addi 5, 3, 1 ; CHECK-NEXT: rlwinm 3, 5, 2, 28, 29
; CHECK-NEXT: addi 5, 5, 1
; CHECK-NEXT: stxvw4x 34, 0, 4 ; CHECK-NEXT: stxvw4x 34, 0, 4
; CHECK-NEXT: rlwinm 3, 3, 2, 28, 29
; CHECK-NEXT: rlwinm 5, 5, 2, 28, 29 ; CHECK-NEXT: rlwinm 5, 5, 2, 28, 29
; CHECK-NEXT: lwzx 3, 4, 3 ; CHECK-NEXT: lwzx 3, 4, 3
; CHECK-NEXT: lwzx 4, 4, 5 ; CHECK-NEXT: lwzx 4, 4, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%vecext = extractelement <2 x i64> %vul, i32 %i %vecext = extractelement <2 x i64> %vul, i32 %i
ret i64 %vecext ret i64 %vecext
} }
▲ Show 20 Lines • Show All 100 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/aix_scalar_vector_permuted.ll

llvm/test/CodeGen/PowerPC/all-atomics.ll

llvm/test/CodeGen/PowerPC/and-extend-combine.ll

llvm/test/CodeGen/PowerPC/asm-template-I.ll

llvm/test/CodeGen/PowerPC/atomics-i128-ldst.ll

llvm/test/CodeGen/PowerPC/atomics-i128.ll

Show First 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
; PPC-PWR8-NEXT: stwu r1, -48(r1) ; PPC-PWR8-NEXT: stwu r1, -48(r1)
; PPC-PWR8-NEXT: stw r0, 52(r1) ; PPC-PWR8-NEXT: stw r0, 52(r1)
; PPC-PWR8-NEXT: .cfi_def_cfa_offset 48 ; PPC-PWR8-NEXT: .cfi_def_cfa_offset 48
; PPC-PWR8-NEXT: .cfi_offset lr, 4 ; PPC-PWR8-NEXT: .cfi_offset lr, 4
; PPC-PWR8-NEXT: mr r4, r3 ; PPC-PWR8-NEXT: mr r4, r3
; PPC-PWR8-NEXT: stw r7, 40(r1) ; PPC-PWR8-NEXT: stw r7, 40(r1)
; PPC-PWR8-NEXT: stw r6, 36(r1) ; PPC-PWR8-NEXT: stw r6, 36(r1)
; PPC-PWR8-NEXT: addi r6, r1, 16 ; PPC-PWR8-NEXT: addi r6, r1, 16
; PPC-PWR8-NEXT: li r3, 16
; PPC-PWR8-NEXT: li r7, 5
; PPC-PWR8-NEXT: stw r5, 32(r1) ; PPC-PWR8-NEXT: stw r5, 32(r1)
; PPC-PWR8-NEXT: addi r5, r1, 32 ; PPC-PWR8-NEXT: addi r5, r1, 32
; PPC-PWR8-NEXT: li r3, 16
; PPC-PWR8-NEXT: li r7, 5
; PPC-PWR8-NEXT: stw r8, 44(r1) ; PPC-PWR8-NEXT: stw r8, 44(r1)
; PPC-PWR8-NEXT: bl __atomic_exchange ; PPC-PWR8-NEXT: bl __atomic_exchange
; PPC-PWR8-NEXT: lwz r6, 28(r1) ; PPC-PWR8-NEXT: lwz r6, 28(r1)
; PPC-PWR8-NEXT: lwz r5, 24(r1) ; PPC-PWR8-NEXT: lwz r5, 24(r1)
; PPC-PWR8-NEXT: lwz r4, 20(r1) ; PPC-PWR8-NEXT: lwz r4, 20(r1)
; PPC-PWR8-NEXT: lwz r3, 16(r1) ; PPC-PWR8-NEXT: lwz r3, 16(r1)
; PPC-PWR8-NEXT: lwz r0, 52(r1) ; PPC-PWR8-NEXT: lwz r0, 52(r1)
; PPC-PWR8-NEXT: addi r1, r1, 48 ; PPC-PWR8-NEXT: addi r1, r1, 48
▲ Show 20 Lines • Show All 81 Lines • ▼ Show 20 Lines
; PPC-PWR8-NEXT: .cfi_offset r27, -20 ; PPC-PWR8-NEXT: .cfi_offset r27, -20
; PPC-PWR8-NEXT: .cfi_offset r28, -16 ; PPC-PWR8-NEXT: .cfi_offset r28, -16
; PPC-PWR8-NEXT: .cfi_offset r29, -12 ; PPC-PWR8-NEXT: .cfi_offset r29, -12
; PPC-PWR8-NEXT: .cfi_offset r30, -8 ; PPC-PWR8-NEXT: .cfi_offset r30, -8
; PPC-PWR8-NEXT: stw r26, 56(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r26, 56(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: stw r27, 60(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r27, 60(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: mr r27, r5 ; PPC-PWR8-NEXT: mr r27, r5
; PPC-PWR8-NEXT: mr r26, r3 ; PPC-PWR8-NEXT: mr r26, r3
; PPC-PWR8-NEXT: lwz r5, 8(r3)
; PPC-PWR8-NEXT: lwz r4, 4(r3)
; PPC-PWR8-NEXT: stw r28, 64(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r28, 64(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: mr r28, r6 ; PPC-PWR8-NEXT: mr r28, r6
; PPC-PWR8-NEXT: lwz r6, 12(r3) ; PPC-PWR8-NEXT: lwz r6, 12(r3)
; PPC-PWR8-NEXT: lwz r3, 0(r3)
; PPC-PWR8-NEXT: stw r24, 48(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r24, 48(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: addi r24, r1, 16 ; PPC-PWR8-NEXT: lwz r5, 8(r3)
; PPC-PWR8-NEXT: lwz r4, 4(r3)
; PPC-PWR8-NEXT: stw r25, 52(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r25, 52(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: addi r25, r1, 32
; PPC-PWR8-NEXT: lwz r3, 0(r3)
; PPC-PWR8-NEXT: stw r29, 68(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r29, 68(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: mr r29, r7 ; PPC-PWR8-NEXT: mr r29, r7
; PPC-PWR8-NEXT: addi r25, r1, 32 ; PPC-PWR8-NEXT: addi r24, r1, 16
; PPC-PWR8-NEXT: stw r30, 72(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r30, 72(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: mr r30, r8 ; PPC-PWR8-NEXT: mr r30, r8
; PPC-PWR8-NEXT: .p2align 4 ; PPC-PWR8-NEXT: .p2align 4
; PPC-PWR8-NEXT: .LBB1_1: # %atomicrmw.start ; PPC-PWR8-NEXT: .LBB1_1: # %atomicrmw.start
; PPC-PWR8-NEXT: # ; PPC-PWR8-NEXT: #
; PPC-PWR8-NEXT: addc r7, r6, r30 ; PPC-PWR8-NEXT: addc r7, r6, r30
; PPC-PWR8-NEXT: stw r4, 36(r1) ; PPC-PWR8-NEXT: stw r4, 36(r1)
; PPC-PWR8-NEXT: stw r3, 32(r1) ; PPC-PWR8-NEXT: stw r3, 32(r1)
; PPC-PWR8-NEXT: adde r8, r5, r29 ; PPC-PWR8-NEXT: adde r8, r5, r29
; PPC-PWR8-NEXT: stw r5, 40(r1) ; PPC-PWR8-NEXT: stw r5, 40(r1)
; PPC-PWR8-NEXT: stw r6, 44(r1) ; PPC-PWR8-NEXT: stw r6, 44(r1)
; PPC-PWR8-NEXT: mr r5, r25 ; PPC-PWR8-NEXT: mr r5, r25
; PPC-PWR8-NEXT: mr r6, r24
; PPC-PWR8-NEXT: adde r4, r4, r28 ; PPC-PWR8-NEXT: adde r4, r4, r28
; PPC-PWR8-NEXT: stw r7, 28(r1) ; PPC-PWR8-NEXT: stw r7, 28(r1)
; PPC-PWR8-NEXT: stw r8, 24(r1) ; PPC-PWR8-NEXT: li r7, 5
; PPC-PWR8-NEXT: mr r6, r24
; PPC-PWR8-NEXT: adde r3, r3, r27 ; PPC-PWR8-NEXT: adde r3, r3, r27
; PPC-PWR8-NEXT: stw r8, 24(r1)
; PPC-PWR8-NEXT: li r8, 5
; PPC-PWR8-NEXT: stw r4, 20(r1) ; PPC-PWR8-NEXT: stw r4, 20(r1)
; PPC-PWR8-NEXT: mr r4, r26 ; PPC-PWR8-NEXT: mr r4, r26
; PPC-PWR8-NEXT: li r7, 5
; PPC-PWR8-NEXT: stw r3, 16(r1) ; PPC-PWR8-NEXT: stw r3, 16(r1)
; PPC-PWR8-NEXT: li r3, 16 ; PPC-PWR8-NEXT: li r3, 16
; PPC-PWR8-NEXT: li r8, 5
; PPC-PWR8-NEXT: bl __atomic_compare_exchange ; PPC-PWR8-NEXT: bl __atomic_compare_exchange
; PPC-PWR8-NEXT: cmplwi r3, 0 ; PPC-PWR8-NEXT: mr r7, r3
; PPC-PWR8-NEXT: lwz r6, 44(r1) ; PPC-PWR8-NEXT: lwz r6, 44(r1)
; PPC-PWR8-NEXT: lwz r5, 40(r1) ; PPC-PWR8-NEXT: lwz r5, 40(r1)
; PPC-PWR8-NEXT: lwz r4, 36(r1) ; PPC-PWR8-NEXT: lwz r4, 36(r1)
; PPC-PWR8-NEXT: lwz r3, 32(r1) ; PPC-PWR8-NEXT: lwz r3, 32(r1)
; PPC-PWR8-NEXT: cmplwi r7, 0
; PPC-PWR8-NEXT: beq cr0, .LBB1_1 ; PPC-PWR8-NEXT: beq cr0, .LBB1_1
; PPC-PWR8-NEXT: # %bb.2: # %atomicrmw.end ; PPC-PWR8-NEXT: # %bb.2: # %atomicrmw.end
; PPC-PWR8-NEXT: lwz r30, 72(r1) # 4-byte Folded Reload ; PPC-PWR8-NEXT: lwz r30, 72(r1) # 4-byte Folded Reload
; PPC-PWR8-NEXT: lwz r29, 68(r1) # 4-byte Folded Reload ; PPC-PWR8-NEXT: lwz r29, 68(r1) # 4-byte Folded Reload
; PPC-PWR8-NEXT: lwz r28, 64(r1) # 4-byte Folded Reload ; PPC-PWR8-NEXT: lwz r28, 64(r1) # 4-byte Folded Reload
; PPC-PWR8-NEXT: lwz r27, 60(r1) # 4-byte Folded Reload ; PPC-PWR8-NEXT: lwz r27, 60(r1) # 4-byte Folded Reload
; PPC-PWR8-NEXT: lwz r26, 56(r1) # 4-byte Folded Reload ; PPC-PWR8-NEXT: lwz r26, 56(r1) # 4-byte Folded Reload
; PPC-PWR8-NEXT: lwz r25, 52(r1) # 4-byte Folded Reload ; PPC-PWR8-NEXT: lwz r25, 52(r1) # 4-byte Folded Reload
▲ Show 20 Lines • Show All 84 Lines • ▼ Show 20 Lines
; PPC-PWR8-NEXT: .cfi_offset r27, -20 ; PPC-PWR8-NEXT: .cfi_offset r27, -20
; PPC-PWR8-NEXT: .cfi_offset r28, -16 ; PPC-PWR8-NEXT: .cfi_offset r28, -16
; PPC-PWR8-NEXT: .cfi_offset r29, -12 ; PPC-PWR8-NEXT: .cfi_offset r29, -12
; PPC-PWR8-NEXT: .cfi_offset r30, -8 ; PPC-PWR8-NEXT: .cfi_offset r30, -8
; PPC-PWR8-NEXT: stw r26, 56(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r26, 56(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: stw r27, 60(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r27, 60(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: mr r27, r5 ; PPC-PWR8-NEXT: mr r27, r5
; PPC-PWR8-NEXT: mr r26, r3 ; PPC-PWR8-NEXT: mr r26, r3
; PPC-PWR8-NEXT: lwz r5, 8(r3)
; PPC-PWR8-NEXT: lwz r4, 4(r3)
; PPC-PWR8-NEXT: stw r28, 64(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r28, 64(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: mr r28, r6 ; PPC-PWR8-NEXT: mr r28, r6
; PPC-PWR8-NEXT: lwz r6, 12(r3) ; PPC-PWR8-NEXT: lwz r6, 12(r3)
; PPC-PWR8-NEXT: lwz r3, 0(r3)
; PPC-PWR8-NEXT: stw r24, 48(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r24, 48(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: addi r24, r1, 16 ; PPC-PWR8-NEXT: lwz r5, 8(r3)
; PPC-PWR8-NEXT: lwz r4, 4(r3)
; PPC-PWR8-NEXT: stw r25, 52(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r25, 52(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: addi r25, r1, 32
; PPC-PWR8-NEXT: lwz r3, 0(r3)
; PPC-PWR8-NEXT: stw r29, 68(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r29, 68(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: mr r29, r7 ; PPC-PWR8-NEXT: mr r29, r7
; PPC-PWR8-NEXT: addi r25, r1, 32 ; PPC-PWR8-NEXT: addi r24, r1, 16
; PPC-PWR8-NEXT: stw r30, 72(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r30, 72(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: mr r30, r8 ; PPC-PWR8-NEXT: mr r30, r8
; PPC-PWR8-NEXT: .p2align 4 ; PPC-PWR8-NEXT: .p2align 4
; PPC-PWR8-NEXT: .LBB2_1: # %atomicrmw.start ; PPC-PWR8-NEXT: .LBB2_1: # %atomicrmw.start
; PPC-PWR8-NEXT: # ; PPC-PWR8-NEXT: #
; PPC-PWR8-NEXT: subc r7, r6, r30 ; PPC-PWR8-NEXT: subc r7, r6, r30
; PPC-PWR8-NEXT: stw r4, 36(r1) ; PPC-PWR8-NEXT: stw r4, 36(r1)
; PPC-PWR8-NEXT: stw r3, 32(r1) ; PPC-PWR8-NEXT: stw r3, 32(r1)
; PPC-PWR8-NEXT: subfe r8, r29, r5 ; PPC-PWR8-NEXT: subfe r8, r29, r5
; PPC-PWR8-NEXT: stw r5, 40(r1) ; PPC-PWR8-NEXT: stw r5, 40(r1)
; PPC-PWR8-NEXT: stw r6, 44(r1) ; PPC-PWR8-NEXT: stw r6, 44(r1)
; PPC-PWR8-NEXT: mr r5, r25 ; PPC-PWR8-NEXT: mr r5, r25
; PPC-PWR8-NEXT: mr r6, r24
; PPC-PWR8-NEXT: subfe r4, r28, r4 ; PPC-PWR8-NEXT: subfe r4, r28, r4
; PPC-PWR8-NEXT: stw r7, 28(r1) ; PPC-PWR8-NEXT: stw r7, 28(r1)
; PPC-PWR8-NEXT: stw r8, 24(r1) ; PPC-PWR8-NEXT: li r7, 5
; PPC-PWR8-NEXT: mr r6, r24
; PPC-PWR8-NEXT: subfe r3, r27, r3 ; PPC-PWR8-NEXT: subfe r3, r27, r3
; PPC-PWR8-NEXT: stw r8, 24(r1)
; PPC-PWR8-NEXT: li r8, 5
; PPC-PWR8-NEXT: stw r4, 20(r1) ; PPC-PWR8-NEXT: stw r4, 20(r1)
; PPC-PWR8-NEXT: mr r4, r26 ; PPC-PWR8-NEXT: mr r4, r26
; PPC-PWR8-NEXT: li r7, 5
; PPC-PWR8-NEXT: stw r3, 16(r1) ; PPC-PWR8-NEXT: stw r3, 16(r1)
; PPC-PWR8-NEXT: li r3, 16 ; PPC-PWR8-NEXT: li r3, 16
; PPC-PWR8-NEXT: li r8, 5
; PPC-PWR8-NEXT: bl __atomic_compare_exchange ; PPC-PWR8-NEXT: bl __atomic_compare_exchange
; PPC-PWR8-NEXT: cmplwi r3, 0 ; PPC-PWR8-NEXT: mr r7, r3
; PPC-PWR8-NEXT: lwz r6, 44(r1) ; PPC-PWR8-NEXT: lwz r6, 44(r1)
; PPC-PWR8-NEXT: lwz r5, 40(r1) ; PPC-PWR8-NEXT: lwz r5, 40(r1)
; PPC-PWR8-NEXT: lwz r4, 36(r1) ; PPC-PWR8-NEXT: lwz r4, 36(r1)
; PPC-PWR8-NEXT: lwz r3, 32(r1) ; PPC-PWR8-NEXT: lwz r3, 32(r1)
; PPC-PWR8-NEXT: cmplwi r7, 0
; PPC-PWR8-NEXT: beq cr0, .LBB2_1 ; PPC-PWR8-NEXT: beq cr0, .LBB2_1
; PPC-PWR8-NEXT: # %bb.2: # %atomicrmw.end ; PPC-PWR8-NEXT: # %bb.2: # %atomicrmw.end
; PPC-PWR8-NEXT: lwz r30, 72(r1) # 4-byte Folded Reload ; PPC-PWR8-NEXT: lwz r30, 72(r1) # 4-byte Folded Reload
; PPC-PWR8-NEXT: lwz r29, 68(r1) # 4-byte Folded Reload ; PPC-PWR8-NEXT: lwz r29, 68(r1) # 4-byte Folded Reload
; PPC-PWR8-NEXT: lwz r28, 64(r1) # 4-byte Folded Reload ; PPC-PWR8-NEXT: lwz r28, 64(r1) # 4-byte Folded Reload
; PPC-PWR8-NEXT: lwz r27, 60(r1) # 4-byte Folded Reload ; PPC-PWR8-NEXT: lwz r27, 60(r1) # 4-byte Folded Reload
; PPC-PWR8-NEXT: lwz r26, 56(r1) # 4-byte Folded Reload ; PPC-PWR8-NEXT: lwz r26, 56(r1) # 4-byte Folded Reload
; PPC-PWR8-NEXT: lwz r25, 52(r1) # 4-byte Folded Reload ; PPC-PWR8-NEXT: lwz r25, 52(r1) # 4-byte Folded Reload
▲ Show 20 Lines • Show All 84 Lines • ▼ Show 20 Lines
; PPC-PWR8-NEXT: .cfi_offset r27, -20 ; PPC-PWR8-NEXT: .cfi_offset r27, -20
; PPC-PWR8-NEXT: .cfi_offset r28, -16 ; PPC-PWR8-NEXT: .cfi_offset r28, -16
; PPC-PWR8-NEXT: .cfi_offset r29, -12 ; PPC-PWR8-NEXT: .cfi_offset r29, -12
; PPC-PWR8-NEXT: .cfi_offset r30, -8 ; PPC-PWR8-NEXT: .cfi_offset r30, -8
; PPC-PWR8-NEXT: stw r26, 56(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r26, 56(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: stw r27, 60(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r27, 60(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: mr r27, r5 ; PPC-PWR8-NEXT: mr r27, r5
; PPC-PWR8-NEXT: mr r26, r3 ; PPC-PWR8-NEXT: mr r26, r3
; PPC-PWR8-NEXT: lwz r5, 8(r3)
; PPC-PWR8-NEXT: lwz r4, 4(r3)
; PPC-PWR8-NEXT: stw r28, 64(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r28, 64(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: mr r28, r6 ; PPC-PWR8-NEXT: mr r28, r6
; PPC-PWR8-NEXT: lwz r6, 12(r3) ; PPC-PWR8-NEXT: lwz r6, 12(r3)
; PPC-PWR8-NEXT: lwz r3, 0(r3)
; PPC-PWR8-NEXT: stw r24, 48(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r24, 48(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: addi r24, r1, 16 ; PPC-PWR8-NEXT: lwz r5, 8(r3)
; PPC-PWR8-NEXT: lwz r4, 4(r3)
; PPC-PWR8-NEXT: stw r25, 52(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r25, 52(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: addi r25, r1, 32
; PPC-PWR8-NEXT: lwz r3, 0(r3)
; PPC-PWR8-NEXT: stw r29, 68(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r29, 68(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: mr r29, r7 ; PPC-PWR8-NEXT: mr r29, r7
; PPC-PWR8-NEXT: addi r25, r1, 32 ; PPC-PWR8-NEXT: addi r24, r1, 16
; PPC-PWR8-NEXT: stw r30, 72(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r30, 72(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: mr r30, r8 ; PPC-PWR8-NEXT: mr r30, r8
; PPC-PWR8-NEXT: .p2align 4 ; PPC-PWR8-NEXT: .p2align 4
; PPC-PWR8-NEXT: .LBB3_1: # %atomicrmw.start ; PPC-PWR8-NEXT: .LBB3_1: # %atomicrmw.start
; PPC-PWR8-NEXT: # ; PPC-PWR8-NEXT: #
; PPC-PWR8-NEXT: stw r3, 32(r1) ; PPC-PWR8-NEXT: stw r3, 32(r1)
; PPC-PWR8-NEXT: stw r4, 36(r1)
; PPC-PWR8-NEXT: and r7, r5, r29
; PPC-PWR8-NEXT: and r8, r6, r30
; PPC-PWR8-NEXT: and r3, r3, r27 ; PPC-PWR8-NEXT: and r3, r3, r27
; PPC-PWR8-NEXT: stw r4, 36(r1)
; PPC-PWR8-NEXT: and r4, r4, r28 ; PPC-PWR8-NEXT: and r4, r4, r28
; PPC-PWR8-NEXT: and r7, r5, r29
; PPC-PWR8-NEXT: stw r5, 40(r1) ; PPC-PWR8-NEXT: stw r5, 40(r1)
; PPC-PWR8-NEXT: and r5, r6, r30
; PPC-PWR8-NEXT: stw r6, 44(r1) ; PPC-PWR8-NEXT: stw r6, 44(r1)
shchenzUnsubmitted
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negative change, now we have more mr which is not free on pwr8.

shchenz: negative change, now we have more `mr` which is not free on pwr8.
qiucfAuthorUnsubmitted
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The BB with negative result is quite simple:

SU(0):   %29:gprc = COPY $r3
SU(1):   %34:gprc = LWZ 12, %stack.0
SU(2):   %33:gprc = LWZ 8, %stack.0
SU(3):   %32:gprc = LWZ 4, %stack.0
SU(4):   %31:gprc = LWZ 0, %stack.0
SU(5):   %30:crrc = CMPLWI %29:gprc, 0

The old scheduling model puts SU(5) just after SU(0), so that %29:gprc is assigned with r3. With the new scheduling model, the BB is unchanged after pre-isel scheduling.

I think it's more likely an issue of the scheduler exposed by new model and I'll further look at why regpressure is not respected here. But here I'm curious why the register allocator not assign r3 to %29.

qiucf: The BB with negative result is quite simple: ``` SU(0): %29:gprc = COPY $r3 SU(1): %34…
; PPC-PWR8-NEXT: mr r5, r25 ; PPC-PWR8-NEXT: stw r5, 28(r1)
; PPC-PWR8-NEXT: mr r6, r24
; PPC-PWR8-NEXT: stw r8, 28(r1)
; PPC-PWR8-NEXT: stw r7, 24(r1) ; PPC-PWR8-NEXT: stw r7, 24(r1)
; PPC-PWR8-NEXT: mr r5, r25
; PPC-PWR8-NEXT: li r7, 5 ; PPC-PWR8-NEXT: li r7, 5
; PPC-PWR8-NEXT: li r8, 5
; PPC-PWR8-NEXT: stw r4, 20(r1) ; PPC-PWR8-NEXT: stw r4, 20(r1)
; PPC-PWR8-NEXT: stw r3, 16(r1) ; PPC-PWR8-NEXT: stw r3, 16(r1)
; PPC-PWR8-NEXT: li r3, 16 ; PPC-PWR8-NEXT: li r3, 16
; PPC-PWR8-NEXT: mr r4, r26 ; PPC-PWR8-NEXT: mr r4, r26
; PPC-PWR8-NEXT: mr r6, r24
; PPC-PWR8-NEXT: li r8, 5
; PPC-PWR8-NEXT: bl __atomic_compare_exchange ; PPC-PWR8-NEXT: bl __atomic_compare_exchange
; PPC-PWR8-NEXT: cmplwi r3, 0 ; PPC-PWR8-NEXT: mr r7, r3
; PPC-PWR8-NEXT: lwz r6, 44(r1) ; PPC-PWR8-NEXT: lwz r6, 44(r1)
; PPC-PWR8-NEXT: lwz r5, 40(r1) ; PPC-PWR8-NEXT: lwz r5, 40(r1)
; PPC-PWR8-NEXT: lwz r4, 36(r1) ; PPC-PWR8-NEXT: lwz r4, 36(r1)
; PPC-PWR8-NEXT: lwz r3, 32(r1) ; PPC-PWR8-NEXT: lwz r3, 32(r1)
; PPC-PWR8-NEXT: cmplwi r7, 0
; PPC-PWR8-NEXT: beq cr0, .LBB3_1 ; PPC-PWR8-NEXT: beq cr0, .LBB3_1
; PPC-PWR8-NEXT: # %bb.2: # %atomicrmw.end ; PPC-PWR8-NEXT: # %bb.2: # %atomicrmw.end
; PPC-PWR8-NEXT: lwz r30, 72(r1) # 4-byte Folded Reload ; PPC-PWR8-NEXT: lwz r30, 72(r1) # 4-byte Folded Reload
; PPC-PWR8-NEXT: lwz r29, 68(r1) # 4-byte Folded Reload ; PPC-PWR8-NEXT: lwz r29, 68(r1) # 4-byte Folded Reload
; PPC-PWR8-NEXT: lwz r28, 64(r1) # 4-byte Folded Reload ; PPC-PWR8-NEXT: lwz r28, 64(r1) # 4-byte Folded Reload
; PPC-PWR8-NEXT: lwz r27, 60(r1) # 4-byte Folded Reload ; PPC-PWR8-NEXT: lwz r27, 60(r1) # 4-byte Folded Reload
; PPC-PWR8-NEXT: lwz r26, 56(r1) # 4-byte Folded Reload ; PPC-PWR8-NEXT: lwz r26, 56(r1) # 4-byte Folded Reload
; PPC-PWR8-NEXT: lwz r25, 52(r1) # 4-byte Folded Reload ; PPC-PWR8-NEXT: lwz r25, 52(r1) # 4-byte Folded Reload
▲ Show 20 Lines • Show All 84 Lines • ▼ Show 20 Lines
; PPC-PWR8-NEXT: .cfi_offset r27, -20 ; PPC-PWR8-NEXT: .cfi_offset r27, -20
; PPC-PWR8-NEXT: .cfi_offset r28, -16 ; PPC-PWR8-NEXT: .cfi_offset r28, -16
; PPC-PWR8-NEXT: .cfi_offset r29, -12 ; PPC-PWR8-NEXT: .cfi_offset r29, -12
; PPC-PWR8-NEXT: .cfi_offset r30, -8 ; PPC-PWR8-NEXT: .cfi_offset r30, -8
; PPC-PWR8-NEXT: stw r26, 56(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r26, 56(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: stw r27, 60(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r27, 60(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: mr r27, r5 ; PPC-PWR8-NEXT: mr r27, r5
; PPC-PWR8-NEXT: mr r26, r3 ; PPC-PWR8-NEXT: mr r26, r3
; PPC-PWR8-NEXT: lwz r5, 8(r3)
; PPC-PWR8-NEXT: lwz r4, 4(r3)
; PPC-PWR8-NEXT: stw r28, 64(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r28, 64(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: mr r28, r6 ; PPC-PWR8-NEXT: mr r28, r6
; PPC-PWR8-NEXT: lwz r6, 12(r3) ; PPC-PWR8-NEXT: lwz r6, 12(r3)
; PPC-PWR8-NEXT: lwz r3, 0(r3)
; PPC-PWR8-NEXT: stw r24, 48(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r24, 48(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: addi r24, r1, 16 ; PPC-PWR8-NEXT: lwz r5, 8(r3)
; PPC-PWR8-NEXT: lwz r4, 4(r3)
; PPC-PWR8-NEXT: stw r25, 52(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r25, 52(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: addi r25, r1, 32
; PPC-PWR8-NEXT: lwz r3, 0(r3)
; PPC-PWR8-NEXT: stw r29, 68(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r29, 68(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: mr r29, r7 ; PPC-PWR8-NEXT: mr r29, r7
; PPC-PWR8-NEXT: addi r25, r1, 32 ; PPC-PWR8-NEXT: addi r24, r1, 16
; PPC-PWR8-NEXT: stw r30, 72(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r30, 72(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: mr r30, r8 ; PPC-PWR8-NEXT: mr r30, r8
; PPC-PWR8-NEXT: .p2align 4 ; PPC-PWR8-NEXT: .p2align 4
; PPC-PWR8-NEXT: .LBB4_1: # %atomicrmw.start ; PPC-PWR8-NEXT: .LBB4_1: # %atomicrmw.start
; PPC-PWR8-NEXT: # ; PPC-PWR8-NEXT: #
; PPC-PWR8-NEXT: stw r3, 32(r1) ; PPC-PWR8-NEXT: stw r3, 32(r1)
; PPC-PWR8-NEXT: stw r4, 36(r1)
; PPC-PWR8-NEXT: or r7, r5, r29
; PPC-PWR8-NEXT: or r8, r6, r30
; PPC-PWR8-NEXT: or r3, r3, r27 ; PPC-PWR8-NEXT: or r3, r3, r27
; PPC-PWR8-NEXT: stw r4, 36(r1)
; PPC-PWR8-NEXT: or r4, r4, r28 ; PPC-PWR8-NEXT: or r4, r4, r28
; PPC-PWR8-NEXT: or r7, r5, r29
; PPC-PWR8-NEXT: stw r5, 40(r1) ; PPC-PWR8-NEXT: stw r5, 40(r1)
; PPC-PWR8-NEXT: or r5, r6, r30
; PPC-PWR8-NEXT: stw r6, 44(r1) ; PPC-PWR8-NEXT: stw r6, 44(r1)
; PPC-PWR8-NEXT: mr r5, r25 ; PPC-PWR8-NEXT: stw r5, 28(r1)
; PPC-PWR8-NEXT: mr r6, r24
; PPC-PWR8-NEXT: stw r8, 28(r1)
; PPC-PWR8-NEXT: stw r7, 24(r1) ; PPC-PWR8-NEXT: stw r7, 24(r1)
; PPC-PWR8-NEXT: mr r5, r25
; PPC-PWR8-NEXT: li r7, 5 ; PPC-PWR8-NEXT: li r7, 5
; PPC-PWR8-NEXT: li r8, 5
; PPC-PWR8-NEXT: stw r4, 20(r1) ; PPC-PWR8-NEXT: stw r4, 20(r1)
; PPC-PWR8-NEXT: stw r3, 16(r1) ; PPC-PWR8-NEXT: stw r3, 16(r1)
; PPC-PWR8-NEXT: li r3, 16 ; PPC-PWR8-NEXT: li r3, 16
; PPC-PWR8-NEXT: mr r4, r26 ; PPC-PWR8-NEXT: mr r4, r26
; PPC-PWR8-NEXT: mr r6, r24
; PPC-PWR8-NEXT: li r8, 5
; PPC-PWR8-NEXT: bl __atomic_compare_exchange ; PPC-PWR8-NEXT: bl __atomic_compare_exchange
; PPC-PWR8-NEXT: cmplwi r3, 0 ; PPC-PWR8-NEXT: mr r7, r3
; PPC-PWR8-NEXT: lwz r6, 44(r1) ; PPC-PWR8-NEXT: lwz r6, 44(r1)
; PPC-PWR8-NEXT: lwz r5, 40(r1) ; PPC-PWR8-NEXT: lwz r5, 40(r1)
; PPC-PWR8-NEXT: lwz r4, 36(r1) ; PPC-PWR8-NEXT: lwz r4, 36(r1)
; PPC-PWR8-NEXT: lwz r3, 32(r1) ; PPC-PWR8-NEXT: lwz r3, 32(r1)
; PPC-PWR8-NEXT: cmplwi r7, 0
; PPC-PWR8-NEXT: beq cr0, .LBB4_1 ; PPC-PWR8-NEXT: beq cr0, .LBB4_1
; PPC-PWR8-NEXT: # %bb.2: # %atomicrmw.end ; PPC-PWR8-NEXT: # %bb.2: # %atomicrmw.end
; PPC-PWR8-NEXT: lwz r30, 72(r1) # 4-byte Folded Reload ; PPC-PWR8-NEXT: lwz r30, 72(r1) # 4-byte Folded Reload
; PPC-PWR8-NEXT: lwz r29, 68(r1) # 4-byte Folded Reload ; PPC-PWR8-NEXT: lwz r29, 68(r1) # 4-byte Folded Reload
; PPC-PWR8-NEXT: lwz r28, 64(r1) # 4-byte Folded Reload ; PPC-PWR8-NEXT: lwz r28, 64(r1) # 4-byte Folded Reload
; PPC-PWR8-NEXT: lwz r27, 60(r1) # 4-byte Folded Reload ; PPC-PWR8-NEXT: lwz r27, 60(r1) # 4-byte Folded Reload
; PPC-PWR8-NEXT: lwz r26, 56(r1) # 4-byte Folded Reload ; PPC-PWR8-NEXT: lwz r26, 56(r1) # 4-byte Folded Reload
; PPC-PWR8-NEXT: lwz r25, 52(r1) # 4-byte Folded Reload ; PPC-PWR8-NEXT: lwz r25, 52(r1) # 4-byte Folded Reload
▲ Show 20 Lines • Show All 84 Lines • ▼ Show 20 Lines
; PPC-PWR8-NEXT: .cfi_offset r27, -20 ; PPC-PWR8-NEXT: .cfi_offset r27, -20
; PPC-PWR8-NEXT: .cfi_offset r28, -16 ; PPC-PWR8-NEXT: .cfi_offset r28, -16
; PPC-PWR8-NEXT: .cfi_offset r29, -12 ; PPC-PWR8-NEXT: .cfi_offset r29, -12
; PPC-PWR8-NEXT: .cfi_offset r30, -8 ; PPC-PWR8-NEXT: .cfi_offset r30, -8
; PPC-PWR8-NEXT: stw r26, 56(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r26, 56(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: stw r27, 60(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r27, 60(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: mr r27, r5 ; PPC-PWR8-NEXT: mr r27, r5
; PPC-PWR8-NEXT: mr r26, r3 ; PPC-PWR8-NEXT: mr r26, r3
; PPC-PWR8-NEXT: lwz r5, 8(r3)
; PPC-PWR8-NEXT: lwz r4, 4(r3)
; PPC-PWR8-NEXT: stw r28, 64(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r28, 64(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: mr r28, r6 ; PPC-PWR8-NEXT: mr r28, r6
; PPC-PWR8-NEXT: lwz r6, 12(r3) ; PPC-PWR8-NEXT: lwz r6, 12(r3)
; PPC-PWR8-NEXT: lwz r3, 0(r3)
; PPC-PWR8-NEXT: stw r24, 48(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r24, 48(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: addi r24, r1, 16 ; PPC-PWR8-NEXT: lwz r5, 8(r3)
; PPC-PWR8-NEXT: lwz r4, 4(r3)
; PPC-PWR8-NEXT: stw r25, 52(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r25, 52(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: addi r25, r1, 32
; PPC-PWR8-NEXT: lwz r3, 0(r3)
; PPC-PWR8-NEXT: stw r29, 68(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r29, 68(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: mr r29, r7 ; PPC-PWR8-NEXT: mr r29, r7
; PPC-PWR8-NEXT: addi r25, r1, 32 ; PPC-PWR8-NEXT: addi r24, r1, 16
; PPC-PWR8-NEXT: stw r30, 72(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r30, 72(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: mr r30, r8 ; PPC-PWR8-NEXT: mr r30, r8
; PPC-PWR8-NEXT: .p2align 4 ; PPC-PWR8-NEXT: .p2align 4
; PPC-PWR8-NEXT: .LBB5_1: # %atomicrmw.start ; PPC-PWR8-NEXT: .LBB5_1: # %atomicrmw.start
; PPC-PWR8-NEXT: # ; PPC-PWR8-NEXT: #
; PPC-PWR8-NEXT: stw r3, 32(r1) ; PPC-PWR8-NEXT: stw r3, 32(r1)
; PPC-PWR8-NEXT: stw r4, 36(r1)
; PPC-PWR8-NEXT: xor r7, r5, r29
; PPC-PWR8-NEXT: xor r8, r6, r30
; PPC-PWR8-NEXT: xor r3, r3, r27 ; PPC-PWR8-NEXT: xor r3, r3, r27
; PPC-PWR8-NEXT: stw r4, 36(r1)
; PPC-PWR8-NEXT: xor r4, r4, r28 ; PPC-PWR8-NEXT: xor r4, r4, r28
; PPC-PWR8-NEXT: xor r7, r5, r29
; PPC-PWR8-NEXT: stw r5, 40(r1) ; PPC-PWR8-NEXT: stw r5, 40(r1)
; PPC-PWR8-NEXT: xor r5, r6, r30
; PPC-PWR8-NEXT: stw r6, 44(r1) ; PPC-PWR8-NEXT: stw r6, 44(r1)
; PPC-PWR8-NEXT: mr r5, r25 ; PPC-PWR8-NEXT: stw r5, 28(r1)
; PPC-PWR8-NEXT: mr r6, r24
; PPC-PWR8-NEXT: stw r8, 28(r1)
; PPC-PWR8-NEXT: stw r7, 24(r1) ; PPC-PWR8-NEXT: stw r7, 24(r1)
; PPC-PWR8-NEXT: mr r5, r25
; PPC-PWR8-NEXT: li r7, 5 ; PPC-PWR8-NEXT: li r7, 5
; PPC-PWR8-NEXT: li r8, 5
; PPC-PWR8-NEXT: stw r4, 20(r1) ; PPC-PWR8-NEXT: stw r4, 20(r1)
; PPC-PWR8-NEXT: stw r3, 16(r1) ; PPC-PWR8-NEXT: stw r3, 16(r1)
; PPC-PWR8-NEXT: li r3, 16 ; PPC-PWR8-NEXT: li r3, 16
; PPC-PWR8-NEXT: mr r4, r26 ; PPC-PWR8-NEXT: mr r4, r26
; PPC-PWR8-NEXT: mr r6, r24
; PPC-PWR8-NEXT: li r8, 5
; PPC-PWR8-NEXT: bl __atomic_compare_exchange ; PPC-PWR8-NEXT: bl __atomic_compare_exchange
; PPC-PWR8-NEXT: cmplwi r3, 0 ; PPC-PWR8-NEXT: mr r7, r3
; PPC-PWR8-NEXT: lwz r6, 44(r1) ; PPC-PWR8-NEXT: lwz r6, 44(r1)
; PPC-PWR8-NEXT: lwz r5, 40(r1) ; PPC-PWR8-NEXT: lwz r5, 40(r1)
; PPC-PWR8-NEXT: lwz r4, 36(r1) ; PPC-PWR8-NEXT: lwz r4, 36(r1)
; PPC-PWR8-NEXT: lwz r3, 32(r1) ; PPC-PWR8-NEXT: lwz r3, 32(r1)
; PPC-PWR8-NEXT: cmplwi r7, 0
; PPC-PWR8-NEXT: beq cr0, .LBB5_1 ; PPC-PWR8-NEXT: beq cr0, .LBB5_1
; PPC-PWR8-NEXT: # %bb.2: # %atomicrmw.end ; PPC-PWR8-NEXT: # %bb.2: # %atomicrmw.end
; PPC-PWR8-NEXT: lwz r30, 72(r1) # 4-byte Folded Reload ; PPC-PWR8-NEXT: lwz r30, 72(r1) # 4-byte Folded Reload
; PPC-PWR8-NEXT: lwz r29, 68(r1) # 4-byte Folded Reload ; PPC-PWR8-NEXT: lwz r29, 68(r1) # 4-byte Folded Reload
; PPC-PWR8-NEXT: lwz r28, 64(r1) # 4-byte Folded Reload ; PPC-PWR8-NEXT: lwz r28, 64(r1) # 4-byte Folded Reload
; PPC-PWR8-NEXT: lwz r27, 60(r1) # 4-byte Folded Reload ; PPC-PWR8-NEXT: lwz r27, 60(r1) # 4-byte Folded Reload
; PPC-PWR8-NEXT: lwz r26, 56(r1) # 4-byte Folded Reload ; PPC-PWR8-NEXT: lwz r26, 56(r1) # 4-byte Folded Reload
; PPC-PWR8-NEXT: lwz r25, 52(r1) # 4-byte Folded Reload ; PPC-PWR8-NEXT: lwz r25, 52(r1) # 4-byte Folded Reload
▲ Show 20 Lines • Show All 84 Lines • ▼ Show 20 Lines
; PPC-PWR8-NEXT: .cfi_offset r27, -20 ; PPC-PWR8-NEXT: .cfi_offset r27, -20
; PPC-PWR8-NEXT: .cfi_offset r28, -16 ; PPC-PWR8-NEXT: .cfi_offset r28, -16
; PPC-PWR8-NEXT: .cfi_offset r29, -12 ; PPC-PWR8-NEXT: .cfi_offset r29, -12
; PPC-PWR8-NEXT: .cfi_offset r30, -8 ; PPC-PWR8-NEXT: .cfi_offset r30, -8
; PPC-PWR8-NEXT: stw r26, 56(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r26, 56(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: stw r27, 60(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r27, 60(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: mr r27, r5 ; PPC-PWR8-NEXT: mr r27, r5
; PPC-PWR8-NEXT: mr r26, r3 ; PPC-PWR8-NEXT: mr r26, r3
; PPC-PWR8-NEXT: lwz r5, 8(r3)
; PPC-PWR8-NEXT: lwz r4, 4(r3)
; PPC-PWR8-NEXT: stw r28, 64(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r28, 64(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: mr r28, r6 ; PPC-PWR8-NEXT: mr r28, r6
; PPC-PWR8-NEXT: lwz r6, 12(r3) ; PPC-PWR8-NEXT: lwz r6, 12(r3)
; PPC-PWR8-NEXT: lwz r3, 0(r3)
; PPC-PWR8-NEXT: stw r24, 48(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r24, 48(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: addi r24, r1, 16 ; PPC-PWR8-NEXT: lwz r5, 8(r3)
; PPC-PWR8-NEXT: lwz r4, 4(r3)
; PPC-PWR8-NEXT: stw r25, 52(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r25, 52(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: addi r25, r1, 32
; PPC-PWR8-NEXT: lwz r3, 0(r3)
; PPC-PWR8-NEXT: stw r29, 68(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r29, 68(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: mr r29, r7 ; PPC-PWR8-NEXT: mr r29, r7
; PPC-PWR8-NEXT: addi r25, r1, 32 ; PPC-PWR8-NEXT: addi r24, r1, 16
; PPC-PWR8-NEXT: stw r30, 72(r1) # 4-byte Folded Spill ; PPC-PWR8-NEXT: stw r30, 72(r1) # 4-byte Folded Spill
; PPC-PWR8-NEXT: mr r30, r8 ; PPC-PWR8-NEXT: mr r30, r8
; PPC-PWR8-NEXT: .p2align 4 ; PPC-PWR8-NEXT: .p2align 4
; PPC-PWR8-NEXT: .LBB6_1: # %atomicrmw.start ; PPC-PWR8-NEXT: .LBB6_1: # %atomicrmw.start
; PPC-PWR8-NEXT: # ; PPC-PWR8-NEXT: #
; PPC-PWR8-NEXT: stw r3, 32(r1) ; PPC-PWR8-NEXT: stw r3, 32(r1)
; PPC-PWR8-NEXT: stw r4, 36(r1)
; PPC-PWR8-NEXT: nand r7, r5, r29
; PPC-PWR8-NEXT: nand r8, r6, r30
; PPC-PWR8-NEXT: nand r3, r3, r27 ; PPC-PWR8-NEXT: nand r3, r3, r27
; PPC-PWR8-NEXT: stw r4, 36(r1)
; PPC-PWR8-NEXT: nand r4, r4, r28 ; PPC-PWR8-NEXT: nand r4, r4, r28
; PPC-PWR8-NEXT: nand r7, r5, r29
; PPC-PWR8-NEXT: stw r5, 40(r1) ; PPC-PWR8-NEXT: stw r5, 40(r1)
; PPC-PWR8-NEXT: nand r5, r6, r30
; PPC-PWR8-NEXT: stw r6, 44(r1) ; PPC-PWR8-NEXT: stw r6, 44(r1)
; PPC-PWR8-NEXT: mr r5, r25 ; PPC-PWR8-NEXT: stw r5, 28(r1)
; PPC-PWR8-NEXT: mr r6, r24
; PPC-PWR8-NEXT: stw r8, 28(r1)
; PPC-PWR8-NEXT: stw r7, 24(r1) ; PPC-PWR8-NEXT: stw r7, 24(r1)
; PPC-PWR8-NEXT: mr r5, r25
; PPC-PWR8-NEXT: li r7, 5 ; PPC-PWR8-NEXT: li r7, 5
; PPC-PWR8-NEXT: li r8, 5
; PPC-PWR8-NEXT: stw r4, 20(r1) ; PPC-PWR8-NEXT: stw r4, 20(r1)
; PPC-PWR8-NEXT: stw r3, 16(r1) ; PPC-PWR8-NEXT: stw r3, 16(r1)
; PPC-PWR8-NEXT: li r3, 16 ; PPC-PWR8-NEXT: li r3, 16
; PPC-PWR8-NEXT: mr r4, r26 ; PPC-PWR8-NEXT: mr r4, r26
; PPC-PWR8-NEXT: mr r6, r24
; PPC-PWR8-NEXT: li r8, 5
; PPC-PWR8-NEXT: bl __atomic_compare_exchange ; PPC-PWR8-NEXT: bl __atomic_compare_exchange
; PPC-PWR8-NEXT: cmplwi r3, 0 ; PPC-PWR8-NEXT: mr r7, r3
; PPC-PWR8-NEXT: lwz r6, 44(r1) ; PPC-PWR8-NEXT: lwz r6, 44(r1)
; PPC-PWR8-NEXT: lwz r5, 40(r1) ; PPC-PWR8-NEXT: lwz r5, 40(r1)
; PPC-PWR8-NEXT: lwz r4, 36(r1) ; PPC-PWR8-NEXT: lwz r4, 36(r1)
; PPC-PWR8-NEXT: lwz r3, 32(r1) ; PPC-PWR8-NEXT: lwz r3, 32(r1)
; PPC-PWR8-NEXT: cmplwi r7, 0
; PPC-PWR8-NEXT: beq cr0, .LBB6_1 ; PPC-PWR8-NEXT: beq cr0, .LBB6_1
; PPC-PWR8-NEXT: # %bb.2: # %atomicrmw.end ; PPC-PWR8-NEXT: # %bb.2: # %atomicrmw.end
; PPC-PWR8-NEXT: lwz r30, 72(r1) # 4-byte Folded Reload ; PPC-PWR8-NEXT: lwz r30, 72(r1) # 4-byte Folded Reload
; PPC-PWR8-NEXT: lwz r29, 68(r1) # 4-byte Folded Reload ; PPC-PWR8-NEXT: lwz r29, 68(r1) # 4-byte Folded Reload
; PPC-PWR8-NEXT: lwz r28, 64(r1) # 4-byte Folded Reload ; PPC-PWR8-NEXT: lwz r28, 64(r1) # 4-byte Folded Reload
; PPC-PWR8-NEXT: lwz r27, 60(r1) # 4-byte Folded Reload ; PPC-PWR8-NEXT: lwz r27, 60(r1) # 4-byte Folded Reload
; PPC-PWR8-NEXT: lwz r26, 56(r1) # 4-byte Folded Reload ; PPC-PWR8-NEXT: lwz r26, 56(r1) # 4-byte Folded Reload
; PPC-PWR8-NEXT: lwz r25, 52(r1) # 4-byte Folded Reload ; PPC-PWR8-NEXT: lwz r25, 52(r1) # 4-byte Folded Reload
▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Lines
; PPC-PWR8-LABEL: cas_weak_acquire_acquire: ; PPC-PWR8-LABEL: cas_weak_acquire_acquire:
; PPC-PWR8: # %bb.0: # %entry ; PPC-PWR8: # %bb.0: # %entry
; PPC-PWR8-NEXT: mflr r0 ; PPC-PWR8-NEXT: mflr r0
; PPC-PWR8-NEXT: stwu r1, -48(r1) ; PPC-PWR8-NEXT: stwu r1, -48(r1)
; PPC-PWR8-NEXT: stw r0, 52(r1) ; PPC-PWR8-NEXT: stw r0, 52(r1)
; PPC-PWR8-NEXT: .cfi_def_cfa_offset 48 ; PPC-PWR8-NEXT: .cfi_def_cfa_offset 48
; PPC-PWR8-NEXT: .cfi_offset lr, 4 ; PPC-PWR8-NEXT: .cfi_offset lr, 4
; PPC-PWR8-NEXT: mr r4, r3 ; PPC-PWR8-NEXT: mr r4, r3
; PPC-PWR8-NEXT: lwz r3, 56(r1) ; PPC-PWR8-NEXT: lwz r3, 60(r1)
; PPC-PWR8-NEXT: lwz r11, 60(r1)
; PPC-PWR8-NEXT: stw r8, 44(r1) ; PPC-PWR8-NEXT: stw r8, 44(r1)
; PPC-PWR8-NEXT: stw r7, 40(r1) ; PPC-PWR8-NEXT: stw r7, 40(r1)
; PPC-PWR8-NEXT: li r7, 2
; PPC-PWR8-NEXT: li r8, 2
; PPC-PWR8-NEXT: stw r6, 36(r1) ; PPC-PWR8-NEXT: stw r6, 36(r1)
; PPC-PWR8-NEXT: stw r5, 32(r1) ; PPC-PWR8-NEXT: stw r5, 32(r1)
; PPC-PWR8-NEXT: addi r5, r1, 32 ; PPC-PWR8-NEXT: addi r5, r1, 32
; PPC-PWR8-NEXT: addi r6, r1, 16 ; PPC-PWR8-NEXT: addi r6, r1, 16
; PPC-PWR8-NEXT: stw r3, 24(r1) ; PPC-PWR8-NEXT: li r7, 2
; PPC-PWR8-NEXT: li r3, 16 ; PPC-PWR8-NEXT: li r8, 2
; PPC-PWR8-NEXT: stw r11, 28(r1)
; PPC-PWR8-NEXT: stw r10, 20(r1) ; PPC-PWR8-NEXT: stw r10, 20(r1)
; PPC-PWR8-NEXT: stw r9, 16(r1) ; PPC-PWR8-NEXT: stw r9, 16(r1)
; PPC-PWR8-NEXT: stw r3, 28(r1)
; PPC-PWR8-NEXT: lwz r3, 56(r1)
; PPC-PWR8-NEXT: stw r3, 24(r1)
; PPC-PWR8-NEXT: li r3, 16
; PPC-PWR8-NEXT: bl __atomic_compare_exchange ; PPC-PWR8-NEXT: bl __atomic_compare_exchange
; PPC-PWR8-NEXT: lwz r6, 44(r1) ; PPC-PWR8-NEXT: lwz r6, 44(r1)
; PPC-PWR8-NEXT: lwz r5, 40(r1) ; PPC-PWR8-NEXT: lwz r5, 40(r1)
; PPC-PWR8-NEXT: lwz r4, 36(r1) ; PPC-PWR8-NEXT: lwz r4, 36(r1)
; PPC-PWR8-NEXT: lwz r3, 32(r1) ; PPC-PWR8-NEXT: lwz r3, 32(r1)
; PPC-PWR8-NEXT: lwz r0, 52(r1) ; PPC-PWR8-NEXT: lwz r0, 52(r1)
; PPC-PWR8-NEXT: addi r1, r1, 48 ; PPC-PWR8-NEXT: addi r1, r1, 48
; PPC-PWR8-NEXT: mtlr r0 ; PPC-PWR8-NEXT: mtlr r0
▲ Show 20 Lines • Show All 103 Lines • ▼ Show 20 Lines
; PPC-PWR8-LABEL: cas_weak_release_monotonic: ; PPC-PWR8-LABEL: cas_weak_release_monotonic:
; PPC-PWR8: # %bb.0: # %entry ; PPC-PWR8: # %bb.0: # %entry
; PPC-PWR8-NEXT: mflr r0 ; PPC-PWR8-NEXT: mflr r0
; PPC-PWR8-NEXT: stwu r1, -48(r1) ; PPC-PWR8-NEXT: stwu r1, -48(r1)
; PPC-PWR8-NEXT: stw r0, 52(r1) ; PPC-PWR8-NEXT: stw r0, 52(r1)
; PPC-PWR8-NEXT: .cfi_def_cfa_offset 48 ; PPC-PWR8-NEXT: .cfi_def_cfa_offset 48
; PPC-PWR8-NEXT: .cfi_offset lr, 4 ; PPC-PWR8-NEXT: .cfi_offset lr, 4
; PPC-PWR8-NEXT: mr r4, r3 ; PPC-PWR8-NEXT: mr r4, r3
; PPC-PWR8-NEXT: lwz r3, 56(r1) ; PPC-PWR8-NEXT: lwz r3, 60(r1)
; PPC-PWR8-NEXT: lwz r11, 60(r1)
; PPC-PWR8-NEXT: stw r8, 44(r1) ; PPC-PWR8-NEXT: stw r8, 44(r1)
; PPC-PWR8-NEXT: stw r7, 40(r1) ; PPC-PWR8-NEXT: stw r7, 40(r1)
; PPC-PWR8-NEXT: li r7, 3
; PPC-PWR8-NEXT: li r8, 0
; PPC-PWR8-NEXT: stw r6, 36(r1) ; PPC-PWR8-NEXT: stw r6, 36(r1)
; PPC-PWR8-NEXT: stw r5, 32(r1) ; PPC-PWR8-NEXT: stw r5, 32(r1)
; PPC-PWR8-NEXT: addi r5, r1, 32 ; PPC-PWR8-NEXT: addi r5, r1, 32
; PPC-PWR8-NEXT: addi r6, r1, 16 ; PPC-PWR8-NEXT: addi r6, r1, 16
; PPC-PWR8-NEXT: stw r3, 24(r1) ; PPC-PWR8-NEXT: li r7, 3
; PPC-PWR8-NEXT: li r3, 16 ; PPC-PWR8-NEXT: li r8, 0
; PPC-PWR8-NEXT: stw r11, 28(r1)
; PPC-PWR8-NEXT: stw r10, 20(r1) ; PPC-PWR8-NEXT: stw r10, 20(r1)
; PPC-PWR8-NEXT: stw r9, 16(r1) ; PPC-PWR8-NEXT: stw r9, 16(r1)
; PPC-PWR8-NEXT: stw r3, 28(r1)
; PPC-PWR8-NEXT: lwz r3, 56(r1)
; PPC-PWR8-NEXT: stw r3, 24(r1)
; PPC-PWR8-NEXT: li r3, 16
; PPC-PWR8-NEXT: bl __atomic_compare_exchange ; PPC-PWR8-NEXT: bl __atomic_compare_exchange
; PPC-PWR8-NEXT: lwz r6, 44(r1) ; PPC-PWR8-NEXT: lwz r6, 44(r1)
; PPC-PWR8-NEXT: lwz r5, 40(r1) ; PPC-PWR8-NEXT: lwz r5, 40(r1)
; PPC-PWR8-NEXT: lwz r4, 36(r1) ; PPC-PWR8-NEXT: lwz r4, 36(r1)
; PPC-PWR8-NEXT: lwz r3, 32(r1) ; PPC-PWR8-NEXT: lwz r3, 32(r1)
; PPC-PWR8-NEXT: lwz r0, 52(r1) ; PPC-PWR8-NEXT: lwz r0, 52(r1)
; PPC-PWR8-NEXT: addi r1, r1, 48 ; PPC-PWR8-NEXT: addi r1, r1, 48
; PPC-PWR8-NEXT: mtlr r0 ; PPC-PWR8-NEXT: mtlr r0
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; PPC-PWR8-LABEL: cas_sc_sc: ; PPC-PWR8-LABEL: cas_sc_sc:
; PPC-PWR8: # %bb.0: # %entry ; PPC-PWR8: # %bb.0: # %entry
; PPC-PWR8-NEXT: mflr r0 ; PPC-PWR8-NEXT: mflr r0
; PPC-PWR8-NEXT: stwu r1, -48(r1) ; PPC-PWR8-NEXT: stwu r1, -48(r1)
; PPC-PWR8-NEXT: stw r0, 52(r1) ; PPC-PWR8-NEXT: stw r0, 52(r1)
; PPC-PWR8-NEXT: .cfi_def_cfa_offset 48 ; PPC-PWR8-NEXT: .cfi_def_cfa_offset 48
; PPC-PWR8-NEXT: .cfi_offset lr, 4 ; PPC-PWR8-NEXT: .cfi_offset lr, 4
; PPC-PWR8-NEXT: mr r4, r3 ; PPC-PWR8-NEXT: mr r4, r3
; PPC-PWR8-NEXT: lwz r3, 56(r1) ; PPC-PWR8-NEXT: lwz r3, 60(r1)
; PPC-PWR8-NEXT: lwz r11, 60(r1)
; PPC-PWR8-NEXT: stw r8, 44(r1) ; PPC-PWR8-NEXT: stw r8, 44(r1)
; PPC-PWR8-NEXT: stw r7, 40(r1) ; PPC-PWR8-NEXT: stw r7, 40(r1)
; PPC-PWR8-NEXT: li r7, 5
; PPC-PWR8-NEXT: li r8, 5
; PPC-PWR8-NEXT: stw r6, 36(r1) ; PPC-PWR8-NEXT: stw r6, 36(r1)
; PPC-PWR8-NEXT: stw r5, 32(r1) ; PPC-PWR8-NEXT: stw r5, 32(r1)
; PPC-PWR8-NEXT: addi r5, r1, 32 ; PPC-PWR8-NEXT: addi r5, r1, 32
; PPC-PWR8-NEXT: addi r6, r1, 16 ; PPC-PWR8-NEXT: addi r6, r1, 16
; PPC-PWR8-NEXT: stw r3, 24(r1) ; PPC-PWR8-NEXT: li r7, 5
; PPC-PWR8-NEXT: li r3, 16 ; PPC-PWR8-NEXT: li r8, 5
; PPC-PWR8-NEXT: stw r11, 28(r1)
; PPC-PWR8-NEXT: stw r10, 20(r1) ; PPC-PWR8-NEXT: stw r10, 20(r1)
; PPC-PWR8-NEXT: stw r9, 16(r1) ; PPC-PWR8-NEXT: stw r9, 16(r1)
; PPC-PWR8-NEXT: stw r3, 28(r1)
; PPC-PWR8-NEXT: lwz r3, 56(r1)
; PPC-PWR8-NEXT: stw r3, 24(r1)
; PPC-PWR8-NEXT: li r3, 16
; PPC-PWR8-NEXT: bl __atomic_compare_exchange ; PPC-PWR8-NEXT: bl __atomic_compare_exchange
; PPC-PWR8-NEXT: lwz r6, 44(r1) ; PPC-PWR8-NEXT: lwz r6, 44(r1)
; PPC-PWR8-NEXT: lwz r5, 40(r1) ; PPC-PWR8-NEXT: lwz r5, 40(r1)
; PPC-PWR8-NEXT: lwz r4, 36(r1) ; PPC-PWR8-NEXT: lwz r4, 36(r1)
; PPC-PWR8-NEXT: lwz r3, 32(r1) ; PPC-PWR8-NEXT: lwz r3, 32(r1)
; PPC-PWR8-NEXT: lwz r0, 52(r1) ; PPC-PWR8-NEXT: lwz r0, 52(r1)
; PPC-PWR8-NEXT: addi r1, r1, 48 ; PPC-PWR8-NEXT: addi r1, r1, 48
; PPC-PWR8-NEXT: mtlr r0 ; PPC-PWR8-NEXT: mtlr r0
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; PPC-PWR8-LABEL: cas_acqrel_acquire: ; PPC-PWR8-LABEL: cas_acqrel_acquire:
; PPC-PWR8: # %bb.0: # %entry ; PPC-PWR8: # %bb.0: # %entry
; PPC-PWR8-NEXT: mflr r0 ; PPC-PWR8-NEXT: mflr r0
; PPC-PWR8-NEXT: stwu r1, -48(r1) ; PPC-PWR8-NEXT: stwu r1, -48(r1)
; PPC-PWR8-NEXT: stw r0, 52(r1) ; PPC-PWR8-NEXT: stw r0, 52(r1)
; PPC-PWR8-NEXT: .cfi_def_cfa_offset 48 ; PPC-PWR8-NEXT: .cfi_def_cfa_offset 48
; PPC-PWR8-NEXT: .cfi_offset lr, 4 ; PPC-PWR8-NEXT: .cfi_offset lr, 4
; PPC-PWR8-NEXT: mr r4, r3 ; PPC-PWR8-NEXT: mr r4, r3
; PPC-PWR8-NEXT: lwz r3, 56(r1) ; PPC-PWR8-NEXT: lwz r3, 60(r1)
; PPC-PWR8-NEXT: lwz r11, 60(r1)
; PPC-PWR8-NEXT: stw r8, 44(r1) ; PPC-PWR8-NEXT: stw r8, 44(r1)
; PPC-PWR8-NEXT: stw r7, 40(r1) ; PPC-PWR8-NEXT: stw r7, 40(r1)
; PPC-PWR8-NEXT: li r7, 4
; PPC-PWR8-NEXT: li r8, 2
; PPC-PWR8-NEXT: stw r6, 36(r1) ; PPC-PWR8-NEXT: stw r6, 36(r1)
; PPC-PWR8-NEXT: stw r5, 32(r1) ; PPC-PWR8-NEXT: stw r5, 32(r1)
; PPC-PWR8-NEXT: addi r5, r1, 32 ; PPC-PWR8-NEXT: addi r5, r1, 32
; PPC-PWR8-NEXT: addi r6, r1, 16 ; PPC-PWR8-NEXT: addi r6, r1, 16
; PPC-PWR8-NEXT: stw r3, 24(r1) ; PPC-PWR8-NEXT: li r7, 4
; PPC-PWR8-NEXT: li r3, 16 ; PPC-PWR8-NEXT: li r8, 2
; PPC-PWR8-NEXT: stw r11, 28(r1)
; PPC-PWR8-NEXT: stw r10, 20(r1) ; PPC-PWR8-NEXT: stw r10, 20(r1)
; PPC-PWR8-NEXT: stw r9, 16(r1) ; PPC-PWR8-NEXT: stw r9, 16(r1)
; PPC-PWR8-NEXT: stw r3, 28(r1)
; PPC-PWR8-NEXT: lwz r3, 56(r1)
; PPC-PWR8-NEXT: stw r3, 24(r1)
; PPC-PWR8-NEXT: li r3, 16
; PPC-PWR8-NEXT: bl __atomic_compare_exchange ; PPC-PWR8-NEXT: bl __atomic_compare_exchange
; PPC-PWR8-NEXT: lwz r6, 44(r1) ; PPC-PWR8-NEXT: lwz r6, 44(r1)
; PPC-PWR8-NEXT: lwz r5, 40(r1) ; PPC-PWR8-NEXT: lwz r5, 40(r1)
; PPC-PWR8-NEXT: lwz r4, 36(r1) ; PPC-PWR8-NEXT: lwz r4, 36(r1)
; PPC-PWR8-NEXT: lwz r3, 32(r1) ; PPC-PWR8-NEXT: lwz r3, 32(r1)
; PPC-PWR8-NEXT: lwz r0, 52(r1) ; PPC-PWR8-NEXT: lwz r0, 52(r1)
; PPC-PWR8-NEXT: addi r1, r1, 48 ; PPC-PWR8-NEXT: addi r1, r1, 48
; PPC-PWR8-NEXT: mtlr r0 ; PPC-PWR8-NEXT: mtlr r0
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; PPC-PWR8-LABEL: cas_acqrel_acquire_check_succ: ; PPC-PWR8-LABEL: cas_acqrel_acquire_check_succ:
; PPC-PWR8: # %bb.0: # %entry ; PPC-PWR8: # %bb.0: # %entry
; PPC-PWR8-NEXT: mflr r0 ; PPC-PWR8-NEXT: mflr r0
; PPC-PWR8-NEXT: stwu r1, -48(r1) ; PPC-PWR8-NEXT: stwu r1, -48(r1)
; PPC-PWR8-NEXT: stw r0, 52(r1) ; PPC-PWR8-NEXT: stw r0, 52(r1)
; PPC-PWR8-NEXT: .cfi_def_cfa_offset 48 ; PPC-PWR8-NEXT: .cfi_def_cfa_offset 48
; PPC-PWR8-NEXT: .cfi_offset lr, 4 ; PPC-PWR8-NEXT: .cfi_offset lr, 4
; PPC-PWR8-NEXT: mr r4, r3 ; PPC-PWR8-NEXT: mr r4, r3
; PPC-PWR8-NEXT: lwz r3, 56(r1) ; PPC-PWR8-NEXT: lwz r3, 60(r1)
; PPC-PWR8-NEXT: lwz r11, 60(r1)
; PPC-PWR8-NEXT: stw r8, 44(r1) ; PPC-PWR8-NEXT: stw r8, 44(r1)
; PPC-PWR8-NEXT: stw r7, 40(r1) ; PPC-PWR8-NEXT: stw r7, 40(r1)
; PPC-PWR8-NEXT: li r7, 4
; PPC-PWR8-NEXT: li r8, 2
; PPC-PWR8-NEXT: stw r6, 36(r1) ; PPC-PWR8-NEXT: stw r6, 36(r1)
; PPC-PWR8-NEXT: stw r5, 32(r1) ; PPC-PWR8-NEXT: stw r5, 32(r1)
; PPC-PWR8-NEXT: addi r5, r1, 32 ; PPC-PWR8-NEXT: addi r5, r1, 32
; PPC-PWR8-NEXT: addi r6, r1, 16 ; PPC-PWR8-NEXT: addi r6, r1, 16
; PPC-PWR8-NEXT: stw r3, 24(r1) ; PPC-PWR8-NEXT: li r7, 4
; PPC-PWR8-NEXT: li r3, 16 ; PPC-PWR8-NEXT: li r8, 2
; PPC-PWR8-NEXT: stw r11, 28(r1)
; PPC-PWR8-NEXT: stw r10, 20(r1) ; PPC-PWR8-NEXT: stw r10, 20(r1)
; PPC-PWR8-NEXT: stw r9, 16(r1) ; PPC-PWR8-NEXT: stw r9, 16(r1)
; PPC-PWR8-NEXT: stw r3, 28(r1)
; PPC-PWR8-NEXT: lwz r3, 56(r1)
; PPC-PWR8-NEXT: stw r3, 24(r1)
; PPC-PWR8-NEXT: li r3, 16
; PPC-PWR8-NEXT: bl __atomic_compare_exchange ; PPC-PWR8-NEXT: bl __atomic_compare_exchange
; PPC-PWR8-NEXT: lwz r0, 52(r1) ; PPC-PWR8-NEXT: lwz r0, 52(r1)
; PPC-PWR8-NEXT: addi r1, r1, 48 ; PPC-PWR8-NEXT: addi r1, r1, 48
; PPC-PWR8-NEXT: mtlr r0 ; PPC-PWR8-NEXT: mtlr r0
; PPC-PWR8-NEXT: blr ; PPC-PWR8-NEXT: blr
entry: entry:
%0 = cmpxchg ptr %a, i128 %cmp, i128 %new acq_rel acquire %0 = cmpxchg ptr %a, i128 %cmp, i128 %new acq_rel acquire
%1 = extractvalue { i128, i1 } %0, 1 %1 = extractvalue { i128, i1 } %0, 1
ret i1 %1 ret i1 %1
} }

llvm/test/CodeGen/PowerPC/atomics-i16-ldst.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-P10 ; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-P10
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-P10 ; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-P10
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10,CHECK-P9 ; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10,CHECK-P9 ; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10,CHECK-P8 ; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10,CHECK-P8 ; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10
; Function Attrs: nofree norecurse nounwind uwtable willreturn ; Function Attrs: nofree norecurse nounwind uwtable willreturn
define dso_local signext i16 @ld_0_int16_t_uint8_t(i64 %ptr) { define dso_local signext i16 @ld_0_int16_t_uint8_t(i64 %ptr) {
; CHECK-LABEL: ld_0_int16_t_uint8_t: ; CHECK-LABEL: ld_0_int16_t_uint8_t:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 0(r3) ; CHECK-NEXT: lbz r3, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
▲ Show 20 Lines • Show All 141 Lines • ▼ Show 20 Lines
; CHECK-P10-LABEL: ld_disjoint_align32_int16_t_uint8_t: ; CHECK-P10-LABEL: ld_disjoint_align32_int16_t_uint8_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r4, -15264 ; CHECK-P10-NEXT: lis r4, -15264
; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: and r3, r3, r4
; CHECK-P10-NEXT: plbz r3, 999990000(r3), 0 ; CHECK-P10-NEXT: plbz r3, 999990000(r3), 0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_disjoint_align32_int16_t_uint8_t: ; CHECK-PREP10-LABEL: ld_disjoint_align32_int16_t_uint8_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r4, -15264 ; CHECK-PREP10-NEXT: lis r4, -15264
; CHECK-P9-NEXT: and r3, r3, r4 ; CHECK-PREP10-NEXT: and r3, r3, r4
; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-PREP10-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-PREP10-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lbzx r3, r3, r4 ; CHECK-PREP10-NEXT: lbzx r3, r3, r4
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
shchenzUnsubmitted
Not Done
ReplyInline Actions

We may need another name for check prefix PREP10? And also double check if prefixes P8 and P9 are still used in this file?

shchenz: We may need another name for check prefix `PREP10`? And also double check if prefixes `P8` and…
qiucfAuthorUnsubmitted
Done
ReplyInline Actions

Like CHECK-NONP10 or CHECK-P8P9? But it actually has the same meaning as CHECK-PREP10.

qiucf: Like `CHECK-NONP10` or `CHECK-P8P9`? But it actually has the same meaning as `CHECK-PREP10`.
;
; CHECK-P8-LABEL: ld_disjoint_align32_int16_t_uint8_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r4, -15264
; CHECK-P8-NEXT: lis r5, 15258
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lbzx r3, r3, r4
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%1 = load atomic i8, ptr %0 monotonic, align 16 %1 = load atomic i8, ptr %0 monotonic, align 16
%conv = zext i8 %1 to i16 %conv = zext i8 %1 to i16
ret i16 %conv ret i16 %conv
} }
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; CHECK-P10-LABEL: ld_disjoint_align32_int16_t_int8_t: ; CHECK-P10-LABEL: ld_disjoint_align32_int16_t_int8_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r4, -15264 ; CHECK-P10-NEXT: lis r4, -15264
; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: and r3, r3, r4
; CHECK-P10-NEXT: plbz r3, 999990000(r3), 0 ; CHECK-P10-NEXT: plbz r3, 999990000(r3), 0
; CHECK-P10-NEXT: extsb r3, r3 ; CHECK-P10-NEXT: extsb r3, r3
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_disjoint_align32_int16_t_int8_t: ; CHECK-PREP10-LABEL: ld_disjoint_align32_int16_t_int8_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r4, -15264 ; CHECK-PREP10-NEXT: lis r4, -15264
; CHECK-P9-NEXT: and r3, r3, r4 ; CHECK-PREP10-NEXT: and r3, r3, r4
; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-PREP10-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-PREP10-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lbzx r3, r3, r4 ; CHECK-PREP10-NEXT: lbzx r3, r3, r4
; CHECK-P9-NEXT: extsb r3, r3 ; CHECK-PREP10-NEXT: extsb r3, r3
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_int16_t_int8_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r4, -15264
; CHECK-P8-NEXT: lis r5, 15258
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lbzx r3, r3, r4
; CHECK-P8-NEXT: extsb r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%1 = load atomic i8, ptr %0 monotonic, align 16 %1 = load atomic i8, ptr %0 monotonic, align 16
%conv = sext i8 %1 to i16 %conv = sext i8 %1 to i16
ret i16 %conv ret i16 %conv
} }
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; CHECK-P10-LABEL: ld_disjoint_align32_int16_t_uint16_t: ; CHECK-P10-LABEL: ld_disjoint_align32_int16_t_uint16_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r4, -15264 ; CHECK-P10-NEXT: lis r4, -15264
; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: and r3, r3, r4
; CHECK-P10-NEXT: plhz r3, 999990000(r3), 0 ; CHECK-P10-NEXT: plhz r3, 999990000(r3), 0
; CHECK-P10-NEXT: extsh r3, r3 ; CHECK-P10-NEXT: extsh r3, r3
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_disjoint_align32_int16_t_uint16_t: ; CHECK-PREP10-LABEL: ld_disjoint_align32_int16_t_uint16_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r4, -15264 ; CHECK-PREP10-NEXT: lis r4, -15264
; CHECK-P9-NEXT: and r3, r3, r4 ; CHECK-PREP10-NEXT: and r3, r3, r4
; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-PREP10-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-PREP10-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lhzx r3, r3, r4 ; CHECK-PREP10-NEXT: lhzx r3, r3, r4
; CHECK-P9-NEXT: extsh r3, r3 ; CHECK-PREP10-NEXT: extsh r3, r3
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_int16_t_uint16_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r4, -15264
; CHECK-P8-NEXT: lis r5, 15258
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lhzx r3, r3, r4
; CHECK-P8-NEXT: extsh r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%1 = load atomic i16, ptr %0 monotonic, align 16 %1 = load atomic i16, ptr %0 monotonic, align 16
ret i16 %1 ret i16 %1
} }
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; CHECK-P10-LABEL: ld_disjoint_align32_int16_t_uint32_t: ; CHECK-P10-LABEL: ld_disjoint_align32_int16_t_uint32_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r4, -15264 ; CHECK-P10-NEXT: lis r4, -15264
; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: and r3, r3, r4
; CHECK-P10-NEXT: plwz r3, 999990000(r3), 0 ; CHECK-P10-NEXT: plwz r3, 999990000(r3), 0
; CHECK-P10-NEXT: extsh r3, r3 ; CHECK-P10-NEXT: extsh r3, r3
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_disjoint_align32_int16_t_uint32_t: ; CHECK-PREP10-LABEL: ld_disjoint_align32_int16_t_uint32_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r4, -15264 ; CHECK-PREP10-NEXT: lis r4, -15264
; CHECK-P9-NEXT: and r3, r3, r4 ; CHECK-PREP10-NEXT: and r3, r3, r4
; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-PREP10-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-PREP10-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lwzx r3, r3, r4 ; CHECK-PREP10-NEXT: lwzx r3, r3, r4
; CHECK-P9-NEXT: extsh r3, r3 ; CHECK-PREP10-NEXT: extsh r3, r3
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_int16_t_uint32_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r4, -15264
; CHECK-P8-NEXT: lis r5, 15258
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lwzx r3, r3, r4
; CHECK-P8-NEXT: extsh r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%1 = load atomic i32, ptr %0 monotonic, align 16 %1 = load atomic i32, ptr %0 monotonic, align 16
%conv = trunc i32 %1 to i16 %conv = trunc i32 %1 to i16
ret i16 %conv ret i16 %conv
} }
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; CHECK-P10-LABEL: ld_disjoint_align32_int16_t_uint64_t: ; CHECK-P10-LABEL: ld_disjoint_align32_int16_t_uint64_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r4, -15264 ; CHECK-P10-NEXT: lis r4, -15264
; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: and r3, r3, r4
; CHECK-P10-NEXT: pld r3, 999990000(r3), 0 ; CHECK-P10-NEXT: pld r3, 999990000(r3), 0
; CHECK-P10-NEXT: extsh r3, r3 ; CHECK-P10-NEXT: extsh r3, r3
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_disjoint_align32_int16_t_uint64_t: ; CHECK-PREP10-LABEL: ld_disjoint_align32_int16_t_uint64_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r4, -15264 ; CHECK-PREP10-NEXT: lis r4, -15264
; CHECK-P9-NEXT: and r3, r3, r4 ; CHECK-PREP10-NEXT: and r3, r3, r4
; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-PREP10-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-PREP10-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: ldx r3, r3, r4 ; CHECK-PREP10-NEXT: ldx r3, r3, r4
; CHECK-P9-NEXT: extsh r3, r3 ; CHECK-PREP10-NEXT: extsh r3, r3
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_int16_t_uint64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r4, -15264
; CHECK-P8-NEXT: lis r5, 15258
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: ldx r3, r3, r4
; CHECK-P8-NEXT: extsh r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%1 = load atomic i64, ptr %0 monotonic, align 16 %1 = load atomic i64, ptr %0 monotonic, align 16
%conv = trunc i64 %1 to i16 %conv = trunc i64 %1 to i16
ret i16 %conv ret i16 %conv
} }
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; CHECK-P10-LABEL: ld_disjoint_align32_uint16_t_uint8_t: ; CHECK-P10-LABEL: ld_disjoint_align32_uint16_t_uint8_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r4, -15264 ; CHECK-P10-NEXT: lis r4, -15264
; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: and r3, r3, r4
; CHECK-P10-NEXT: plbz r3, 999990000(r3), 0 ; CHECK-P10-NEXT: plbz r3, 999990000(r3), 0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_disjoint_align32_uint16_t_uint8_t: ; CHECK-PREP10-LABEL: ld_disjoint_align32_uint16_t_uint8_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r4, -15264 ; CHECK-PREP10-NEXT: lis r4, -15264
; CHECK-P9-NEXT: and r3, r3, r4 ; CHECK-PREP10-NEXT: and r3, r3, r4
; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-PREP10-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-PREP10-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lbzx r3, r3, r4 ; CHECK-PREP10-NEXT: lbzx r3, r3, r4
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint16_t_uint8_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r4, -15264
; CHECK-P8-NEXT: lis r5, 15258
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lbzx r3, r3, r4
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%1 = load atomic i8, ptr %0 monotonic, align 16 %1 = load atomic i8, ptr %0 monotonic, align 16
%conv = zext i8 %1 to i16 %conv = zext i8 %1 to i16
ret i16 %conv ret i16 %conv
} }
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; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r4, -15264 ; CHECK-P10-NEXT: lis r4, -15264
; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: and r3, r3, r4
; CHECK-P10-NEXT: plbz r3, 999990000(r3), 0 ; CHECK-P10-NEXT: plbz r3, 999990000(r3), 0
; CHECK-P10-NEXT: extsb r3, r3 ; CHECK-P10-NEXT: extsb r3, r3
; CHECK-P10-NEXT: clrldi r3, r3, 48 ; CHECK-P10-NEXT: clrldi r3, r3, 48
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_disjoint_align32_uint16_t_int8_t: ; CHECK-PREP10-LABEL: ld_disjoint_align32_uint16_t_int8_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r4, -15264 ; CHECK-PREP10-NEXT: lis r4, -15264
; CHECK-P9-NEXT: and r3, r3, r4 ; CHECK-PREP10-NEXT: and r3, r3, r4
; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-PREP10-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-PREP10-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lbzx r3, r3, r4 ; CHECK-PREP10-NEXT: lbzx r3, r3, r4
; CHECK-P9-NEXT: extsb r3, r3 ; CHECK-PREP10-NEXT: extsb r3, r3
; CHECK-P9-NEXT: clrldi r3, r3, 48 ; CHECK-PREP10-NEXT: clrldi r3, r3, 48
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint16_t_int8_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r4, -15264
; CHECK-P8-NEXT: lis r5, 15258
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lbzx r3, r3, r4
; CHECK-P8-NEXT: extsb r3, r3
; CHECK-P8-NEXT: clrldi r3, r3, 48
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%1 = load atomic i8, ptr %0 monotonic, align 16 %1 = load atomic i8, ptr %0 monotonic, align 16
%conv = sext i8 %1 to i16 %conv = sext i8 %1 to i16
ret i16 %conv ret i16 %conv
} }
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; CHECK-P10-LABEL: ld_disjoint_align32_uint16_t_uint16_t: ; CHECK-P10-LABEL: ld_disjoint_align32_uint16_t_uint16_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r4, -15264 ; CHECK-P10-NEXT: lis r4, -15264
; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: and r3, r3, r4
; CHECK-P10-NEXT: plhz r3, 999990000(r3), 0 ; CHECK-P10-NEXT: plhz r3, 999990000(r3), 0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_disjoint_align32_uint16_t_uint16_t: ; CHECK-PREP10-LABEL: ld_disjoint_align32_uint16_t_uint16_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r4, -15264 ; CHECK-PREP10-NEXT: lis r4, -15264
; CHECK-P9-NEXT: and r3, r3, r4 ; CHECK-PREP10-NEXT: and r3, r3, r4
; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-PREP10-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-PREP10-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lhzx r3, r3, r4 ; CHECK-PREP10-NEXT: lhzx r3, r3, r4
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint16_t_uint16_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r4, -15264
; CHECK-P8-NEXT: lis r5, 15258
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lhzx r3, r3, r4
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%1 = load atomic i16, ptr %0 monotonic, align 16 %1 = load atomic i16, ptr %0 monotonic, align 16
ret i16 %1 ret i16 %1
} }
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; CHECK-P10-LABEL: ld_disjoint_align32_uint16_t_uint32_t: ; CHECK-P10-LABEL: ld_disjoint_align32_uint16_t_uint32_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r4, -15264 ; CHECK-P10-NEXT: lis r4, -15264
; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: and r3, r3, r4
; CHECK-P10-NEXT: plwz r3, 999990000(r3), 0 ; CHECK-P10-NEXT: plwz r3, 999990000(r3), 0
; CHECK-P10-NEXT: clrldi r3, r3, 48 ; CHECK-P10-NEXT: clrldi r3, r3, 48
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_disjoint_align32_uint16_t_uint32_t: ; CHECK-PREP10-LABEL: ld_disjoint_align32_uint16_t_uint32_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r4, -15264 ; CHECK-PREP10-NEXT: lis r4, -15264
; CHECK-P9-NEXT: and r3, r3, r4 ; CHECK-PREP10-NEXT: and r3, r3, r4
; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-PREP10-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-PREP10-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lwzx r3, r3, r4 ; CHECK-PREP10-NEXT: lwzx r3, r3, r4
; CHECK-P9-NEXT: clrldi r3, r3, 48 ; CHECK-PREP10-NEXT: clrldi r3, r3, 48
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint16_t_uint32_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r4, -15264
; CHECK-P8-NEXT: lis r5, 15258
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lwzx r3, r3, r4
; CHECK-P8-NEXT: clrldi r3, r3, 48
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%1 = load atomic i32, ptr %0 monotonic, align 16 %1 = load atomic i32, ptr %0 monotonic, align 16
%conv = trunc i32 %1 to i16 %conv = trunc i32 %1 to i16
ret i16 %conv ret i16 %conv
} }
▲ Show 20 Lines • Show All 269 Lines • ▼ Show 20 Lines
; CHECK-P10-LABEL: ld_disjoint_align32_uint16_t_uint64_t: ; CHECK-P10-LABEL: ld_disjoint_align32_uint16_t_uint64_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r4, -15264 ; CHECK-P10-NEXT: lis r4, -15264
; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: and r3, r3, r4
; CHECK-P10-NEXT: pld r3, 999990000(r3), 0 ; CHECK-P10-NEXT: pld r3, 999990000(r3), 0
; CHECK-P10-NEXT: clrldi r3, r3, 48 ; CHECK-P10-NEXT: clrldi r3, r3, 48
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_disjoint_align32_uint16_t_uint64_t: ; CHECK-PREP10-LABEL: ld_disjoint_align32_uint16_t_uint64_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r4, -15264 ; CHECK-PREP10-NEXT: lis r4, -15264
; CHECK-P9-NEXT: and r3, r3, r4 ; CHECK-PREP10-NEXT: and r3, r3, r4
; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-PREP10-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-PREP10-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: ldx r3, r3, r4 ; CHECK-PREP10-NEXT: ldx r3, r3, r4
; CHECK-P9-NEXT: clrldi r3, r3, 48 ; CHECK-PREP10-NEXT: clrldi r3, r3, 48
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint16_t_uint64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r4, -15264
; CHECK-P8-NEXT: lis r5, 15258
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: ldx r3, r3, r4
; CHECK-P8-NEXT: clrldi r3, r3, 48
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%1 = load atomic i64, ptr %0 monotonic, align 16 %1 = load atomic i64, ptr %0 monotonic, align 16
%conv = trunc i64 %1 to i16 %conv = trunc i64 %1 to i16
ret i16 %conv ret i16 %conv
} }
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define dso_local void @st_disjoint_align32_uint16_t_uint8_t(i64 %ptr, i16 zeroext %str) { define dso_local void @st_disjoint_align32_uint16_t_uint8_t(i64 %ptr, i16 zeroext %str) {
; CHECK-P10-LABEL: st_disjoint_align32_uint16_t_uint8_t: ; CHECK-P10-LABEL: st_disjoint_align32_uint16_t_uint8_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r5, -15264 ; CHECK-P10-NEXT: lis r5, -15264
; CHECK-P10-NEXT: and r3, r3, r5 ; CHECK-P10-NEXT: and r3, r3, r5
; CHECK-P10-NEXT: pstb r4, 999990000(r3), 0 ; CHECK-P10-NEXT: pstb r4, 999990000(r3), 0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_disjoint_align32_uint16_t_uint8_t: ; CHECK-PREP10-LABEL: st_disjoint_align32_uint16_t_uint8_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r5, -15264 ; CHECK-PREP10-NEXT: lis r5, -15264
; CHECK-P9-NEXT: and r3, r3, r5 ; CHECK-PREP10-NEXT: and r3, r3, r5
; CHECK-P9-NEXT: lis r5, 15258 ; CHECK-PREP10-NEXT: lis r5, 15258
; CHECK-P9-NEXT: ori r5, r5, 41712 ; CHECK-PREP10-NEXT: ori r5, r5, 41712
; CHECK-P9-NEXT: stbx r4, r3, r5 ; CHECK-PREP10-NEXT: stbx r4, r3, r5
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align32_uint16_t_uint8_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r5, -15264
; CHECK-P8-NEXT: lis r6, 15258
; CHECK-P8-NEXT: and r3, r3, r5
; CHECK-P8-NEXT: ori r5, r6, 41712
; CHECK-P8-NEXT: stbx r4, r3, r5
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%conv = trunc i16 %str to i8 %conv = trunc i16 %str to i8
store atomic i8 %conv, ptr %0 monotonic, align 16 store atomic i8 %conv, ptr %0 monotonic, align 16
ret void ret void
} }
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define dso_local void @st_disjoint_align32_uint16_t_uint16_t(i64 %ptr, i16 zeroext %str) { define dso_local void @st_disjoint_align32_uint16_t_uint16_t(i64 %ptr, i16 zeroext %str) {
; CHECK-P10-LABEL: st_disjoint_align32_uint16_t_uint16_t: ; CHECK-P10-LABEL: st_disjoint_align32_uint16_t_uint16_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r5, -15264 ; CHECK-P10-NEXT: lis r5, -15264
; CHECK-P10-NEXT: and r3, r3, r5 ; CHECK-P10-NEXT: and r3, r3, r5
; CHECK-P10-NEXT: psth r4, 999990000(r3), 0 ; CHECK-P10-NEXT: psth r4, 999990000(r3), 0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_disjoint_align32_uint16_t_uint16_t: ; CHECK-PREP10-LABEL: st_disjoint_align32_uint16_t_uint16_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r5, -15264 ; CHECK-PREP10-NEXT: lis r5, -15264
; CHECK-P9-NEXT: and r3, r3, r5 ; CHECK-PREP10-NEXT: and r3, r3, r5
; CHECK-P9-NEXT: lis r5, 15258 ; CHECK-PREP10-NEXT: lis r5, 15258
; CHECK-P9-NEXT: ori r5, r5, 41712 ; CHECK-PREP10-NEXT: ori r5, r5, 41712
; CHECK-P9-NEXT: sthx r4, r3, r5 ; CHECK-PREP10-NEXT: sthx r4, r3, r5
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align32_uint16_t_uint16_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r5, -15264
; CHECK-P8-NEXT: lis r6, 15258
; CHECK-P8-NEXT: and r3, r3, r5
; CHECK-P8-NEXT: ori r5, r6, 41712
; CHECK-P8-NEXT: sthx r4, r3, r5
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
store atomic i16 %str, ptr %0 monotonic, align 16 store atomic i16 %str, ptr %0 monotonic, align 16
ret void ret void
} }
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define dso_local void @st_disjoint_align32_uint16_t_uint32_t(i64 %ptr, i16 zeroext %str) { define dso_local void @st_disjoint_align32_uint16_t_uint32_t(i64 %ptr, i16 zeroext %str) {
; CHECK-P10-LABEL: st_disjoint_align32_uint16_t_uint32_t: ; CHECK-P10-LABEL: st_disjoint_align32_uint16_t_uint32_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r5, -15264 ; CHECK-P10-NEXT: lis r5, -15264
; CHECK-P10-NEXT: and r3, r3, r5 ; CHECK-P10-NEXT: and r3, r3, r5
; CHECK-P10-NEXT: pstw r4, 999990000(r3), 0 ; CHECK-P10-NEXT: pstw r4, 999990000(r3), 0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_disjoint_align32_uint16_t_uint32_t: ; CHECK-PREP10-LABEL: st_disjoint_align32_uint16_t_uint32_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r5, -15264 ; CHECK-PREP10-NEXT: lis r5, -15264
; CHECK-P9-NEXT: and r3, r3, r5 ; CHECK-PREP10-NEXT: and r3, r3, r5
; CHECK-P9-NEXT: lis r5, 15258 ; CHECK-PREP10-NEXT: lis r5, 15258
; CHECK-P9-NEXT: ori r5, r5, 41712 ; CHECK-PREP10-NEXT: ori r5, r5, 41712
; CHECK-P9-NEXT: stwx r4, r3, r5 ; CHECK-PREP10-NEXT: stwx r4, r3, r5
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align32_uint16_t_uint32_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r5, -15264
; CHECK-P8-NEXT: lis r6, 15258
; CHECK-P8-NEXT: and r3, r3, r5
; CHECK-P8-NEXT: ori r5, r6, 41712
; CHECK-P8-NEXT: stwx r4, r3, r5
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%conv = zext i16 %str to i32 %conv = zext i16 %str to i32
store atomic i32 %conv, ptr %0 monotonic, align 16 store atomic i32 %conv, ptr %0 monotonic, align 16
ret void ret void
} }
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define dso_local void @st_disjoint_align32_uint16_t_uint64_t(i64 %ptr, i16 zeroext %str) { define dso_local void @st_disjoint_align32_uint16_t_uint64_t(i64 %ptr, i16 zeroext %str) {
; CHECK-P10-LABEL: st_disjoint_align32_uint16_t_uint64_t: ; CHECK-P10-LABEL: st_disjoint_align32_uint16_t_uint64_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r5, -15264 ; CHECK-P10-NEXT: lis r5, -15264
; CHECK-P10-NEXT: and r3, r3, r5 ; CHECK-P10-NEXT: and r3, r3, r5
; CHECK-P10-NEXT: pstd r4, 999990000(r3), 0 ; CHECK-P10-NEXT: pstd r4, 999990000(r3), 0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_disjoint_align32_uint16_t_uint64_t: ; CHECK-PREP10-LABEL: st_disjoint_align32_uint16_t_uint64_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r5, -15264 ; CHECK-PREP10-NEXT: lis r5, -15264
; CHECK-P9-NEXT: and r3, r3, r5 ; CHECK-PREP10-NEXT: and r3, r3, r5
; CHECK-P9-NEXT: lis r5, 15258 ; CHECK-PREP10-NEXT: lis r5, 15258
; CHECK-P9-NEXT: ori r5, r5, 41712 ; CHECK-PREP10-NEXT: ori r5, r5, 41712
; CHECK-P9-NEXT: stdx r4, r3, r5 ; CHECK-PREP10-NEXT: stdx r4, r3, r5
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align32_uint16_t_uint64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r5, -15264
; CHECK-P8-NEXT: lis r6, 15258
; CHECK-P8-NEXT: and r3, r3, r5
; CHECK-P8-NEXT: ori r5, r6, 41712
; CHECK-P8-NEXT: stdx r4, r3, r5
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%conv = zext i16 %str to i64 %conv = zext i16 %str to i64
store atomic i64 %conv, ptr %0 monotonic, align 16 store atomic i64 %conv, ptr %0 monotonic, align 16
ret void ret void
} }
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define dso_local void @st_disjoint_align32_int16_t_uint32_t(i64 %ptr, i16 signext %str) { define dso_local void @st_disjoint_align32_int16_t_uint32_t(i64 %ptr, i16 signext %str) {
; CHECK-P10-LABEL: st_disjoint_align32_int16_t_uint32_t: ; CHECK-P10-LABEL: st_disjoint_align32_int16_t_uint32_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r5, -15264 ; CHECK-P10-NEXT: lis r5, -15264
; CHECK-P10-NEXT: and r3, r3, r5 ; CHECK-P10-NEXT: and r3, r3, r5
; CHECK-P10-NEXT: pstw r4, 999990000(r3), 0 ; CHECK-P10-NEXT: pstw r4, 999990000(r3), 0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_disjoint_align32_int16_t_uint32_t: ; CHECK-PREP10-LABEL: st_disjoint_align32_int16_t_uint32_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r5, -15264 ; CHECK-PREP10-NEXT: lis r5, -15264
; CHECK-P9-NEXT: and r3, r3, r5 ; CHECK-PREP10-NEXT: and r3, r3, r5
; CHECK-P9-NEXT: lis r5, 15258 ; CHECK-PREP10-NEXT: lis r5, 15258
; CHECK-P9-NEXT: ori r5, r5, 41712 ; CHECK-PREP10-NEXT: ori r5, r5, 41712
; CHECK-P9-NEXT: stwx r4, r3, r5 ; CHECK-PREP10-NEXT: stwx r4, r3, r5
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align32_int16_t_uint32_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r5, -15264
; CHECK-P8-NEXT: lis r6, 15258
; CHECK-P8-NEXT: and r3, r3, r5
; CHECK-P8-NEXT: ori r5, r6, 41712
; CHECK-P8-NEXT: stwx r4, r3, r5
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%conv = sext i16 %str to i32 %conv = sext i16 %str to i32
store atomic i32 %conv, ptr %0 monotonic, align 16 store atomic i32 %conv, ptr %0 monotonic, align 16
ret void ret void
} }
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define dso_local void @st_disjoint_align32_int16_t_uint64_t(i64 %ptr, i16 signext %str) { define dso_local void @st_disjoint_align32_int16_t_uint64_t(i64 %ptr, i16 signext %str) {
; CHECK-P10-LABEL: st_disjoint_align32_int16_t_uint64_t: ; CHECK-P10-LABEL: st_disjoint_align32_int16_t_uint64_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r5, -15264 ; CHECK-P10-NEXT: lis r5, -15264
; CHECK-P10-NEXT: and r3, r3, r5 ; CHECK-P10-NEXT: and r3, r3, r5
; CHECK-P10-NEXT: pstd r4, 999990000(r3), 0 ; CHECK-P10-NEXT: pstd r4, 999990000(r3), 0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_disjoint_align32_int16_t_uint64_t: ; CHECK-PREP10-LABEL: st_disjoint_align32_int16_t_uint64_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r5, -15264 ; CHECK-PREP10-NEXT: lis r5, -15264
; CHECK-P9-NEXT: and r3, r3, r5 ; CHECK-PREP10-NEXT: and r3, r3, r5
; CHECK-P9-NEXT: lis r5, 15258 ; CHECK-PREP10-NEXT: lis r5, 15258
; CHECK-P9-NEXT: ori r5, r5, 41712 ; CHECK-PREP10-NEXT: ori r5, r5, 41712
; CHECK-P9-NEXT: stdx r4, r3, r5 ; CHECK-PREP10-NEXT: stdx r4, r3, r5
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align32_int16_t_uint64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r5, -15264
; CHECK-P8-NEXT: lis r6, 15258
; CHECK-P8-NEXT: and r3, r3, r5
; CHECK-P8-NEXT: ori r5, r6, 41712
; CHECK-P8-NEXT: stdx r4, r3, r5
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%conv = sext i16 %str to i64 %conv = sext i16 %str to i64
store atomic i64 %conv, ptr %0 monotonic, align 16 store atomic i64 %conv, ptr %0 monotonic, align 16
ret void ret void
} }
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; CHECK-PREP10-NEXT: ori r4, r4, 19025 ; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: std r3, 0(r4) ; CHECK-PREP10-NEXT: std r3, 0(r4)
; CHECK-PREP10-NEXT: blr ; CHECK-PREP10-NEXT: blr
entry: entry:
%conv = sext i16 %str to i64 %conv = sext i16 %str to i64
store atomic i64 %conv, ptr inttoptr (i64 1000000000000 to ptr) monotonic, align 4096 store atomic i64 %conv, ptr inttoptr (i64 1000000000000 to ptr) monotonic, align 4096
ret void ret void
} }
shchenzUnsubmitted
Not Done
ReplyInline Actions

Ah, it show P8 and P9 are not used, we should delete them in the run lines.

shchenz: Ah, it show P8 and P9 are not used, we should delete them in the run lines.
shchenzUnsubmitted
Done
ReplyInline Actions

There are still unused check prefix in the run lines.

shchenz: There are still unused check prefix in the run lines.

llvm/test/CodeGen/PowerPC/atomics-i32-ldst.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-P10 ; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-P10
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-P10 ; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-P10
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10,CHECK-P9 ; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10,CHECK-P9 ; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10,CHECK-P8 ; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10,CHECK-P8 ; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10
; Function Attrs: nofree norecurse nounwind uwtable willreturn ; Function Attrs: nofree norecurse nounwind uwtable willreturn
define dso_local signext i32 @ld_0_int32_t_uint8_t(i64 %ptr) { define dso_local signext i32 @ld_0_int32_t_uint8_t(i64 %ptr) {
; CHECK-LABEL: ld_0_int32_t_uint8_t: ; CHECK-LABEL: ld_0_int32_t_uint8_t:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 0(r3) ; CHECK-NEXT: lbz r3, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
▲ Show 20 Lines • Show All 141 Lines • ▼ Show 20 Lines
; CHECK-P10-LABEL: ld_disjoint_align32_int32_t_uint8_t: ; CHECK-P10-LABEL: ld_disjoint_align32_int32_t_uint8_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r4, -15264 ; CHECK-P10-NEXT: lis r4, -15264
; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: and r3, r3, r4
; CHECK-P10-NEXT: plbz r3, 999990000(r3), 0 ; CHECK-P10-NEXT: plbz r3, 999990000(r3), 0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_disjoint_align32_int32_t_uint8_t: ; CHECK-PREP10-LABEL: ld_disjoint_align32_int32_t_uint8_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r4, -15264 ; CHECK-PREP10-NEXT: lis r4, -15264
; CHECK-P9-NEXT: and r3, r3, r4 ; CHECK-PREP10-NEXT: and r3, r3, r4
; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-PREP10-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-PREP10-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lbzx r3, r3, r4 ; CHECK-PREP10-NEXT: lbzx r3, r3, r4
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_int32_t_uint8_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r4, -15264
; CHECK-P8-NEXT: lis r5, 15258
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lbzx r3, r3, r4
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%1 = load atomic i8, ptr %0 monotonic, align 16 %1 = load atomic i8, ptr %0 monotonic, align 16
%conv = zext i8 %1 to i32 %conv = zext i8 %1 to i32
ret i32 %conv ret i32 %conv
} }
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; CHECK-P10-LABEL: ld_disjoint_align32_int32_t_int8_t: ; CHECK-P10-LABEL: ld_disjoint_align32_int32_t_int8_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r4, -15264 ; CHECK-P10-NEXT: lis r4, -15264
; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: and r3, r3, r4
; CHECK-P10-NEXT: plbz r3, 999990000(r3), 0 ; CHECK-P10-NEXT: plbz r3, 999990000(r3), 0
; CHECK-P10-NEXT: extsb r3, r3 ; CHECK-P10-NEXT: extsb r3, r3
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_disjoint_align32_int32_t_int8_t: ; CHECK-PREP10-LABEL: ld_disjoint_align32_int32_t_int8_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r4, -15264 ; CHECK-PREP10-NEXT: lis r4, -15264
; CHECK-P9-NEXT: and r3, r3, r4 ; CHECK-PREP10-NEXT: and r3, r3, r4
; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-PREP10-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-PREP10-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lbzx r3, r3, r4 ; CHECK-PREP10-NEXT: lbzx r3, r3, r4
; CHECK-P9-NEXT: extsb r3, r3 ; CHECK-PREP10-NEXT: extsb r3, r3
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_int32_t_int8_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r4, -15264
; CHECK-P8-NEXT: lis r5, 15258
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lbzx r3, r3, r4
; CHECK-P8-NEXT: extsb r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%1 = load atomic i8, ptr %0 monotonic, align 16 %1 = load atomic i8, ptr %0 monotonic, align 16
%conv = sext i8 %1 to i32 %conv = sext i8 %1 to i32
ret i32 %conv ret i32 %conv
} }
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; CHECK-P10-LABEL: ld_disjoint_align32_int32_t_uint16_t: ; CHECK-P10-LABEL: ld_disjoint_align32_int32_t_uint16_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r4, -15264 ; CHECK-P10-NEXT: lis r4, -15264
; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: and r3, r3, r4
; CHECK-P10-NEXT: plhz r3, 999990000(r3), 0 ; CHECK-P10-NEXT: plhz r3, 999990000(r3), 0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_disjoint_align32_int32_t_uint16_t: ; CHECK-PREP10-LABEL: ld_disjoint_align32_int32_t_uint16_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r4, -15264 ; CHECK-PREP10-NEXT: lis r4, -15264
; CHECK-P9-NEXT: and r3, r3, r4 ; CHECK-PREP10-NEXT: and r3, r3, r4
; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-PREP10-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-PREP10-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lhzx r3, r3, r4 ; CHECK-PREP10-NEXT: lhzx r3, r3, r4
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_int32_t_uint16_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r4, -15264
; CHECK-P8-NEXT: lis r5, 15258
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lhzx r3, r3, r4
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%1 = load atomic i16, ptr %0 monotonic, align 16 %1 = load atomic i16, ptr %0 monotonic, align 16
%conv = zext i16 %1 to i32 %conv = zext i16 %1 to i32
ret i32 %conv ret i32 %conv
} }
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; CHECK-P10-LABEL: ld_disjoint_align32_int32_t_int16_t: ; CHECK-P10-LABEL: ld_disjoint_align32_int32_t_int16_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r4, -15264 ; CHECK-P10-NEXT: lis r4, -15264
; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: and r3, r3, r4
; CHECK-P10-NEXT: plhz r3, 999990000(r3), 0 ; CHECK-P10-NEXT: plhz r3, 999990000(r3), 0
; CHECK-P10-NEXT: extsh r3, r3 ; CHECK-P10-NEXT: extsh r3, r3
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_disjoint_align32_int32_t_int16_t: ; CHECK-PREP10-LABEL: ld_disjoint_align32_int32_t_int16_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r4, -15264 ; CHECK-PREP10-NEXT: lis r4, -15264
; CHECK-P9-NEXT: and r3, r3, r4 ; CHECK-PREP10-NEXT: and r3, r3, r4
; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-PREP10-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-PREP10-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lhzx r3, r3, r4 ; CHECK-PREP10-NEXT: lhzx r3, r3, r4
; CHECK-P9-NEXT: extsh r3, r3 ; CHECK-PREP10-NEXT: extsh r3, r3
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_int32_t_int16_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r4, -15264
; CHECK-P8-NEXT: lis r5, 15258
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lhzx r3, r3, r4
; CHECK-P8-NEXT: extsh r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%1 = load atomic i16, ptr %0 monotonic, align 16 %1 = load atomic i16, ptr %0 monotonic, align 16
%conv = sext i16 %1 to i32 %conv = sext i16 %1 to i32
ret i32 %conv ret i32 %conv
} }
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; CHECK-P10-LABEL: ld_disjoint_align32_int32_t_uint32_t: ; CHECK-P10-LABEL: ld_disjoint_align32_int32_t_uint32_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r4, -15264 ; CHECK-P10-NEXT: lis r4, -15264
; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: and r3, r3, r4
; CHECK-P10-NEXT: plwz r3, 999990000(r3), 0 ; CHECK-P10-NEXT: plwz r3, 999990000(r3), 0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-P10-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_disjoint_align32_int32_t_uint32_t: ; CHECK-PREP10-LABEL: ld_disjoint_align32_int32_t_uint32_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r4, -15264 ; CHECK-PREP10-NEXT: lis r4, -15264
; CHECK-P9-NEXT: and r3, r3, r4 ; CHECK-PREP10-NEXT: and r3, r3, r4
; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-PREP10-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-PREP10-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lwax r3, r3, r4 ; CHECK-PREP10-NEXT: lwax r3, r3, r4
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_int32_t_uint32_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r4, -15264
; CHECK-P8-NEXT: lis r5, 15258
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lwax r3, r3, r4
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%1 = load atomic i32, ptr %0 monotonic, align 16 %1 = load atomic i32, ptr %0 monotonic, align 16
ret i32 %1 ret i32 %1
} }
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; CHECK-P10-LABEL: ld_disjoint_align32_int32_t_uint64_t: ; CHECK-P10-LABEL: ld_disjoint_align32_int32_t_uint64_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r4, -15264 ; CHECK-P10-NEXT: lis r4, -15264
; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: and r3, r3, r4
; CHECK-P10-NEXT: pld r3, 999990000(r3), 0 ; CHECK-P10-NEXT: pld r3, 999990000(r3), 0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-P10-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_disjoint_align32_int32_t_uint64_t: ; CHECK-PREP10-LABEL: ld_disjoint_align32_int32_t_uint64_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r4, -15264 ; CHECK-PREP10-NEXT: lis r4, -15264
; CHECK-P9-NEXT: and r3, r3, r4 ; CHECK-PREP10-NEXT: and r3, r3, r4
; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-PREP10-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-PREP10-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: ldx r3, r3, r4 ; CHECK-PREP10-NEXT: ldx r3, r3, r4
; CHECK-P9-NEXT: extsw r3, r3 ; CHECK-PREP10-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_int32_t_uint64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r4, -15264
; CHECK-P8-NEXT: lis r5, 15258
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: ldx r3, r3, r4
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%1 = load atomic i64, ptr %0 monotonic, align 16 %1 = load atomic i64, ptr %0 monotonic, align 16
%conv = trunc i64 %1 to i32 %conv = trunc i64 %1 to i32
ret i32 %conv ret i32 %conv
} }
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; CHECK-P10-LABEL: ld_disjoint_align32_uint32_t_uint8_t: ; CHECK-P10-LABEL: ld_disjoint_align32_uint32_t_uint8_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r4, -15264 ; CHECK-P10-NEXT: lis r4, -15264
; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: and r3, r3, r4
; CHECK-P10-NEXT: plbz r3, 999990000(r3), 0 ; CHECK-P10-NEXT: plbz r3, 999990000(r3), 0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_disjoint_align32_uint32_t_uint8_t: ; CHECK-PREP10-LABEL: ld_disjoint_align32_uint32_t_uint8_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r4, -15264 ; CHECK-PREP10-NEXT: lis r4, -15264
; CHECK-P9-NEXT: and r3, r3, r4 ; CHECK-PREP10-NEXT: and r3, r3, r4
; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-PREP10-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-PREP10-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lbzx r3, r3, r4 ; CHECK-PREP10-NEXT: lbzx r3, r3, r4
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint32_t_uint8_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r4, -15264
; CHECK-P8-NEXT: lis r5, 15258
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lbzx r3, r3, r4
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%1 = load atomic i8, ptr %0 monotonic, align 16 %1 = load atomic i8, ptr %0 monotonic, align 16
%conv = zext i8 %1 to i32 %conv = zext i8 %1 to i32
ret i32 %conv ret i32 %conv
} }
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; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r4, -15264 ; CHECK-P10-NEXT: lis r4, -15264
; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: and r3, r3, r4
; CHECK-P10-NEXT: plbz r3, 999990000(r3), 0 ; CHECK-P10-NEXT: plbz r3, 999990000(r3), 0
; CHECK-P10-NEXT: extsb r3, r3 ; CHECK-P10-NEXT: extsb r3, r3
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_disjoint_align32_uint32_t_int8_t: ; CHECK-PREP10-LABEL: ld_disjoint_align32_uint32_t_int8_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r4, -15264 ; CHECK-PREP10-NEXT: lis r4, -15264
; CHECK-P9-NEXT: and r3, r3, r4 ; CHECK-PREP10-NEXT: and r3, r3, r4
; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-PREP10-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-PREP10-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lbzx r3, r3, r4 ; CHECK-PREP10-NEXT: lbzx r3, r3, r4
; CHECK-P9-NEXT: extsb r3, r3 ; CHECK-PREP10-NEXT: extsb r3, r3
; CHECK-P9-NEXT: clrldi r3, r3, 32 ; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint32_t_int8_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r4, -15264
; CHECK-P8-NEXT: lis r5, 15258
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lbzx r3, r3, r4
; CHECK-P8-NEXT: extsb r3, r3
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%1 = load atomic i8, ptr %0 monotonic, align 16 %1 = load atomic i8, ptr %0 monotonic, align 16
%conv = sext i8 %1 to i32 %conv = sext i8 %1 to i32
ret i32 %conv ret i32 %conv
} }
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; CHECK-P10-LABEL: ld_disjoint_align32_uint32_t_uint16_t: ; CHECK-P10-LABEL: ld_disjoint_align32_uint32_t_uint16_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r4, -15264 ; CHECK-P10-NEXT: lis r4, -15264
; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: and r3, r3, r4
; CHECK-P10-NEXT: plhz r3, 999990000(r3), 0 ; CHECK-P10-NEXT: plhz r3, 999990000(r3), 0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_disjoint_align32_uint32_t_uint16_t: ; CHECK-PREP10-LABEL: ld_disjoint_align32_uint32_t_uint16_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r4, -15264 ; CHECK-PREP10-NEXT: lis r4, -15264
; CHECK-P9-NEXT: and r3, r3, r4 ; CHECK-PREP10-NEXT: and r3, r3, r4
; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-PREP10-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-PREP10-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lhzx r3, r3, r4 ; CHECK-PREP10-NEXT: lhzx r3, r3, r4
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint32_t_uint16_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r4, -15264
; CHECK-P8-NEXT: lis r5, 15258
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lhzx r3, r3, r4
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%1 = load atomic i16, ptr %0 monotonic, align 16 %1 = load atomic i16, ptr %0 monotonic, align 16
%conv = zext i16 %1 to i32 %conv = zext i16 %1 to i32
ret i32 %conv ret i32 %conv
} }
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; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r4, -15264 ; CHECK-P10-NEXT: lis r4, -15264
; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: and r3, r3, r4
; CHECK-P10-NEXT: plhz r3, 999990000(r3), 0 ; CHECK-P10-NEXT: plhz r3, 999990000(r3), 0
; CHECK-P10-NEXT: extsh r3, r3 ; CHECK-P10-NEXT: extsh r3, r3
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_disjoint_align32_uint32_t_int16_t: ; CHECK-PREP10-LABEL: ld_disjoint_align32_uint32_t_int16_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r4, -15264 ; CHECK-PREP10-NEXT: lis r4, -15264
; CHECK-P9-NEXT: and r3, r3, r4 ; CHECK-PREP10-NEXT: and r3, r3, r4
; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-PREP10-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-PREP10-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lhax r3, r3, r4 ; CHECK-PREP10-NEXT: lhax r3, r3, r4
; CHECK-P9-NEXT: clrldi r3, r3, 32 ; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint32_t_int16_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r4, -15264
; CHECK-P8-NEXT: lis r5, 15258
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lhax r3, r3, r4
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%1 = load atomic i16, ptr %0 monotonic, align 16 %1 = load atomic i16, ptr %0 monotonic, align 16
%conv = sext i16 %1 to i32 %conv = sext i16 %1 to i32
ret i32 %conv ret i32 %conv
} }
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; CHECK-P10-LABEL: ld_disjoint_align32_uint32_t_uint32_t: ; CHECK-P10-LABEL: ld_disjoint_align32_uint32_t_uint32_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r4, -15264 ; CHECK-P10-NEXT: lis r4, -15264
; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: and r3, r3, r4
; CHECK-P10-NEXT: plwz r3, 999990000(r3), 0 ; CHECK-P10-NEXT: plwz r3, 999990000(r3), 0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_disjoint_align32_uint32_t_uint32_t: ; CHECK-PREP10-LABEL: ld_disjoint_align32_uint32_t_uint32_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r4, -15264 ; CHECK-PREP10-NEXT: lis r4, -15264
; CHECK-P9-NEXT: and r3, r3, r4 ; CHECK-PREP10-NEXT: and r3, r3, r4
; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-PREP10-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-PREP10-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lwzx r3, r3, r4 ; CHECK-PREP10-NEXT: lwzx r3, r3, r4
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint32_t_uint32_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r4, -15264
; CHECK-P8-NEXT: lis r5, 15258
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lwzx r3, r3, r4
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%1 = load atomic i32, ptr %0 monotonic, align 16 %1 = load atomic i32, ptr %0 monotonic, align 16
ret i32 %1 ret i32 %1
} }
▲ Show 20 Lines • Show All 255 Lines • ▼ Show 20 Lines
; CHECK-P10-LABEL: ld_disjoint_align32_uint32_t_uint64_t: ; CHECK-P10-LABEL: ld_disjoint_align32_uint32_t_uint64_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r4, -15264 ; CHECK-P10-NEXT: lis r4, -15264
; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: and r3, r3, r4
; CHECK-P10-NEXT: pld r3, 999990000(r3), 0 ; CHECK-P10-NEXT: pld r3, 999990000(r3), 0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_disjoint_align32_uint32_t_uint64_t: ; CHECK-PREP10-LABEL: ld_disjoint_align32_uint32_t_uint64_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r4, -15264 ; CHECK-PREP10-NEXT: lis r4, -15264
; CHECK-P9-NEXT: and r3, r3, r4 ; CHECK-PREP10-NEXT: and r3, r3, r4
; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-PREP10-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-PREP10-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: ldx r3, r3, r4 ; CHECK-PREP10-NEXT: ldx r3, r3, r4
; CHECK-P9-NEXT: clrldi r3, r3, 32 ; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint32_t_uint64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r4, -15264
; CHECK-P8-NEXT: lis r5, 15258
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: ldx r3, r3, r4
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%1 = load atomic i64, ptr %0 monotonic, align 16 %1 = load atomic i64, ptr %0 monotonic, align 16
%conv = trunc i64 %1 to i32 %conv = trunc i64 %1 to i32
ret i32 %conv ret i32 %conv
} }
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define dso_local void @st_disjoint_align32_uint32_t_uint8_t(i64 %ptr, i32 zeroext %str) { define dso_local void @st_disjoint_align32_uint32_t_uint8_t(i64 %ptr, i32 zeroext %str) {
; CHECK-P10-LABEL: st_disjoint_align32_uint32_t_uint8_t: ; CHECK-P10-LABEL: st_disjoint_align32_uint32_t_uint8_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r5, -15264 ; CHECK-P10-NEXT: lis r5, -15264
; CHECK-P10-NEXT: and r3, r3, r5 ; CHECK-P10-NEXT: and r3, r3, r5
; CHECK-P10-NEXT: pstb r4, 999990000(r3), 0 ; CHECK-P10-NEXT: pstb r4, 999990000(r3), 0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_disjoint_align32_uint32_t_uint8_t: ; CHECK-PREP10-LABEL: st_disjoint_align32_uint32_t_uint8_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r5, -15264 ; CHECK-PREP10-NEXT: lis r5, -15264
; CHECK-P9-NEXT: and r3, r3, r5 ; CHECK-PREP10-NEXT: and r3, r3, r5
; CHECK-P9-NEXT: lis r5, 15258 ; CHECK-PREP10-NEXT: lis r5, 15258
; CHECK-P9-NEXT: ori r5, r5, 41712 ; CHECK-PREP10-NEXT: ori r5, r5, 41712
; CHECK-P9-NEXT: stbx r4, r3, r5 ; CHECK-PREP10-NEXT: stbx r4, r3, r5
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align32_uint32_t_uint8_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r5, -15264
; CHECK-P8-NEXT: lis r6, 15258
; CHECK-P8-NEXT: and r3, r3, r5
; CHECK-P8-NEXT: ori r5, r6, 41712
; CHECK-P8-NEXT: stbx r4, r3, r5
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%conv = trunc i32 %str to i8 %conv = trunc i32 %str to i8
store atomic i8 %conv, ptr %0 monotonic, align 16 store atomic i8 %conv, ptr %0 monotonic, align 16
ret void ret void
} }
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define dso_local void @st_disjoint_align32_uint32_t_uint16_t(i64 %ptr, i32 zeroext %str) { define dso_local void @st_disjoint_align32_uint32_t_uint16_t(i64 %ptr, i32 zeroext %str) {
; CHECK-P10-LABEL: st_disjoint_align32_uint32_t_uint16_t: ; CHECK-P10-LABEL: st_disjoint_align32_uint32_t_uint16_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r5, -15264 ; CHECK-P10-NEXT: lis r5, -15264
; CHECK-P10-NEXT: and r3, r3, r5 ; CHECK-P10-NEXT: and r3, r3, r5
; CHECK-P10-NEXT: psth r4, 999990000(r3), 0 ; CHECK-P10-NEXT: psth r4, 999990000(r3), 0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_disjoint_align32_uint32_t_uint16_t: ; CHECK-PREP10-LABEL: st_disjoint_align32_uint32_t_uint16_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r5, -15264 ; CHECK-PREP10-NEXT: lis r5, -15264
; CHECK-P9-NEXT: and r3, r3, r5 ; CHECK-PREP10-NEXT: and r3, r3, r5
; CHECK-P9-NEXT: lis r5, 15258 ; CHECK-PREP10-NEXT: lis r5, 15258
; CHECK-P9-NEXT: ori r5, r5, 41712 ; CHECK-PREP10-NEXT: ori r5, r5, 41712
; CHECK-P9-NEXT: sthx r4, r3, r5 ; CHECK-PREP10-NEXT: sthx r4, r3, r5
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align32_uint32_t_uint16_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r5, -15264
; CHECK-P8-NEXT: lis r6, 15258
; CHECK-P8-NEXT: and r3, r3, r5
; CHECK-P8-NEXT: ori r5, r6, 41712
; CHECK-P8-NEXT: sthx r4, r3, r5
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%conv = trunc i32 %str to i16 %conv = trunc i32 %str to i16
store atomic i16 %conv, ptr %0 monotonic, align 16 store atomic i16 %conv, ptr %0 monotonic, align 16
ret void ret void
} }
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define dso_local void @st_disjoint_align32_uint32_t_uint32_t(i64 %ptr, i32 zeroext %str) { define dso_local void @st_disjoint_align32_uint32_t_uint32_t(i64 %ptr, i32 zeroext %str) {
; CHECK-P10-LABEL: st_disjoint_align32_uint32_t_uint32_t: ; CHECK-P10-LABEL: st_disjoint_align32_uint32_t_uint32_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r5, -15264 ; CHECK-P10-NEXT: lis r5, -15264
; CHECK-P10-NEXT: and r3, r3, r5 ; CHECK-P10-NEXT: and r3, r3, r5
; CHECK-P10-NEXT: pstw r4, 999990000(r3), 0 ; CHECK-P10-NEXT: pstw r4, 999990000(r3), 0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_disjoint_align32_uint32_t_uint32_t: ; CHECK-PREP10-LABEL: st_disjoint_align32_uint32_t_uint32_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r5, -15264 ; CHECK-PREP10-NEXT: lis r5, -15264
; CHECK-P9-NEXT: and r3, r3, r5 ; CHECK-PREP10-NEXT: and r3, r3, r5
; CHECK-P9-NEXT: lis r5, 15258 ; CHECK-PREP10-NEXT: lis r5, 15258
; CHECK-P9-NEXT: ori r5, r5, 41712 ; CHECK-PREP10-NEXT: ori r5, r5, 41712
; CHECK-P9-NEXT: stwx r4, r3, r5 ; CHECK-PREP10-NEXT: stwx r4, r3, r5
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align32_uint32_t_uint32_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r5, -15264
; CHECK-P8-NEXT: lis r6, 15258
; CHECK-P8-NEXT: and r3, r3, r5
; CHECK-P8-NEXT: ori r5, r6, 41712
; CHECK-P8-NEXT: stwx r4, r3, r5
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
store atomic i32 %str, ptr %0 monotonic, align 16 store atomic i32 %str, ptr %0 monotonic, align 16
ret void ret void
} }
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define dso_local void @st_disjoint_align32_uint32_t_uint64_t(i64 %ptr, i32 zeroext %str) { define dso_local void @st_disjoint_align32_uint32_t_uint64_t(i64 %ptr, i32 zeroext %str) {
; CHECK-P10-LABEL: st_disjoint_align32_uint32_t_uint64_t: ; CHECK-P10-LABEL: st_disjoint_align32_uint32_t_uint64_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r5, -15264 ; CHECK-P10-NEXT: lis r5, -15264
; CHECK-P10-NEXT: and r3, r3, r5 ; CHECK-P10-NEXT: and r3, r3, r5
; CHECK-P10-NEXT: pstd r4, 999990000(r3), 0 ; CHECK-P10-NEXT: pstd r4, 999990000(r3), 0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_disjoint_align32_uint32_t_uint64_t: ; CHECK-PREP10-LABEL: st_disjoint_align32_uint32_t_uint64_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r5, -15264 ; CHECK-PREP10-NEXT: lis r5, -15264
; CHECK-P9-NEXT: and r3, r3, r5 ; CHECK-PREP10-NEXT: and r3, r3, r5
; CHECK-P9-NEXT: lis r5, 15258 ; CHECK-PREP10-NEXT: lis r5, 15258
; CHECK-P9-NEXT: ori r5, r5, 41712 ; CHECK-PREP10-NEXT: ori r5, r5, 41712
; CHECK-P9-NEXT: stdx r4, r3, r5 ; CHECK-PREP10-NEXT: stdx r4, r3, r5
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align32_uint32_t_uint64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r5, -15264
; CHECK-P8-NEXT: lis r6, 15258
; CHECK-P8-NEXT: and r3, r3, r5
; CHECK-P8-NEXT: ori r5, r6, 41712
; CHECK-P8-NEXT: stdx r4, r3, r5
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%conv = zext i32 %str to i64 %conv = zext i32 %str to i64
store atomic i64 %conv, ptr %0 monotonic, align 16 store atomic i64 %conv, ptr %0 monotonic, align 16
ret void ret void
} }
▲ Show 20 Lines • Show All 249 Lines • ▼ Show 20 Lines
define dso_local void @st_disjoint_align32_int32_t_uint64_t(i64 %ptr, i32 signext %str) { define dso_local void @st_disjoint_align32_int32_t_uint64_t(i64 %ptr, i32 signext %str) {
; CHECK-P10-LABEL: st_disjoint_align32_int32_t_uint64_t: ; CHECK-P10-LABEL: st_disjoint_align32_int32_t_uint64_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r5, -15264 ; CHECK-P10-NEXT: lis r5, -15264
; CHECK-P10-NEXT: and r3, r3, r5 ; CHECK-P10-NEXT: and r3, r3, r5
; CHECK-P10-NEXT: pstd r4, 999990000(r3), 0 ; CHECK-P10-NEXT: pstd r4, 999990000(r3), 0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_disjoint_align32_int32_t_uint64_t: ; CHECK-PREP10-LABEL: st_disjoint_align32_int32_t_uint64_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r5, -15264 ; CHECK-PREP10-NEXT: lis r5, -15264
; CHECK-P9-NEXT: and r3, r3, r5 ; CHECK-PREP10-NEXT: and r3, r3, r5
; CHECK-P9-NEXT: lis r5, 15258 ; CHECK-PREP10-NEXT: lis r5, 15258
; CHECK-P9-NEXT: ori r5, r5, 41712 ; CHECK-PREP10-NEXT: ori r5, r5, 41712
; CHECK-P9-NEXT: stdx r4, r3, r5 ; CHECK-PREP10-NEXT: stdx r4, r3, r5
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align32_int32_t_uint64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r5, -15264
; CHECK-P8-NEXT: lis r6, 15258
; CHECK-P8-NEXT: and r3, r3, r5
; CHECK-P8-NEXT: ori r5, r6, 41712
; CHECK-P8-NEXT: stdx r4, r3, r5
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%conv = sext i32 %str to i64 %conv = sext i32 %str to i64
store atomic i64 %conv, ptr %0 monotonic, align 16 store atomic i64 %conv, ptr %0 monotonic, align 16
ret void ret void
} }
▲ Show 20 Lines • Show All 93 Lines • ▼ Show 20 Lines
; CHECK-PREP10-NEXT: ori r4, r4, 19025 ; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: std r3, 0(r4) ; CHECK-PREP10-NEXT: std r3, 0(r4)
; CHECK-PREP10-NEXT: blr ; CHECK-PREP10-NEXT: blr
entry: entry:
%conv = sext i32 %str to i64 %conv = sext i32 %str to i64
store atomic i64 %conv, ptr inttoptr (i64 1000000000000 to ptr) monotonic, align 4096 store atomic i64 %conv, ptr inttoptr (i64 1000000000000 to ptr) monotonic, align 4096
ret void ret void
} }
shchenzUnsubmitted
Done
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Ditto

shchenz: Ditto
shchenzUnsubmitted
Done
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Please delete the unused check prefixes, so that we won't have this note.

shchenz: Please delete the unused check prefixes, so that we won't have this note.

llvm/test/CodeGen/PowerPC/atomics-i64-ldst.ll

llvm/test/CodeGen/PowerPC/atomics-i8-ldst.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-P10 ; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-P10
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-P10 ; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-P10
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10,CHECK-P9 ; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10,CHECK-P9 ; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10,CHECK-P8 ; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10,CHECK-P8 ; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10
; Function Attrs: nofree norecurse nounwind uwtable willreturn ; Function Attrs: nofree norecurse nounwind uwtable willreturn
define dso_local signext i8 @ld_0_int8_t_uint8_t(i64 %ptr) { define dso_local signext i8 @ld_0_int8_t_uint8_t(i64 %ptr) {
; CHECK-LABEL: ld_0_int8_t_uint8_t: ; CHECK-LABEL: ld_0_int8_t_uint8_t:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 0(r3) ; CHECK-NEXT: lbz r3, 0(r3)
; CHECK-NEXT: extsb r3, r3 ; CHECK-NEXT: extsb r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
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; CHECK-P10-LABEL: ld_disjoint_align32_int8_t_uint8_t: ; CHECK-P10-LABEL: ld_disjoint_align32_int8_t_uint8_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r4, -15264 ; CHECK-P10-NEXT: lis r4, -15264
; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: and r3, r3, r4
; CHECK-P10-NEXT: plbz r3, 999990000(r3), 0 ; CHECK-P10-NEXT: plbz r3, 999990000(r3), 0
; CHECK-P10-NEXT: extsb r3, r3 ; CHECK-P10-NEXT: extsb r3, r3
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_disjoint_align32_int8_t_uint8_t: ; CHECK-PREP10-LABEL: ld_disjoint_align32_int8_t_uint8_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r4, -15264 ; CHECK-PREP10-NEXT: lis r4, -15264
; CHECK-P9-NEXT: and r3, r3, r4 ; CHECK-PREP10-NEXT: and r3, r3, r4
; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-PREP10-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-PREP10-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lbzx r3, r3, r4 ; CHECK-PREP10-NEXT: lbzx r3, r3, r4
; CHECK-P9-NEXT: extsb r3, r3 ; CHECK-PREP10-NEXT: extsb r3, r3
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_int8_t_uint8_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r4, -15264
; CHECK-P8-NEXT: lis r5, 15258
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lbzx r3, r3, r4
; CHECK-P8-NEXT: extsb r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%1 = load atomic i8, ptr %0 monotonic, align 16 %1 = load atomic i8, ptr %0 monotonic, align 16
ret i8 %1 ret i8 %1
} }
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; CHECK-P10-LABEL: ld_disjoint_align32_int8_t_uint16_t: ; CHECK-P10-LABEL: ld_disjoint_align32_int8_t_uint16_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r4, -15264 ; CHECK-P10-NEXT: lis r4, -15264
; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: and r3, r3, r4
; CHECK-P10-NEXT: plhz r3, 999990000(r3), 0 ; CHECK-P10-NEXT: plhz r3, 999990000(r3), 0
; CHECK-P10-NEXT: extsb r3, r3 ; CHECK-P10-NEXT: extsb r3, r3
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_disjoint_align32_int8_t_uint16_t: ; CHECK-PREP10-LABEL: ld_disjoint_align32_int8_t_uint16_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r4, -15264 ; CHECK-PREP10-NEXT: lis r4, -15264
; CHECK-P9-NEXT: and r3, r3, r4 ; CHECK-PREP10-NEXT: and r3, r3, r4
; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-PREP10-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-PREP10-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lhzx r3, r3, r4 ; CHECK-PREP10-NEXT: lhzx r3, r3, r4
; CHECK-P9-NEXT: extsb r3, r3 ; CHECK-PREP10-NEXT: extsb r3, r3
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_int8_t_uint16_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r4, -15264
; CHECK-P8-NEXT: lis r5, 15258
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lhzx r3, r3, r4
; CHECK-P8-NEXT: extsb r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%1 = load atomic i16, ptr %0 monotonic, align 16 %1 = load atomic i16, ptr %0 monotonic, align 16
%conv = trunc i16 %1 to i8 %conv = trunc i16 %1 to i8
ret i8 %conv ret i8 %conv
} }
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; CHECK-P10-LABEL: ld_disjoint_align32_int8_t_uint32_t: ; CHECK-P10-LABEL: ld_disjoint_align32_int8_t_uint32_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r4, -15264 ; CHECK-P10-NEXT: lis r4, -15264
; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: and r3, r3, r4
; CHECK-P10-NEXT: plwz r3, 999990000(r3), 0 ; CHECK-P10-NEXT: plwz r3, 999990000(r3), 0
; CHECK-P10-NEXT: extsb r3, r3 ; CHECK-P10-NEXT: extsb r3, r3
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_disjoint_align32_int8_t_uint32_t: ; CHECK-PREP10-LABEL: ld_disjoint_align32_int8_t_uint32_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r4, -15264 ; CHECK-PREP10-NEXT: lis r4, -15264
; CHECK-P9-NEXT: and r3, r3, r4 ; CHECK-PREP10-NEXT: and r3, r3, r4
; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-PREP10-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-PREP10-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lwzx r3, r3, r4 ; CHECK-PREP10-NEXT: lwzx r3, r3, r4
; CHECK-P9-NEXT: extsb r3, r3 ; CHECK-PREP10-NEXT: extsb r3, r3
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_int8_t_uint32_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r4, -15264
; CHECK-P8-NEXT: lis r5, 15258
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lwzx r3, r3, r4
; CHECK-P8-NEXT: extsb r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%1 = load atomic i32, ptr %0 monotonic, align 16 %1 = load atomic i32, ptr %0 monotonic, align 16
%conv = trunc i32 %1 to i8 %conv = trunc i32 %1 to i8
ret i8 %conv ret i8 %conv
} }
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; CHECK-P10-LABEL: ld_disjoint_align32_int8_t_uint64_t: ; CHECK-P10-LABEL: ld_disjoint_align32_int8_t_uint64_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r4, -15264 ; CHECK-P10-NEXT: lis r4, -15264
; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: and r3, r3, r4
; CHECK-P10-NEXT: pld r3, 999990000(r3), 0 ; CHECK-P10-NEXT: pld r3, 999990000(r3), 0
; CHECK-P10-NEXT: extsb r3, r3 ; CHECK-P10-NEXT: extsb r3, r3
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_disjoint_align32_int8_t_uint64_t: ; CHECK-PREP10-LABEL: ld_disjoint_align32_int8_t_uint64_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r4, -15264 ; CHECK-PREP10-NEXT: lis r4, -15264
; CHECK-P9-NEXT: and r3, r3, r4 ; CHECK-PREP10-NEXT: and r3, r3, r4
; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-PREP10-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-PREP10-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: ldx r3, r3, r4 ; CHECK-PREP10-NEXT: ldx r3, r3, r4
; CHECK-P9-NEXT: extsb r3, r3 ; CHECK-PREP10-NEXT: extsb r3, r3
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_int8_t_uint64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r4, -15264
; CHECK-P8-NEXT: lis r5, 15258
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: ldx r3, r3, r4
; CHECK-P8-NEXT: extsb r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%1 = load atomic i64, ptr %0 monotonic, align 16 %1 = load atomic i64, ptr %0 monotonic, align 16
%conv = trunc i64 %1 to i8 %conv = trunc i64 %1 to i8
ret i8 %conv ret i8 %conv
} }
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; CHECK-P10-LABEL: ld_disjoint_align32_uint8_t_uint8_t: ; CHECK-P10-LABEL: ld_disjoint_align32_uint8_t_uint8_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r4, -15264 ; CHECK-P10-NEXT: lis r4, -15264
; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: and r3, r3, r4
; CHECK-P10-NEXT: plbz r3, 999990000(r3), 0 ; CHECK-P10-NEXT: plbz r3, 999990000(r3), 0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_disjoint_align32_uint8_t_uint8_t: ; CHECK-PREP10-LABEL: ld_disjoint_align32_uint8_t_uint8_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r4, -15264 ; CHECK-PREP10-NEXT: lis r4, -15264
; CHECK-P9-NEXT: and r3, r3, r4 ; CHECK-PREP10-NEXT: and r3, r3, r4
; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-PREP10-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-PREP10-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lbzx r3, r3, r4 ; CHECK-PREP10-NEXT: lbzx r3, r3, r4
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint8_t_uint8_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r4, -15264
; CHECK-P8-NEXT: lis r5, 15258
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lbzx r3, r3, r4
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%1 = load atomic i8, ptr %0 monotonic, align 16 %1 = load atomic i8, ptr %0 monotonic, align 16
ret i8 %1 ret i8 %1
} }
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; CHECK-P10-LABEL: ld_disjoint_align32_uint8_t_uint16_t: ; CHECK-P10-LABEL: ld_disjoint_align32_uint8_t_uint16_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r4, -15264 ; CHECK-P10-NEXT: lis r4, -15264
; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: and r3, r3, r4
; CHECK-P10-NEXT: plhz r3, 999990000(r3), 0 ; CHECK-P10-NEXT: plhz r3, 999990000(r3), 0
; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: clrldi r3, r3, 56
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_disjoint_align32_uint8_t_uint16_t: ; CHECK-PREP10-LABEL: ld_disjoint_align32_uint8_t_uint16_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r4, -15264 ; CHECK-PREP10-NEXT: lis r4, -15264
; CHECK-P9-NEXT: and r3, r3, r4 ; CHECK-PREP10-NEXT: and r3, r3, r4
; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-PREP10-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-PREP10-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lhzx r3, r3, r4 ; CHECK-PREP10-NEXT: lhzx r3, r3, r4
; CHECK-P9-NEXT: clrldi r3, r3, 56 ; CHECK-PREP10-NEXT: clrldi r3, r3, 56
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint8_t_uint16_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r4, -15264
; CHECK-P8-NEXT: lis r5, 15258
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lhzx r3, r3, r4
; CHECK-P8-NEXT: clrldi r3, r3, 56
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%1 = load atomic i16, ptr %0 monotonic, align 16 %1 = load atomic i16, ptr %0 monotonic, align 16
%conv = trunc i16 %1 to i8 %conv = trunc i16 %1 to i8
ret i8 %conv ret i8 %conv
} }
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; CHECK-P10-LABEL: ld_disjoint_align32_uint8_t_uint32_t: ; CHECK-P10-LABEL: ld_disjoint_align32_uint8_t_uint32_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r4, -15264 ; CHECK-P10-NEXT: lis r4, -15264
; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: and r3, r3, r4
; CHECK-P10-NEXT: plwz r3, 999990000(r3), 0 ; CHECK-P10-NEXT: plwz r3, 999990000(r3), 0
; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: clrldi r3, r3, 56
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_disjoint_align32_uint8_t_uint32_t: ; CHECK-PREP10-LABEL: ld_disjoint_align32_uint8_t_uint32_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r4, -15264 ; CHECK-PREP10-NEXT: lis r4, -15264
; CHECK-P9-NEXT: and r3, r3, r4 ; CHECK-PREP10-NEXT: and r3, r3, r4
; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-PREP10-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-PREP10-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lwzx r3, r3, r4 ; CHECK-PREP10-NEXT: lwzx r3, r3, r4
; CHECK-P9-NEXT: clrldi r3, r3, 56 ; CHECK-PREP10-NEXT: clrldi r3, r3, 56
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint8_t_uint32_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r4, -15264
; CHECK-P8-NEXT: lis r5, 15258
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lwzx r3, r3, r4
; CHECK-P8-NEXT: clrldi r3, r3, 56
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%1 = load atomic i32, ptr %0 monotonic, align 16 %1 = load atomic i32, ptr %0 monotonic, align 16
%conv = trunc i32 %1 to i8 %conv = trunc i32 %1 to i8
ret i8 %conv ret i8 %conv
} }
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; CHECK-P10-LABEL: ld_disjoint_align32_uint8_t_uint64_t: ; CHECK-P10-LABEL: ld_disjoint_align32_uint8_t_uint64_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r4, -15264 ; CHECK-P10-NEXT: lis r4, -15264
; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: and r3, r3, r4
; CHECK-P10-NEXT: pld r3, 999990000(r3), 0 ; CHECK-P10-NEXT: pld r3, 999990000(r3), 0
; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: clrldi r3, r3, 56
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_disjoint_align32_uint8_t_uint64_t: ; CHECK-PREP10-LABEL: ld_disjoint_align32_uint8_t_uint64_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r4, -15264 ; CHECK-PREP10-NEXT: lis r4, -15264
; CHECK-P9-NEXT: and r3, r3, r4 ; CHECK-PREP10-NEXT: and r3, r3, r4
; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-PREP10-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-PREP10-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: ldx r3, r3, r4 ; CHECK-PREP10-NEXT: ldx r3, r3, r4
; CHECK-P9-NEXT: clrldi r3, r3, 56 ; CHECK-PREP10-NEXT: clrldi r3, r3, 56
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint8_t_uint64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r4, -15264
; CHECK-P8-NEXT: lis r5, 15258
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: ldx r3, r3, r4
; CHECK-P8-NEXT: clrldi r3, r3, 56
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%1 = load atomic i64, ptr %0 monotonic, align 16 %1 = load atomic i64, ptr %0 monotonic, align 16
%conv = trunc i64 %1 to i8 %conv = trunc i64 %1 to i8
ret i8 %conv ret i8 %conv
} }
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define dso_local void @st_disjoint_align32_uint8_t_uint8_t(i64 %ptr, i8 zeroext %str) { define dso_local void @st_disjoint_align32_uint8_t_uint8_t(i64 %ptr, i8 zeroext %str) {
; CHECK-P10-LABEL: st_disjoint_align32_uint8_t_uint8_t: ; CHECK-P10-LABEL: st_disjoint_align32_uint8_t_uint8_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r5, -15264 ; CHECK-P10-NEXT: lis r5, -15264
; CHECK-P10-NEXT: and r3, r3, r5 ; CHECK-P10-NEXT: and r3, r3, r5
; CHECK-P10-NEXT: pstb r4, 999990000(r3), 0 ; CHECK-P10-NEXT: pstb r4, 999990000(r3), 0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_disjoint_align32_uint8_t_uint8_t: ; CHECK-PREP10-LABEL: st_disjoint_align32_uint8_t_uint8_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r5, -15264 ; CHECK-PREP10-NEXT: lis r5, -15264
; CHECK-P9-NEXT: and r3, r3, r5 ; CHECK-PREP10-NEXT: and r3, r3, r5
; CHECK-P9-NEXT: lis r5, 15258 ; CHECK-PREP10-NEXT: lis r5, 15258
; CHECK-P9-NEXT: ori r5, r5, 41712 ; CHECK-PREP10-NEXT: ori r5, r5, 41712
; CHECK-P9-NEXT: stbx r4, r3, r5 ; CHECK-PREP10-NEXT: stbx r4, r3, r5
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align32_uint8_t_uint8_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r5, -15264
; CHECK-P8-NEXT: lis r6, 15258
; CHECK-P8-NEXT: and r3, r3, r5
; CHECK-P8-NEXT: ori r5, r6, 41712
; CHECK-P8-NEXT: stbx r4, r3, r5
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
store atomic i8 %str, ptr %0 monotonic, align 16 store atomic i8 %str, ptr %0 monotonic, align 16
ret void ret void
} }
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define dso_local void @st_disjoint_align32_uint8_t_uint16_t(i64 %ptr, i8 zeroext %str) { define dso_local void @st_disjoint_align32_uint8_t_uint16_t(i64 %ptr, i8 zeroext %str) {
; CHECK-P10-LABEL: st_disjoint_align32_uint8_t_uint16_t: ; CHECK-P10-LABEL: st_disjoint_align32_uint8_t_uint16_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r5, -15264 ; CHECK-P10-NEXT: lis r5, -15264
; CHECK-P10-NEXT: and r3, r3, r5 ; CHECK-P10-NEXT: and r3, r3, r5
; CHECK-P10-NEXT: psth r4, 999990000(r3), 0 ; CHECK-P10-NEXT: psth r4, 999990000(r3), 0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_disjoint_align32_uint8_t_uint16_t: ; CHECK-PREP10-LABEL: st_disjoint_align32_uint8_t_uint16_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r5, -15264 ; CHECK-PREP10-NEXT: lis r5, -15264
; CHECK-P9-NEXT: and r3, r3, r5 ; CHECK-PREP10-NEXT: and r3, r3, r5
; CHECK-P9-NEXT: lis r5, 15258 ; CHECK-PREP10-NEXT: lis r5, 15258
; CHECK-P9-NEXT: ori r5, r5, 41712 ; CHECK-PREP10-NEXT: ori r5, r5, 41712
; CHECK-P9-NEXT: sthx r4, r3, r5 ; CHECK-PREP10-NEXT: sthx r4, r3, r5
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align32_uint8_t_uint16_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r5, -15264
; CHECK-P8-NEXT: lis r6, 15258
; CHECK-P8-NEXT: and r3, r3, r5
; CHECK-P8-NEXT: ori r5, r6, 41712
; CHECK-P8-NEXT: sthx r4, r3, r5
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%conv = zext i8 %str to i16 %conv = zext i8 %str to i16
store atomic i16 %conv, ptr %0 monotonic, align 16 store atomic i16 %conv, ptr %0 monotonic, align 16
ret void ret void
} }
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define dso_local void @st_disjoint_align32_uint8_t_uint32_t(i64 %ptr, i8 zeroext %str) { define dso_local void @st_disjoint_align32_uint8_t_uint32_t(i64 %ptr, i8 zeroext %str) {
; CHECK-P10-LABEL: st_disjoint_align32_uint8_t_uint32_t: ; CHECK-P10-LABEL: st_disjoint_align32_uint8_t_uint32_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r5, -15264 ; CHECK-P10-NEXT: lis r5, -15264
; CHECK-P10-NEXT: and r3, r3, r5 ; CHECK-P10-NEXT: and r3, r3, r5
; CHECK-P10-NEXT: pstw r4, 999990000(r3), 0 ; CHECK-P10-NEXT: pstw r4, 999990000(r3), 0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_disjoint_align32_uint8_t_uint32_t: ; CHECK-PREP10-LABEL: st_disjoint_align32_uint8_t_uint32_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r5, -15264 ; CHECK-PREP10-NEXT: lis r5, -15264
; CHECK-P9-NEXT: and r3, r3, r5 ; CHECK-PREP10-NEXT: and r3, r3, r5
; CHECK-P9-NEXT: lis r5, 15258 ; CHECK-PREP10-NEXT: lis r5, 15258
; CHECK-P9-NEXT: ori r5, r5, 41712 ; CHECK-PREP10-NEXT: ori r5, r5, 41712
; CHECK-P9-NEXT: stwx r4, r3, r5 ; CHECK-PREP10-NEXT: stwx r4, r3, r5
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align32_uint8_t_uint32_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r5, -15264
; CHECK-P8-NEXT: lis r6, 15258
; CHECK-P8-NEXT: and r3, r3, r5
; CHECK-P8-NEXT: ori r5, r6, 41712
; CHECK-P8-NEXT: stwx r4, r3, r5
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%conv = zext i8 %str to i32 %conv = zext i8 %str to i32
store atomic i32 %conv, ptr %0 monotonic, align 16 store atomic i32 %conv, ptr %0 monotonic, align 16
ret void ret void
} }
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define dso_local void @st_disjoint_align32_uint8_t_uint64_t(i64 %ptr, i8 zeroext %str) { define dso_local void @st_disjoint_align32_uint8_t_uint64_t(i64 %ptr, i8 zeroext %str) {
; CHECK-P10-LABEL: st_disjoint_align32_uint8_t_uint64_t: ; CHECK-P10-LABEL: st_disjoint_align32_uint8_t_uint64_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r5, -15264 ; CHECK-P10-NEXT: lis r5, -15264
; CHECK-P10-NEXT: and r3, r3, r5 ; CHECK-P10-NEXT: and r3, r3, r5
; CHECK-P10-NEXT: pstd r4, 999990000(r3), 0 ; CHECK-P10-NEXT: pstd r4, 999990000(r3), 0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_disjoint_align32_uint8_t_uint64_t: ; CHECK-PREP10-LABEL: st_disjoint_align32_uint8_t_uint64_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r5, -15264 ; CHECK-PREP10-NEXT: lis r5, -15264
; CHECK-P9-NEXT: and r3, r3, r5 ; CHECK-PREP10-NEXT: and r3, r3, r5
; CHECK-P9-NEXT: lis r5, 15258 ; CHECK-PREP10-NEXT: lis r5, 15258
; CHECK-P9-NEXT: ori r5, r5, 41712 ; CHECK-PREP10-NEXT: ori r5, r5, 41712
; CHECK-P9-NEXT: stdx r4, r3, r5 ; CHECK-PREP10-NEXT: stdx r4, r3, r5
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align32_uint8_t_uint64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r5, -15264
; CHECK-P8-NEXT: lis r6, 15258
; CHECK-P8-NEXT: and r3, r3, r5
; CHECK-P8-NEXT: ori r5, r6, 41712
; CHECK-P8-NEXT: stdx r4, r3, r5
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%conv = zext i8 %str to i64 %conv = zext i8 %str to i64
store atomic i64 %conv, ptr %0 monotonic, align 16 store atomic i64 %conv, ptr %0 monotonic, align 16
ret void ret void
} }
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define dso_local void @st_disjoint_align32_int8_t_uint16_t(i64 %ptr, i8 signext %str) { define dso_local void @st_disjoint_align32_int8_t_uint16_t(i64 %ptr, i8 signext %str) {
; CHECK-P10-LABEL: st_disjoint_align32_int8_t_uint16_t: ; CHECK-P10-LABEL: st_disjoint_align32_int8_t_uint16_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r5, -15264 ; CHECK-P10-NEXT: lis r5, -15264
; CHECK-P10-NEXT: and r3, r3, r5 ; CHECK-P10-NEXT: and r3, r3, r5
; CHECK-P10-NEXT: psth r4, 999990000(r3), 0 ; CHECK-P10-NEXT: psth r4, 999990000(r3), 0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_disjoint_align32_int8_t_uint16_t: ; CHECK-PREP10-LABEL: st_disjoint_align32_int8_t_uint16_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r5, -15264 ; CHECK-PREP10-NEXT: lis r5, -15264
; CHECK-P9-NEXT: and r3, r3, r5 ; CHECK-PREP10-NEXT: and r3, r3, r5
; CHECK-P9-NEXT: lis r5, 15258 ; CHECK-PREP10-NEXT: lis r5, 15258
; CHECK-P9-NEXT: ori r5, r5, 41712 ; CHECK-PREP10-NEXT: ori r5, r5, 41712
; CHECK-P9-NEXT: sthx r4, r3, r5 ; CHECK-PREP10-NEXT: sthx r4, r3, r5
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align32_int8_t_uint16_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r5, -15264
; CHECK-P8-NEXT: lis r6, 15258
; CHECK-P8-NEXT: and r3, r3, r5
; CHECK-P8-NEXT: ori r5, r6, 41712
; CHECK-P8-NEXT: sthx r4, r3, r5
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%conv = sext i8 %str to i16 %conv = sext i8 %str to i16
store atomic i16 %conv, ptr %0 monotonic, align 16 store atomic i16 %conv, ptr %0 monotonic, align 16
ret void ret void
} }
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define dso_local void @st_disjoint_align32_int8_t_uint32_t(i64 %ptr, i8 signext %str) { define dso_local void @st_disjoint_align32_int8_t_uint32_t(i64 %ptr, i8 signext %str) {
; CHECK-P10-LABEL: st_disjoint_align32_int8_t_uint32_t: ; CHECK-P10-LABEL: st_disjoint_align32_int8_t_uint32_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r5, -15264 ; CHECK-P10-NEXT: lis r5, -15264
; CHECK-P10-NEXT: and r3, r3, r5 ; CHECK-P10-NEXT: and r3, r3, r5
; CHECK-P10-NEXT: pstw r4, 999990000(r3), 0 ; CHECK-P10-NEXT: pstw r4, 999990000(r3), 0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_disjoint_align32_int8_t_uint32_t: ; CHECK-PREP10-LABEL: st_disjoint_align32_int8_t_uint32_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r5, -15264 ; CHECK-PREP10-NEXT: lis r5, -15264
; CHECK-P9-NEXT: and r3, r3, r5 ; CHECK-PREP10-NEXT: and r3, r3, r5
; CHECK-P9-NEXT: lis r5, 15258 ; CHECK-PREP10-NEXT: lis r5, 15258
; CHECK-P9-NEXT: ori r5, r5, 41712 ; CHECK-PREP10-NEXT: ori r5, r5, 41712
; CHECK-P9-NEXT: stwx r4, r3, r5 ; CHECK-PREP10-NEXT: stwx r4, r3, r5
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align32_int8_t_uint32_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r5, -15264
; CHECK-P8-NEXT: lis r6, 15258
; CHECK-P8-NEXT: and r3, r3, r5
; CHECK-P8-NEXT: ori r5, r6, 41712
; CHECK-P8-NEXT: stwx r4, r3, r5
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%conv = sext i8 %str to i32 %conv = sext i8 %str to i32
store atomic i32 %conv, ptr %0 monotonic, align 16 store atomic i32 %conv, ptr %0 monotonic, align 16
ret void ret void
} }
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define dso_local void @st_disjoint_align32_int8_t_uint64_t(i64 %ptr, i8 signext %str) { define dso_local void @st_disjoint_align32_int8_t_uint64_t(i64 %ptr, i8 signext %str) {
; CHECK-P10-LABEL: st_disjoint_align32_int8_t_uint64_t: ; CHECK-P10-LABEL: st_disjoint_align32_int8_t_uint64_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r5, -15264 ; CHECK-P10-NEXT: lis r5, -15264
; CHECK-P10-NEXT: and r3, r3, r5 ; CHECK-P10-NEXT: and r3, r3, r5
; CHECK-P10-NEXT: pstd r4, 999990000(r3), 0 ; CHECK-P10-NEXT: pstd r4, 999990000(r3), 0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_disjoint_align32_int8_t_uint64_t: ; CHECK-PREP10-LABEL: st_disjoint_align32_int8_t_uint64_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r5, -15264 ; CHECK-PREP10-NEXT: lis r5, -15264
; CHECK-P9-NEXT: and r3, r3, r5 ; CHECK-PREP10-NEXT: and r3, r3, r5
; CHECK-P9-NEXT: lis r5, 15258 ; CHECK-PREP10-NEXT: lis r5, 15258
; CHECK-P9-NEXT: ori r5, r5, 41712 ; CHECK-PREP10-NEXT: ori r5, r5, 41712
; CHECK-P9-NEXT: stdx r4, r3, r5 ; CHECK-PREP10-NEXT: stdx r4, r3, r5
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align32_int8_t_uint64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r5, -15264
; CHECK-P8-NEXT: lis r6, 15258
; CHECK-P8-NEXT: and r3, r3, r5
; CHECK-P8-NEXT: ori r5, r6, 41712
; CHECK-P8-NEXT: stdx r4, r3, r5
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%conv = sext i8 %str to i64 %conv = sext i8 %str to i64
store atomic i64 %conv, ptr %0 monotonic, align 16 store atomic i64 %conv, ptr %0 monotonic, align 16
ret void ret void
} }
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; CHECK-PREP10-NEXT: ori r4, r4, 19025 ; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: std r3, 0(r4) ; CHECK-PREP10-NEXT: std r3, 0(r4)
; CHECK-PREP10-NEXT: blr ; CHECK-PREP10-NEXT: blr
entry: entry:
%conv = sext i8 %str to i64 %conv = sext i8 %str to i64
store atomic i64 %conv, ptr inttoptr (i64 1000000000000 to ptr) monotonic, align 4096 store atomic i64 %conv, ptr inttoptr (i64 1000000000000 to ptr) monotonic, align 4096
ret void ret void
} }
shchenzUnsubmitted
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Ditto

shchenz: Ditto
shchenzUnsubmitted
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Please try to remove this NOTE.

shchenz: Please try to remove this NOTE.

llvm/test/CodeGen/PowerPC/atomics-regression.ll

Show First 20 Lines • Show All 447 Lines • ▼ Show 20 Lines
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val acquire acquire %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val acquire acquire
ret void ret void
} }
define void @test43(ptr %ptr, i8 %cmp, i8 %val) { define void @test43(ptr %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test43: ; PPC64LE-LABEL: test43:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
shchenzUnsubmitted
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Aren't the atomic related instructions are barriers to the scheduler? Can you check why there are changes around them? Thanks.

shchenz: Aren't the atomic related instructions are barriers to the scheduler? Can you check why there…
qiucfAuthorUnsubmitted
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lwsync (SYNC) is treated as global memory barrier. But clrlwi (RLWINM) neither writes nor reads any memory, so scheduling such instruction around SYNC is okay. BTW, the new codegen is the original order.

qiucf: `lwsync` (`SYNC`) is treated as global memory barrier. But `clrlwi` (`RLWINM`) neither writes…
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: .LBB43_1: ; PPC64LE-NEXT: .LBB43_1:
; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 6, 4 ; PPC64LE-NEXT: cmpw 6, 4
; PPC64LE-NEXT: bnelr 0 ; PPC64LE-NEXT: bnelr 0
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB43_1 ; PPC64LE-NEXT: bne 0, .LBB43_1
; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val release monotonic %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val release monotonic
ret void ret void
} }
define void @test44(ptr %ptr, i8 %cmp, i8 %val) { define void @test44(ptr %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test44: ; PPC64LE-LABEL: test44:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: .LBB44_1: ; PPC64LE-NEXT: .LBB44_1:
; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 6, 4 ; PPC64LE-NEXT: cmpw 6, 4
; PPC64LE-NEXT: bne 0, .LBB44_3 ; PPC64LE-NEXT: bne 0, .LBB44_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB44_1 ; PPC64LE-NEXT: bne 0, .LBB44_1
; PPC64LE-NEXT: .LBB44_3: ; PPC64LE-NEXT: .LBB44_3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val release acquire %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val release acquire
ret void ret void
} }
define void @test45(ptr %ptr, i8 %cmp, i8 %val) { define void @test45(ptr %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test45: ; PPC64LE-LABEL: test45:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: .LBB45_1: ; PPC64LE-NEXT: .LBB45_1:
; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 6, 4 ; PPC64LE-NEXT: cmpw 6, 4
; PPC64LE-NEXT: bne 0, .LBB45_3 ; PPC64LE-NEXT: bne 0, .LBB45_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB45_1 ; PPC64LE-NEXT: bne 0, .LBB45_1
; PPC64LE-NEXT: .LBB45_3: ; PPC64LE-NEXT: .LBB45_3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val acq_rel monotonic %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val acq_rel monotonic
ret void ret void
} }
define void @test46(ptr %ptr, i8 %cmp, i8 %val) { define void @test46(ptr %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test46: ; PPC64LE-LABEL: test46:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: .LBB46_1: ; PPC64LE-NEXT: .LBB46_1:
; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 6, 4 ; PPC64LE-NEXT: cmpw 6, 4
; PPC64LE-NEXT: bne 0, .LBB46_3 ; PPC64LE-NEXT: bne 0, .LBB46_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB46_1 ; PPC64LE-NEXT: bne 0, .LBB46_1
; PPC64LE-NEXT: .LBB46_3: ; PPC64LE-NEXT: .LBB46_3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val acq_rel acquire %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val acq_rel acquire
ret void ret void
} }
define void @test47(ptr %ptr, i8 %cmp, i8 %val) { define void @test47(ptr %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test47: ; PPC64LE-LABEL: test47:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: .LBB47_1: ; PPC64LE-NEXT: .LBB47_1:
; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 6, 4 ; PPC64LE-NEXT: cmpw 6, 4
; PPC64LE-NEXT: bne 0, .LBB47_3 ; PPC64LE-NEXT: bne 0, .LBB47_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB47_1 ; PPC64LE-NEXT: bne 0, .LBB47_1
; PPC64LE-NEXT: .LBB47_3: ; PPC64LE-NEXT: .LBB47_3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val seq_cst monotonic %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val seq_cst monotonic
ret void ret void
} }
define void @test48(ptr %ptr, i8 %cmp, i8 %val) { define void @test48(ptr %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test48: ; PPC64LE-LABEL: test48:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: .LBB48_1: ; PPC64LE-NEXT: .LBB48_1:
; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 6, 4 ; PPC64LE-NEXT: cmpw 6, 4
; PPC64LE-NEXT: bne 0, .LBB48_3 ; PPC64LE-NEXT: bne 0, .LBB48_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB48_1 ; PPC64LE-NEXT: bne 0, .LBB48_1
; PPC64LE-NEXT: .LBB48_3: ; PPC64LE-NEXT: .LBB48_3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val seq_cst acquire %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val seq_cst acquire
ret void ret void
} }
define void @test49(ptr %ptr, i8 %cmp, i8 %val) { define void @test49(ptr %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test49: ; PPC64LE-LABEL: test49:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: .LBB49_1: ; PPC64LE-NEXT: .LBB49_1:
; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 6, 4 ; PPC64LE-NEXT: cmpw 6, 4
; PPC64LE-NEXT: bne 0, .LBB49_3 ; PPC64LE-NEXT: bne 0, .LBB49_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB49_1 ; PPC64LE-NEXT: bne 0, .LBB49_1
; PPC64LE-NEXT: .LBB49_3: ; PPC64LE-NEXT: .LBB49_3:
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; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val acquire acquire %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val acquire acquire
ret void ret void
} }
define void @test53(ptr %ptr, i16 %cmp, i16 %val) { define void @test53(ptr %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test53: ; PPC64LE-LABEL: test53:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: .LBB53_1: ; PPC64LE-NEXT: .LBB53_1:
; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 6, 4 ; PPC64LE-NEXT: cmpw 6, 4
; PPC64LE-NEXT: bnelr 0 ; PPC64LE-NEXT: bnelr 0
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB53_1 ; PPC64LE-NEXT: bne 0, .LBB53_1
; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val release monotonic %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val release monotonic
ret void ret void
} }
define void @test54(ptr %ptr, i16 %cmp, i16 %val) { define void @test54(ptr %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test54: ; PPC64LE-LABEL: test54:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: .LBB54_1: ; PPC64LE-NEXT: .LBB54_1:
; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 6, 4 ; PPC64LE-NEXT: cmpw 6, 4
; PPC64LE-NEXT: bne 0, .LBB54_3 ; PPC64LE-NEXT: bne 0, .LBB54_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB54_1 ; PPC64LE-NEXT: bne 0, .LBB54_1
; PPC64LE-NEXT: .LBB54_3: ; PPC64LE-NEXT: .LBB54_3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val release acquire %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val release acquire
ret void ret void
} }
define void @test55(ptr %ptr, i16 %cmp, i16 %val) { define void @test55(ptr %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test55: ; PPC64LE-LABEL: test55:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: .LBB55_1: ; PPC64LE-NEXT: .LBB55_1:
; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 6, 4 ; PPC64LE-NEXT: cmpw 6, 4
; PPC64LE-NEXT: bne 0, .LBB55_3 ; PPC64LE-NEXT: bne 0, .LBB55_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB55_1 ; PPC64LE-NEXT: bne 0, .LBB55_1
; PPC64LE-NEXT: .LBB55_3: ; PPC64LE-NEXT: .LBB55_3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val acq_rel monotonic %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val acq_rel monotonic
ret void ret void
} }
define void @test56(ptr %ptr, i16 %cmp, i16 %val) { define void @test56(ptr %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test56: ; PPC64LE-LABEL: test56:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: .LBB56_1: ; PPC64LE-NEXT: .LBB56_1:
; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 6, 4 ; PPC64LE-NEXT: cmpw 6, 4
; PPC64LE-NEXT: bne 0, .LBB56_3 ; PPC64LE-NEXT: bne 0, .LBB56_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB56_1 ; PPC64LE-NEXT: bne 0, .LBB56_1
; PPC64LE-NEXT: .LBB56_3: ; PPC64LE-NEXT: .LBB56_3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val acq_rel acquire %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val acq_rel acquire
ret void ret void
} }
define void @test57(ptr %ptr, i16 %cmp, i16 %val) { define void @test57(ptr %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test57: ; PPC64LE-LABEL: test57:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: .LBB57_1: ; PPC64LE-NEXT: .LBB57_1:
; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 6, 4 ; PPC64LE-NEXT: cmpw 6, 4
; PPC64LE-NEXT: bne 0, .LBB57_3 ; PPC64LE-NEXT: bne 0, .LBB57_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB57_1 ; PPC64LE-NEXT: bne 0, .LBB57_1
; PPC64LE-NEXT: .LBB57_3: ; PPC64LE-NEXT: .LBB57_3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val seq_cst monotonic %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val seq_cst monotonic
ret void ret void
} }
define void @test58(ptr %ptr, i16 %cmp, i16 %val) { define void @test58(ptr %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test58: ; PPC64LE-LABEL: test58:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: .LBB58_1: ; PPC64LE-NEXT: .LBB58_1:
; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 6, 4 ; PPC64LE-NEXT: cmpw 6, 4
; PPC64LE-NEXT: bne 0, .LBB58_3 ; PPC64LE-NEXT: bne 0, .LBB58_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB58_1 ; PPC64LE-NEXT: bne 0, .LBB58_1
; PPC64LE-NEXT: .LBB58_3: ; PPC64LE-NEXT: .LBB58_3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val seq_cst acquire %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val seq_cst acquire
ret void ret void
} }
define void @test59(ptr %ptr, i16 %cmp, i16 %val) { define void @test59(ptr %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test59: ; PPC64LE-LABEL: test59:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: .LBB59_1: ; PPC64LE-NEXT: .LBB59_1:
; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 6, 4 ; PPC64LE-NEXT: cmpw 6, 4
; PPC64LE-NEXT: bne 0, .LBB59_3 ; PPC64LE-NEXT: bne 0, .LBB59_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB59_1 ; PPC64LE-NEXT: bne 0, .LBB59_1
; PPC64LE-NEXT: .LBB59_3: ; PPC64LE-NEXT: .LBB59_3:
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; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val syncscope("singlethread") acquire acquire %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val syncscope("singlethread") acquire acquire
ret void ret void
} }
define void @test83(ptr %ptr, i8 %cmp, i8 %val) { define void @test83(ptr %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test83: ; PPC64LE-LABEL: test83:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: .LBB83_1: ; PPC64LE-NEXT: .LBB83_1:
; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 6, 4 ; PPC64LE-NEXT: cmpw 6, 4
; PPC64LE-NEXT: bnelr 0 ; PPC64LE-NEXT: bnelr 0
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB83_1 ; PPC64LE-NEXT: bne 0, .LBB83_1
; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val syncscope("singlethread") release monotonic %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val syncscope("singlethread") release monotonic
ret void ret void
} }
define void @test84(ptr %ptr, i8 %cmp, i8 %val) { define void @test84(ptr %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test84: ; PPC64LE-LABEL: test84:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: .LBB84_1: ; PPC64LE-NEXT: .LBB84_1:
; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 6, 4 ; PPC64LE-NEXT: cmpw 6, 4
; PPC64LE-NEXT: bne 0, .LBB84_3 ; PPC64LE-NEXT: bne 0, .LBB84_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB84_1 ; PPC64LE-NEXT: bne 0, .LBB84_1
; PPC64LE-NEXT: .LBB84_3: ; PPC64LE-NEXT: .LBB84_3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val syncscope("singlethread") release acquire %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val syncscope("singlethread") release acquire
ret void ret void
} }
define void @test85(ptr %ptr, i8 %cmp, i8 %val) { define void @test85(ptr %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test85: ; PPC64LE-LABEL: test85:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: .LBB85_1: ; PPC64LE-NEXT: .LBB85_1:
; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 6, 4 ; PPC64LE-NEXT: cmpw 6, 4
; PPC64LE-NEXT: bne 0, .LBB85_3 ; PPC64LE-NEXT: bne 0, .LBB85_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB85_1 ; PPC64LE-NEXT: bne 0, .LBB85_1
; PPC64LE-NEXT: .LBB85_3: ; PPC64LE-NEXT: .LBB85_3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val syncscope("singlethread") acq_rel monotonic %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val syncscope("singlethread") acq_rel monotonic
ret void ret void
} }
define void @test86(ptr %ptr, i8 %cmp, i8 %val) { define void @test86(ptr %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test86: ; PPC64LE-LABEL: test86:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: .LBB86_1: ; PPC64LE-NEXT: .LBB86_1:
; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 6, 4 ; PPC64LE-NEXT: cmpw 6, 4
; PPC64LE-NEXT: bne 0, .LBB86_3 ; PPC64LE-NEXT: bne 0, .LBB86_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB86_1 ; PPC64LE-NEXT: bne 0, .LBB86_1
; PPC64LE-NEXT: .LBB86_3: ; PPC64LE-NEXT: .LBB86_3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val syncscope("singlethread") acq_rel acquire %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val syncscope("singlethread") acq_rel acquire
ret void ret void
} }
define void @test87(ptr %ptr, i8 %cmp, i8 %val) { define void @test87(ptr %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test87: ; PPC64LE-LABEL: test87:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: .LBB87_1: ; PPC64LE-NEXT: .LBB87_1:
; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 6, 4 ; PPC64LE-NEXT: cmpw 6, 4
; PPC64LE-NEXT: bne 0, .LBB87_3 ; PPC64LE-NEXT: bne 0, .LBB87_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB87_1 ; PPC64LE-NEXT: bne 0, .LBB87_1
; PPC64LE-NEXT: .LBB87_3: ; PPC64LE-NEXT: .LBB87_3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val syncscope("singlethread") seq_cst monotonic %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val syncscope("singlethread") seq_cst monotonic
ret void ret void
} }
define void @test88(ptr %ptr, i8 %cmp, i8 %val) { define void @test88(ptr %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test88: ; PPC64LE-LABEL: test88:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: .LBB88_1: ; PPC64LE-NEXT: .LBB88_1:
; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 6, 4 ; PPC64LE-NEXT: cmpw 6, 4
; PPC64LE-NEXT: bne 0, .LBB88_3 ; PPC64LE-NEXT: bne 0, .LBB88_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB88_1 ; PPC64LE-NEXT: bne 0, .LBB88_1
; PPC64LE-NEXT: .LBB88_3: ; PPC64LE-NEXT: .LBB88_3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val syncscope("singlethread") seq_cst acquire %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val syncscope("singlethread") seq_cst acquire
ret void ret void
} }
define void @test89(ptr %ptr, i8 %cmp, i8 %val) { define void @test89(ptr %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test89: ; PPC64LE-LABEL: test89:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: .LBB89_1: ; PPC64LE-NEXT: .LBB89_1:
; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 6, 4 ; PPC64LE-NEXT: cmpw 6, 4
; PPC64LE-NEXT: bne 0, .LBB89_3 ; PPC64LE-NEXT: bne 0, .LBB89_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB89_1 ; PPC64LE-NEXT: bne 0, .LBB89_1
; PPC64LE-NEXT: .LBB89_3: ; PPC64LE-NEXT: .LBB89_3:
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; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val syncscope("singlethread") acquire acquire %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val syncscope("singlethread") acquire acquire
ret void ret void
} }
define void @test93(ptr %ptr, i16 %cmp, i16 %val) { define void @test93(ptr %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test93: ; PPC64LE-LABEL: test93:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: .LBB93_1: ; PPC64LE-NEXT: .LBB93_1:
; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 6, 4 ; PPC64LE-NEXT: cmpw 6, 4
; PPC64LE-NEXT: bnelr 0 ; PPC64LE-NEXT: bnelr 0
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB93_1 ; PPC64LE-NEXT: bne 0, .LBB93_1
; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val syncscope("singlethread") release monotonic %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val syncscope("singlethread") release monotonic
ret void ret void
} }
define void @test94(ptr %ptr, i16 %cmp, i16 %val) { define void @test94(ptr %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test94: ; PPC64LE-LABEL: test94:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: .LBB94_1: ; PPC64LE-NEXT: .LBB94_1:
; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 6, 4 ; PPC64LE-NEXT: cmpw 6, 4
; PPC64LE-NEXT: bne 0, .LBB94_3 ; PPC64LE-NEXT: bne 0, .LBB94_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB94_1 ; PPC64LE-NEXT: bne 0, .LBB94_1
; PPC64LE-NEXT: .LBB94_3: ; PPC64LE-NEXT: .LBB94_3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val syncscope("singlethread") release acquire %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val syncscope("singlethread") release acquire
ret void ret void
} }
define void @test95(ptr %ptr, i16 %cmp, i16 %val) { define void @test95(ptr %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test95: ; PPC64LE-LABEL: test95:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: .LBB95_1: ; PPC64LE-NEXT: .LBB95_1:
; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 6, 4 ; PPC64LE-NEXT: cmpw 6, 4
; PPC64LE-NEXT: bne 0, .LBB95_3 ; PPC64LE-NEXT: bne 0, .LBB95_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB95_1 ; PPC64LE-NEXT: bne 0, .LBB95_1
; PPC64LE-NEXT: .LBB95_3: ; PPC64LE-NEXT: .LBB95_3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val syncscope("singlethread") acq_rel monotonic %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val syncscope("singlethread") acq_rel monotonic
ret void ret void
} }
define void @test96(ptr %ptr, i16 %cmp, i16 %val) { define void @test96(ptr %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test96: ; PPC64LE-LABEL: test96:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: .LBB96_1: ; PPC64LE-NEXT: .LBB96_1:
; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 6, 4 ; PPC64LE-NEXT: cmpw 6, 4
; PPC64LE-NEXT: bne 0, .LBB96_3 ; PPC64LE-NEXT: bne 0, .LBB96_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB96_1 ; PPC64LE-NEXT: bne 0, .LBB96_1
; PPC64LE-NEXT: .LBB96_3: ; PPC64LE-NEXT: .LBB96_3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val syncscope("singlethread") acq_rel acquire %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val syncscope("singlethread") acq_rel acquire
ret void ret void
} }
define void @test97(ptr %ptr, i16 %cmp, i16 %val) { define void @test97(ptr %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test97: ; PPC64LE-LABEL: test97:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: .LBB97_1: ; PPC64LE-NEXT: .LBB97_1:
; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 6, 4 ; PPC64LE-NEXT: cmpw 6, 4
; PPC64LE-NEXT: bne 0, .LBB97_3 ; PPC64LE-NEXT: bne 0, .LBB97_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB97_1 ; PPC64LE-NEXT: bne 0, .LBB97_1
; PPC64LE-NEXT: .LBB97_3: ; PPC64LE-NEXT: .LBB97_3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val syncscope("singlethread") seq_cst monotonic %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val syncscope("singlethread") seq_cst monotonic
ret void ret void
} }
define void @test98(ptr %ptr, i16 %cmp, i16 %val) { define void @test98(ptr %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test98: ; PPC64LE-LABEL: test98:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: .LBB98_1: ; PPC64LE-NEXT: .LBB98_1:
; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 6, 4 ; PPC64LE-NEXT: cmpw 6, 4
; PPC64LE-NEXT: bne 0, .LBB98_3 ; PPC64LE-NEXT: bne 0, .LBB98_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB98_1 ; PPC64LE-NEXT: bne 0, .LBB98_1
; PPC64LE-NEXT: .LBB98_3: ; PPC64LE-NEXT: .LBB98_3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val syncscope("singlethread") seq_cst acquire %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val syncscope("singlethread") seq_cst acquire
ret void ret void
} }
define void @test99(ptr %ptr, i16 %cmp, i16 %val) { define void @test99(ptr %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test99: ; PPC64LE-LABEL: test99:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: .LBB99_1: ; PPC64LE-NEXT: .LBB99_1:
; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 6, 4 ; PPC64LE-NEXT: cmpw 6, 4
; PPC64LE-NEXT: bne 0, .LBB99_3 ; PPC64LE-NEXT: bne 0, .LBB99_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB99_1 ; PPC64LE-NEXT: bne 0, .LBB99_1
; PPC64LE-NEXT: .LBB99_3: ; PPC64LE-NEXT: .LBB99_3:
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; PPC64LE-LABEL: test123: ; PPC64LE-LABEL: test123:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB123_1: ; PPC64LE-NEXT: .LBB123_1:
; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: stbcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB123_1 ; PPC64LE-NEXT: bne 0, .LBB123_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw xchg ptr %ptr, i8 %val acq_rel %ret = atomicrmw xchg ptr %ptr, i8 %val acq_rel
ret i8 %ret ret i8 %ret
} }
define i8 @test124(ptr %ptr, i8 %val) { define i8 @test124(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test124: ; PPC64LE-LABEL: test124:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB124_1: ; PPC64LE-NEXT: .LBB124_1:
; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: stbcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB124_1 ; PPC64LE-NEXT: bne 0, .LBB124_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw xchg ptr %ptr, i8 %val seq_cst %ret = atomicrmw xchg ptr %ptr, i8 %val seq_cst
ret i8 %ret ret i8 %ret
} }
define i16 @test125(ptr %ptr, i16 %val) { define i16 @test125(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test125: ; PPC64LE-LABEL: test125:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE-LABEL: test128: ; PPC64LE-LABEL: test128:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB128_1: ; PPC64LE-NEXT: .LBB128_1:
; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: sthcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB128_1 ; PPC64LE-NEXT: bne 0, .LBB128_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw xchg ptr %ptr, i16 %val acq_rel %ret = atomicrmw xchg ptr %ptr, i16 %val acq_rel
ret i16 %ret ret i16 %ret
} }
define i16 @test129(ptr %ptr, i16 %val) { define i16 @test129(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test129: ; PPC64LE-LABEL: test129:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB129_1: ; PPC64LE-NEXT: .LBB129_1:
; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: sthcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB129_1 ; PPC64LE-NEXT: bne 0, .LBB129_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw xchg ptr %ptr, i16 %val seq_cst %ret = atomicrmw xchg ptr %ptr, i16 %val seq_cst
ret i16 %ret ret i16 %ret
} }
define i32 @test130(ptr %ptr, i32 %val) { define i32 @test130(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test130: ; PPC64LE-LABEL: test130:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE-LABEL: test133: ; PPC64LE-LABEL: test133:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB133_1: ; PPC64LE-NEXT: .LBB133_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB133_1 ; PPC64LE-NEXT: bne 0, .LBB133_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw xchg ptr %ptr, i32 %val acq_rel %ret = atomicrmw xchg ptr %ptr, i32 %val acq_rel
ret i32 %ret ret i32 %ret
} }
define i32 @test134(ptr %ptr, i32 %val) { define i32 @test134(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test134: ; PPC64LE-LABEL: test134:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB134_1: ; PPC64LE-NEXT: .LBB134_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB134_1 ; PPC64LE-NEXT: bne 0, .LBB134_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw xchg ptr %ptr, i32 %val seq_cst %ret = atomicrmw xchg ptr %ptr, i32 %val seq_cst
ret i32 %ret ret i32 %ret
} }
define i64 @test135(ptr %ptr, i64 %val) { define i64 @test135(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test135: ; PPC64LE-LABEL: test135:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE-LABEL: test138: ; PPC64LE-LABEL: test138:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB138_1: ; PPC64LE-NEXT: .LBB138_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB138_1 ; PPC64LE-NEXT: bne 0, .LBB138_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw xchg ptr %ptr, i64 %val acq_rel %ret = atomicrmw xchg ptr %ptr, i64 %val acq_rel
ret i64 %ret ret i64 %ret
} }
define i64 @test139(ptr %ptr, i64 %val) { define i64 @test139(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test139: ; PPC64LE-LABEL: test139:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB139_1: ; PPC64LE-NEXT: .LBB139_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB139_1 ; PPC64LE-NEXT: bne 0, .LBB139_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw xchg ptr %ptr, i64 %val seq_cst %ret = atomicrmw xchg ptr %ptr, i64 %val seq_cst
ret i64 %ret ret i64 %ret
} }
define i8 @test140(ptr %ptr, i8 %val) { define i8 @test140(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test140: ; PPC64LE-LABEL: test140:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB143_1: ; PPC64LE-NEXT: .LBB143_1:
; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: add 6, 4, 5
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB143_1 ; PPC64LE-NEXT: bne 0, .LBB143_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw add ptr %ptr, i8 %val acq_rel %ret = atomicrmw add ptr %ptr, i8 %val acq_rel
ret i8 %ret ret i8 %ret
} }
define i8 @test144(ptr %ptr, i8 %val) { define i8 @test144(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test144: ; PPC64LE-LABEL: test144:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB144_1: ; PPC64LE-NEXT: .LBB144_1:
; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: add 6, 4, 5
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB144_1 ; PPC64LE-NEXT: bne 0, .LBB144_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw add ptr %ptr, i8 %val seq_cst %ret = atomicrmw add ptr %ptr, i8 %val seq_cst
ret i8 %ret ret i8 %ret
} }
define i16 @test145(ptr %ptr, i16 %val) { define i16 @test145(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test145: ; PPC64LE-LABEL: test145:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB148_1: ; PPC64LE-NEXT: .LBB148_1:
; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: add 6, 4, 5
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB148_1 ; PPC64LE-NEXT: bne 0, .LBB148_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw add ptr %ptr, i16 %val acq_rel %ret = atomicrmw add ptr %ptr, i16 %val acq_rel
ret i16 %ret ret i16 %ret
} }
define i16 @test149(ptr %ptr, i16 %val) { define i16 @test149(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test149: ; PPC64LE-LABEL: test149:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB149_1: ; PPC64LE-NEXT: .LBB149_1:
; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: add 6, 4, 5
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB149_1 ; PPC64LE-NEXT: bne 0, .LBB149_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw add ptr %ptr, i16 %val seq_cst %ret = atomicrmw add ptr %ptr, i16 %val seq_cst
ret i16 %ret ret i16 %ret
} }
define i32 @test150(ptr %ptr, i32 %val) { define i32 @test150(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test150: ; PPC64LE-LABEL: test150:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB153_1: ; PPC64LE-NEXT: .LBB153_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: add 6, 4, 5
; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB153_1 ; PPC64LE-NEXT: bne 0, .LBB153_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw add ptr %ptr, i32 %val acq_rel %ret = atomicrmw add ptr %ptr, i32 %val acq_rel
ret i32 %ret ret i32 %ret
} }
define i32 @test154(ptr %ptr, i32 %val) { define i32 @test154(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test154: ; PPC64LE-LABEL: test154:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB154_1: ; PPC64LE-NEXT: .LBB154_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: add 6, 4, 5
; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB154_1 ; PPC64LE-NEXT: bne 0, .LBB154_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw add ptr %ptr, i32 %val seq_cst %ret = atomicrmw add ptr %ptr, i32 %val seq_cst
ret i32 %ret ret i32 %ret
} }
define i64 @test155(ptr %ptr, i64 %val) { define i64 @test155(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test155: ; PPC64LE-LABEL: test155:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB158_1: ; PPC64LE-NEXT: .LBB158_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: add 6, 4, 5
; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB158_1 ; PPC64LE-NEXT: bne 0, .LBB158_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw add ptr %ptr, i64 %val acq_rel %ret = atomicrmw add ptr %ptr, i64 %val acq_rel
ret i64 %ret ret i64 %ret
} }
define i64 @test159(ptr %ptr, i64 %val) { define i64 @test159(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test159: ; PPC64LE-LABEL: test159:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB159_1: ; PPC64LE-NEXT: .LBB159_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: add 6, 4, 5
; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB159_1 ; PPC64LE-NEXT: bne 0, .LBB159_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw add ptr %ptr, i64 %val seq_cst %ret = atomicrmw add ptr %ptr, i64 %val seq_cst
ret i64 %ret ret i64 %ret
} }
define i8 @test160(ptr %ptr, i8 %val) { define i8 @test160(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test160: ; PPC64LE-LABEL: test160:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB163_1: ; PPC64LE-NEXT: .LBB163_1:
; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: sub 6, 5, 4
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB163_1 ; PPC64LE-NEXT: bne 0, .LBB163_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw sub ptr %ptr, i8 %val acq_rel %ret = atomicrmw sub ptr %ptr, i8 %val acq_rel
ret i8 %ret ret i8 %ret
} }
define i8 @test164(ptr %ptr, i8 %val) { define i8 @test164(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test164: ; PPC64LE-LABEL: test164:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB164_1: ; PPC64LE-NEXT: .LBB164_1:
; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: sub 6, 5, 4
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB164_1 ; PPC64LE-NEXT: bne 0, .LBB164_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw sub ptr %ptr, i8 %val seq_cst %ret = atomicrmw sub ptr %ptr, i8 %val seq_cst
ret i8 %ret ret i8 %ret
} }
define i16 @test165(ptr %ptr, i16 %val) { define i16 @test165(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test165: ; PPC64LE-LABEL: test165:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB168_1: ; PPC64LE-NEXT: .LBB168_1:
; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: sub 6, 5, 4
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB168_1 ; PPC64LE-NEXT: bne 0, .LBB168_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw sub ptr %ptr, i16 %val acq_rel %ret = atomicrmw sub ptr %ptr, i16 %val acq_rel
ret i16 %ret ret i16 %ret
} }
define i16 @test169(ptr %ptr, i16 %val) { define i16 @test169(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test169: ; PPC64LE-LABEL: test169:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB169_1: ; PPC64LE-NEXT: .LBB169_1:
; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: sub 6, 5, 4
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB169_1 ; PPC64LE-NEXT: bne 0, .LBB169_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw sub ptr %ptr, i16 %val seq_cst %ret = atomicrmw sub ptr %ptr, i16 %val seq_cst
ret i16 %ret ret i16 %ret
} }
define i32 @test170(ptr %ptr, i32 %val) { define i32 @test170(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test170: ; PPC64LE-LABEL: test170:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB173_1: ; PPC64LE-NEXT: .LBB173_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: sub 6, 5, 4
; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB173_1 ; PPC64LE-NEXT: bne 0, .LBB173_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw sub ptr %ptr, i32 %val acq_rel %ret = atomicrmw sub ptr %ptr, i32 %val acq_rel
ret i32 %ret ret i32 %ret
} }
define i32 @test174(ptr %ptr, i32 %val) { define i32 @test174(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test174: ; PPC64LE-LABEL: test174:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB174_1: ; PPC64LE-NEXT: .LBB174_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: sub 6, 5, 4
; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB174_1 ; PPC64LE-NEXT: bne 0, .LBB174_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw sub ptr %ptr, i32 %val seq_cst %ret = atomicrmw sub ptr %ptr, i32 %val seq_cst
ret i32 %ret ret i32 %ret
} }
define i64 @test175(ptr %ptr, i64 %val) { define i64 @test175(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test175: ; PPC64LE-LABEL: test175:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB178_1: ; PPC64LE-NEXT: .LBB178_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: sub 6, 5, 4
; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB178_1 ; PPC64LE-NEXT: bne 0, .LBB178_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw sub ptr %ptr, i64 %val acq_rel %ret = atomicrmw sub ptr %ptr, i64 %val acq_rel
ret i64 %ret ret i64 %ret
} }
define i64 @test179(ptr %ptr, i64 %val) { define i64 @test179(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test179: ; PPC64LE-LABEL: test179:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB179_1: ; PPC64LE-NEXT: .LBB179_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: sub 6, 5, 4
; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB179_1 ; PPC64LE-NEXT: bne 0, .LBB179_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw sub ptr %ptr, i64 %val seq_cst %ret = atomicrmw sub ptr %ptr, i64 %val seq_cst
ret i64 %ret ret i64 %ret
} }
define i8 @test180(ptr %ptr, i8 %val) { define i8 @test180(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test180: ; PPC64LE-LABEL: test180:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB183_1: ; PPC64LE-NEXT: .LBB183_1:
; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: and 6, 4, 5
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB183_1 ; PPC64LE-NEXT: bne 0, .LBB183_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw and ptr %ptr, i8 %val acq_rel %ret = atomicrmw and ptr %ptr, i8 %val acq_rel
ret i8 %ret ret i8 %ret
} }
define i8 @test184(ptr %ptr, i8 %val) { define i8 @test184(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test184: ; PPC64LE-LABEL: test184:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB184_1: ; PPC64LE-NEXT: .LBB184_1:
; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: and 6, 4, 5
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB184_1 ; PPC64LE-NEXT: bne 0, .LBB184_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw and ptr %ptr, i8 %val seq_cst %ret = atomicrmw and ptr %ptr, i8 %val seq_cst
ret i8 %ret ret i8 %ret
} }
define i16 @test185(ptr %ptr, i16 %val) { define i16 @test185(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test185: ; PPC64LE-LABEL: test185:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB188_1: ; PPC64LE-NEXT: .LBB188_1:
; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: and 6, 4, 5
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB188_1 ; PPC64LE-NEXT: bne 0, .LBB188_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw and ptr %ptr, i16 %val acq_rel %ret = atomicrmw and ptr %ptr, i16 %val acq_rel
ret i16 %ret ret i16 %ret
} }
define i16 @test189(ptr %ptr, i16 %val) { define i16 @test189(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test189: ; PPC64LE-LABEL: test189:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB189_1: ; PPC64LE-NEXT: .LBB189_1:
; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: and 6, 4, 5
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB189_1 ; PPC64LE-NEXT: bne 0, .LBB189_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw and ptr %ptr, i16 %val seq_cst %ret = atomicrmw and ptr %ptr, i16 %val seq_cst
ret i16 %ret ret i16 %ret
} }
define i32 @test190(ptr %ptr, i32 %val) { define i32 @test190(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test190: ; PPC64LE-LABEL: test190:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB193_1: ; PPC64LE-NEXT: .LBB193_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: and 6, 4, 5
; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB193_1 ; PPC64LE-NEXT: bne 0, .LBB193_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw and ptr %ptr, i32 %val acq_rel %ret = atomicrmw and ptr %ptr, i32 %val acq_rel
ret i32 %ret ret i32 %ret
} }
define i32 @test194(ptr %ptr, i32 %val) { define i32 @test194(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test194: ; PPC64LE-LABEL: test194:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB194_1: ; PPC64LE-NEXT: .LBB194_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: and 6, 4, 5
; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB194_1 ; PPC64LE-NEXT: bne 0, .LBB194_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw and ptr %ptr, i32 %val seq_cst %ret = atomicrmw and ptr %ptr, i32 %val seq_cst
ret i32 %ret ret i32 %ret
} }
define i64 @test195(ptr %ptr, i64 %val) { define i64 @test195(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test195: ; PPC64LE-LABEL: test195:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB198_1: ; PPC64LE-NEXT: .LBB198_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: and 6, 4, 5
; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB198_1 ; PPC64LE-NEXT: bne 0, .LBB198_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw and ptr %ptr, i64 %val acq_rel %ret = atomicrmw and ptr %ptr, i64 %val acq_rel
ret i64 %ret ret i64 %ret
} }
define i64 @test199(ptr %ptr, i64 %val) { define i64 @test199(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test199: ; PPC64LE-LABEL: test199:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB199_1: ; PPC64LE-NEXT: .LBB199_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: and 6, 4, 5
; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB199_1 ; PPC64LE-NEXT: bne 0, .LBB199_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw and ptr %ptr, i64 %val seq_cst %ret = atomicrmw and ptr %ptr, i64 %val seq_cst
ret i64 %ret ret i64 %ret
} }
define i8 @test200(ptr %ptr, i8 %val) { define i8 @test200(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test200: ; PPC64LE-LABEL: test200:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB203_1: ; PPC64LE-NEXT: .LBB203_1:
; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: nand 6, 4, 5
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB203_1 ; PPC64LE-NEXT: bne 0, .LBB203_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw nand ptr %ptr, i8 %val acq_rel %ret = atomicrmw nand ptr %ptr, i8 %val acq_rel
ret i8 %ret ret i8 %ret
} }
define i8 @test204(ptr %ptr, i8 %val) { define i8 @test204(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test204: ; PPC64LE-LABEL: test204:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB204_1: ; PPC64LE-NEXT: .LBB204_1:
; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: nand 6, 4, 5
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB204_1 ; PPC64LE-NEXT: bne 0, .LBB204_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw nand ptr %ptr, i8 %val seq_cst %ret = atomicrmw nand ptr %ptr, i8 %val seq_cst
ret i8 %ret ret i8 %ret
} }
define i16 @test205(ptr %ptr, i16 %val) { define i16 @test205(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test205: ; PPC64LE-LABEL: test205:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB208_1: ; PPC64LE-NEXT: .LBB208_1:
; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: nand 6, 4, 5
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB208_1 ; PPC64LE-NEXT: bne 0, .LBB208_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw nand ptr %ptr, i16 %val acq_rel %ret = atomicrmw nand ptr %ptr, i16 %val acq_rel
ret i16 %ret ret i16 %ret
} }
define i16 @test209(ptr %ptr, i16 %val) { define i16 @test209(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test209: ; PPC64LE-LABEL: test209:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB209_1: ; PPC64LE-NEXT: .LBB209_1:
; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: nand 6, 4, 5
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB209_1 ; PPC64LE-NEXT: bne 0, .LBB209_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw nand ptr %ptr, i16 %val seq_cst %ret = atomicrmw nand ptr %ptr, i16 %val seq_cst
ret i16 %ret ret i16 %ret
} }
define i32 @test210(ptr %ptr, i32 %val) { define i32 @test210(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test210: ; PPC64LE-LABEL: test210:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB213_1: ; PPC64LE-NEXT: .LBB213_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: nand 6, 4, 5
; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB213_1 ; PPC64LE-NEXT: bne 0, .LBB213_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw nand ptr %ptr, i32 %val acq_rel %ret = atomicrmw nand ptr %ptr, i32 %val acq_rel
ret i32 %ret ret i32 %ret
} }
define i32 @test214(ptr %ptr, i32 %val) { define i32 @test214(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test214: ; PPC64LE-LABEL: test214:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB214_1: ; PPC64LE-NEXT: .LBB214_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: nand 6, 4, 5
; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB214_1 ; PPC64LE-NEXT: bne 0, .LBB214_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw nand ptr %ptr, i32 %val seq_cst %ret = atomicrmw nand ptr %ptr, i32 %val seq_cst
ret i32 %ret ret i32 %ret
} }
define i64 @test215(ptr %ptr, i64 %val) { define i64 @test215(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test215: ; PPC64LE-LABEL: test215:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB218_1: ; PPC64LE-NEXT: .LBB218_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: nand 6, 4, 5
; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB218_1 ; PPC64LE-NEXT: bne 0, .LBB218_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw nand ptr %ptr, i64 %val acq_rel %ret = atomicrmw nand ptr %ptr, i64 %val acq_rel
ret i64 %ret ret i64 %ret
} }
define i64 @test219(ptr %ptr, i64 %val) { define i64 @test219(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test219: ; PPC64LE-LABEL: test219:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB219_1: ; PPC64LE-NEXT: .LBB219_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: nand 6, 4, 5
; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB219_1 ; PPC64LE-NEXT: bne 0, .LBB219_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw nand ptr %ptr, i64 %val seq_cst %ret = atomicrmw nand ptr %ptr, i64 %val seq_cst
ret i64 %ret ret i64 %ret
} }
define i8 @test220(ptr %ptr, i8 %val) { define i8 @test220(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test220: ; PPC64LE-LABEL: test220:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB223_1: ; PPC64LE-NEXT: .LBB223_1:
; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: or 6, 4, 5
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB223_1 ; PPC64LE-NEXT: bne 0, .LBB223_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw or ptr %ptr, i8 %val acq_rel %ret = atomicrmw or ptr %ptr, i8 %val acq_rel
ret i8 %ret ret i8 %ret
} }
define i8 @test224(ptr %ptr, i8 %val) { define i8 @test224(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test224: ; PPC64LE-LABEL: test224:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB224_1: ; PPC64LE-NEXT: .LBB224_1:
; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: or 6, 4, 5
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB224_1 ; PPC64LE-NEXT: bne 0, .LBB224_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw or ptr %ptr, i8 %val seq_cst %ret = atomicrmw or ptr %ptr, i8 %val seq_cst
ret i8 %ret ret i8 %ret
} }
define i16 @test225(ptr %ptr, i16 %val) { define i16 @test225(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test225: ; PPC64LE-LABEL: test225:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB228_1: ; PPC64LE-NEXT: .LBB228_1:
; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: or 6, 4, 5
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB228_1 ; PPC64LE-NEXT: bne 0, .LBB228_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw or ptr %ptr, i16 %val acq_rel %ret = atomicrmw or ptr %ptr, i16 %val acq_rel
ret i16 %ret ret i16 %ret
} }
define i16 @test229(ptr %ptr, i16 %val) { define i16 @test229(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test229: ; PPC64LE-LABEL: test229:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB229_1: ; PPC64LE-NEXT: .LBB229_1:
; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: or 6, 4, 5
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB229_1 ; PPC64LE-NEXT: bne 0, .LBB229_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw or ptr %ptr, i16 %val seq_cst %ret = atomicrmw or ptr %ptr, i16 %val seq_cst
ret i16 %ret ret i16 %ret
} }
define i32 @test230(ptr %ptr, i32 %val) { define i32 @test230(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test230: ; PPC64LE-LABEL: test230:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB233_1: ; PPC64LE-NEXT: .LBB233_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: or 6, 4, 5
; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB233_1 ; PPC64LE-NEXT: bne 0, .LBB233_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw or ptr %ptr, i32 %val acq_rel %ret = atomicrmw or ptr %ptr, i32 %val acq_rel
ret i32 %ret ret i32 %ret
} }
define i32 @test234(ptr %ptr, i32 %val) { define i32 @test234(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test234: ; PPC64LE-LABEL: test234:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB234_1: ; PPC64LE-NEXT: .LBB234_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: or 6, 4, 5
; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB234_1 ; PPC64LE-NEXT: bne 0, .LBB234_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw or ptr %ptr, i32 %val seq_cst %ret = atomicrmw or ptr %ptr, i32 %val seq_cst
ret i32 %ret ret i32 %ret
} }
define i64 @test235(ptr %ptr, i64 %val) { define i64 @test235(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test235: ; PPC64LE-LABEL: test235:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB238_1: ; PPC64LE-NEXT: .LBB238_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: or 6, 4, 5
; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB238_1 ; PPC64LE-NEXT: bne 0, .LBB238_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw or ptr %ptr, i64 %val acq_rel %ret = atomicrmw or ptr %ptr, i64 %val acq_rel
ret i64 %ret ret i64 %ret
} }
define i64 @test239(ptr %ptr, i64 %val) { define i64 @test239(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test239: ; PPC64LE-LABEL: test239:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB239_1: ; PPC64LE-NEXT: .LBB239_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: or 6, 4, 5
; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB239_1 ; PPC64LE-NEXT: bne 0, .LBB239_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw or ptr %ptr, i64 %val seq_cst %ret = atomicrmw or ptr %ptr, i64 %val seq_cst
ret i64 %ret ret i64 %ret
} }
define i8 @test240(ptr %ptr, i8 %val) { define i8 @test240(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test240: ; PPC64LE-LABEL: test240:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB243_1: ; PPC64LE-NEXT: .LBB243_1:
; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: xor 6, 4, 5
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB243_1 ; PPC64LE-NEXT: bne 0, .LBB243_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw xor ptr %ptr, i8 %val acq_rel %ret = atomicrmw xor ptr %ptr, i8 %val acq_rel
ret i8 %ret ret i8 %ret
} }
define i8 @test244(ptr %ptr, i8 %val) { define i8 @test244(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test244: ; PPC64LE-LABEL: test244:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB244_1: ; PPC64LE-NEXT: .LBB244_1:
; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: xor 6, 4, 5
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB244_1 ; PPC64LE-NEXT: bne 0, .LBB244_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw xor ptr %ptr, i8 %val seq_cst %ret = atomicrmw xor ptr %ptr, i8 %val seq_cst
ret i8 %ret ret i8 %ret
} }
define i16 @test245(ptr %ptr, i16 %val) { define i16 @test245(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test245: ; PPC64LE-LABEL: test245:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB248_1: ; PPC64LE-NEXT: .LBB248_1:
; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: xor 6, 4, 5
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB248_1 ; PPC64LE-NEXT: bne 0, .LBB248_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw xor ptr %ptr, i16 %val acq_rel %ret = atomicrmw xor ptr %ptr, i16 %val acq_rel
ret i16 %ret ret i16 %ret
} }
define i16 @test249(ptr %ptr, i16 %val) { define i16 @test249(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test249: ; PPC64LE-LABEL: test249:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB249_1: ; PPC64LE-NEXT: .LBB249_1:
; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: xor 6, 4, 5
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB249_1 ; PPC64LE-NEXT: bne 0, .LBB249_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw xor ptr %ptr, i16 %val seq_cst %ret = atomicrmw xor ptr %ptr, i16 %val seq_cst
ret i16 %ret ret i16 %ret
} }
define i32 @test250(ptr %ptr, i32 %val) { define i32 @test250(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test250: ; PPC64LE-LABEL: test250:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB253_1: ; PPC64LE-NEXT: .LBB253_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: xor 6, 4, 5
; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB253_1 ; PPC64LE-NEXT: bne 0, .LBB253_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw xor ptr %ptr, i32 %val acq_rel %ret = atomicrmw xor ptr %ptr, i32 %val acq_rel
ret i32 %ret ret i32 %ret
} }
define i32 @test254(ptr %ptr, i32 %val) { define i32 @test254(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test254: ; PPC64LE-LABEL: test254:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB254_1: ; PPC64LE-NEXT: .LBB254_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: xor 6, 4, 5
; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB254_1 ; PPC64LE-NEXT: bne 0, .LBB254_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw xor ptr %ptr, i32 %val seq_cst %ret = atomicrmw xor ptr %ptr, i32 %val seq_cst
ret i32 %ret ret i32 %ret
} }
define i64 @test255(ptr %ptr, i64 %val) { define i64 @test255(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test255: ; PPC64LE-LABEL: test255:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB258_1: ; PPC64LE-NEXT: .LBB258_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: xor 6, 4, 5
; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB258_1 ; PPC64LE-NEXT: bne 0, .LBB258_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw xor ptr %ptr, i64 %val acq_rel %ret = atomicrmw xor ptr %ptr, i64 %val acq_rel
ret i64 %ret ret i64 %ret
} }
define i64 @test259(ptr %ptr, i64 %val) { define i64 @test259(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test259: ; PPC64LE-LABEL: test259:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB259_1: ; PPC64LE-NEXT: .LBB259_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: xor 6, 4, 5
; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB259_1 ; PPC64LE-NEXT: bne 0, .LBB259_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw xor ptr %ptr, i64 %val seq_cst %ret = atomicrmw xor ptr %ptr, i64 %val seq_cst
ret i64 %ret ret i64 %ret
} }
define i8 @test260(ptr %ptr, i8 %val) { define i8 @test260(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test260: ; PPC64LE-LABEL: test260:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE-NEXT: lbarx 4, 0, 3 ; PPC64LE-NEXT: lbarx 4, 0, 3
; PPC64LE-NEXT: extsb 6, 4 ; PPC64LE-NEXT: extsb 6, 4
; PPC64LE-NEXT: cmpw 6, 5 ; PPC64LE-NEXT: cmpw 6, 5
; PPC64LE-NEXT: bgt 0, .LBB261_3 ; PPC64LE-NEXT: bgt 0, .LBB261_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB261_1 ; PPC64LE-NEXT: bne 0, .LBB261_1
; PPC64LE-NEXT: .LBB261_3: ; PPC64LE-NEXT: .LBB261_3:
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw max ptr %ptr, i8 %val acquire %ret = atomicrmw max ptr %ptr, i8 %val acquire
ret i8 %ret ret i8 %ret
} }
define i8 @test262(ptr %ptr, i8 %val) { define i8 @test262(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test262: ; PPC64LE-LABEL: test262:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: extsb 5, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: extsb 5, 4
; PPC64LE-NEXT: .LBB262_1: ; PPC64LE-NEXT: .LBB262_1:
; PPC64LE-NEXT: lbarx 4, 0, 3 ; PPC64LE-NEXT: lbarx 4, 0, 3
; PPC64LE-NEXT: extsb 6, 4 ; PPC64LE-NEXT: extsb 6, 4
; PPC64LE-NEXT: cmpw 6, 5 ; PPC64LE-NEXT: cmpw 6, 5
; PPC64LE-NEXT: bgt 0, .LBB262_3 ; PPC64LE-NEXT: bgt 0, .LBB262_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB262_1 ; PPC64LE-NEXT: bne 0, .LBB262_1
; PPC64LE-NEXT: .LBB262_3: ; PPC64LE-NEXT: .LBB262_3:
; PPC64LE-NEXT: mr 3, 4 ; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw max ptr %ptr, i8 %val release %ret = atomicrmw max ptr %ptr, i8 %val release
ret i8 %ret ret i8 %ret
} }
define i8 @test263(ptr %ptr, i8 %val) { define i8 @test263(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test263: ; PPC64LE-LABEL: test263:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: extsb 5, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: extsb 5, 4
; PPC64LE-NEXT: .LBB263_1: ; PPC64LE-NEXT: .LBB263_1:
; PPC64LE-NEXT: lbarx 4, 0, 3 ; PPC64LE-NEXT: lbarx 4, 0, 3
; PPC64LE-NEXT: extsb 6, 4 ; PPC64LE-NEXT: extsb 6, 4
; PPC64LE-NEXT: cmpw 6, 5 ; PPC64LE-NEXT: cmpw 6, 5
; PPC64LE-NEXT: bgt 0, .LBB263_3 ; PPC64LE-NEXT: bgt 0, .LBB263_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB263_1 ; PPC64LE-NEXT: bne 0, .LBB263_1
; PPC64LE-NEXT: .LBB263_3: ; PPC64LE-NEXT: .LBB263_3:
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw max ptr %ptr, i8 %val acq_rel %ret = atomicrmw max ptr %ptr, i8 %val acq_rel
ret i8 %ret ret i8 %ret
} }
define i8 @test264(ptr %ptr, i8 %val) { define i8 @test264(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test264: ; PPC64LE-LABEL: test264:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: extsb 5, 4
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: extsb 5, 4
; PPC64LE-NEXT: .LBB264_1: ; PPC64LE-NEXT: .LBB264_1:
; PPC64LE-NEXT: lbarx 4, 0, 3 ; PPC64LE-NEXT: lbarx 4, 0, 3
; PPC64LE-NEXT: extsb 6, 4 ; PPC64LE-NEXT: extsb 6, 4
; PPC64LE-NEXT: cmpw 6, 5 ; PPC64LE-NEXT: cmpw 6, 5
; PPC64LE-NEXT: bgt 0, .LBB264_3 ; PPC64LE-NEXT: bgt 0, .LBB264_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB264_1 ; PPC64LE-NEXT: bne 0, .LBB264_1
; PPC64LE-NEXT: .LBB264_3: ; PPC64LE-NEXT: .LBB264_3:
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw max ptr %ptr, i8 %val seq_cst %ret = atomicrmw max ptr %ptr, i8 %val seq_cst
ret i8 %ret ret i8 %ret
} }
define i16 @test265(ptr %ptr, i16 %val) { define i16 @test265(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test265: ; PPC64LE-LABEL: test265:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE-NEXT: lharx 4, 0, 3 ; PPC64LE-NEXT: lharx 4, 0, 3
; PPC64LE-NEXT: extsh 6, 4 ; PPC64LE-NEXT: extsh 6, 4
; PPC64LE-NEXT: cmpw 6, 5 ; PPC64LE-NEXT: cmpw 6, 5
; PPC64LE-NEXT: bgt 0, .LBB266_3 ; PPC64LE-NEXT: bgt 0, .LBB266_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB266_1 ; PPC64LE-NEXT: bne 0, .LBB266_1
; PPC64LE-NEXT: .LBB266_3: ; PPC64LE-NEXT: .LBB266_3:
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw max ptr %ptr, i16 %val acquire %ret = atomicrmw max ptr %ptr, i16 %val acquire
ret i16 %ret ret i16 %ret
} }
define i16 @test267(ptr %ptr, i16 %val) { define i16 @test267(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test267: ; PPC64LE-LABEL: test267:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: extsh 5, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: extsh 5, 4
; PPC64LE-NEXT: .LBB267_1: ; PPC64LE-NEXT: .LBB267_1:
; PPC64LE-NEXT: lharx 4, 0, 3 ; PPC64LE-NEXT: lharx 4, 0, 3
; PPC64LE-NEXT: extsh 6, 4 ; PPC64LE-NEXT: extsh 6, 4
; PPC64LE-NEXT: cmpw 6, 5 ; PPC64LE-NEXT: cmpw 6, 5
; PPC64LE-NEXT: bgt 0, .LBB267_3 ; PPC64LE-NEXT: bgt 0, .LBB267_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB267_1 ; PPC64LE-NEXT: bne 0, .LBB267_1
; PPC64LE-NEXT: .LBB267_3: ; PPC64LE-NEXT: .LBB267_3:
; PPC64LE-NEXT: mr 3, 4 ; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw max ptr %ptr, i16 %val release %ret = atomicrmw max ptr %ptr, i16 %val release
ret i16 %ret ret i16 %ret
} }
define i16 @test268(ptr %ptr, i16 %val) { define i16 @test268(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test268: ; PPC64LE-LABEL: test268:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: extsh 5, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: extsh 5, 4
; PPC64LE-NEXT: .LBB268_1: ; PPC64LE-NEXT: .LBB268_1:
; PPC64LE-NEXT: lharx 4, 0, 3 ; PPC64LE-NEXT: lharx 4, 0, 3
; PPC64LE-NEXT: extsh 6, 4 ; PPC64LE-NEXT: extsh 6, 4
; PPC64LE-NEXT: cmpw 6, 5 ; PPC64LE-NEXT: cmpw 6, 5
; PPC64LE-NEXT: bgt 0, .LBB268_3 ; PPC64LE-NEXT: bgt 0, .LBB268_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB268_1 ; PPC64LE-NEXT: bne 0, .LBB268_1
; PPC64LE-NEXT: .LBB268_3: ; PPC64LE-NEXT: .LBB268_3:
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw max ptr %ptr, i16 %val acq_rel %ret = atomicrmw max ptr %ptr, i16 %val acq_rel
ret i16 %ret ret i16 %ret
} }
define i16 @test269(ptr %ptr, i16 %val) { define i16 @test269(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test269: ; PPC64LE-LABEL: test269:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: extsh 5, 4
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: extsh 5, 4
; PPC64LE-NEXT: .LBB269_1: ; PPC64LE-NEXT: .LBB269_1:
; PPC64LE-NEXT: lharx 4, 0, 3 ; PPC64LE-NEXT: lharx 4, 0, 3
; PPC64LE-NEXT: extsh 6, 4 ; PPC64LE-NEXT: extsh 6, 4
; PPC64LE-NEXT: cmpw 6, 5 ; PPC64LE-NEXT: cmpw 6, 5
; PPC64LE-NEXT: bgt 0, .LBB269_3 ; PPC64LE-NEXT: bgt 0, .LBB269_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB269_1 ; PPC64LE-NEXT: bne 0, .LBB269_1
; PPC64LE-NEXT: .LBB269_3: ; PPC64LE-NEXT: .LBB269_3:
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw max ptr %ptr, i16 %val seq_cst %ret = atomicrmw max ptr %ptr, i16 %val seq_cst
ret i16 %ret ret i16 %ret
} }
define i32 @test270(ptr %ptr, i32 %val) { define i32 @test270(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test270: ; PPC64LE-LABEL: test270:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE-NEXT: .LBB273_1: ; PPC64LE-NEXT: .LBB273_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: cmpw 5, 4 ; PPC64LE-NEXT: cmpw 5, 4
; PPC64LE-NEXT: bgt 0, .LBB273_3 ; PPC64LE-NEXT: bgt 0, .LBB273_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB273_1 ; PPC64LE-NEXT: bne 0, .LBB273_1
; PPC64LE-NEXT: .LBB273_3: ; PPC64LE-NEXT: .LBB273_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw max ptr %ptr, i32 %val acq_rel %ret = atomicrmw max ptr %ptr, i32 %val acq_rel
ret i32 %ret ret i32 %ret
} }
define i32 @test274(ptr %ptr, i32 %val) { define i32 @test274(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test274: ; PPC64LE-LABEL: test274:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB274_1: ; PPC64LE-NEXT: .LBB274_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: cmpw 5, 4 ; PPC64LE-NEXT: cmpw 5, 4
; PPC64LE-NEXT: bgt 0, .LBB274_3 ; PPC64LE-NEXT: bgt 0, .LBB274_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB274_1 ; PPC64LE-NEXT: bne 0, .LBB274_1
; PPC64LE-NEXT: .LBB274_3: ; PPC64LE-NEXT: .LBB274_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw max ptr %ptr, i32 %val seq_cst %ret = atomicrmw max ptr %ptr, i32 %val seq_cst
ret i32 %ret ret i32 %ret
} }
define i64 @test275(ptr %ptr, i64 %val) { define i64 @test275(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test275: ; PPC64LE-LABEL: test275:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; PPC64LE-NEXT: .LBB278_1: ; PPC64LE-NEXT: .LBB278_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: cmpd 5, 4 ; PPC64LE-NEXT: cmpd 5, 4
; PPC64LE-NEXT: bgt 0, .LBB278_3 ; PPC64LE-NEXT: bgt 0, .LBB278_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB278_1 ; PPC64LE-NEXT: bne 0, .LBB278_1
; PPC64LE-NEXT: .LBB278_3: ; PPC64LE-NEXT: .LBB278_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw max ptr %ptr, i64 %val acq_rel %ret = atomicrmw max ptr %ptr, i64 %val acq_rel
ret i64 %ret ret i64 %ret
} }
define i64 @test279(ptr %ptr, i64 %val) { define i64 @test279(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test279: ; PPC64LE-LABEL: test279:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB279_1: ; PPC64LE-NEXT: .LBB279_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: cmpd 5, 4 ; PPC64LE-NEXT: cmpd 5, 4
; PPC64LE-NEXT: bgt 0, .LBB279_3 ; PPC64LE-NEXT: bgt 0, .LBB279_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB279_1 ; PPC64LE-NEXT: bne 0, .LBB279_1
; PPC64LE-NEXT: .LBB279_3: ; PPC64LE-NEXT: .LBB279_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw max ptr %ptr, i64 %val seq_cst %ret = atomicrmw max ptr %ptr, i64 %val seq_cst
ret i64 %ret ret i64 %ret
} }
define i8 @test280(ptr %ptr, i8 %val) { define i8 @test280(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test280: ; PPC64LE-LABEL: test280:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE-NEXT: lbarx 4, 0, 3 ; PPC64LE-NEXT: lbarx 4, 0, 3
; PPC64LE-NEXT: extsb 6, 4 ; PPC64LE-NEXT: extsb 6, 4
; PPC64LE-NEXT: cmpw 6, 5 ; PPC64LE-NEXT: cmpw 6, 5
; PPC64LE-NEXT: blt 0, .LBB281_3 ; PPC64LE-NEXT: blt 0, .LBB281_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB281_1 ; PPC64LE-NEXT: bne 0, .LBB281_1
; PPC64LE-NEXT: .LBB281_3: ; PPC64LE-NEXT: .LBB281_3:
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw min ptr %ptr, i8 %val acquire %ret = atomicrmw min ptr %ptr, i8 %val acquire
ret i8 %ret ret i8 %ret
} }
define i8 @test282(ptr %ptr, i8 %val) { define i8 @test282(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test282: ; PPC64LE-LABEL: test282:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: extsb 5, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: extsb 5, 4
; PPC64LE-NEXT: .LBB282_1: ; PPC64LE-NEXT: .LBB282_1:
; PPC64LE-NEXT: lbarx 4, 0, 3 ; PPC64LE-NEXT: lbarx 4, 0, 3
; PPC64LE-NEXT: extsb 6, 4 ; PPC64LE-NEXT: extsb 6, 4
; PPC64LE-NEXT: cmpw 6, 5 ; PPC64LE-NEXT: cmpw 6, 5
; PPC64LE-NEXT: blt 0, .LBB282_3 ; PPC64LE-NEXT: blt 0, .LBB282_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB282_1 ; PPC64LE-NEXT: bne 0, .LBB282_1
; PPC64LE-NEXT: .LBB282_3: ; PPC64LE-NEXT: .LBB282_3:
; PPC64LE-NEXT: mr 3, 4 ; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw min ptr %ptr, i8 %val release %ret = atomicrmw min ptr %ptr, i8 %val release
ret i8 %ret ret i8 %ret
} }
define i8 @test283(ptr %ptr, i8 %val) { define i8 @test283(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test283: ; PPC64LE-LABEL: test283:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: extsb 5, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: extsb 5, 4
; PPC64LE-NEXT: .LBB283_1: ; PPC64LE-NEXT: .LBB283_1:
; PPC64LE-NEXT: lbarx 4, 0, 3 ; PPC64LE-NEXT: lbarx 4, 0, 3
; PPC64LE-NEXT: extsb 6, 4 ; PPC64LE-NEXT: extsb 6, 4
; PPC64LE-NEXT: cmpw 6, 5 ; PPC64LE-NEXT: cmpw 6, 5
; PPC64LE-NEXT: blt 0, .LBB283_3 ; PPC64LE-NEXT: blt 0, .LBB283_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB283_1 ; PPC64LE-NEXT: bne 0, .LBB283_1
; PPC64LE-NEXT: .LBB283_3: ; PPC64LE-NEXT: .LBB283_3:
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw min ptr %ptr, i8 %val acq_rel %ret = atomicrmw min ptr %ptr, i8 %val acq_rel
ret i8 %ret ret i8 %ret
} }
define i8 @test284(ptr %ptr, i8 %val) { define i8 @test284(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test284: ; PPC64LE-LABEL: test284:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: extsb 5, 4
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: extsb 5, 4
; PPC64LE-NEXT: .LBB284_1: ; PPC64LE-NEXT: .LBB284_1:
; PPC64LE-NEXT: lbarx 4, 0, 3 ; PPC64LE-NEXT: lbarx 4, 0, 3
; PPC64LE-NEXT: extsb 6, 4 ; PPC64LE-NEXT: extsb 6, 4
; PPC64LE-NEXT: cmpw 6, 5 ; PPC64LE-NEXT: cmpw 6, 5
; PPC64LE-NEXT: blt 0, .LBB284_3 ; PPC64LE-NEXT: blt 0, .LBB284_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB284_1 ; PPC64LE-NEXT: bne 0, .LBB284_1
; PPC64LE-NEXT: .LBB284_3: ; PPC64LE-NEXT: .LBB284_3:
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw min ptr %ptr, i8 %val seq_cst %ret = atomicrmw min ptr %ptr, i8 %val seq_cst
ret i8 %ret ret i8 %ret
} }
define i16 @test285(ptr %ptr, i16 %val) { define i16 @test285(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test285: ; PPC64LE-LABEL: test285:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
Show All 21 Lines
; PPC64LE-NEXT: lharx 4, 0, 3 ; PPC64LE-NEXT: lharx 4, 0, 3
; PPC64LE-NEXT: extsh 6, 4 ; PPC64LE-NEXT: extsh 6, 4
; PPC64LE-NEXT: cmpw 6, 5 ; PPC64LE-NEXT: cmpw 6, 5
; PPC64LE-NEXT: blt 0, .LBB286_3 ; PPC64LE-NEXT: blt 0, .LBB286_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB286_1 ; PPC64LE-NEXT: bne 0, .LBB286_1
; PPC64LE-NEXT: .LBB286_3: ; PPC64LE-NEXT: .LBB286_3:
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw min ptr %ptr, i16 %val acquire %ret = atomicrmw min ptr %ptr, i16 %val acquire
ret i16 %ret ret i16 %ret
} }
define i16 @test287(ptr %ptr, i16 %val) { define i16 @test287(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test287: ; PPC64LE-LABEL: test287:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: extsh 5, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: extsh 5, 4
; PPC64LE-NEXT: .LBB287_1: ; PPC64LE-NEXT: .LBB287_1:
; PPC64LE-NEXT: lharx 4, 0, 3 ; PPC64LE-NEXT: lharx 4, 0, 3
; PPC64LE-NEXT: extsh 6, 4 ; PPC64LE-NEXT: extsh 6, 4
; PPC64LE-NEXT: cmpw 6, 5 ; PPC64LE-NEXT: cmpw 6, 5
; PPC64LE-NEXT: blt 0, .LBB287_3 ; PPC64LE-NEXT: blt 0, .LBB287_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB287_1 ; PPC64LE-NEXT: bne 0, .LBB287_1
; PPC64LE-NEXT: .LBB287_3: ; PPC64LE-NEXT: .LBB287_3:
; PPC64LE-NEXT: mr 3, 4 ; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw min ptr %ptr, i16 %val release %ret = atomicrmw min ptr %ptr, i16 %val release
ret i16 %ret ret i16 %ret
} }
define i16 @test288(ptr %ptr, i16 %val) { define i16 @test288(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test288: ; PPC64LE-LABEL: test288:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: extsh 5, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: extsh 5, 4
; PPC64LE-NEXT: .LBB288_1: ; PPC64LE-NEXT: .LBB288_1:
; PPC64LE-NEXT: lharx 4, 0, 3 ; PPC64LE-NEXT: lharx 4, 0, 3
; PPC64LE-NEXT: extsh 6, 4 ; PPC64LE-NEXT: extsh 6, 4
; PPC64LE-NEXT: cmpw 6, 5 ; PPC64LE-NEXT: cmpw 6, 5
; PPC64LE-NEXT: blt 0, .LBB288_3 ; PPC64LE-NEXT: blt 0, .LBB288_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB288_1 ; PPC64LE-NEXT: bne 0, .LBB288_1
; PPC64LE-NEXT: .LBB288_3: ; PPC64LE-NEXT: .LBB288_3:
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw min ptr %ptr, i16 %val acq_rel %ret = atomicrmw min ptr %ptr, i16 %val acq_rel
ret i16 %ret ret i16 %ret
} }
define i16 @test289(ptr %ptr, i16 %val) { define i16 @test289(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test289: ; PPC64LE-LABEL: test289:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: extsh 5, 4
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: extsh 5, 4
; PPC64LE-NEXT: .LBB289_1: ; PPC64LE-NEXT: .LBB289_1:
; PPC64LE-NEXT: lharx 4, 0, 3 ; PPC64LE-NEXT: lharx 4, 0, 3
; PPC64LE-NEXT: extsh 6, 4 ; PPC64LE-NEXT: extsh 6, 4
; PPC64LE-NEXT: cmpw 6, 5 ; PPC64LE-NEXT: cmpw 6, 5
; PPC64LE-NEXT: blt 0, .LBB289_3 ; PPC64LE-NEXT: blt 0, .LBB289_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB289_1 ; PPC64LE-NEXT: bne 0, .LBB289_1
; PPC64LE-NEXT: .LBB289_3: ; PPC64LE-NEXT: .LBB289_3:
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw min ptr %ptr, i16 %val seq_cst %ret = atomicrmw min ptr %ptr, i16 %val seq_cst
ret i16 %ret ret i16 %ret
} }
define i32 @test290(ptr %ptr, i32 %val) { define i32 @test290(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test290: ; PPC64LE-LABEL: test290:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE-NEXT: .LBB293_1: ; PPC64LE-NEXT: .LBB293_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: cmpw 5, 4 ; PPC64LE-NEXT: cmpw 5, 4
; PPC64LE-NEXT: blt 0, .LBB293_3 ; PPC64LE-NEXT: blt 0, .LBB293_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB293_1 ; PPC64LE-NEXT: bne 0, .LBB293_1
; PPC64LE-NEXT: .LBB293_3: ; PPC64LE-NEXT: .LBB293_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw min ptr %ptr, i32 %val acq_rel %ret = atomicrmw min ptr %ptr, i32 %val acq_rel
ret i32 %ret ret i32 %ret
} }
define i32 @test294(ptr %ptr, i32 %val) { define i32 @test294(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test294: ; PPC64LE-LABEL: test294:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB294_1: ; PPC64LE-NEXT: .LBB294_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: cmpw 5, 4 ; PPC64LE-NEXT: cmpw 5, 4
; PPC64LE-NEXT: blt 0, .LBB294_3 ; PPC64LE-NEXT: blt 0, .LBB294_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB294_1 ; PPC64LE-NEXT: bne 0, .LBB294_1
; PPC64LE-NEXT: .LBB294_3: ; PPC64LE-NEXT: .LBB294_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw min ptr %ptr, i32 %val seq_cst %ret = atomicrmw min ptr %ptr, i32 %val seq_cst
ret i32 %ret ret i32 %ret
} }
define i64 @test295(ptr %ptr, i64 %val) { define i64 @test295(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test295: ; PPC64LE-LABEL: test295:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE-NEXT: .LBB298_1: ; PPC64LE-NEXT: .LBB298_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: cmpd 5, 4 ; PPC64LE-NEXT: cmpd 5, 4
; PPC64LE-NEXT: blt 0, .LBB298_3 ; PPC64LE-NEXT: blt 0, .LBB298_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB298_1 ; PPC64LE-NEXT: bne 0, .LBB298_1
; PPC64LE-NEXT: .LBB298_3: ; PPC64LE-NEXT: .LBB298_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw min ptr %ptr, i64 %val acq_rel %ret = atomicrmw min ptr %ptr, i64 %val acq_rel
ret i64 %ret ret i64 %ret
} }
define i64 @test299(ptr %ptr, i64 %val) { define i64 @test299(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test299: ; PPC64LE-LABEL: test299:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB299_1: ; PPC64LE-NEXT: .LBB299_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: cmpd 5, 4 ; PPC64LE-NEXT: cmpd 5, 4
; PPC64LE-NEXT: blt 0, .LBB299_3 ; PPC64LE-NEXT: blt 0, .LBB299_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB299_1 ; PPC64LE-NEXT: bne 0, .LBB299_1
; PPC64LE-NEXT: .LBB299_3: ; PPC64LE-NEXT: .LBB299_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw min ptr %ptr, i64 %val seq_cst %ret = atomicrmw min ptr %ptr, i64 %val seq_cst
ret i64 %ret ret i64 %ret
} }
define i8 @test300(ptr %ptr, i8 %val) { define i8 @test300(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test300: ; PPC64LE-LABEL: test300:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE-NEXT: .LBB303_1: ; PPC64LE-NEXT: .LBB303_1:
; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: cmplw 5, 4 ; PPC64LE-NEXT: cmplw 5, 4
; PPC64LE-NEXT: bgt 0, .LBB303_3 ; PPC64LE-NEXT: bgt 0, .LBB303_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: stbcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB303_1 ; PPC64LE-NEXT: bne 0, .LBB303_1
; PPC64LE-NEXT: .LBB303_3: ; PPC64LE-NEXT: .LBB303_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw umax ptr %ptr, i8 %val acq_rel %ret = atomicrmw umax ptr %ptr, i8 %val acq_rel
ret i8 %ret ret i8 %ret
} }
define i8 @test304(ptr %ptr, i8 %val) { define i8 @test304(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test304: ; PPC64LE-LABEL: test304:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB304_1: ; PPC64LE-NEXT: .LBB304_1:
; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: cmplw 5, 4 ; PPC64LE-NEXT: cmplw 5, 4
; PPC64LE-NEXT: bgt 0, .LBB304_3 ; PPC64LE-NEXT: bgt 0, .LBB304_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: stbcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB304_1 ; PPC64LE-NEXT: bne 0, .LBB304_1
; PPC64LE-NEXT: .LBB304_3: ; PPC64LE-NEXT: .LBB304_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw umax ptr %ptr, i8 %val seq_cst %ret = atomicrmw umax ptr %ptr, i8 %val seq_cst
ret i8 %ret ret i8 %ret
} }
define i16 @test305(ptr %ptr, i16 %val) { define i16 @test305(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test305: ; PPC64LE-LABEL: test305:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE-NEXT: .LBB308_1: ; PPC64LE-NEXT: .LBB308_1:
; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: cmplw 5, 4 ; PPC64LE-NEXT: cmplw 5, 4
; PPC64LE-NEXT: bgt 0, .LBB308_3 ; PPC64LE-NEXT: bgt 0, .LBB308_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: sthcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB308_1 ; PPC64LE-NEXT: bne 0, .LBB308_1
; PPC64LE-NEXT: .LBB308_3: ; PPC64LE-NEXT: .LBB308_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw umax ptr %ptr, i16 %val acq_rel %ret = atomicrmw umax ptr %ptr, i16 %val acq_rel
ret i16 %ret ret i16 %ret
} }
define i16 @test309(ptr %ptr, i16 %val) { define i16 @test309(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test309: ; PPC64LE-LABEL: test309:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB309_1: ; PPC64LE-NEXT: .LBB309_1:
; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: cmplw 5, 4 ; PPC64LE-NEXT: cmplw 5, 4
; PPC64LE-NEXT: bgt 0, .LBB309_3 ; PPC64LE-NEXT: bgt 0, .LBB309_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: sthcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB309_1 ; PPC64LE-NEXT: bne 0, .LBB309_1
; PPC64LE-NEXT: .LBB309_3: ; PPC64LE-NEXT: .LBB309_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw umax ptr %ptr, i16 %val seq_cst %ret = atomicrmw umax ptr %ptr, i16 %val seq_cst
ret i16 %ret ret i16 %ret
} }
define i32 @test310(ptr %ptr, i32 %val) { define i32 @test310(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test310: ; PPC64LE-LABEL: test310:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE-NEXT: .LBB313_1: ; PPC64LE-NEXT: .LBB313_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: cmplw 5, 4 ; PPC64LE-NEXT: cmplw 5, 4
; PPC64LE-NEXT: bgt 0, .LBB313_3 ; PPC64LE-NEXT: bgt 0, .LBB313_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB313_1 ; PPC64LE-NEXT: bne 0, .LBB313_1
; PPC64LE-NEXT: .LBB313_3: ; PPC64LE-NEXT: .LBB313_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw umax ptr %ptr, i32 %val acq_rel %ret = atomicrmw umax ptr %ptr, i32 %val acq_rel
ret i32 %ret ret i32 %ret
} }
define i32 @test314(ptr %ptr, i32 %val) { define i32 @test314(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test314: ; PPC64LE-LABEL: test314:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB314_1: ; PPC64LE-NEXT: .LBB314_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: cmplw 5, 4 ; PPC64LE-NEXT: cmplw 5, 4
; PPC64LE-NEXT: bgt 0, .LBB314_3 ; PPC64LE-NEXT: bgt 0, .LBB314_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB314_1 ; PPC64LE-NEXT: bne 0, .LBB314_1
; PPC64LE-NEXT: .LBB314_3: ; PPC64LE-NEXT: .LBB314_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw umax ptr %ptr, i32 %val seq_cst %ret = atomicrmw umax ptr %ptr, i32 %val seq_cst
ret i32 %ret ret i32 %ret
} }
define i64 @test315(ptr %ptr, i64 %val) { define i64 @test315(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test315: ; PPC64LE-LABEL: test315:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE-NEXT: .LBB318_1: ; PPC64LE-NEXT: .LBB318_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: cmpld 5, 4 ; PPC64LE-NEXT: cmpld 5, 4
; PPC64LE-NEXT: bgt 0, .LBB318_3 ; PPC64LE-NEXT: bgt 0, .LBB318_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB318_1 ; PPC64LE-NEXT: bne 0, .LBB318_1
; PPC64LE-NEXT: .LBB318_3: ; PPC64LE-NEXT: .LBB318_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw umax ptr %ptr, i64 %val acq_rel %ret = atomicrmw umax ptr %ptr, i64 %val acq_rel
ret i64 %ret ret i64 %ret
} }
define i64 @test319(ptr %ptr, i64 %val) { define i64 @test319(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test319: ; PPC64LE-LABEL: test319:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB319_1: ; PPC64LE-NEXT: .LBB319_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: cmpld 5, 4 ; PPC64LE-NEXT: cmpld 5, 4
; PPC64LE-NEXT: bgt 0, .LBB319_3 ; PPC64LE-NEXT: bgt 0, .LBB319_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB319_1 ; PPC64LE-NEXT: bne 0, .LBB319_1
; PPC64LE-NEXT: .LBB319_3: ; PPC64LE-NEXT: .LBB319_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw umax ptr %ptr, i64 %val seq_cst %ret = atomicrmw umax ptr %ptr, i64 %val seq_cst
ret i64 %ret ret i64 %ret
} }
define i8 @test320(ptr %ptr, i8 %val) { define i8 @test320(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test320: ; PPC64LE-LABEL: test320:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE-NEXT: .LBB323_1: ; PPC64LE-NEXT: .LBB323_1:
; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: cmplw 5, 4 ; PPC64LE-NEXT: cmplw 5, 4
; PPC64LE-NEXT: blt 0, .LBB323_3 ; PPC64LE-NEXT: blt 0, .LBB323_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: stbcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB323_1 ; PPC64LE-NEXT: bne 0, .LBB323_1
; PPC64LE-NEXT: .LBB323_3: ; PPC64LE-NEXT: .LBB323_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw umin ptr %ptr, i8 %val acq_rel %ret = atomicrmw umin ptr %ptr, i8 %val acq_rel
ret i8 %ret ret i8 %ret
} }
define i8 @test324(ptr %ptr, i8 %val) { define i8 @test324(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test324: ; PPC64LE-LABEL: test324:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB324_1: ; PPC64LE-NEXT: .LBB324_1:
; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: cmplw 5, 4 ; PPC64LE-NEXT: cmplw 5, 4
; PPC64LE-NEXT: blt 0, .LBB324_3 ; PPC64LE-NEXT: blt 0, .LBB324_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: stbcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB324_1 ; PPC64LE-NEXT: bne 0, .LBB324_1
; PPC64LE-NEXT: .LBB324_3: ; PPC64LE-NEXT: .LBB324_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw umin ptr %ptr, i8 %val seq_cst %ret = atomicrmw umin ptr %ptr, i8 %val seq_cst
ret i8 %ret ret i8 %ret
} }
define i16 @test325(ptr %ptr, i16 %val) { define i16 @test325(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test325: ; PPC64LE-LABEL: test325:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE-NEXT: .LBB328_1: ; PPC64LE-NEXT: .LBB328_1:
; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: cmplw 5, 4 ; PPC64LE-NEXT: cmplw 5, 4
; PPC64LE-NEXT: blt 0, .LBB328_3 ; PPC64LE-NEXT: blt 0, .LBB328_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: sthcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB328_1 ; PPC64LE-NEXT: bne 0, .LBB328_1
; PPC64LE-NEXT: .LBB328_3: ; PPC64LE-NEXT: .LBB328_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw umin ptr %ptr, i16 %val acq_rel %ret = atomicrmw umin ptr %ptr, i16 %val acq_rel
ret i16 %ret ret i16 %ret
} }
define i16 @test329(ptr %ptr, i16 %val) { define i16 @test329(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test329: ; PPC64LE-LABEL: test329:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB329_1: ; PPC64LE-NEXT: .LBB329_1:
; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: cmplw 5, 4 ; PPC64LE-NEXT: cmplw 5, 4
; PPC64LE-NEXT: blt 0, .LBB329_3 ; PPC64LE-NEXT: blt 0, .LBB329_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: sthcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB329_1 ; PPC64LE-NEXT: bne 0, .LBB329_1
; PPC64LE-NEXT: .LBB329_3: ; PPC64LE-NEXT: .LBB329_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw umin ptr %ptr, i16 %val seq_cst %ret = atomicrmw umin ptr %ptr, i16 %val seq_cst
ret i16 %ret ret i16 %ret
} }
define i32 @test330(ptr %ptr, i32 %val) { define i32 @test330(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test330: ; PPC64LE-LABEL: test330:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE-NEXT: .LBB333_1: ; PPC64LE-NEXT: .LBB333_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: cmplw 5, 4 ; PPC64LE-NEXT: cmplw 5, 4
; PPC64LE-NEXT: blt 0, .LBB333_3 ; PPC64LE-NEXT: blt 0, .LBB333_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB333_1 ; PPC64LE-NEXT: bne 0, .LBB333_1
; PPC64LE-NEXT: .LBB333_3: ; PPC64LE-NEXT: .LBB333_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw umin ptr %ptr, i32 %val acq_rel %ret = atomicrmw umin ptr %ptr, i32 %val acq_rel
ret i32 %ret ret i32 %ret
} }
define i32 @test334(ptr %ptr, i32 %val) { define i32 @test334(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test334: ; PPC64LE-LABEL: test334:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB334_1: ; PPC64LE-NEXT: .LBB334_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: cmplw 5, 4 ; PPC64LE-NEXT: cmplw 5, 4
; PPC64LE-NEXT: blt 0, .LBB334_3 ; PPC64LE-NEXT: blt 0, .LBB334_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB334_1 ; PPC64LE-NEXT: bne 0, .LBB334_1
; PPC64LE-NEXT: .LBB334_3: ; PPC64LE-NEXT: .LBB334_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw umin ptr %ptr, i32 %val seq_cst %ret = atomicrmw umin ptr %ptr, i32 %val seq_cst
ret i32 %ret ret i32 %ret
} }
define i64 @test335(ptr %ptr, i64 %val) { define i64 @test335(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test335: ; PPC64LE-LABEL: test335:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE-NEXT: .LBB338_1: ; PPC64LE-NEXT: .LBB338_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: cmpld 5, 4 ; PPC64LE-NEXT: cmpld 5, 4
; PPC64LE-NEXT: blt 0, .LBB338_3 ; PPC64LE-NEXT: blt 0, .LBB338_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB338_1 ; PPC64LE-NEXT: bne 0, .LBB338_1
; PPC64LE-NEXT: .LBB338_3: ; PPC64LE-NEXT: .LBB338_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw umin ptr %ptr, i64 %val acq_rel %ret = atomicrmw umin ptr %ptr, i64 %val acq_rel
ret i64 %ret ret i64 %ret
} }
define i64 @test339(ptr %ptr, i64 %val) { define i64 @test339(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test339: ; PPC64LE-LABEL: test339:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB339_1: ; PPC64LE-NEXT: .LBB339_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: cmpld 5, 4 ; PPC64LE-NEXT: cmpld 5, 4
; PPC64LE-NEXT: blt 0, .LBB339_3 ; PPC64LE-NEXT: blt 0, .LBB339_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB339_1 ; PPC64LE-NEXT: bne 0, .LBB339_1
; PPC64LE-NEXT: .LBB339_3: ; PPC64LE-NEXT: .LBB339_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw umin ptr %ptr, i64 %val seq_cst %ret = atomicrmw umin ptr %ptr, i64 %val seq_cst
ret i64 %ret ret i64 %ret
} }
define i8 @test340(ptr %ptr, i8 %val) { define i8 @test340(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test340: ; PPC64LE-LABEL: test340:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE-LABEL: test343: ; PPC64LE-LABEL: test343:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB343_1: ; PPC64LE-NEXT: .LBB343_1:
; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: stbcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB343_1 ; PPC64LE-NEXT: bne 0, .LBB343_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw xchg ptr %ptr, i8 %val syncscope("singlethread") acq_rel %ret = atomicrmw xchg ptr %ptr, i8 %val syncscope("singlethread") acq_rel
ret i8 %ret ret i8 %ret
} }
define i8 @test344(ptr %ptr, i8 %val) { define i8 @test344(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test344: ; PPC64LE-LABEL: test344:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB344_1: ; PPC64LE-NEXT: .LBB344_1:
; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: stbcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB344_1 ; PPC64LE-NEXT: bne 0, .LBB344_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw xchg ptr %ptr, i8 %val syncscope("singlethread") seq_cst %ret = atomicrmw xchg ptr %ptr, i8 %val syncscope("singlethread") seq_cst
ret i8 %ret ret i8 %ret
} }
define i16 @test345(ptr %ptr, i16 %val) { define i16 @test345(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test345: ; PPC64LE-LABEL: test345:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE-LABEL: test348: ; PPC64LE-LABEL: test348:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB348_1: ; PPC64LE-NEXT: .LBB348_1:
; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: sthcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB348_1 ; PPC64LE-NEXT: bne 0, .LBB348_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw xchg ptr %ptr, i16 %val syncscope("singlethread") acq_rel %ret = atomicrmw xchg ptr %ptr, i16 %val syncscope("singlethread") acq_rel
ret i16 %ret ret i16 %ret
} }
define i16 @test349(ptr %ptr, i16 %val) { define i16 @test349(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test349: ; PPC64LE-LABEL: test349:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB349_1: ; PPC64LE-NEXT: .LBB349_1:
; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: sthcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB349_1 ; PPC64LE-NEXT: bne 0, .LBB349_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw xchg ptr %ptr, i16 %val syncscope("singlethread") seq_cst %ret = atomicrmw xchg ptr %ptr, i16 %val syncscope("singlethread") seq_cst
ret i16 %ret ret i16 %ret
} }
define i32 @test350(ptr %ptr, i32 %val) { define i32 @test350(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test350: ; PPC64LE-LABEL: test350:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE-LABEL: test353: ; PPC64LE-LABEL: test353:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB353_1: ; PPC64LE-NEXT: .LBB353_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB353_1 ; PPC64LE-NEXT: bne 0, .LBB353_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw xchg ptr %ptr, i32 %val syncscope("singlethread") acq_rel %ret = atomicrmw xchg ptr %ptr, i32 %val syncscope("singlethread") acq_rel
ret i32 %ret ret i32 %ret
} }
define i32 @test354(ptr %ptr, i32 %val) { define i32 @test354(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test354: ; PPC64LE-LABEL: test354:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB354_1: ; PPC64LE-NEXT: .LBB354_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB354_1 ; PPC64LE-NEXT: bne 0, .LBB354_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw xchg ptr %ptr, i32 %val syncscope("singlethread") seq_cst %ret = atomicrmw xchg ptr %ptr, i32 %val syncscope("singlethread") seq_cst
ret i32 %ret ret i32 %ret
} }
define i64 @test355(ptr %ptr, i64 %val) { define i64 @test355(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test355: ; PPC64LE-LABEL: test355:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE-LABEL: test358: ; PPC64LE-LABEL: test358:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB358_1: ; PPC64LE-NEXT: .LBB358_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB358_1 ; PPC64LE-NEXT: bne 0, .LBB358_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw xchg ptr %ptr, i64 %val syncscope("singlethread") acq_rel %ret = atomicrmw xchg ptr %ptr, i64 %val syncscope("singlethread") acq_rel
ret i64 %ret ret i64 %ret
} }
define i64 @test359(ptr %ptr, i64 %val) { define i64 @test359(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test359: ; PPC64LE-LABEL: test359:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB359_1: ; PPC64LE-NEXT: .LBB359_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB359_1 ; PPC64LE-NEXT: bne 0, .LBB359_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw xchg ptr %ptr, i64 %val syncscope("singlethread") seq_cst %ret = atomicrmw xchg ptr %ptr, i64 %val syncscope("singlethread") seq_cst
ret i64 %ret ret i64 %ret
} }
define i8 @test360(ptr %ptr, i8 %val) { define i8 @test360(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test360: ; PPC64LE-LABEL: test360:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB363_1: ; PPC64LE-NEXT: .LBB363_1:
; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: add 6, 4, 5
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB363_1 ; PPC64LE-NEXT: bne 0, .LBB363_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw add ptr %ptr, i8 %val syncscope("singlethread") acq_rel %ret = atomicrmw add ptr %ptr, i8 %val syncscope("singlethread") acq_rel
ret i8 %ret ret i8 %ret
} }
define i8 @test364(ptr %ptr, i8 %val) { define i8 @test364(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test364: ; PPC64LE-LABEL: test364:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB364_1: ; PPC64LE-NEXT: .LBB364_1:
; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: add 6, 4, 5
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB364_1 ; PPC64LE-NEXT: bne 0, .LBB364_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw add ptr %ptr, i8 %val syncscope("singlethread") seq_cst %ret = atomicrmw add ptr %ptr, i8 %val syncscope("singlethread") seq_cst
ret i8 %ret ret i8 %ret
} }
define i16 @test365(ptr %ptr, i16 %val) { define i16 @test365(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test365: ; PPC64LE-LABEL: test365:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB368_1: ; PPC64LE-NEXT: .LBB368_1:
; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: add 6, 4, 5
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB368_1 ; PPC64LE-NEXT: bne 0, .LBB368_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw add ptr %ptr, i16 %val syncscope("singlethread") acq_rel %ret = atomicrmw add ptr %ptr, i16 %val syncscope("singlethread") acq_rel
ret i16 %ret ret i16 %ret
} }
define i16 @test369(ptr %ptr, i16 %val) { define i16 @test369(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test369: ; PPC64LE-LABEL: test369:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB369_1: ; PPC64LE-NEXT: .LBB369_1:
; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: add 6, 4, 5
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB369_1 ; PPC64LE-NEXT: bne 0, .LBB369_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw add ptr %ptr, i16 %val syncscope("singlethread") seq_cst %ret = atomicrmw add ptr %ptr, i16 %val syncscope("singlethread") seq_cst
ret i16 %ret ret i16 %ret
} }
define i32 @test370(ptr %ptr, i32 %val) { define i32 @test370(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test370: ; PPC64LE-LABEL: test370:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB373_1: ; PPC64LE-NEXT: .LBB373_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: add 6, 4, 5
; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB373_1 ; PPC64LE-NEXT: bne 0, .LBB373_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw add ptr %ptr, i32 %val syncscope("singlethread") acq_rel %ret = atomicrmw add ptr %ptr, i32 %val syncscope("singlethread") acq_rel
ret i32 %ret ret i32 %ret
} }
define i32 @test374(ptr %ptr, i32 %val) { define i32 @test374(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test374: ; PPC64LE-LABEL: test374:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB374_1: ; PPC64LE-NEXT: .LBB374_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: add 6, 4, 5
; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB374_1 ; PPC64LE-NEXT: bne 0, .LBB374_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw add ptr %ptr, i32 %val syncscope("singlethread") seq_cst %ret = atomicrmw add ptr %ptr, i32 %val syncscope("singlethread") seq_cst
ret i32 %ret ret i32 %ret
} }
define i64 @test375(ptr %ptr, i64 %val) { define i64 @test375(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test375: ; PPC64LE-LABEL: test375:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB378_1: ; PPC64LE-NEXT: .LBB378_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: add 6, 4, 5
; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB378_1 ; PPC64LE-NEXT: bne 0, .LBB378_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw add ptr %ptr, i64 %val syncscope("singlethread") acq_rel %ret = atomicrmw add ptr %ptr, i64 %val syncscope("singlethread") acq_rel
ret i64 %ret ret i64 %ret
} }
define i64 @test379(ptr %ptr, i64 %val) { define i64 @test379(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test379: ; PPC64LE-LABEL: test379:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB379_1: ; PPC64LE-NEXT: .LBB379_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: add 6, 4, 5
; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB379_1 ; PPC64LE-NEXT: bne 0, .LBB379_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw add ptr %ptr, i64 %val syncscope("singlethread") seq_cst %ret = atomicrmw add ptr %ptr, i64 %val syncscope("singlethread") seq_cst
ret i64 %ret ret i64 %ret
} }
define i8 @test380(ptr %ptr, i8 %val) { define i8 @test380(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test380: ; PPC64LE-LABEL: test380:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB383_1: ; PPC64LE-NEXT: .LBB383_1:
; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: sub 6, 5, 4
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB383_1 ; PPC64LE-NEXT: bne 0, .LBB383_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw sub ptr %ptr, i8 %val syncscope("singlethread") acq_rel %ret = atomicrmw sub ptr %ptr, i8 %val syncscope("singlethread") acq_rel
ret i8 %ret ret i8 %ret
} }
define i8 @test384(ptr %ptr, i8 %val) { define i8 @test384(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test384: ; PPC64LE-LABEL: test384:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB384_1: ; PPC64LE-NEXT: .LBB384_1:
; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: sub 6, 5, 4
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB384_1 ; PPC64LE-NEXT: bne 0, .LBB384_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw sub ptr %ptr, i8 %val syncscope("singlethread") seq_cst %ret = atomicrmw sub ptr %ptr, i8 %val syncscope("singlethread") seq_cst
ret i8 %ret ret i8 %ret
} }
define i16 @test385(ptr %ptr, i16 %val) { define i16 @test385(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test385: ; PPC64LE-LABEL: test385:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB388_1: ; PPC64LE-NEXT: .LBB388_1:
; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: sub 6, 5, 4
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB388_1 ; PPC64LE-NEXT: bne 0, .LBB388_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw sub ptr %ptr, i16 %val syncscope("singlethread") acq_rel %ret = atomicrmw sub ptr %ptr, i16 %val syncscope("singlethread") acq_rel
ret i16 %ret ret i16 %ret
} }
define i16 @test389(ptr %ptr, i16 %val) { define i16 @test389(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test389: ; PPC64LE-LABEL: test389:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB389_1: ; PPC64LE-NEXT: .LBB389_1:
; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: sub 6, 5, 4
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB389_1 ; PPC64LE-NEXT: bne 0, .LBB389_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw sub ptr %ptr, i16 %val syncscope("singlethread") seq_cst %ret = atomicrmw sub ptr %ptr, i16 %val syncscope("singlethread") seq_cst
ret i16 %ret ret i16 %ret
} }
define i32 @test390(ptr %ptr, i32 %val) { define i32 @test390(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test390: ; PPC64LE-LABEL: test390:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB393_1: ; PPC64LE-NEXT: .LBB393_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: sub 6, 5, 4
; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB393_1 ; PPC64LE-NEXT: bne 0, .LBB393_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw sub ptr %ptr, i32 %val syncscope("singlethread") acq_rel %ret = atomicrmw sub ptr %ptr, i32 %val syncscope("singlethread") acq_rel
ret i32 %ret ret i32 %ret
} }
define i32 @test394(ptr %ptr, i32 %val) { define i32 @test394(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test394: ; PPC64LE-LABEL: test394:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB394_1: ; PPC64LE-NEXT: .LBB394_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: sub 6, 5, 4
; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB394_1 ; PPC64LE-NEXT: bne 0, .LBB394_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw sub ptr %ptr, i32 %val syncscope("singlethread") seq_cst %ret = atomicrmw sub ptr %ptr, i32 %val syncscope("singlethread") seq_cst
ret i32 %ret ret i32 %ret
} }
define i64 @test395(ptr %ptr, i64 %val) { define i64 @test395(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test395: ; PPC64LE-LABEL: test395:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB398_1: ; PPC64LE-NEXT: .LBB398_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: sub 6, 5, 4
; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB398_1 ; PPC64LE-NEXT: bne 0, .LBB398_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw sub ptr %ptr, i64 %val syncscope("singlethread") acq_rel %ret = atomicrmw sub ptr %ptr, i64 %val syncscope("singlethread") acq_rel
ret i64 %ret ret i64 %ret
} }
define i64 @test399(ptr %ptr, i64 %val) { define i64 @test399(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test399: ; PPC64LE-LABEL: test399:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB399_1: ; PPC64LE-NEXT: .LBB399_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: sub 6, 5, 4
; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB399_1 ; PPC64LE-NEXT: bne 0, .LBB399_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw sub ptr %ptr, i64 %val syncscope("singlethread") seq_cst %ret = atomicrmw sub ptr %ptr, i64 %val syncscope("singlethread") seq_cst
ret i64 %ret ret i64 %ret
} }
define i8 @test400(ptr %ptr, i8 %val) { define i8 @test400(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test400: ; PPC64LE-LABEL: test400:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB403_1: ; PPC64LE-NEXT: .LBB403_1:
; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: and 6, 4, 5
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB403_1 ; PPC64LE-NEXT: bne 0, .LBB403_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw and ptr %ptr, i8 %val syncscope("singlethread") acq_rel %ret = atomicrmw and ptr %ptr, i8 %val syncscope("singlethread") acq_rel
ret i8 %ret ret i8 %ret
} }
define i8 @test404(ptr %ptr, i8 %val) { define i8 @test404(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test404: ; PPC64LE-LABEL: test404:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB404_1: ; PPC64LE-NEXT: .LBB404_1:
; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: and 6, 4, 5
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB404_1 ; PPC64LE-NEXT: bne 0, .LBB404_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw and ptr %ptr, i8 %val syncscope("singlethread") seq_cst %ret = atomicrmw and ptr %ptr, i8 %val syncscope("singlethread") seq_cst
ret i8 %ret ret i8 %ret
} }
define i16 @test405(ptr %ptr, i16 %val) { define i16 @test405(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test405: ; PPC64LE-LABEL: test405:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB408_1: ; PPC64LE-NEXT: .LBB408_1:
; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: and 6, 4, 5
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB408_1 ; PPC64LE-NEXT: bne 0, .LBB408_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw and ptr %ptr, i16 %val syncscope("singlethread") acq_rel %ret = atomicrmw and ptr %ptr, i16 %val syncscope("singlethread") acq_rel
ret i16 %ret ret i16 %ret
} }
define i16 @test409(ptr %ptr, i16 %val) { define i16 @test409(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test409: ; PPC64LE-LABEL: test409:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB409_1: ; PPC64LE-NEXT: .LBB409_1:
; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: and 6, 4, 5
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB409_1 ; PPC64LE-NEXT: bne 0, .LBB409_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw and ptr %ptr, i16 %val syncscope("singlethread") seq_cst %ret = atomicrmw and ptr %ptr, i16 %val syncscope("singlethread") seq_cst
ret i16 %ret ret i16 %ret
} }
define i32 @test410(ptr %ptr, i32 %val) { define i32 @test410(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test410: ; PPC64LE-LABEL: test410:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB413_1: ; PPC64LE-NEXT: .LBB413_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: and 6, 4, 5
; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB413_1 ; PPC64LE-NEXT: bne 0, .LBB413_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw and ptr %ptr, i32 %val syncscope("singlethread") acq_rel %ret = atomicrmw and ptr %ptr, i32 %val syncscope("singlethread") acq_rel
ret i32 %ret ret i32 %ret
} }
define i32 @test414(ptr %ptr, i32 %val) { define i32 @test414(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test414: ; PPC64LE-LABEL: test414:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB414_1: ; PPC64LE-NEXT: .LBB414_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: and 6, 4, 5
; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB414_1 ; PPC64LE-NEXT: bne 0, .LBB414_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw and ptr %ptr, i32 %val syncscope("singlethread") seq_cst %ret = atomicrmw and ptr %ptr, i32 %val syncscope("singlethread") seq_cst
ret i32 %ret ret i32 %ret
} }
define i64 @test415(ptr %ptr, i64 %val) { define i64 @test415(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test415: ; PPC64LE-LABEL: test415:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB418_1: ; PPC64LE-NEXT: .LBB418_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: and 6, 4, 5
; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB418_1 ; PPC64LE-NEXT: bne 0, .LBB418_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw and ptr %ptr, i64 %val syncscope("singlethread") acq_rel %ret = atomicrmw and ptr %ptr, i64 %val syncscope("singlethread") acq_rel
ret i64 %ret ret i64 %ret
} }
define i64 @test419(ptr %ptr, i64 %val) { define i64 @test419(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test419: ; PPC64LE-LABEL: test419:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB419_1: ; PPC64LE-NEXT: .LBB419_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: and 6, 4, 5
; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB419_1 ; PPC64LE-NEXT: bne 0, .LBB419_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw and ptr %ptr, i64 %val syncscope("singlethread") seq_cst %ret = atomicrmw and ptr %ptr, i64 %val syncscope("singlethread") seq_cst
ret i64 %ret ret i64 %ret
} }
define i8 @test420(ptr %ptr, i8 %val) { define i8 @test420(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test420: ; PPC64LE-LABEL: test420:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB423_1: ; PPC64LE-NEXT: .LBB423_1:
; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: nand 6, 4, 5
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB423_1 ; PPC64LE-NEXT: bne 0, .LBB423_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw nand ptr %ptr, i8 %val syncscope("singlethread") acq_rel %ret = atomicrmw nand ptr %ptr, i8 %val syncscope("singlethread") acq_rel
ret i8 %ret ret i8 %ret
} }
define i8 @test424(ptr %ptr, i8 %val) { define i8 @test424(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test424: ; PPC64LE-LABEL: test424:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB424_1: ; PPC64LE-NEXT: .LBB424_1:
; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: nand 6, 4, 5
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB424_1 ; PPC64LE-NEXT: bne 0, .LBB424_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw nand ptr %ptr, i8 %val syncscope("singlethread") seq_cst %ret = atomicrmw nand ptr %ptr, i8 %val syncscope("singlethread") seq_cst
ret i8 %ret ret i8 %ret
} }
define i16 @test425(ptr %ptr, i16 %val) { define i16 @test425(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test425: ; PPC64LE-LABEL: test425:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB428_1: ; PPC64LE-NEXT: .LBB428_1:
; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: nand 6, 4, 5
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB428_1 ; PPC64LE-NEXT: bne 0, .LBB428_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw nand ptr %ptr, i16 %val syncscope("singlethread") acq_rel %ret = atomicrmw nand ptr %ptr, i16 %val syncscope("singlethread") acq_rel
ret i16 %ret ret i16 %ret
} }
define i16 @test429(ptr %ptr, i16 %val) { define i16 @test429(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test429: ; PPC64LE-LABEL: test429:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB429_1: ; PPC64LE-NEXT: .LBB429_1:
; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: nand 6, 4, 5
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB429_1 ; PPC64LE-NEXT: bne 0, .LBB429_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw nand ptr %ptr, i16 %val syncscope("singlethread") seq_cst %ret = atomicrmw nand ptr %ptr, i16 %val syncscope("singlethread") seq_cst
ret i16 %ret ret i16 %ret
} }
define i32 @test430(ptr %ptr, i32 %val) { define i32 @test430(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test430: ; PPC64LE-LABEL: test430:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB433_1: ; PPC64LE-NEXT: .LBB433_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: nand 6, 4, 5
; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB433_1 ; PPC64LE-NEXT: bne 0, .LBB433_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw nand ptr %ptr, i32 %val syncscope("singlethread") acq_rel %ret = atomicrmw nand ptr %ptr, i32 %val syncscope("singlethread") acq_rel
ret i32 %ret ret i32 %ret
} }
define i32 @test434(ptr %ptr, i32 %val) { define i32 @test434(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test434: ; PPC64LE-LABEL: test434:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB434_1: ; PPC64LE-NEXT: .LBB434_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: nand 6, 4, 5
; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB434_1 ; PPC64LE-NEXT: bne 0, .LBB434_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw nand ptr %ptr, i32 %val syncscope("singlethread") seq_cst %ret = atomicrmw nand ptr %ptr, i32 %val syncscope("singlethread") seq_cst
ret i32 %ret ret i32 %ret
} }
define i64 @test435(ptr %ptr, i64 %val) { define i64 @test435(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test435: ; PPC64LE-LABEL: test435:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB438_1: ; PPC64LE-NEXT: .LBB438_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: nand 6, 4, 5
; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB438_1 ; PPC64LE-NEXT: bne 0, .LBB438_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw nand ptr %ptr, i64 %val syncscope("singlethread") acq_rel %ret = atomicrmw nand ptr %ptr, i64 %val syncscope("singlethread") acq_rel
ret i64 %ret ret i64 %ret
} }
define i64 @test439(ptr %ptr, i64 %val) { define i64 @test439(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test439: ; PPC64LE-LABEL: test439:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB439_1: ; PPC64LE-NEXT: .LBB439_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: nand 6, 4, 5
; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB439_1 ; PPC64LE-NEXT: bne 0, .LBB439_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw nand ptr %ptr, i64 %val syncscope("singlethread") seq_cst %ret = atomicrmw nand ptr %ptr, i64 %val syncscope("singlethread") seq_cst
ret i64 %ret ret i64 %ret
} }
define i8 @test440(ptr %ptr, i8 %val) { define i8 @test440(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test440: ; PPC64LE-LABEL: test440:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB443_1: ; PPC64LE-NEXT: .LBB443_1:
; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: or 6, 4, 5
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB443_1 ; PPC64LE-NEXT: bne 0, .LBB443_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw or ptr %ptr, i8 %val syncscope("singlethread") acq_rel %ret = atomicrmw or ptr %ptr, i8 %val syncscope("singlethread") acq_rel
ret i8 %ret ret i8 %ret
} }
define i8 @test444(ptr %ptr, i8 %val) { define i8 @test444(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test444: ; PPC64LE-LABEL: test444:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB444_1: ; PPC64LE-NEXT: .LBB444_1:
; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: or 6, 4, 5
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB444_1 ; PPC64LE-NEXT: bne 0, .LBB444_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw or ptr %ptr, i8 %val syncscope("singlethread") seq_cst %ret = atomicrmw or ptr %ptr, i8 %val syncscope("singlethread") seq_cst
ret i8 %ret ret i8 %ret
} }
define i16 @test445(ptr %ptr, i16 %val) { define i16 @test445(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test445: ; PPC64LE-LABEL: test445:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB448_1: ; PPC64LE-NEXT: .LBB448_1:
; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: or 6, 4, 5
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB448_1 ; PPC64LE-NEXT: bne 0, .LBB448_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw or ptr %ptr, i16 %val syncscope("singlethread") acq_rel %ret = atomicrmw or ptr %ptr, i16 %val syncscope("singlethread") acq_rel
ret i16 %ret ret i16 %ret
} }
define i16 @test449(ptr %ptr, i16 %val) { define i16 @test449(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test449: ; PPC64LE-LABEL: test449:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB449_1: ; PPC64LE-NEXT: .LBB449_1:
; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: or 6, 4, 5
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB449_1 ; PPC64LE-NEXT: bne 0, .LBB449_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw or ptr %ptr, i16 %val syncscope("singlethread") seq_cst %ret = atomicrmw or ptr %ptr, i16 %val syncscope("singlethread") seq_cst
ret i16 %ret ret i16 %ret
} }
define i32 @test450(ptr %ptr, i32 %val) { define i32 @test450(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test450: ; PPC64LE-LABEL: test450:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB453_1: ; PPC64LE-NEXT: .LBB453_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: or 6, 4, 5
; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB453_1 ; PPC64LE-NEXT: bne 0, .LBB453_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw or ptr %ptr, i32 %val syncscope("singlethread") acq_rel %ret = atomicrmw or ptr %ptr, i32 %val syncscope("singlethread") acq_rel
ret i32 %ret ret i32 %ret
} }
define i32 @test454(ptr %ptr, i32 %val) { define i32 @test454(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test454: ; PPC64LE-LABEL: test454:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB454_1: ; PPC64LE-NEXT: .LBB454_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: or 6, 4, 5
; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB454_1 ; PPC64LE-NEXT: bne 0, .LBB454_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw or ptr %ptr, i32 %val syncscope("singlethread") seq_cst %ret = atomicrmw or ptr %ptr, i32 %val syncscope("singlethread") seq_cst
ret i32 %ret ret i32 %ret
} }
define i64 @test455(ptr %ptr, i64 %val) { define i64 @test455(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test455: ; PPC64LE-LABEL: test455:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB458_1: ; PPC64LE-NEXT: .LBB458_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: or 6, 4, 5
; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB458_1 ; PPC64LE-NEXT: bne 0, .LBB458_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw or ptr %ptr, i64 %val syncscope("singlethread") acq_rel %ret = atomicrmw or ptr %ptr, i64 %val syncscope("singlethread") acq_rel
ret i64 %ret ret i64 %ret
} }
define i64 @test459(ptr %ptr, i64 %val) { define i64 @test459(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test459: ; PPC64LE-LABEL: test459:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB459_1: ; PPC64LE-NEXT: .LBB459_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: or 6, 4, 5
; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB459_1 ; PPC64LE-NEXT: bne 0, .LBB459_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw or ptr %ptr, i64 %val syncscope("singlethread") seq_cst %ret = atomicrmw or ptr %ptr, i64 %val syncscope("singlethread") seq_cst
ret i64 %ret ret i64 %ret
} }
define i8 @test460(ptr %ptr, i8 %val) { define i8 @test460(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test460: ; PPC64LE-LABEL: test460:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB463_1: ; PPC64LE-NEXT: .LBB463_1:
; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: xor 6, 4, 5
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB463_1 ; PPC64LE-NEXT: bne 0, .LBB463_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw xor ptr %ptr, i8 %val syncscope("singlethread") acq_rel %ret = atomicrmw xor ptr %ptr, i8 %val syncscope("singlethread") acq_rel
ret i8 %ret ret i8 %ret
} }
define i8 @test464(ptr %ptr, i8 %val) { define i8 @test464(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test464: ; PPC64LE-LABEL: test464:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB464_1: ; PPC64LE-NEXT: .LBB464_1:
; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: xor 6, 4, 5
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB464_1 ; PPC64LE-NEXT: bne 0, .LBB464_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw xor ptr %ptr, i8 %val syncscope("singlethread") seq_cst %ret = atomicrmw xor ptr %ptr, i8 %val syncscope("singlethread") seq_cst
ret i8 %ret ret i8 %ret
} }
define i16 @test465(ptr %ptr, i16 %val) { define i16 @test465(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test465: ; PPC64LE-LABEL: test465:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB468_1: ; PPC64LE-NEXT: .LBB468_1:
; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: xor 6, 4, 5
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB468_1 ; PPC64LE-NEXT: bne 0, .LBB468_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw xor ptr %ptr, i16 %val syncscope("singlethread") acq_rel %ret = atomicrmw xor ptr %ptr, i16 %val syncscope("singlethread") acq_rel
ret i16 %ret ret i16 %ret
} }
define i16 @test469(ptr %ptr, i16 %val) { define i16 @test469(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test469: ; PPC64LE-LABEL: test469:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB469_1: ; PPC64LE-NEXT: .LBB469_1:
; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: xor 6, 4, 5
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB469_1 ; PPC64LE-NEXT: bne 0, .LBB469_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw xor ptr %ptr, i16 %val syncscope("singlethread") seq_cst %ret = atomicrmw xor ptr %ptr, i16 %val syncscope("singlethread") seq_cst
ret i16 %ret ret i16 %ret
} }
define i32 @test470(ptr %ptr, i32 %val) { define i32 @test470(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test470: ; PPC64LE-LABEL: test470:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB473_1: ; PPC64LE-NEXT: .LBB473_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: xor 6, 4, 5
; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB473_1 ; PPC64LE-NEXT: bne 0, .LBB473_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw xor ptr %ptr, i32 %val syncscope("singlethread") acq_rel %ret = atomicrmw xor ptr %ptr, i32 %val syncscope("singlethread") acq_rel
ret i32 %ret ret i32 %ret
} }
define i32 @test474(ptr %ptr, i32 %val) { define i32 @test474(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test474: ; PPC64LE-LABEL: test474:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB474_1: ; PPC64LE-NEXT: .LBB474_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: xor 6, 4, 5
; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB474_1 ; PPC64LE-NEXT: bne 0, .LBB474_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw xor ptr %ptr, i32 %val syncscope("singlethread") seq_cst %ret = atomicrmw xor ptr %ptr, i32 %val syncscope("singlethread") seq_cst
ret i32 %ret ret i32 %ret
} }
define i64 @test475(ptr %ptr, i64 %val) { define i64 @test475(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test475: ; PPC64LE-LABEL: test475:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB478_1: ; PPC64LE-NEXT: .LBB478_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: xor 6, 4, 5
; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB478_1 ; PPC64LE-NEXT: bne 0, .LBB478_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw xor ptr %ptr, i64 %val syncscope("singlethread") acq_rel %ret = atomicrmw xor ptr %ptr, i64 %val syncscope("singlethread") acq_rel
ret i64 %ret ret i64 %ret
} }
define i64 @test479(ptr %ptr, i64 %val) { define i64 @test479(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test479: ; PPC64LE-LABEL: test479:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB479_1: ; PPC64LE-NEXT: .LBB479_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: xor 6, 4, 5
; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB479_1 ; PPC64LE-NEXT: bne 0, .LBB479_1
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw xor ptr %ptr, i64 %val syncscope("singlethread") seq_cst %ret = atomicrmw xor ptr %ptr, i64 %val syncscope("singlethread") seq_cst
ret i64 %ret ret i64 %ret
} }
define i8 @test480(ptr %ptr, i8 %val) { define i8 @test480(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test480: ; PPC64LE-LABEL: test480:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE-NEXT: lbarx 4, 0, 3 ; PPC64LE-NEXT: lbarx 4, 0, 3
; PPC64LE-NEXT: extsb 6, 4 ; PPC64LE-NEXT: extsb 6, 4
; PPC64LE-NEXT: cmpw 6, 5 ; PPC64LE-NEXT: cmpw 6, 5
; PPC64LE-NEXT: bgt 0, .LBB481_3 ; PPC64LE-NEXT: bgt 0, .LBB481_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB481_1 ; PPC64LE-NEXT: bne 0, .LBB481_1
; PPC64LE-NEXT: .LBB481_3: ; PPC64LE-NEXT: .LBB481_3:
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw max ptr %ptr, i8 %val syncscope("singlethread") acquire %ret = atomicrmw max ptr %ptr, i8 %val syncscope("singlethread") acquire
ret i8 %ret ret i8 %ret
} }
define i8 @test482(ptr %ptr, i8 %val) { define i8 @test482(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test482: ; PPC64LE-LABEL: test482:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: extsb 5, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: extsb 5, 4
; PPC64LE-NEXT: .LBB482_1: ; PPC64LE-NEXT: .LBB482_1:
; PPC64LE-NEXT: lbarx 4, 0, 3 ; PPC64LE-NEXT: lbarx 4, 0, 3
; PPC64LE-NEXT: extsb 6, 4 ; PPC64LE-NEXT: extsb 6, 4
; PPC64LE-NEXT: cmpw 6, 5 ; PPC64LE-NEXT: cmpw 6, 5
; PPC64LE-NEXT: bgt 0, .LBB482_3 ; PPC64LE-NEXT: bgt 0, .LBB482_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB482_1 ; PPC64LE-NEXT: bne 0, .LBB482_1
; PPC64LE-NEXT: .LBB482_3: ; PPC64LE-NEXT: .LBB482_3:
; PPC64LE-NEXT: mr 3, 4 ; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw max ptr %ptr, i8 %val syncscope("singlethread") release %ret = atomicrmw max ptr %ptr, i8 %val syncscope("singlethread") release
ret i8 %ret ret i8 %ret
} }
define i8 @test483(ptr %ptr, i8 %val) { define i8 @test483(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test483: ; PPC64LE-LABEL: test483:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: extsb 5, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: extsb 5, 4
; PPC64LE-NEXT: .LBB483_1: ; PPC64LE-NEXT: .LBB483_1:
; PPC64LE-NEXT: lbarx 4, 0, 3 ; PPC64LE-NEXT: lbarx 4, 0, 3
; PPC64LE-NEXT: extsb 6, 4 ; PPC64LE-NEXT: extsb 6, 4
; PPC64LE-NEXT: cmpw 6, 5 ; PPC64LE-NEXT: cmpw 6, 5
; PPC64LE-NEXT: bgt 0, .LBB483_3 ; PPC64LE-NEXT: bgt 0, .LBB483_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB483_1 ; PPC64LE-NEXT: bne 0, .LBB483_1
; PPC64LE-NEXT: .LBB483_3: ; PPC64LE-NEXT: .LBB483_3:
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw max ptr %ptr, i8 %val syncscope("singlethread") acq_rel %ret = atomicrmw max ptr %ptr, i8 %val syncscope("singlethread") acq_rel
ret i8 %ret ret i8 %ret
} }
define i8 @test484(ptr %ptr, i8 %val) { define i8 @test484(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test484: ; PPC64LE-LABEL: test484:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: extsb 5, 4
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: extsb 5, 4
; PPC64LE-NEXT: .LBB484_1: ; PPC64LE-NEXT: .LBB484_1:
; PPC64LE-NEXT: lbarx 4, 0, 3 ; PPC64LE-NEXT: lbarx 4, 0, 3
; PPC64LE-NEXT: extsb 6, 4 ; PPC64LE-NEXT: extsb 6, 4
; PPC64LE-NEXT: cmpw 6, 5 ; PPC64LE-NEXT: cmpw 6, 5
; PPC64LE-NEXT: bgt 0, .LBB484_3 ; PPC64LE-NEXT: bgt 0, .LBB484_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB484_1 ; PPC64LE-NEXT: bne 0, .LBB484_1
; PPC64LE-NEXT: .LBB484_3: ; PPC64LE-NEXT: .LBB484_3:
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw max ptr %ptr, i8 %val syncscope("singlethread") seq_cst %ret = atomicrmw max ptr %ptr, i8 %val syncscope("singlethread") seq_cst
ret i8 %ret ret i8 %ret
} }
define i16 @test485(ptr %ptr, i16 %val) { define i16 @test485(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test485: ; PPC64LE-LABEL: test485:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE-NEXT: lharx 4, 0, 3 ; PPC64LE-NEXT: lharx 4, 0, 3
; PPC64LE-NEXT: extsh 6, 4 ; PPC64LE-NEXT: extsh 6, 4
; PPC64LE-NEXT: cmpw 6, 5 ; PPC64LE-NEXT: cmpw 6, 5
; PPC64LE-NEXT: bgt 0, .LBB486_3 ; PPC64LE-NEXT: bgt 0, .LBB486_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB486_1 ; PPC64LE-NEXT: bne 0, .LBB486_1
; PPC64LE-NEXT: .LBB486_3: ; PPC64LE-NEXT: .LBB486_3:
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw max ptr %ptr, i16 %val syncscope("singlethread") acquire %ret = atomicrmw max ptr %ptr, i16 %val syncscope("singlethread") acquire
ret i16 %ret ret i16 %ret
} }
define i16 @test487(ptr %ptr, i16 %val) { define i16 @test487(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test487: ; PPC64LE-LABEL: test487:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: extsh 5, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: extsh 5, 4
; PPC64LE-NEXT: .LBB487_1: ; PPC64LE-NEXT: .LBB487_1:
; PPC64LE-NEXT: lharx 4, 0, 3 ; PPC64LE-NEXT: lharx 4, 0, 3
; PPC64LE-NEXT: extsh 6, 4 ; PPC64LE-NEXT: extsh 6, 4
; PPC64LE-NEXT: cmpw 6, 5 ; PPC64LE-NEXT: cmpw 6, 5
; PPC64LE-NEXT: bgt 0, .LBB487_3 ; PPC64LE-NEXT: bgt 0, .LBB487_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB487_1 ; PPC64LE-NEXT: bne 0, .LBB487_1
; PPC64LE-NEXT: .LBB487_3: ; PPC64LE-NEXT: .LBB487_3:
; PPC64LE-NEXT: mr 3, 4 ; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw max ptr %ptr, i16 %val syncscope("singlethread") release %ret = atomicrmw max ptr %ptr, i16 %val syncscope("singlethread") release
ret i16 %ret ret i16 %ret
} }
define i16 @test488(ptr %ptr, i16 %val) { define i16 @test488(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test488: ; PPC64LE-LABEL: test488:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: extsh 5, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: extsh 5, 4
; PPC64LE-NEXT: .LBB488_1: ; PPC64LE-NEXT: .LBB488_1:
; PPC64LE-NEXT: lharx 4, 0, 3 ; PPC64LE-NEXT: lharx 4, 0, 3
; PPC64LE-NEXT: extsh 6, 4 ; PPC64LE-NEXT: extsh 6, 4
; PPC64LE-NEXT: cmpw 6, 5 ; PPC64LE-NEXT: cmpw 6, 5
; PPC64LE-NEXT: bgt 0, .LBB488_3 ; PPC64LE-NEXT: bgt 0, .LBB488_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB488_1 ; PPC64LE-NEXT: bne 0, .LBB488_1
; PPC64LE-NEXT: .LBB488_3: ; PPC64LE-NEXT: .LBB488_3:
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw max ptr %ptr, i16 %val syncscope("singlethread") acq_rel %ret = atomicrmw max ptr %ptr, i16 %val syncscope("singlethread") acq_rel
ret i16 %ret ret i16 %ret
} }
define i16 @test489(ptr %ptr, i16 %val) { define i16 @test489(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test489: ; PPC64LE-LABEL: test489:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: extsh 5, 4
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: extsh 5, 4
; PPC64LE-NEXT: .LBB489_1: ; PPC64LE-NEXT: .LBB489_1:
; PPC64LE-NEXT: lharx 4, 0, 3 ; PPC64LE-NEXT: lharx 4, 0, 3
; PPC64LE-NEXT: extsh 6, 4 ; PPC64LE-NEXT: extsh 6, 4
; PPC64LE-NEXT: cmpw 6, 5 ; PPC64LE-NEXT: cmpw 6, 5
; PPC64LE-NEXT: bgt 0, .LBB489_3 ; PPC64LE-NEXT: bgt 0, .LBB489_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB489_1 ; PPC64LE-NEXT: bne 0, .LBB489_1
; PPC64LE-NEXT: .LBB489_3: ; PPC64LE-NEXT: .LBB489_3:
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw max ptr %ptr, i16 %val syncscope("singlethread") seq_cst %ret = atomicrmw max ptr %ptr, i16 %val syncscope("singlethread") seq_cst
ret i16 %ret ret i16 %ret
} }
define i32 @test490(ptr %ptr, i32 %val) { define i32 @test490(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test490: ; PPC64LE-LABEL: test490:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; PPC64LE-NEXT: .LBB493_1: ; PPC64LE-NEXT: .LBB493_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: cmpw 5, 4 ; PPC64LE-NEXT: cmpw 5, 4
; PPC64LE-NEXT: bgt 0, .LBB493_3 ; PPC64LE-NEXT: bgt 0, .LBB493_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB493_1 ; PPC64LE-NEXT: bne 0, .LBB493_1
; PPC64LE-NEXT: .LBB493_3: ; PPC64LE-NEXT: .LBB493_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw max ptr %ptr, i32 %val syncscope("singlethread") acq_rel %ret = atomicrmw max ptr %ptr, i32 %val syncscope("singlethread") acq_rel
ret i32 %ret ret i32 %ret
} }
define i32 @test494(ptr %ptr, i32 %val) { define i32 @test494(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test494: ; PPC64LE-LABEL: test494:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB494_1: ; PPC64LE-NEXT: .LBB494_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: cmpw 5, 4 ; PPC64LE-NEXT: cmpw 5, 4
; PPC64LE-NEXT: bgt 0, .LBB494_3 ; PPC64LE-NEXT: bgt 0, .LBB494_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB494_1 ; PPC64LE-NEXT: bne 0, .LBB494_1
; PPC64LE-NEXT: .LBB494_3: ; PPC64LE-NEXT: .LBB494_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw max ptr %ptr, i32 %val syncscope("singlethread") seq_cst %ret = atomicrmw max ptr %ptr, i32 %val syncscope("singlethread") seq_cst
ret i32 %ret ret i32 %ret
} }
define i64 @test495(ptr %ptr, i64 %val) { define i64 @test495(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test495: ; PPC64LE-LABEL: test495:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; PPC64LE-NEXT: .LBB498_1: ; PPC64LE-NEXT: .LBB498_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: cmpd 5, 4 ; PPC64LE-NEXT: cmpd 5, 4
; PPC64LE-NEXT: bgt 0, .LBB498_3 ; PPC64LE-NEXT: bgt 0, .LBB498_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB498_1 ; PPC64LE-NEXT: bne 0, .LBB498_1
; PPC64LE-NEXT: .LBB498_3: ; PPC64LE-NEXT: .LBB498_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw max ptr %ptr, i64 %val syncscope("singlethread") acq_rel %ret = atomicrmw max ptr %ptr, i64 %val syncscope("singlethread") acq_rel
ret i64 %ret ret i64 %ret
} }
define i64 @test499(ptr %ptr, i64 %val) { define i64 @test499(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test499: ; PPC64LE-LABEL: test499:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB499_1: ; PPC64LE-NEXT: .LBB499_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: cmpd 5, 4 ; PPC64LE-NEXT: cmpd 5, 4
; PPC64LE-NEXT: bgt 0, .LBB499_3 ; PPC64LE-NEXT: bgt 0, .LBB499_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB499_1 ; PPC64LE-NEXT: bne 0, .LBB499_1
; PPC64LE-NEXT: .LBB499_3: ; PPC64LE-NEXT: .LBB499_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw max ptr %ptr, i64 %val syncscope("singlethread") seq_cst %ret = atomicrmw max ptr %ptr, i64 %val syncscope("singlethread") seq_cst
ret i64 %ret ret i64 %ret
} }
define i8 @test500(ptr %ptr, i8 %val) { define i8 @test500(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test500: ; PPC64LE-LABEL: test500:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE-NEXT: lbarx 4, 0, 3 ; PPC64LE-NEXT: lbarx 4, 0, 3
; PPC64LE-NEXT: extsb 6, 4 ; PPC64LE-NEXT: extsb 6, 4
; PPC64LE-NEXT: cmpw 6, 5 ; PPC64LE-NEXT: cmpw 6, 5
; PPC64LE-NEXT: blt 0, .LBB501_3 ; PPC64LE-NEXT: blt 0, .LBB501_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB501_1 ; PPC64LE-NEXT: bne 0, .LBB501_1
; PPC64LE-NEXT: .LBB501_3: ; PPC64LE-NEXT: .LBB501_3:
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw min ptr %ptr, i8 %val syncscope("singlethread") acquire %ret = atomicrmw min ptr %ptr, i8 %val syncscope("singlethread") acquire
ret i8 %ret ret i8 %ret
} }
define i8 @test502(ptr %ptr, i8 %val) { define i8 @test502(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test502: ; PPC64LE-LABEL: test502:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: extsb 5, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: extsb 5, 4
; PPC64LE-NEXT: .LBB502_1: ; PPC64LE-NEXT: .LBB502_1:
; PPC64LE-NEXT: lbarx 4, 0, 3 ; PPC64LE-NEXT: lbarx 4, 0, 3
; PPC64LE-NEXT: extsb 6, 4 ; PPC64LE-NEXT: extsb 6, 4
; PPC64LE-NEXT: cmpw 6, 5 ; PPC64LE-NEXT: cmpw 6, 5
; PPC64LE-NEXT: blt 0, .LBB502_3 ; PPC64LE-NEXT: blt 0, .LBB502_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB502_1 ; PPC64LE-NEXT: bne 0, .LBB502_1
; PPC64LE-NEXT: .LBB502_3: ; PPC64LE-NEXT: .LBB502_3:
; PPC64LE-NEXT: mr 3, 4 ; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw min ptr %ptr, i8 %val syncscope("singlethread") release %ret = atomicrmw min ptr %ptr, i8 %val syncscope("singlethread") release
ret i8 %ret ret i8 %ret
} }
define i8 @test503(ptr %ptr, i8 %val) { define i8 @test503(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test503: ; PPC64LE-LABEL: test503:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: extsb 5, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: extsb 5, 4
; PPC64LE-NEXT: .LBB503_1: ; PPC64LE-NEXT: .LBB503_1:
; PPC64LE-NEXT: lbarx 4, 0, 3 ; PPC64LE-NEXT: lbarx 4, 0, 3
; PPC64LE-NEXT: extsb 6, 4 ; PPC64LE-NEXT: extsb 6, 4
; PPC64LE-NEXT: cmpw 6, 5 ; PPC64LE-NEXT: cmpw 6, 5
; PPC64LE-NEXT: blt 0, .LBB503_3 ; PPC64LE-NEXT: blt 0, .LBB503_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB503_1 ; PPC64LE-NEXT: bne 0, .LBB503_1
; PPC64LE-NEXT: .LBB503_3: ; PPC64LE-NEXT: .LBB503_3:
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw min ptr %ptr, i8 %val syncscope("singlethread") acq_rel %ret = atomicrmw min ptr %ptr, i8 %val syncscope("singlethread") acq_rel
ret i8 %ret ret i8 %ret
} }
define i8 @test504(ptr %ptr, i8 %val) { define i8 @test504(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test504: ; PPC64LE-LABEL: test504:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: extsb 5, 4
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: extsb 5, 4
; PPC64LE-NEXT: .LBB504_1: ; PPC64LE-NEXT: .LBB504_1:
; PPC64LE-NEXT: lbarx 4, 0, 3 ; PPC64LE-NEXT: lbarx 4, 0, 3
; PPC64LE-NEXT: extsb 6, 4 ; PPC64LE-NEXT: extsb 6, 4
; PPC64LE-NEXT: cmpw 6, 5 ; PPC64LE-NEXT: cmpw 6, 5
; PPC64LE-NEXT: blt 0, .LBB504_3 ; PPC64LE-NEXT: blt 0, .LBB504_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB504_1 ; PPC64LE-NEXT: bne 0, .LBB504_1
; PPC64LE-NEXT: .LBB504_3: ; PPC64LE-NEXT: .LBB504_3:
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw min ptr %ptr, i8 %val syncscope("singlethread") seq_cst %ret = atomicrmw min ptr %ptr, i8 %val syncscope("singlethread") seq_cst
ret i8 %ret ret i8 %ret
} }
define i16 @test505(ptr %ptr, i16 %val) { define i16 @test505(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test505: ; PPC64LE-LABEL: test505:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE-NEXT: lharx 4, 0, 3 ; PPC64LE-NEXT: lharx 4, 0, 3
; PPC64LE-NEXT: extsh 6, 4 ; PPC64LE-NEXT: extsh 6, 4
; PPC64LE-NEXT: cmpw 6, 5 ; PPC64LE-NEXT: cmpw 6, 5
; PPC64LE-NEXT: blt 0, .LBB506_3 ; PPC64LE-NEXT: blt 0, .LBB506_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB506_1 ; PPC64LE-NEXT: bne 0, .LBB506_1
; PPC64LE-NEXT: .LBB506_3: ; PPC64LE-NEXT: .LBB506_3:
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw min ptr %ptr, i16 %val syncscope("singlethread") acquire %ret = atomicrmw min ptr %ptr, i16 %val syncscope("singlethread") acquire
ret i16 %ret ret i16 %ret
} }
define i16 @test507(ptr %ptr, i16 %val) { define i16 @test507(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test507: ; PPC64LE-LABEL: test507:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: extsh 5, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: extsh 5, 4
; PPC64LE-NEXT: .LBB507_1: ; PPC64LE-NEXT: .LBB507_1:
; PPC64LE-NEXT: lharx 4, 0, 3 ; PPC64LE-NEXT: lharx 4, 0, 3
; PPC64LE-NEXT: extsh 6, 4 ; PPC64LE-NEXT: extsh 6, 4
; PPC64LE-NEXT: cmpw 6, 5 ; PPC64LE-NEXT: cmpw 6, 5
; PPC64LE-NEXT: blt 0, .LBB507_3 ; PPC64LE-NEXT: blt 0, .LBB507_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB507_1 ; PPC64LE-NEXT: bne 0, .LBB507_1
; PPC64LE-NEXT: .LBB507_3: ; PPC64LE-NEXT: .LBB507_3:
; PPC64LE-NEXT: mr 3, 4 ; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw min ptr %ptr, i16 %val syncscope("singlethread") release %ret = atomicrmw min ptr %ptr, i16 %val syncscope("singlethread") release
ret i16 %ret ret i16 %ret
} }
define i16 @test508(ptr %ptr, i16 %val) { define i16 @test508(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test508: ; PPC64LE-LABEL: test508:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: extsh 5, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: extsh 5, 4
; PPC64LE-NEXT: .LBB508_1: ; PPC64LE-NEXT: .LBB508_1:
; PPC64LE-NEXT: lharx 4, 0, 3 ; PPC64LE-NEXT: lharx 4, 0, 3
; PPC64LE-NEXT: extsh 6, 4 ; PPC64LE-NEXT: extsh 6, 4
; PPC64LE-NEXT: cmpw 6, 5 ; PPC64LE-NEXT: cmpw 6, 5
; PPC64LE-NEXT: blt 0, .LBB508_3 ; PPC64LE-NEXT: blt 0, .LBB508_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB508_1 ; PPC64LE-NEXT: bne 0, .LBB508_1
; PPC64LE-NEXT: .LBB508_3: ; PPC64LE-NEXT: .LBB508_3:
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw min ptr %ptr, i16 %val syncscope("singlethread") acq_rel %ret = atomicrmw min ptr %ptr, i16 %val syncscope("singlethread") acq_rel
ret i16 %ret ret i16 %ret
} }
define i16 @test509(ptr %ptr, i16 %val) { define i16 @test509(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test509: ; PPC64LE-LABEL: test509:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: extsh 5, 4
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: extsh 5, 4
; PPC64LE-NEXT: .LBB509_1: ; PPC64LE-NEXT: .LBB509_1:
; PPC64LE-NEXT: lharx 4, 0, 3 ; PPC64LE-NEXT: lharx 4, 0, 3
; PPC64LE-NEXT: extsh 6, 4 ; PPC64LE-NEXT: extsh 6, 4
; PPC64LE-NEXT: cmpw 6, 5 ; PPC64LE-NEXT: cmpw 6, 5
; PPC64LE-NEXT: blt 0, .LBB509_3 ; PPC64LE-NEXT: blt 0, .LBB509_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB509_1 ; PPC64LE-NEXT: bne 0, .LBB509_1
; PPC64LE-NEXT: .LBB509_3: ; PPC64LE-NEXT: .LBB509_3:
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 4
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw min ptr %ptr, i16 %val syncscope("singlethread") seq_cst %ret = atomicrmw min ptr %ptr, i16 %val syncscope("singlethread") seq_cst
ret i16 %ret ret i16 %ret
} }
define i32 @test510(ptr %ptr, i32 %val) { define i32 @test510(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test510: ; PPC64LE-LABEL: test510:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; PPC64LE-NEXT: .LBB513_1: ; PPC64LE-NEXT: .LBB513_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: cmpw 5, 4 ; PPC64LE-NEXT: cmpw 5, 4
; PPC64LE-NEXT: blt 0, .LBB513_3 ; PPC64LE-NEXT: blt 0, .LBB513_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB513_1 ; PPC64LE-NEXT: bne 0, .LBB513_1
; PPC64LE-NEXT: .LBB513_3: ; PPC64LE-NEXT: .LBB513_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw min ptr %ptr, i32 %val syncscope("singlethread") acq_rel %ret = atomicrmw min ptr %ptr, i32 %val syncscope("singlethread") acq_rel
ret i32 %ret ret i32 %ret
} }
define i32 @test514(ptr %ptr, i32 %val) { define i32 @test514(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test514: ; PPC64LE-LABEL: test514:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB514_1: ; PPC64LE-NEXT: .LBB514_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: cmpw 5, 4 ; PPC64LE-NEXT: cmpw 5, 4
; PPC64LE-NEXT: blt 0, .LBB514_3 ; PPC64LE-NEXT: blt 0, .LBB514_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB514_1 ; PPC64LE-NEXT: bne 0, .LBB514_1
; PPC64LE-NEXT: .LBB514_3: ; PPC64LE-NEXT: .LBB514_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw min ptr %ptr, i32 %val syncscope("singlethread") seq_cst %ret = atomicrmw min ptr %ptr, i32 %val syncscope("singlethread") seq_cst
ret i32 %ret ret i32 %ret
} }
define i64 @test515(ptr %ptr, i64 %val) { define i64 @test515(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test515: ; PPC64LE-LABEL: test515:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; PPC64LE-NEXT: .LBB518_1: ; PPC64LE-NEXT: .LBB518_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: cmpd 5, 4 ; PPC64LE-NEXT: cmpd 5, 4
; PPC64LE-NEXT: blt 0, .LBB518_3 ; PPC64LE-NEXT: blt 0, .LBB518_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB518_1 ; PPC64LE-NEXT: bne 0, .LBB518_1
; PPC64LE-NEXT: .LBB518_3: ; PPC64LE-NEXT: .LBB518_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw min ptr %ptr, i64 %val syncscope("singlethread") acq_rel %ret = atomicrmw min ptr %ptr, i64 %val syncscope("singlethread") acq_rel
ret i64 %ret ret i64 %ret
} }
define i64 @test519(ptr %ptr, i64 %val) { define i64 @test519(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test519: ; PPC64LE-LABEL: test519:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB519_1: ; PPC64LE-NEXT: .LBB519_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: cmpd 5, 4 ; PPC64LE-NEXT: cmpd 5, 4
; PPC64LE-NEXT: blt 0, .LBB519_3 ; PPC64LE-NEXT: blt 0, .LBB519_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB519_1 ; PPC64LE-NEXT: bne 0, .LBB519_1
; PPC64LE-NEXT: .LBB519_3: ; PPC64LE-NEXT: .LBB519_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw min ptr %ptr, i64 %val syncscope("singlethread") seq_cst %ret = atomicrmw min ptr %ptr, i64 %val syncscope("singlethread") seq_cst
ret i64 %ret ret i64 %ret
} }
define i8 @test520(ptr %ptr, i8 %val) { define i8 @test520(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test520: ; PPC64LE-LABEL: test520:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; PPC64LE-NEXT: .LBB523_1: ; PPC64LE-NEXT: .LBB523_1:
; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: cmplw 5, 4 ; PPC64LE-NEXT: cmplw 5, 4
; PPC64LE-NEXT: bgt 0, .LBB523_3 ; PPC64LE-NEXT: bgt 0, .LBB523_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: stbcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB523_1 ; PPC64LE-NEXT: bne 0, .LBB523_1
; PPC64LE-NEXT: .LBB523_3: ; PPC64LE-NEXT: .LBB523_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw umax ptr %ptr, i8 %val syncscope("singlethread") acq_rel %ret = atomicrmw umax ptr %ptr, i8 %val syncscope("singlethread") acq_rel
ret i8 %ret ret i8 %ret
} }
define i8 @test524(ptr %ptr, i8 %val) { define i8 @test524(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test524: ; PPC64LE-LABEL: test524:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB524_1: ; PPC64LE-NEXT: .LBB524_1:
; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: cmplw 5, 4 ; PPC64LE-NEXT: cmplw 5, 4
; PPC64LE-NEXT: bgt 0, .LBB524_3 ; PPC64LE-NEXT: bgt 0, .LBB524_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: stbcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB524_1 ; PPC64LE-NEXT: bne 0, .LBB524_1
; PPC64LE-NEXT: .LBB524_3: ; PPC64LE-NEXT: .LBB524_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw umax ptr %ptr, i8 %val syncscope("singlethread") seq_cst %ret = atomicrmw umax ptr %ptr, i8 %val syncscope("singlethread") seq_cst
ret i8 %ret ret i8 %ret
} }
define i16 @test525(ptr %ptr, i16 %val) { define i16 @test525(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test525: ; PPC64LE-LABEL: test525:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; PPC64LE-NEXT: .LBB528_1: ; PPC64LE-NEXT: .LBB528_1:
; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: cmplw 5, 4 ; PPC64LE-NEXT: cmplw 5, 4
; PPC64LE-NEXT: bgt 0, .LBB528_3 ; PPC64LE-NEXT: bgt 0, .LBB528_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: sthcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB528_1 ; PPC64LE-NEXT: bne 0, .LBB528_1
; PPC64LE-NEXT: .LBB528_3: ; PPC64LE-NEXT: .LBB528_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw umax ptr %ptr, i16 %val syncscope("singlethread") acq_rel %ret = atomicrmw umax ptr %ptr, i16 %val syncscope("singlethread") acq_rel
ret i16 %ret ret i16 %ret
} }
define i16 @test529(ptr %ptr, i16 %val) { define i16 @test529(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test529: ; PPC64LE-LABEL: test529:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB529_1: ; PPC64LE-NEXT: .LBB529_1:
; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: cmplw 5, 4 ; PPC64LE-NEXT: cmplw 5, 4
; PPC64LE-NEXT: bgt 0, .LBB529_3 ; PPC64LE-NEXT: bgt 0, .LBB529_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: sthcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB529_1 ; PPC64LE-NEXT: bne 0, .LBB529_1
; PPC64LE-NEXT: .LBB529_3: ; PPC64LE-NEXT: .LBB529_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw umax ptr %ptr, i16 %val syncscope("singlethread") seq_cst %ret = atomicrmw umax ptr %ptr, i16 %val syncscope("singlethread") seq_cst
ret i16 %ret ret i16 %ret
} }
define i32 @test530(ptr %ptr, i32 %val) { define i32 @test530(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test530: ; PPC64LE-LABEL: test530:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; PPC64LE-NEXT: .LBB533_1: ; PPC64LE-NEXT: .LBB533_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: cmplw 5, 4 ; PPC64LE-NEXT: cmplw 5, 4
; PPC64LE-NEXT: bgt 0, .LBB533_3 ; PPC64LE-NEXT: bgt 0, .LBB533_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB533_1 ; PPC64LE-NEXT: bne 0, .LBB533_1
; PPC64LE-NEXT: .LBB533_3: ; PPC64LE-NEXT: .LBB533_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw umax ptr %ptr, i32 %val syncscope("singlethread") acq_rel %ret = atomicrmw umax ptr %ptr, i32 %val syncscope("singlethread") acq_rel
ret i32 %ret ret i32 %ret
} }
define i32 @test534(ptr %ptr, i32 %val) { define i32 @test534(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test534: ; PPC64LE-LABEL: test534:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB534_1: ; PPC64LE-NEXT: .LBB534_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: cmplw 5, 4 ; PPC64LE-NEXT: cmplw 5, 4
; PPC64LE-NEXT: bgt 0, .LBB534_3 ; PPC64LE-NEXT: bgt 0, .LBB534_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB534_1 ; PPC64LE-NEXT: bne 0, .LBB534_1
; PPC64LE-NEXT: .LBB534_3: ; PPC64LE-NEXT: .LBB534_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw umax ptr %ptr, i32 %val syncscope("singlethread") seq_cst %ret = atomicrmw umax ptr %ptr, i32 %val syncscope("singlethread") seq_cst
ret i32 %ret ret i32 %ret
} }
define i64 @test535(ptr %ptr, i64 %val) { define i64 @test535(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test535: ; PPC64LE-LABEL: test535:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; PPC64LE-NEXT: .LBB538_1: ; PPC64LE-NEXT: .LBB538_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: cmpld 5, 4 ; PPC64LE-NEXT: cmpld 5, 4
; PPC64LE-NEXT: bgt 0, .LBB538_3 ; PPC64LE-NEXT: bgt 0, .LBB538_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB538_1 ; PPC64LE-NEXT: bne 0, .LBB538_1
; PPC64LE-NEXT: .LBB538_3: ; PPC64LE-NEXT: .LBB538_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw umax ptr %ptr, i64 %val syncscope("singlethread") acq_rel %ret = atomicrmw umax ptr %ptr, i64 %val syncscope("singlethread") acq_rel
ret i64 %ret ret i64 %ret
} }
define i64 @test539(ptr %ptr, i64 %val) { define i64 @test539(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test539: ; PPC64LE-LABEL: test539:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB539_1: ; PPC64LE-NEXT: .LBB539_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: cmpld 5, 4 ; PPC64LE-NEXT: cmpld 5, 4
; PPC64LE-NEXT: bgt 0, .LBB539_3 ; PPC64LE-NEXT: bgt 0, .LBB539_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB539_1 ; PPC64LE-NEXT: bne 0, .LBB539_1
; PPC64LE-NEXT: .LBB539_3: ; PPC64LE-NEXT: .LBB539_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw umax ptr %ptr, i64 %val syncscope("singlethread") seq_cst %ret = atomicrmw umax ptr %ptr, i64 %val syncscope("singlethread") seq_cst
ret i64 %ret ret i64 %ret
} }
define i8 @test540(ptr %ptr, i8 %val) { define i8 @test540(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test540: ; PPC64LE-LABEL: test540:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; PPC64LE-NEXT: .LBB543_1: ; PPC64LE-NEXT: .LBB543_1:
; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: cmplw 5, 4 ; PPC64LE-NEXT: cmplw 5, 4
; PPC64LE-NEXT: blt 0, .LBB543_3 ; PPC64LE-NEXT: blt 0, .LBB543_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: stbcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB543_1 ; PPC64LE-NEXT: bne 0, .LBB543_1
; PPC64LE-NEXT: .LBB543_3: ; PPC64LE-NEXT: .LBB543_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw umin ptr %ptr, i8 %val syncscope("singlethread") acq_rel %ret = atomicrmw umin ptr %ptr, i8 %val syncscope("singlethread") acq_rel
ret i8 %ret ret i8 %ret
} }
define i8 @test544(ptr %ptr, i8 %val) { define i8 @test544(ptr %ptr, i8 %val) {
; PPC64LE-LABEL: test544: ; PPC64LE-LABEL: test544:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB544_1: ; PPC64LE-NEXT: .LBB544_1:
; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: cmplw 5, 4 ; PPC64LE-NEXT: cmplw 5, 4
; PPC64LE-NEXT: blt 0, .LBB544_3 ; PPC64LE-NEXT: blt 0, .LBB544_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: stbcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB544_1 ; PPC64LE-NEXT: bne 0, .LBB544_1
; PPC64LE-NEXT: .LBB544_3: ; PPC64LE-NEXT: .LBB544_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw umin ptr %ptr, i8 %val syncscope("singlethread") seq_cst %ret = atomicrmw umin ptr %ptr, i8 %val syncscope("singlethread") seq_cst
ret i8 %ret ret i8 %ret
} }
define i16 @test545(ptr %ptr, i16 %val) { define i16 @test545(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test545: ; PPC64LE-LABEL: test545:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; PPC64LE-NEXT: .LBB548_1: ; PPC64LE-NEXT: .LBB548_1:
; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: cmplw 5, 4 ; PPC64LE-NEXT: cmplw 5, 4
; PPC64LE-NEXT: blt 0, .LBB548_3 ; PPC64LE-NEXT: blt 0, .LBB548_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: sthcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB548_1 ; PPC64LE-NEXT: bne 0, .LBB548_1
; PPC64LE-NEXT: .LBB548_3: ; PPC64LE-NEXT: .LBB548_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw umin ptr %ptr, i16 %val syncscope("singlethread") acq_rel %ret = atomicrmw umin ptr %ptr, i16 %val syncscope("singlethread") acq_rel
ret i16 %ret ret i16 %ret
} }
define i16 @test549(ptr %ptr, i16 %val) { define i16 @test549(ptr %ptr, i16 %val) {
; PPC64LE-LABEL: test549: ; PPC64LE-LABEL: test549:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB549_1: ; PPC64LE-NEXT: .LBB549_1:
; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: cmplw 5, 4 ; PPC64LE-NEXT: cmplw 5, 4
; PPC64LE-NEXT: blt 0, .LBB549_3 ; PPC64LE-NEXT: blt 0, .LBB549_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: sthcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB549_1 ; PPC64LE-NEXT: bne 0, .LBB549_1
; PPC64LE-NEXT: .LBB549_3: ; PPC64LE-NEXT: .LBB549_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw umin ptr %ptr, i16 %val syncscope("singlethread") seq_cst %ret = atomicrmw umin ptr %ptr, i16 %val syncscope("singlethread") seq_cst
ret i16 %ret ret i16 %ret
} }
define i32 @test550(ptr %ptr, i32 %val) { define i32 @test550(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test550: ; PPC64LE-LABEL: test550:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE-NEXT: .LBB553_1: ; PPC64LE-NEXT: .LBB553_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: cmplw 5, 4 ; PPC64LE-NEXT: cmplw 5, 4
; PPC64LE-NEXT: blt 0, .LBB553_3 ; PPC64LE-NEXT: blt 0, .LBB553_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB553_1 ; PPC64LE-NEXT: bne 0, .LBB553_1
; PPC64LE-NEXT: .LBB553_3: ; PPC64LE-NEXT: .LBB553_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw umin ptr %ptr, i32 %val syncscope("singlethread") acq_rel %ret = atomicrmw umin ptr %ptr, i32 %val syncscope("singlethread") acq_rel
ret i32 %ret ret i32 %ret
} }
define i32 @test554(ptr %ptr, i32 %val) { define i32 @test554(ptr %ptr, i32 %val) {
; PPC64LE-LABEL: test554: ; PPC64LE-LABEL: test554:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB554_1: ; PPC64LE-NEXT: .LBB554_1:
; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: cmplw 5, 4 ; PPC64LE-NEXT: cmplw 5, 4
; PPC64LE-NEXT: blt 0, .LBB554_3 ; PPC64LE-NEXT: blt 0, .LBB554_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB554_1 ; PPC64LE-NEXT: bne 0, .LBB554_1
; PPC64LE-NEXT: .LBB554_3: ; PPC64LE-NEXT: .LBB554_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw umin ptr %ptr, i32 %val syncscope("singlethread") seq_cst %ret = atomicrmw umin ptr %ptr, i32 %val syncscope("singlethread") seq_cst
ret i32 %ret ret i32 %ret
} }
define i64 @test555(ptr %ptr, i64 %val) { define i64 @test555(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test555: ; PPC64LE-LABEL: test555:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
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; PPC64LE-NEXT: .LBB558_1: ; PPC64LE-NEXT: .LBB558_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: cmpld 5, 4 ; PPC64LE-NEXT: cmpld 5, 4
; PPC64LE-NEXT: blt 0, .LBB558_3 ; PPC64LE-NEXT: blt 0, .LBB558_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB558_1 ; PPC64LE-NEXT: bne 0, .LBB558_1
; PPC64LE-NEXT: .LBB558_3: ; PPC64LE-NEXT: .LBB558_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw umin ptr %ptr, i64 %val syncscope("singlethread") acq_rel %ret = atomicrmw umin ptr %ptr, i64 %val syncscope("singlethread") acq_rel
ret i64 %ret ret i64 %ret
} }
define i64 @test559(ptr %ptr, i64 %val) { define i64 @test559(ptr %ptr, i64 %val) {
; PPC64LE-LABEL: test559: ; PPC64LE-LABEL: test559:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB559_1: ; PPC64LE-NEXT: .LBB559_1:
; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: cmpld 5, 4 ; PPC64LE-NEXT: cmpld 5, 4
; PPC64LE-NEXT: blt 0, .LBB559_3 ; PPC64LE-NEXT: blt 0, .LBB559_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB559_1 ; PPC64LE-NEXT: bne 0, .LBB559_1
; PPC64LE-NEXT: .LBB559_3: ; PPC64LE-NEXT: .LBB559_3:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%ret = atomicrmw umin ptr %ptr, i64 %val syncscope("singlethread") seq_cst %ret = atomicrmw umin ptr %ptr, i64 %val syncscope("singlethread") seq_cst
ret i64 %ret ret i64 %ret
} }
; The second load should never be scheduled before isync. ; The second load should never be scheduled before isync.
define i32 @test_ordering0(ptr %ptr1, ptr %ptr2) { define i32 @test_ordering0(ptr %ptr1, ptr %ptr2) {
; PPC64LE-LABEL: test_ordering0: ; PPC64LE-LABEL: test_ordering0:
Show All 28 Lines

llvm/test/CodeGen/PowerPC/bool-math.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=powerpc64le-- -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -mtriple=powerpc64le-- -mcpu=pwr8 -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -mtriple=powerpc64-ibm-aix-xcoff -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr8 -verify-machineinstrs | FileCheck %s
define i32 @sub_zext_cmp_mask_same_size_result(i32 %x) { define i32 @sub_zext_cmp_mask_same_size_result(i32 %x) {
; CHECK-LABEL: sub_zext_cmp_mask_same_size_result: ; CHECK-LABEL: sub_zext_cmp_mask_same_size_result:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: clrldi 3, 3, 63 ; CHECK-NEXT: clrldi 3, 3, 63
; CHECK-NEXT: ori 3, 3, 65508 ; CHECK-NEXT: ori 3, 3, 65508
; CHECK-NEXT: oris 3, 3, 65535 ; CHECK-NEXT: oris 3, 3, 65535
; CHECK-NEXT: blr ; CHECK-NEXT: blr
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; CHECK-NEXT: ori 3, 3, 36 ; CHECK-NEXT: ori 3, 3, 36
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%a = and i32 %x, 1 %a = and i32 %x, 1
%c = icmp eq i32 %a, 0 %c = icmp eq i32 %a, 0
%r = select i1 %c, i16 36, i16 37 %r = select i1 %c, i16 36, i16 37
ret i16 %r ret i16 %r
} }
define i8 @low_bit_select_constants_bigger_true_same_size_result(i8 %x) { define i8 @low_bit_select_constants_bigger_true_same_size_result(i8 %x) {
shchenzUnsubmitted
Done
ReplyInline Actions

Weird. Now there is no check for this function?

shchenz: Weird. Now there is no check for this function?
qiucfAuthorUnsubmitted
Done
ReplyInline Actions

Because the test RUN line did not specify -mcpu, so that Linux uses pwr8 while AIX uses pwr7. Fixed.

qiucf: Because the test RUN line did not specify `-mcpu`, so that Linux uses pwr8 while AIX uses pwr7.
; CHECK-LABEL: low_bit_select_constants_bigger_true_same_size_result: ; CHECK-LABEL: low_bit_select_constants_bigger_true_same_size_result:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li 4, -29
; CHECK-NEXT: clrldi 3, 3, 63 ; CHECK-NEXT: clrldi 3, 3, 63
; CHECK-NEXT: li 4, -29
; CHECK-NEXT: xor 3, 3, 4 ; CHECK-NEXT: xor 3, 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%a = and i8 %x, 1 %a = and i8 %x, 1
%c = icmp eq i8 %a, 0 %c = icmp eq i8 %a, 0
%r = select i1 %c, i8 227, i8 226 %r = select i1 %c, i8 227, i8 226
ret i8 %r ret i8 %r
} }
Show All 24 Lines

llvm/test/CodeGen/PowerPC/branch_coalesce.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs -enable-ppc-branch-coalesce < %s | FileCheck %s ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs -enable-ppc-branch-coalesce < %s | FileCheck %s
; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -verify-machineinstrs -enable-ppc-branch-coalesce < %s | FileCheck %s ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -verify-machineinstrs -enable-ppc-branch-coalesce < %s | FileCheck %s
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-NOCOALESCE %s ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-NOCOALESCE %s
; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-NOCOALESCE %s ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-NOCOALESCE %s
; Function Attrs: nounwind ; Function Attrs: nounwind
define double @testBranchCoal(double %a, double %b, double %c, i32 %x) { define double @testBranchCoal(double %a, double %b, double %c, i32 %x) {
; CHECK-LABEL: testBranchCoal: ; CHECK-LABEL: testBranchCoal:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmplwi 6, 0 ; CHECK-NEXT: cmplwi 6, 0
; CHECK-NEXT: beq 0, .LBB0_2 ; CHECK-NEXT: beq 0, .LBB0_2
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: addis 3, 2, .LCPI0_0@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI0_0@toc@ha
; CHECK-NEXT: addis 4, 2, .LCPI0_1@toc@ha
; CHECK-NEXT: xxlxor 2, 2, 2 ; CHECK-NEXT: xxlxor 2, 2, 2
; CHECK-NEXT: lfd 1, .LCPI0_0@toc@l(3) ; CHECK-NEXT: lfd 1, .LCPI0_0@toc@l(3)
; CHECK-NEXT: lfd 3, .LCPI0_1@toc@l(4) ; CHECK-NEXT: addis 3, 2, .LCPI0_1@toc@ha
; CHECK-NEXT: lfd 3, .LCPI0_1@toc@l(3)
shchenzUnsubmitted
Not Done
ReplyInline Actions

lower ILP and less registers

shchenz: lower ILP and less registers
; CHECK-NEXT: .LBB0_2: # %entry ; CHECK-NEXT: .LBB0_2: # %entry
; CHECK-NEXT: xsadddp 0, 1, 2 ; CHECK-NEXT: xsadddp 0, 1, 2
; CHECK-NEXT: xsadddp 1, 0, 3 ; CHECK-NEXT: xsadddp 1, 0, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-NOCOALESCE-LABEL: testBranchCoal: ; CHECK-NOCOALESCE-LABEL: testBranchCoal:
; CHECK-NOCOALESCE: # %bb.0: # %entry ; CHECK-NOCOALESCE: # %bb.0: # %entry
; CHECK-NOCOALESCE-NEXT: cmplwi 6, 0 ; CHECK-NOCOALESCE-NEXT: cmplwi 6, 0
Show All 32 Lines

llvm/test/CodeGen/PowerPC/build-vector-tests.ll

llvm/test/CodeGen/PowerPC/builtins-ppc-p8vector.ll

llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll

llvm/test/CodeGen/PowerPC/cfence-float.ll

llvm/test/CodeGen/PowerPC/coldcc2.ll

llvm/test/CodeGen/PowerPC/combine-fneg.ll

llvm/test/CodeGen/PowerPC/combine-sext-and-shl-after-isel.ll

llvm/test/CodeGen/PowerPC/combine_ext_trunc.ll

llvm/test/CodeGen/PowerPC/const-nonsplat-array-init.ll

llvm/test/CodeGen/PowerPC/const-splat-array-init.ll

llvm/test/CodeGen/PowerPC/constant-combines.ll

llvm/test/CodeGen/PowerPC/crypto_bifs_be.ll

llvm/test/CodeGen/PowerPC/csr-split.ll

llvm/test/CodeGen/PowerPC/ctrloop-constrained-fp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple powerpc64le < %s | FileCheck %s ; RUN: llc -mtriple powerpc64le < %s | FileCheck %s
; Check constrained ops converted to call ; Check constrained ops converted to call
define void @test(ptr %cast) { define void @test(ptr %cast) {
; CHECK-LABEL: test: ; CHECK-LABEL: test:
; CHECK: # %bb.0: # %root ; CHECK: # %bb.0: # %root
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: .cfi_def_cfa_offset 64 ; CHECK-NEXT: .cfi_def_cfa_offset 64
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: .cfi_offset r29, -24 ; CHECK-NEXT: .cfi_offset r29, -24
; CHECK-NEXT: .cfi_offset r30, -16 ; CHECK-NEXT: .cfi_offset r30, -16
; CHECK-NEXT: std 29, -24(1) # 8-byte Folded Spill ; CHECK-NEXT: std 29, -24(1) # 8-byte Folded Spill
; CHECK-NEXT: std 30, -16(1) # 8-byte Folded Spill ; CHECK-NEXT: std 30, -16(1) # 8-byte Folded Spill
; CHECK-NEXT: stdu 1, -64(1) ; CHECK-NEXT: stdu 1, -64(1)
; CHECK-NEXT: li 30, 255 ; CHECK-NEXT: addi 30, 3, -8
; CHECK-NEXT: addi 29, 3, -8 ; CHECK-NEXT: li 29, 255
; CHECK-NEXT: std 0, 80(1) ; CHECK-NEXT: std 0, 80(1)
; CHECK-NEXT: .p2align 5 ; CHECK-NEXT: .p2align 5
; CHECK-NEXT: .LBB0_1: # %for.body ; CHECK-NEXT: .LBB0_1: # %for.body
; CHECK-NEXT: # ; CHECK-NEXT: #
; CHECK-NEXT: lfdu 1, 8(29) ; CHECK-NEXT: lfdu 1, 8(30)
; CHECK-NEXT: bl cos ; CHECK-NEXT: bl cos
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi 30, 30, -1 ; CHECK-NEXT: addi 29, 29, -1
; CHECK-NEXT: stfd 1, 0(29) ; CHECK-NEXT: stfd 1, 0(30)
; CHECK-NEXT: cmpldi 30, 0 ; CHECK-NEXT: cmpldi 29, 0
shchenzUnsubmitted
Done
ReplyInline Actions

Positive

shchenz: Positive
; CHECK-NEXT: bc 12, 1, .LBB0_1 ; CHECK-NEXT: bc 12, 1, .LBB0_1
; CHECK-NEXT: # %bb.2: # %exit ; CHECK-NEXT: # %bb.2: # %exit
; CHECK-NEXT: addi 1, 1, 64 ; CHECK-NEXT: addi 1, 1, 64
; CHECK-NEXT: ld 0, 16(1) ; CHECK-NEXT: ld 0, 16(1)
; CHECK-NEXT: ld 30, -16(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 30, -16(1) # 8-byte Folded Reload
; CHECK-NEXT: ld 29, -24(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 29, -24(1) # 8-byte Folded Reload
; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
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llvm/test/CodeGen/PowerPC/ctrloop-fp128.ll

llvm/test/CodeGen/PowerPC/cxx_tlscc64.ll

llvm/test/CodeGen/PowerPC/disable-ctr-ppcf128.ll

llvm/test/CodeGen/PowerPC/elf64-byval-cc.ll

Show All 26 Lines
entry: entry:
%call = call zeroext i8 @test_byval_mem1(ptr byval(%struct_S1) align 1 @gS1) %call = call zeroext i8 @test_byval_mem1(ptr byval(%struct_S1) align 1 @gS1)
ret void ret void
} }
define zeroext i8 @test_byval_mem1(ptr byval(%struct_S1) align 1 %s) { define zeroext i8 @test_byval_mem1(ptr byval(%struct_S1) align 1 %s) {
; CHECK-LABEL: test_byval_mem1: ; CHECK-LABEL: test_byval_mem1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mr 4, 3 ; CHECK-NEXT: stb 3, -8(1)
shchenzUnsubmitted
Done
ReplyInline Actions

postive

shchenz: postive
; CHECK-NEXT: clrldi 3, 3, 56 ; CHECK-NEXT: clrldi 3, 3, 56
; CHECK-NEXT: stb 4, -8(1)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%0 = load i8, ptr %s, align 1 %0 = load i8, ptr %s, align 1
ret i8 %0 ret i8 %0
} }
define void @call_test_byval_mem1_2() #0 { define void @call_test_byval_mem1_2() #0 {
; CHECK-LABEL: call_test_byval_mem1_2: ; CHECK-LABEL: call_test_byval_mem1_2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: stdu 1, -112(1) ; CHECK-NEXT: stdu 1, -112(1)
; CHECK-NEXT: std 0, 128(1) ; CHECK-NEXT: std 0, 128(1)
; CHECK-NEXT: .cfi_def_cfa_offset 112 ; CHECK-NEXT: .cfi_def_cfa_offset 112
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: addis 3, 2, .LC0@toc@ha ; CHECK-NEXT: addis 3, 2, .LC0@toc@ha
; CHECK-NEXT: li 4, 1 ; CHECK-NEXT: li 4, 1
; CHECK-NEXT: li 5, 2 ; CHECK-NEXT: li 5, 2
; CHECK-NEXT: li 6, 3 ; CHECK-NEXT: li 6, 3
; CHECK-NEXT: li 7, 4 ; CHECK-NEXT: li 7, 4
; CHECK-NEXT: li 8, 5 ; CHECK-NEXT: li 8, 5
; CHECK-NEXT: li 9, 6 ; CHECK-NEXT: li 9, 6
; CHECK-NEXT: ld 3, .LC0@toc@l(3)
; CHECK-NEXT: li 10, 7 ; CHECK-NEXT: li 10, 7
; CHECK-NEXT: ld 3, .LC0@toc@l(3)
; CHECK-NEXT: lbz 3, 0(3) ; CHECK-NEXT: lbz 3, 0(3)
; CHECK-NEXT: stb 3, 96(1) ; CHECK-NEXT: stb 3, 96(1)
; CHECK-NEXT: li 3, 0 ; CHECK-NEXT: li 3, 0
; CHECK-NEXT: bl test_byval_mem1_2 ; CHECK-NEXT: bl test_byval_mem1_2
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi 1, 1, 112 ; CHECK-NEXT: addi 1, 1, 112
; CHECK-NEXT: ld 0, 16(1) ; CHECK-NEXT: ld 0, 16(1)
; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: mtlr 0
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define void @call_test_byval_mem1_4() #0 { define void @call_test_byval_mem1_4() #0 {
; CHECK-LABEL: call_test_byval_mem1_4: ; CHECK-LABEL: call_test_byval_mem1_4:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: stdu 1, -112(1) ; CHECK-NEXT: stdu 1, -112(1)
; CHECK-NEXT: std 0, 128(1) ; CHECK-NEXT: std 0, 128(1)
; CHECK-NEXT: .cfi_def_cfa_offset 112 ; CHECK-NEXT: .cfi_def_cfa_offset 112
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: addis 3, 2, .LC0@toc@ha ; CHECK-NEXT: li 3, 7
; CHECK-NEXT: li 4, 7 ; CHECK-NEXT: li 4, 1
; CHECK-NEXT: li 5, 2 ; CHECK-NEXT: li 5, 2
; CHECK-NEXT: li 7, 3 ; CHECK-NEXT: li 7, 3
; CHECK-NEXT: li 8, 4 ; CHECK-NEXT: li 8, 4
; CHECK-NEXT: li 9, 5 ; CHECK-NEXT: li 9, 5
; CHECK-NEXT: li 10, 6 ; CHECK-NEXT: li 10, 6
; CHECK-NEXT: std 3, 96(1)
; CHECK-NEXT: addis 3, 2, .LC0@toc@ha
; CHECK-NEXT: ld 3, .LC0@toc@l(3) ; CHECK-NEXT: ld 3, .LC0@toc@l(3)
; CHECK-NEXT: std 4, 96(1)
; CHECK-NEXT: li 4, 1
; CHECK-NEXT: lbz 6, 0(3) ; CHECK-NEXT: lbz 6, 0(3)
; CHECK-NEXT: li 3, 0 ; CHECK-NEXT: li 3, 0
; CHECK-NEXT: bl test_byval_mem1_4 ; CHECK-NEXT: bl test_byval_mem1_4
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi 1, 1, 112 ; CHECK-NEXT: addi 1, 1, 112
; CHECK-NEXT: ld 0, 16(1) ; CHECK-NEXT: ld 0, 16(1)
; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
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%call = call zeroext i8 @test_byval_mem3(ptr byval(%struct_S3) align 1 @gS3) %call = call zeroext i8 @test_byval_mem3(ptr byval(%struct_S3) align 1 @gS3)
ret void ret void
} }
define zeroext i8 @test_byval_mem3(ptr byval(%struct_S3) align 1 %s) { define zeroext i8 @test_byval_mem3(ptr byval(%struct_S3) align 1 %s) {
; CHECK-LABEL: test_byval_mem3: ; CHECK-LABEL: test_byval_mem3:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sth 3, -8(1) ; CHECK-NEXT: sth 3, -8(1)
; CHECK-NEXT: rldicl 5, 3, 48, 16 ; CHECK-NEXT: rldicl 3, 3, 48, 16
; CHECK-NEXT: lbz 4, -8(1) ; CHECK-NEXT: stb 3, -6(1)
; CHECK-NEXT: stb 5, -6(1) ; CHECK-NEXT: lbz 3, -8(1)
; CHECK-NEXT: mr 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%0 = load i8, ptr %s, align 1 %0 = load i8, ptr %s, align 1
ret i8 %0 ret i8 %0
} }
%struct_S4 = type { [4 x i8] } %struct_S4 = type { [4 x i8] }
@gS4 = external global %struct_S4, align 1 @gS4 = external global %struct_S4, align 1
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entry: entry:
%call = call zeroext i8 @test_byval_mem8(ptr byval(%struct_S8) align 1 @gS8) %call = call zeroext i8 @test_byval_mem8(ptr byval(%struct_S8) align 1 @gS8)
ret void ret void
} }
define zeroext i8 @test_byval_mem8(ptr byval(%struct_S8) align 1 %s) { define zeroext i8 @test_byval_mem8(ptr byval(%struct_S8) align 1 %s) {
; CHECK-LABEL: test_byval_mem8: ; CHECK-LABEL: test_byval_mem8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mr 4, 3 ; CHECK-NEXT: std 3, -8(1)
; CHECK-NEXT: clrldi 3, 3, 56 ; CHECK-NEXT: clrldi 3, 3, 56
; CHECK-NEXT: std 4, -8(1)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%0 = load i8, ptr %s, align 1 %0 = load i8, ptr %s, align 1
ret i8 %0 ret i8 %0
} }
%struct_S32 = type {[32 x i8] } %struct_S32 = type {[32 x i8] }
@gS32 = external global %struct_S32, align 1 @gS32 = external global %struct_S32, align 1
Show All 21 Lines
entry: entry:
%call = call zeroext i8 @test_byval_mem32(ptr byval(%struct_S32) align 1 @gS32) %call = call zeroext i8 @test_byval_mem32(ptr byval(%struct_S32) align 1 @gS32)
ret void ret void
} }
define zeroext i8 @test_byval_mem32(ptr byval(%struct_S32) align 1 %s) { define zeroext i8 @test_byval_mem32(ptr byval(%struct_S32) align 1 %s) {
; CHECK-LABEL: test_byval_mem32: ; CHECK-LABEL: test_byval_mem32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mr 7, 3 ; CHECK-NEXT: std 3, -32(1)
; CHECK-NEXT: clrldi 3, 3, 56 ; CHECK-NEXT: clrldi 3, 3, 56
; CHECK-NEXT: std 4, -24(1) ; CHECK-NEXT: std 4, -24(1)
; CHECK-NEXT: std 5, -16(1) ; CHECK-NEXT: std 5, -16(1)
; CHECK-NEXT: std 6, -8(1) ; CHECK-NEXT: std 6, -8(1)
; CHECK-NEXT: std 7, -32(1)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%0 = load i8, ptr %s, align 1 %0 = load i8, ptr %s, align 1
ret i8 %0 ret i8 %0
} }
define void @call_test_byval_mem32_2() #0 { define void @call_test_byval_mem32_2() #0 {
; CHECK-LABEL: call_test_byval_mem32_2: ; CHECK-LABEL: call_test_byval_mem32_2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: stdu 1, -32(1) ; CHECK-NEXT: stdu 1, -32(1)
; CHECK-NEXT: std 0, 48(1) ; CHECK-NEXT: std 0, 48(1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: addis 3, 2, .LC5@toc@ha ; CHECK-NEXT: addis 3, 2, .LC5@toc@ha
; CHECK-NEXT: vspltisw 2, 1 ; CHECK-NEXT: vspltisw 2, 1
; CHECK-NEXT: ld 3, .LC5@toc@l(3) ; CHECK-NEXT: ld 3, .LC5@toc@l(3)
; CHECK-NEXT: xvcvsxwdp 1, 34 ; CHECK-NEXT: xvcvsxwdp 1, 34
; CHECK-NEXT: # kill: def $f1 killed $f1 killed $vsl1
; CHECK-NEXT: ld 7, 24(3) ; CHECK-NEXT: ld 7, 24(3)
; CHECK-NEXT: ld 6, 16(3) ; CHECK-NEXT: ld 6, 16(3)
; CHECK-NEXT: ld 5, 8(3) ; CHECK-NEXT: ld 5, 8(3)
; CHECK-NEXT: ld 4, 0(3) ; CHECK-NEXT: ld 4, 0(3)
; CHECK-NEXT: # kill: def $f1 killed $f1 killed $vsl1
; CHECK-NEXT: bl test_byval_mem32_2 ; CHECK-NEXT: bl test_byval_mem32_2
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi 1, 1, 32 ; CHECK-NEXT: addi 1, 1, 32
; CHECK-NEXT: ld 0, 16(1) ; CHECK-NEXT: ld 0, 16(1)
; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%call = call zeroext i8 @test_byval_mem32_2(float 1.0, ptr byval(%struct_S32) align 1 @gS32) %call = call zeroext i8 @test_byval_mem32_2(float 1.0, ptr byval(%struct_S32) align 1 @gS32)
Show All 25 Lines
; CHECK-NEXT: addis 3, 2, .LC5@toc@ha ; CHECK-NEXT: addis 3, 2, .LC5@toc@ha
; CHECK-NEXT: li 4, 16 ; CHECK-NEXT: li 4, 16
; CHECK-NEXT: vspltisw 2, 1 ; CHECK-NEXT: vspltisw 2, 1
; CHECK-NEXT: vspltisw 3, 4 ; CHECK-NEXT: vspltisw 3, 4
; CHECK-NEXT: li 5, 3 ; CHECK-NEXT: li 5, 3
; CHECK-NEXT: li 7, 2 ; CHECK-NEXT: li 7, 2
; CHECK-NEXT: ld 3, .LC5@toc@l(3) ; CHECK-NEXT: ld 3, .LC5@toc@l(3)
; CHECK-NEXT: xvcvsxwdp 1, 34 ; CHECK-NEXT: xvcvsxwdp 1, 34
; CHECK-NEXT: lxvd2x 0, 3, 4
; CHECK-NEXT: li 4, 88
; CHECK-NEXT: xvcvsxwdp 2, 35
; CHECK-NEXT: # kill: def $f1 killed $f1 killed $vsl1 ; CHECK-NEXT: # kill: def $f1 killed $f1 killed $vsl1
; CHECK-NEXT: xvcvsxwdp 2, 35
; CHECK-NEXT: # kill: def $f2 killed $f2 killed $vsl2 ; CHECK-NEXT: # kill: def $f2 killed $f2 killed $vsl2
; CHECK-NEXT: lxvd2x 0, 3, 4
; CHECK-NEXT: li 4, 88
; CHECK-NEXT: stxvd2x 0, 1, 4 ; CHECK-NEXT: stxvd2x 0, 1, 4
; CHECK-NEXT: li 4, 72 ; CHECK-NEXT: li 4, 72
; CHECK-NEXT: lxvd2x 0, 0, 3 ; CHECK-NEXT: lxvd2x 0, 0, 3
; CHECK-NEXT: stxvd2x 0, 1, 4 ; CHECK-NEXT: stxvd2x 0, 1, 4
; CHECK-NEXT: ld 10, 16(3) ; CHECK-NEXT: ld 10, 16(3)
; CHECK-NEXT: ld 9, 8(3) ; CHECK-NEXT: ld 9, 8(3)
; CHECK-NEXT: ld 8, 0(3) ; CHECK-NEXT: ld 8, 0(3)
; CHECK-NEXT: li 3, 1 ; CHECK-NEXT: li 3, 1
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llvm/test/CodeGen/PowerPC/extra-toc-reg-deps.ll

llvm/test/CodeGen/PowerPC/extract-and-store.ll

llvm/test/CodeGen/PowerPC/f128-aggregates.ll

llvm/test/CodeGen/PowerPC/f128-arith.ll

llvm/test/CodeGen/PowerPC/f128-bitcast.ll

llvm/test/CodeGen/PowerPC/f128-compare.ll

llvm/test/CodeGen/PowerPC/f128-conv.ll

llvm/test/CodeGen/PowerPC/f128-fma.ll

llvm/test/CodeGen/PowerPC/f128-passByValue.ll

llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll

llvm/test/CodeGen/PowerPC/fma-aggr-FMF.ll

llvm/test/CodeGen/PowerPC/fma-combine.ll

llvm/test/CodeGen/PowerPC/fmf-propagation.ll

llvm/test/CodeGen/PowerPC/fold-rlwinm-1.ll

llvm/test/CodeGen/PowerPC/fp-classify.ll

llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll

llvm/test/CodeGen/PowerPC/fp-strict-conv.ll

llvm/test/CodeGen/PowerPC/fp-strict-fcmp.ll

llvm/test/CodeGen/PowerPC/fp-strict-round.ll

llvm/test/CodeGen/PowerPC/fp-strict.ll

llvm/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll

llvm/test/CodeGen/PowerPC/fpscr-intrinsics.ll

llvm/test/CodeGen/PowerPC/frounds.ll

llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll

llvm/test/CodeGen/PowerPC/funnel-shift.ll

llvm/test/CodeGen/PowerPC/handle-f16-storage-type.ll

llvm/test/CodeGen/PowerPC/huge-frame-call.ll

llvm/test/CodeGen/PowerPC/huge-frame-size.ll

llvm/test/CodeGen/PowerPC/int128_ldst.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr10 \ ; RUN: -mcpu=pwr10 \
; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-P10 ; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-P10
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr10 \ ; RUN: -mcpu=pwr10 \
; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-P10 ; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-P10
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr9 \ ; RUN: -mcpu=pwr9 \
; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10,CHECK-P9 ; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr9 \ ; RUN: -mcpu=pwr9 \
; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10,CHECK-P9 ; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 \ ; RUN: -mcpu=pwr8 \
; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10,CHECK-P8 ; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr8 \ ; RUN: -mcpu=pwr8 \
; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10,CHECK-P8 ; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff \
; RUN: -mcpu=pwr8 \ ; RUN: -mcpu=pwr8 \
; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10,CHECK-P8 ; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local i128 @ld_0___int128___int128(i64 %ptr) { define dso_local i128 @ld_0___int128___int128(i64 %ptr) {
; CHECK-LABEL: ld_0___int128___int128: ; CHECK-LABEL: ld_0___int128___int128:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ld 5, 0(3) ; CHECK-NEXT: ld 5, 0(3)
; CHECK-NEXT: ld 4, 8(3) ; CHECK-NEXT: ld 4, 8(3)
; CHECK-NEXT: mr 3, 5 ; CHECK-NEXT: mr 3, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%0 = inttoptr i64 %ptr to ptr %0 = inttoptr i64 %ptr to ptr
%1 = load i128, ptr %0, align 16 %1 = load i128, ptr %0, align 16
ret i128 %1 ret i128 %1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local i128 @ld_unalign16___int128___int128(ptr nocapture readonly %ptr) { define dso_local i128 @ld_unalign16___int128___int128(ptr nocapture readonly %ptr) {
; CHECK-P10-LABEL: ld_unalign16___int128___int128: ; CHECK-P10-LABEL: ld_unalign16___int128___int128:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pld 5, 1(3), 0 ; CHECK-P10-NEXT: pld 5, 1(3), 0
; CHECK-P10-NEXT: pld 4, 9(3), 0 ; CHECK-P10-NEXT: pld 4, 9(3), 0
; CHECK-P10-NEXT: mr 3, 5 ; CHECK-P10-NEXT: mr 3, 5
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_unalign16___int128___int128: ; CHECK-PREP10-LABEL: ld_unalign16___int128___int128:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: li 4, 1 ; CHECK-PREP10-NEXT: li 4, 1
; CHECK-P9-NEXT: ldx 5, 3, 4 ; CHECK-PREP10-NEXT: ldx 5, 3, 4
; CHECK-P9-NEXT: li 4, 9 ; CHECK-PREP10-NEXT: li 4, 9
; CHECK-P9-NEXT: ldx 4, 3, 4 ; CHECK-PREP10-NEXT: ldx 4, 3, 4
; CHECK-P9-NEXT: mr 3, 5 ; CHECK-PREP10-NEXT: mr 3, 5
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_unalign16___int128___int128:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li 4, 1
; CHECK-P8-NEXT: li 6, 9
; CHECK-P8-NEXT: ldx 5, 3, 4
; CHECK-P8-NEXT: ldx 4, 3, 6
; CHECK-P8-NEXT: mr 3, 5
; CHECK-P8-NEXT: blr
entry: entry:
%add.ptr = getelementptr inbounds i8, ptr %ptr, i64 1 %add.ptr = getelementptr inbounds i8, ptr %ptr, i64 1
%0 = load i128, ptr %add.ptr, align 16 %0 = load i128, ptr %add.ptr, align 16
ret i128 %0 ret i128 %0
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local i128 @ld_align16___int128___int128(ptr nocapture readonly %ptr) { define dso_local i128 @ld_align16___int128___int128(ptr nocapture readonly %ptr) {
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define dso_local i128 @ld_disjoint_unalign16___int128___int128(i64 %ptr) { define dso_local i128 @ld_disjoint_unalign16___int128___int128(i64 %ptr) {
; CHECK-P10-LABEL: ld_disjoint_unalign16___int128___int128: ; CHECK-P10-LABEL: ld_disjoint_unalign16___int128___int128:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: rldicr 4, 3, 0, 51 ; CHECK-P10-NEXT: rldicr 4, 3, 0, 51
; CHECK-P10-NEXT: pld 3, 6(4), 0 ; CHECK-P10-NEXT: pld 3, 6(4), 0
; CHECK-P10-NEXT: pld 4, 14(4), 0 ; CHECK-P10-NEXT: pld 4, 14(4), 0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_disjoint_unalign16___int128___int128: ; CHECK-PREP10-LABEL: ld_disjoint_unalign16___int128___int128:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: rldicr 4, 3, 0, 51 ; CHECK-PREP10-NEXT: rldicr 4, 3, 0, 51
; CHECK-P9-NEXT: li 3, 6 ; CHECK-PREP10-NEXT: li 3, 6
; CHECK-P9-NEXT: li 5, 14 ; CHECK-PREP10-NEXT: li 5, 14
; CHECK-P9-NEXT: ldx 3, 4, 3 ; CHECK-PREP10-NEXT: ldx 3, 4, 3
; CHECK-P9-NEXT: ldx 4, 4, 5 ; CHECK-PREP10-NEXT: ldx 4, 4, 5
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_unalign16___int128___int128:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li 4, 6
; CHECK-P8-NEXT: rldicr 5, 3, 0, 51
; CHECK-P8-NEXT: li 6, 14
; CHECK-P8-NEXT: ldx 3, 5, 4
; CHECK-P8-NEXT: ldx 4, 5, 6
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%or = or i64 %and, 6 %or = or i64 %and, 6
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%1 = load i128, ptr %0, align 16 %1 = load i128, ptr %0, align 16
ret i128 %1 ret i128 %1
} }
Show All 33 Lines
define dso_local i128 @ld_disjoint_unalign32___int128___int128(i64 %ptr) { define dso_local i128 @ld_disjoint_unalign32___int128___int128(i64 %ptr) {
; CHECK-P10-LABEL: ld_disjoint_unalign32___int128___int128: ; CHECK-P10-LABEL: ld_disjoint_unalign32___int128___int128:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: rldicr 4, 3, 0, 43 ; CHECK-P10-NEXT: rldicr 4, 3, 0, 43
; CHECK-P10-NEXT: pld 3, 99999(4), 0 ; CHECK-P10-NEXT: pld 3, 99999(4), 0
; CHECK-P10-NEXT: pld 4, 100007(4), 0 ; CHECK-P10-NEXT: pld 4, 100007(4), 0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_disjoint_unalign32___int128___int128: ; CHECK-PREP10-LABEL: ld_disjoint_unalign32___int128___int128:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis 5, 1 ; CHECK-PREP10-NEXT: lis 5, 1
; CHECK-P9-NEXT: rldicr 4, 3, 0, 43 ; CHECK-PREP10-NEXT: rldicr 4, 3, 0, 43
; CHECK-P9-NEXT: ori 3, 5, 34463 ; CHECK-PREP10-NEXT: ori 3, 5, 34463
; CHECK-P9-NEXT: ori 5, 5, 34471 ; CHECK-PREP10-NEXT: ori 5, 5, 34471
; CHECK-P9-NEXT: ldx 3, 4, 3 ; CHECK-PREP10-NEXT: ldx 3, 4, 3
; CHECK-P9-NEXT: ldx 4, 4, 5 ; CHECK-PREP10-NEXT: ldx 4, 4, 5
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_unalign32___int128___int128:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis 4, 1
; CHECK-P8-NEXT: rldicr 5, 3, 0, 43
; CHECK-P8-NEXT: ori 3, 4, 34463
; CHECK-P8-NEXT: ori 4, 4, 34471
; CHECK-P8-NEXT: ldx 3, 5, 3
; CHECK-P8-NEXT: ldx 4, 5, 4
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1048576 %and = and i64 %ptr, -1048576
%or = or i64 %and, 99999 %or = or i64 %and, 99999
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%1 = load i128, ptr %0, align 16 %1 = load i128, ptr %0, align 16
ret i128 %1 ret i128 %1
} }
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; CHECK-P10-NEXT: pli 3, 3567587329 ; CHECK-P10-NEXT: pli 3, 3567587329
; CHECK-P10-NEXT: rldimi 3, 5, 32, 0 ; CHECK-P10-NEXT: rldimi 3, 5, 32, 0
; CHECK-P10-NEXT: pli 6, 3567587337 ; CHECK-P10-NEXT: pli 6, 3567587337
; CHECK-P10-NEXT: rldimi 6, 5, 32, 0 ; CHECK-P10-NEXT: rldimi 6, 5, 32, 0
; CHECK-P10-NEXT: ldx 3, 4, 3 ; CHECK-P10-NEXT: ldx 3, 4, 3
; CHECK-P10-NEXT: ldx 4, 4, 6 ; CHECK-P10-NEXT: ldx 4, 4, 6
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_disjoint_unalign64___int128___int128: ; CHECK-PREP10-LABEL: ld_disjoint_unalign64___int128___int128:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: rldicr 4, 3, 0, 23 ; CHECK-PREP10-NEXT: rldicr 4, 3, 0, 23
; CHECK-P9-NEXT: li 3, 29 ; CHECK-PREP10-NEXT: li 3, 29
; CHECK-P9-NEXT: rldic 3, 3, 35, 24 ; CHECK-PREP10-NEXT: rldic 3, 3, 35, 24
; CHECK-P9-NEXT: oris 5, 3, 54437 ; CHECK-PREP10-NEXT: oris 5, 3, 54437
; CHECK-P9-NEXT: ori 3, 5, 4097 ; CHECK-PREP10-NEXT: ori 3, 5, 4097
; CHECK-P9-NEXT: ori 5, 5, 4105 ; CHECK-PREP10-NEXT: ori 5, 5, 4105
; CHECK-P9-NEXT: ldx 3, 4, 3 ; CHECK-PREP10-NEXT: ldx 3, 4, 3
; CHECK-P9-NEXT: ldx 4, 4, 5 ; CHECK-PREP10-NEXT: ldx 4, 4, 5
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_unalign64___int128___int128:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li 4, 29
; CHECK-P8-NEXT: rldicr 5, 3, 0, 23
; CHECK-P8-NEXT: rldic 4, 4, 35, 24
; CHECK-P8-NEXT: oris 3, 4, 54437
; CHECK-P8-NEXT: ori 4, 3, 4097
; CHECK-P8-NEXT: ori 6, 3, 4105
; CHECK-P8-NEXT: ldx 3, 5, 4
; CHECK-P8-NEXT: ldx 4, 5, 6
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1099511627776 %and = and i64 %ptr, -1099511627776
%or = or i64 %and, 1000000000001 %or = or i64 %and, 1000000000001
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%1 = load i128, ptr %0, align 16 %1 = load i128, ptr %0, align 16
ret i128 %1 ret i128 %1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local i128 @ld_disjoint_align64___int128___int128(i64 %ptr) { define dso_local i128 @ld_disjoint_align64___int128___int128(i64 %ptr) {
; CHECK-P10-LABEL: ld_disjoint_align64___int128___int128: ; CHECK-P10-LABEL: ld_disjoint_align64___int128___int128:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: rldicr 4, 3, 0, 23 ; CHECK-P10-NEXT: rldicr 4, 3, 0, 23
; CHECK-P10-NEXT: pli 3, 244140625 ; CHECK-P10-NEXT: pli 3, 244140625
; CHECK-P10-NEXT: pli 5, 232 ; CHECK-P10-NEXT: pli 5, 232
; CHECK-P10-NEXT: rldic 3, 3, 12, 24 ; CHECK-P10-NEXT: rldic 3, 3, 12, 24
; CHECK-P10-NEXT: pli 6, 3567587336 ; CHECK-P10-NEXT: pli 6, 3567587336
; CHECK-P10-NEXT: rldimi 6, 5, 32, 0 ; CHECK-P10-NEXT: rldimi 6, 5, 32, 0
; CHECK-P10-NEXT: ldx 3, 4, 3 ; CHECK-P10-NEXT: ldx 3, 4, 3
; CHECK-P10-NEXT: ldx 4, 4, 6 ; CHECK-P10-NEXT: ldx 4, 4, 6
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_disjoint_align64___int128___int128: ; CHECK-PREP10-LABEL: ld_disjoint_align64___int128___int128:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: li 5, 29 ; CHECK-PREP10-NEXT: li 5, 29
; CHECK-P9-NEXT: rldicr 4, 3, 0, 23 ; CHECK-PREP10-NEXT: rldicr 4, 3, 0, 23
; CHECK-P9-NEXT: lis 3, 3725 ; CHECK-PREP10-NEXT: lis 3, 3725
; CHECK-P9-NEXT: rldic 5, 5, 35, 24 ; CHECK-PREP10-NEXT: rldic 5, 5, 35, 24
; CHECK-P9-NEXT: ori 3, 3, 19025 ; CHECK-PREP10-NEXT: ori 3, 3, 19025
; CHECK-P9-NEXT: oris 5, 5, 54437 ; CHECK-PREP10-NEXT: oris 5, 5, 54437
; CHECK-P9-NEXT: rldic 3, 3, 12, 24 ; CHECK-PREP10-NEXT: rldic 3, 3, 12, 24
; CHECK-P9-NEXT: ori 5, 5, 4104 ; CHECK-PREP10-NEXT: ori 5, 5, 4104
; CHECK-P9-NEXT: ldx 3, 4, 3 ; CHECK-PREP10-NEXT: ldx 3, 4, 3
; CHECK-P9-NEXT: ldx 4, 4, 5 ; CHECK-PREP10-NEXT: ldx 4, 4, 5
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align64___int128___int128:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li 4, 29
; CHECK-P8-NEXT: rldicr 5, 3, 0, 23
; CHECK-P8-NEXT: lis 3, 3725
; CHECK-P8-NEXT: rldic 4, 4, 35, 24
; CHECK-P8-NEXT: ori 3, 3, 19025
; CHECK-P8-NEXT: oris 4, 4, 54437
; CHECK-P8-NEXT: rldic 3, 3, 12, 24
; CHECK-P8-NEXT: ori 4, 4, 4104
; CHECK-P8-NEXT: ldx 3, 5, 3
; CHECK-P8-NEXT: ldx 4, 5, 4
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1099511627776 %and = and i64 %ptr, -1099511627776
%or = or i64 %and, 1000000000000 %or = or i64 %and, 1000000000000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
%1 = load i128, ptr %0, align 4096 %1 = load i128, ptr %0, align 4096
ret i128 %1 ret i128 %1
} }
Show All 28 Lines
; CHECK-P10-LABEL: ld_cst_unalign32___int128___int128: ; CHECK-P10-LABEL: ld_cst_unalign32___int128___int128:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli 3, 99999 ; CHECK-P10-NEXT: pli 3, 99999
; CHECK-P10-NEXT: pli 4, 100007 ; CHECK-P10-NEXT: pli 4, 100007
; CHECK-P10-NEXT: ld 3, 0(3) ; CHECK-P10-NEXT: ld 3, 0(3)
; CHECK-P10-NEXT: ld 4, 0(4) ; CHECK-P10-NEXT: ld 4, 0(4)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_cst_unalign32___int128___int128: ; CHECK-PREP10-LABEL: ld_cst_unalign32___int128___int128:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis 4, 1 ; CHECK-PREP10-NEXT: lis 4, 1
; CHECK-P9-NEXT: ori 3, 4, 34463 ; CHECK-PREP10-NEXT: ori 3, 4, 34463
; CHECK-P9-NEXT: ori 4, 4, 34471 ; CHECK-PREP10-NEXT: ori 4, 4, 34471
; CHECK-P9-NEXT: ld 3, 0(3) ; CHECK-PREP10-NEXT: ld 3, 0(3)
; CHECK-P9-NEXT: ld 4, 0(4) ; CHECK-PREP10-NEXT: ld 4, 0(4)
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_unalign32___int128___int128:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis 3, 1
; CHECK-P8-NEXT: ori 4, 3, 34463
; CHECK-P8-NEXT: ori 5, 3, 34471
; CHECK-P8-NEXT: ld 3, 0(4)
; CHECK-P8-NEXT: ld 4, 0(5)
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load i128, ptr inttoptr (i64 99999 to ptr), align 16 %0 = load i128, ptr inttoptr (i64 99999 to ptr), align 16
ret i128 %0 ret i128 %0
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local i128 @ld_cst_align32___int128___int128() { define dso_local i128 @ld_cst_align32___int128___int128() {
; CHECK-LABEL: ld_cst_align32___int128___int128: ; CHECK-LABEL: ld_cst_align32___int128___int128:
Show All 15 Lines
; CHECK-P10-NEXT: pli 3, 3567587329 ; CHECK-P10-NEXT: pli 3, 3567587329
; CHECK-P10-NEXT: rldimi 3, 4, 32, 0 ; CHECK-P10-NEXT: rldimi 3, 4, 32, 0
; CHECK-P10-NEXT: pli 5, 3567587337 ; CHECK-P10-NEXT: pli 5, 3567587337
; CHECK-P10-NEXT: rldimi 5, 4, 32, 0 ; CHECK-P10-NEXT: rldimi 5, 4, 32, 0
; CHECK-P10-NEXT: ld 3, 0(3) ; CHECK-P10-NEXT: ld 3, 0(3)
; CHECK-P10-NEXT: ld 4, 0(5) ; CHECK-P10-NEXT: ld 4, 0(5)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_cst_unalign64___int128___int128: ; CHECK-PREP10-LABEL: ld_cst_unalign64___int128___int128:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: li 3, 29 ; CHECK-PREP10-NEXT: li 3, 29
; CHECK-P9-NEXT: rldic 3, 3, 35, 24 ; CHECK-PREP10-NEXT: rldic 3, 3, 35, 24
; CHECK-P9-NEXT: oris 4, 3, 54437 ; CHECK-PREP10-NEXT: oris 4, 3, 54437
; CHECK-P9-NEXT: ori 3, 4, 4097 ; CHECK-PREP10-NEXT: ori 3, 4, 4097
; CHECK-P9-NEXT: ori 4, 4, 4105 ; CHECK-PREP10-NEXT: ori 4, 4, 4105
; CHECK-P9-NEXT: ld 3, 0(3) ; CHECK-PREP10-NEXT: ld 3, 0(3)
; CHECK-P9-NEXT: ld 4, 0(4) ; CHECK-PREP10-NEXT: ld 4, 0(4)
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_unalign64___int128___int128:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li 3, 29
; CHECK-P8-NEXT: rldic 3, 3, 35, 24
; CHECK-P8-NEXT: oris 3, 3, 54437
; CHECK-P8-NEXT: ori 4, 3, 4097
; CHECK-P8-NEXT: ori 5, 3, 4105
; CHECK-P8-NEXT: ld 3, 0(4)
; CHECK-P8-NEXT: ld 4, 0(5)
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load i128, ptr inttoptr (i64 1000000000001 to ptr), align 16 %0 = load i128, ptr inttoptr (i64 1000000000001 to ptr), align 16
ret i128 %0 ret i128 %0
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local i128 @ld_cst_align64___int128___int128() { define dso_local i128 @ld_cst_align64___int128___int128() {
; CHECK-P10-LABEL: ld_cst_align64___int128___int128: ; CHECK-P10-LABEL: ld_cst_align64___int128___int128:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli 3, 232 ; CHECK-P10-NEXT: pli 3, 232
; CHECK-P10-NEXT: pli 4, 3567587336 ; CHECK-P10-NEXT: pli 4, 3567587336
; CHECK-P10-NEXT: rldimi 4, 3, 32, 0 ; CHECK-P10-NEXT: rldimi 4, 3, 32, 0
; CHECK-P10-NEXT: pli 3, 244140625 ; CHECK-P10-NEXT: pli 3, 244140625
; CHECK-P10-NEXT: rldic 3, 3, 12, 24 ; CHECK-P10-NEXT: rldic 3, 3, 12, 24
; CHECK-P10-NEXT: ld 4, 0(4) ; CHECK-P10-NEXT: ld 4, 0(4)
; CHECK-P10-NEXT: ld 3, 0(3) ; CHECK-P10-NEXT: ld 3, 0(3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_cst_align64___int128___int128: ; CHECK-PREP10-LABEL: ld_cst_align64___int128___int128:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: li 4, 29 ; CHECK-PREP10-NEXT: li 4, 29
; CHECK-P9-NEXT: lis 3, 3725 ; CHECK-PREP10-NEXT: lis 3, 3725
; CHECK-P9-NEXT: rldic 4, 4, 35, 24 ; CHECK-PREP10-NEXT: rldic 4, 4, 35, 24
; CHECK-P9-NEXT: ori 3, 3, 19025 ; CHECK-PREP10-NEXT: ori 3, 3, 19025
; CHECK-P9-NEXT: oris 4, 4, 54437 ; CHECK-PREP10-NEXT: oris 4, 4, 54437
; CHECK-P9-NEXT: rldic 3, 3, 12, 24 ; CHECK-PREP10-NEXT: rldic 3, 3, 12, 24
; CHECK-P9-NEXT: ori 4, 4, 4104 ; CHECK-PREP10-NEXT: ori 4, 4, 4104
; CHECK-P9-NEXT: ld 3, 0(3) ; CHECK-PREP10-NEXT: ld 3, 0(3)
; CHECK-P9-NEXT: ld 4, 0(4) ; CHECK-PREP10-NEXT: ld 4, 0(4)
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align64___int128___int128:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li 3, 29
; CHECK-P8-NEXT: lis 4, 3725
; CHECK-P8-NEXT: rldic 3, 3, 35, 24
; CHECK-P8-NEXT: ori 4, 4, 19025
; CHECK-P8-NEXT: oris 3, 3, 54437
; CHECK-P8-NEXT: rldic 4, 4, 12, 24
; CHECK-P8-NEXT: ori 5, 3, 4104
; CHECK-P8-NEXT: ld 3, 0(4)
; CHECK-P8-NEXT: ld 4, 0(5)
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load i128, ptr inttoptr (i64 1000000000000 to ptr), align 4096 %0 = load i128, ptr inttoptr (i64 1000000000000 to ptr), align 4096
ret i128 %0 ret i128 %0
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_0__int128___int128(i64 %ptr, i128 %str) { define dso_local void @st_0__int128___int128(i64 %ptr, i128 %str) {
; CHECK-LABEL: st_0__int128___int128: ; CHECK-LABEL: st_0__int128___int128:
Show All 10 Lines
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_unalign16__int128___int128(ptr nocapture %ptr, i128 %str) { define dso_local void @st_unalign16__int128___int128(ptr nocapture %ptr, i128 %str) {
; CHECK-P10-LABEL: st_unalign16__int128___int128: ; CHECK-P10-LABEL: st_unalign16__int128___int128:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pstd 5, 9(3), 0 ; CHECK-P10-NEXT: pstd 5, 9(3), 0
; CHECK-P10-NEXT: pstd 4, 1(3), 0 ; CHECK-P10-NEXT: pstd 4, 1(3), 0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_unalign16__int128___int128: ; CHECK-PREP10-LABEL: st_unalign16__int128___int128:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: li 6, 9 ; CHECK-PREP10-NEXT: li 6, 9
; CHECK-P9-NEXT: stdx 5, 3, 6 ; CHECK-PREP10-NEXT: stdx 5, 3, 6
; CHECK-P9-NEXT: li 5, 1 ; CHECK-PREP10-NEXT: li 5, 1
; CHECK-P9-NEXT: stdx 4, 3, 5 ; CHECK-PREP10-NEXT: stdx 4, 3, 5
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_unalign16__int128___int128:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li 6, 9
; CHECK-P8-NEXT: li 7, 1
; CHECK-P8-NEXT: stdx 5, 3, 6
; CHECK-P8-NEXT: stdx 4, 3, 7
; CHECK-P8-NEXT: blr
entry: entry:
%add.ptr = getelementptr inbounds i8, ptr %ptr, i64 1 %add.ptr = getelementptr inbounds i8, ptr %ptr, i64 1
store i128 %str, ptr %add.ptr, align 16 store i128 %str, ptr %add.ptr, align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_align16__int128___int128(ptr nocapture %ptr, i128 %str) { define dso_local void @st_align16__int128___int128(ptr nocapture %ptr, i128 %str) {
▲ Show 20 Lines • Show All 169 Lines • ▼ Show 20 Lines
define dso_local void @st_disjoint_unalign16__int128___int128(i64 %ptr, i128 %str) { define dso_local void @st_disjoint_unalign16__int128___int128(i64 %ptr, i128 %str) {
; CHECK-P10-LABEL: st_disjoint_unalign16__int128___int128: ; CHECK-P10-LABEL: st_disjoint_unalign16__int128___int128:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: rldicr 3, 3, 0, 51 ; CHECK-P10-NEXT: rldicr 3, 3, 0, 51
; CHECK-P10-NEXT: pstd 5, 14(3), 0 ; CHECK-P10-NEXT: pstd 5, 14(3), 0
; CHECK-P10-NEXT: pstd 4, 6(3), 0 ; CHECK-P10-NEXT: pstd 4, 6(3), 0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_disjoint_unalign16__int128___int128: ; CHECK-PREP10-LABEL: st_disjoint_unalign16__int128___int128:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: rldicr 3, 3, 0, 51 ; CHECK-PREP10-NEXT: rldicr 3, 3, 0, 51
; CHECK-P9-NEXT: li 6, 14 ; CHECK-PREP10-NEXT: li 6, 14
; CHECK-P9-NEXT: stdx 5, 3, 6 ; CHECK-PREP10-NEXT: stdx 5, 3, 6
; CHECK-P9-NEXT: li 5, 6 ; CHECK-PREP10-NEXT: li 5, 6
; CHECK-P9-NEXT: stdx 4, 3, 5 ; CHECK-PREP10-NEXT: stdx 4, 3, 5
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_unalign16__int128___int128:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li 6, 14
; CHECK-P8-NEXT: rldicr 3, 3, 0, 51
; CHECK-P8-NEXT: li 7, 6
; CHECK-P8-NEXT: stdx 5, 3, 6
; CHECK-P8-NEXT: stdx 4, 3, 7
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%or = or i64 %and, 6 %or = or i64 %and, 6
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
store i128 %str, ptr %0, align 16 store i128 %str, ptr %0, align 16
ret void ret void
} }
Show All 33 Lines
define dso_local void @st_disjoint_unalign32__int128___int128(i64 %ptr, i128 %str) { define dso_local void @st_disjoint_unalign32__int128___int128(i64 %ptr, i128 %str) {
; CHECK-P10-LABEL: st_disjoint_unalign32__int128___int128: ; CHECK-P10-LABEL: st_disjoint_unalign32__int128___int128:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: rldicr 3, 3, 0, 43 ; CHECK-P10-NEXT: rldicr 3, 3, 0, 43
; CHECK-P10-NEXT: pstd 5, 100007(3), 0 ; CHECK-P10-NEXT: pstd 5, 100007(3), 0
; CHECK-P10-NEXT: pstd 4, 99999(3), 0 ; CHECK-P10-NEXT: pstd 4, 99999(3), 0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_disjoint_unalign32__int128___int128: ; CHECK-PREP10-LABEL: st_disjoint_unalign32__int128___int128:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis 6, 1 ; CHECK-PREP10-NEXT: lis 6, 1
; CHECK-P9-NEXT: rldicr 3, 3, 0, 43 ; CHECK-PREP10-NEXT: rldicr 3, 3, 0, 43
; CHECK-P9-NEXT: ori 7, 6, 34471 ; CHECK-PREP10-NEXT: ori 7, 6, 34471
; CHECK-P9-NEXT: stdx 5, 3, 7 ; CHECK-PREP10-NEXT: stdx 5, 3, 7
; CHECK-P9-NEXT: ori 5, 6, 34463 ; CHECK-PREP10-NEXT: ori 5, 6, 34463
; CHECK-P9-NEXT: stdx 4, 3, 5 ; CHECK-PREP10-NEXT: stdx 4, 3, 5
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_unalign32__int128___int128:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis 6, 1
; CHECK-P8-NEXT: rldicr 3, 3, 0, 43
; CHECK-P8-NEXT: ori 7, 6, 34471
; CHECK-P8-NEXT: ori 6, 6, 34463
; CHECK-P8-NEXT: stdx 5, 3, 7
; CHECK-P8-NEXT: stdx 4, 3, 6
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1048576 %and = and i64 %ptr, -1048576
%or = or i64 %and, 99999 %or = or i64 %and, 99999
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
store i128 %str, ptr %0, align 16 store i128 %str, ptr %0, align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_disjoint_align32__int128___int128(i64 %ptr, i128 %str) { define dso_local void @st_disjoint_align32__int128___int128(i64 %ptr, i128 %str) {
; CHECK-P10-LABEL: st_disjoint_align32__int128___int128: ; CHECK-P10-LABEL: st_disjoint_align32__int128___int128:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: lis 6, -15264 ; CHECK-P10-NEXT: lis 6, -15264
; CHECK-P10-NEXT: and 3, 3, 6 ; CHECK-P10-NEXT: and 3, 3, 6
; CHECK-P10-NEXT: pstd 5, 999990008(3), 0 ; CHECK-P10-NEXT: pstd 5, 999990008(3), 0
; CHECK-P10-NEXT: pstd 4, 999990000(3), 0 ; CHECK-P10-NEXT: pstd 4, 999990000(3), 0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_disjoint_align32__int128___int128: ; CHECK-PREP10-LABEL: st_disjoint_align32__int128___int128:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis 6, -15264 ; CHECK-PREP10-NEXT: lis 6, -15264
; CHECK-P9-NEXT: and 3, 3, 6 ; CHECK-PREP10-NEXT: and 3, 3, 6
; CHECK-P9-NEXT: lis 6, 15258 ; CHECK-PREP10-NEXT: lis 6, 15258
; CHECK-P9-NEXT: ori 7, 6, 41720 ; CHECK-PREP10-NEXT: ori 7, 6, 41720
; CHECK-P9-NEXT: stdx 5, 3, 7 ; CHECK-PREP10-NEXT: stdx 5, 3, 7
; CHECK-P9-NEXT: ori 5, 6, 41712 ; CHECK-PREP10-NEXT: ori 5, 6, 41712
; CHECK-P9-NEXT: stdx 4, 3, 5 ; CHECK-PREP10-NEXT: stdx 4, 3, 5
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align32__int128___int128:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis 6, -15264
; CHECK-P8-NEXT: lis 7, 15258
; CHECK-P8-NEXT: and 3, 3, 6
; CHECK-P8-NEXT: ori 6, 7, 41720
; CHECK-P8-NEXT: ori 7, 7, 41712
; CHECK-P8-NEXT: stdx 5, 3, 6
; CHECK-P8-NEXT: stdx 4, 3, 7
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1000341504 %and = and i64 %ptr, -1000341504
%or = or i64 %and, 999990000 %or = or i64 %and, 999990000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
store i128 %str, ptr %0, align 16 store i128 %str, ptr %0, align 16
ret void ret void
} }
Show All 35 Lines
; CHECK-P10-NEXT: rldicr 3, 3, 0, 23 ; CHECK-P10-NEXT: rldicr 3, 3, 0, 23
; CHECK-P10-NEXT: rldimi 7, 6, 32, 0 ; CHECK-P10-NEXT: rldimi 7, 6, 32, 0
; CHECK-P10-NEXT: stdx 5, 3, 7 ; CHECK-P10-NEXT: stdx 5, 3, 7
; CHECK-P10-NEXT: pli 5, 3567587329 ; CHECK-P10-NEXT: pli 5, 3567587329
; CHECK-P10-NEXT: rldimi 5, 6, 32, 0 ; CHECK-P10-NEXT: rldimi 5, 6, 32, 0
; CHECK-P10-NEXT: stdx 4, 3, 5 ; CHECK-P10-NEXT: stdx 4, 3, 5
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_disjoint_unalign64__int128___int128: ; CHECK-PREP10-LABEL: st_disjoint_unalign64__int128___int128:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: li 6, 29 ; CHECK-PREP10-NEXT: li 6, 29
; CHECK-P9-NEXT: rldicr 3, 3, 0, 23 ; CHECK-PREP10-NEXT: rldicr 3, 3, 0, 23
; CHECK-P9-NEXT: rldic 6, 6, 35, 24 ; CHECK-PREP10-NEXT: rldic 6, 6, 35, 24
; CHECK-P9-NEXT: oris 6, 6, 54437 ; CHECK-PREP10-NEXT: oris 6, 6, 54437
; CHECK-P9-NEXT: ori 7, 6, 4105 ; CHECK-PREP10-NEXT: ori 7, 6, 4105
; CHECK-P9-NEXT: stdx 5, 3, 7 ; CHECK-PREP10-NEXT: stdx 5, 3, 7
; CHECK-P9-NEXT: ori 5, 6, 4097 ; CHECK-PREP10-NEXT: ori 5, 6, 4097
; CHECK-P9-NEXT: stdx 4, 3, 5 ; CHECK-PREP10-NEXT: stdx 4, 3, 5
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_unalign64__int128___int128:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li 6, 29
; CHECK-P8-NEXT: rldicr 3, 3, 0, 23
; CHECK-P8-NEXT: rldic 6, 6, 35, 24
; CHECK-P8-NEXT: oris 6, 6, 54437
; CHECK-P8-NEXT: ori 7, 6, 4105
; CHECK-P8-NEXT: ori 6, 6, 4097
; CHECK-P8-NEXT: stdx 5, 3, 7
; CHECK-P8-NEXT: stdx 4, 3, 6
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1099511627776 %and = and i64 %ptr, -1099511627776
%or = or i64 %and, 1000000000001 %or = or i64 %and, 1000000000001
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
store i128 %str, ptr %0, align 16 store i128 %str, ptr %0, align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_disjoint_align64__int128___int128(i64 %ptr, i128 %str) { define dso_local void @st_disjoint_align64__int128___int128(i64 %ptr, i128 %str) {
; CHECK-P10-LABEL: st_disjoint_align64__int128___int128: ; CHECK-P10-LABEL: st_disjoint_align64__int128___int128:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli 6, 232 ; CHECK-P10-NEXT: pli 6, 232
; CHECK-P10-NEXT: pli 7, 3567587336 ; CHECK-P10-NEXT: pli 7, 3567587336
; CHECK-P10-NEXT: rldicr 3, 3, 0, 23 ; CHECK-P10-NEXT: rldicr 3, 3, 0, 23
; CHECK-P10-NEXT: rldimi 7, 6, 32, 0 ; CHECK-P10-NEXT: rldimi 7, 6, 32, 0
; CHECK-P10-NEXT: stdx 5, 3, 7 ; CHECK-P10-NEXT: stdx 5, 3, 7
; CHECK-P10-NEXT: pli 5, 244140625 ; CHECK-P10-NEXT: pli 5, 244140625
; CHECK-P10-NEXT: rldic 5, 5, 12, 24 ; CHECK-P10-NEXT: rldic 5, 5, 12, 24
; CHECK-P10-NEXT: stdx 4, 3, 5 ; CHECK-P10-NEXT: stdx 4, 3, 5
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_disjoint_align64__int128___int128: ; CHECK-PREP10-LABEL: st_disjoint_align64__int128___int128:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis 6, 3725 ; CHECK-PREP10-NEXT: lis 6, 3725
; CHECK-P9-NEXT: rldicr 3, 3, 0, 23 ; CHECK-PREP10-NEXT: rldicr 3, 3, 0, 23
; CHECK-P9-NEXT: ori 6, 6, 19025 ; CHECK-PREP10-NEXT: ori 6, 6, 19025
; CHECK-P9-NEXT: rldic 6, 6, 12, 24 ; CHECK-PREP10-NEXT: rldic 6, 6, 12, 24
; CHECK-P9-NEXT: stdx 4, 3, 6 ; CHECK-PREP10-NEXT: stdx 4, 3, 6
; CHECK-P9-NEXT: li 4, 29 ; CHECK-PREP10-NEXT: li 4, 29
; CHECK-P9-NEXT: rldic 4, 4, 35, 24 ; CHECK-PREP10-NEXT: rldic 4, 4, 35, 24
; CHECK-P9-NEXT: oris 4, 4, 54437 ; CHECK-PREP10-NEXT: oris 4, 4, 54437
; CHECK-P9-NEXT: ori 4, 4, 4104 ; CHECK-PREP10-NEXT: ori 4, 4, 4104
; CHECK-P9-NEXT: stdx 5, 3, 4 ; CHECK-PREP10-NEXT: stdx 5, 3, 4
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align64__int128___int128:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li 6, 29
; CHECK-P8-NEXT: lis 7, 3725
; CHECK-P8-NEXT: rldic 6, 6, 35, 24
; CHECK-P8-NEXT: ori 7, 7, 19025
; CHECK-P8-NEXT: oris 6, 6, 54437
; CHECK-P8-NEXT: rldicr 3, 3, 0, 23
; CHECK-P8-NEXT: rldic 7, 7, 12, 24
; CHECK-P8-NEXT: ori 6, 6, 4104
; CHECK-P8-NEXT: stdx 4, 3, 7
; CHECK-P8-NEXT: stdx 5, 3, 6
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -1099511627776 %and = and i64 %ptr, -1099511627776
%or = or i64 %and, 1000000000000 %or = or i64 %and, 1000000000000
%0 = inttoptr i64 %or to ptr %0 = inttoptr i64 %or to ptr
store i128 %str, ptr %0, align 4096 store i128 %str, ptr %0, align 4096
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_unalign16__int128___int128(i128 %str) { define dso_local void @st_cst_unalign16__int128___int128(i128 %str) {
; CHECK-P10-LABEL: st_cst_unalign16__int128___int128: ; CHECK-LABEL: st_cst_unalign16__int128___int128:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: li 5, 263 ; CHECK-NEXT: li 5, 263
; CHECK-P10-NEXT: std 4, 0(5) ; CHECK-NEXT: std 4, 0(5)
; CHECK-P10-NEXT: li 4, 255 ; CHECK-NEXT: li 4, 255
; CHECK-P10-NEXT: std 3, 0(4) ; CHECK-NEXT: std 3, 0(4)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_cst_unalign16__int128___int128:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: li 5, 263
; CHECK-P9-NEXT: std 4, 0(5)
; CHECK-P9-NEXT: li 4, 255
; CHECK-P9-NEXT: std 3, 0(4)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_cst_unalign16__int128___int128:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li 5, 263
; CHECK-P8-NEXT: li 6, 255
; CHECK-P8-NEXT: std 4, 0(5)
; CHECK-P8-NEXT: std 3, 0(6)
; CHECK-P8-NEXT: blr
entry: entry:
store i128 %str, ptr inttoptr (i64 255 to ptr), align 16 store i128 %str, ptr inttoptr (i64 255 to ptr), align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align16__int128___int128(i128 %str) { define dso_local void @st_cst_align16__int128___int128(i128 %str) {
; CHECK-LABEL: st_cst_align16__int128___int128: ; CHECK-LABEL: st_cst_align16__int128___int128:
Show All 11 Lines
; CHECK-P10-LABEL: st_cst_unalign32__int128___int128: ; CHECK-P10-LABEL: st_cst_unalign32__int128___int128:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli 5, 100007 ; CHECK-P10-NEXT: pli 5, 100007
; CHECK-P10-NEXT: std 4, 0(5) ; CHECK-P10-NEXT: std 4, 0(5)
; CHECK-P10-NEXT: pli 4, 99999 ; CHECK-P10-NEXT: pli 4, 99999
; CHECK-P10-NEXT: std 3, 0(4) ; CHECK-P10-NEXT: std 3, 0(4)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_cst_unalign32__int128___int128: ; CHECK-PREP10-LABEL: st_cst_unalign32__int128___int128:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis 5, 1 ; CHECK-PREP10-NEXT: lis 5, 1
; CHECK-P9-NEXT: ori 6, 5, 34471 ; CHECK-PREP10-NEXT: ori 6, 5, 34471
; CHECK-P9-NEXT: std 4, 0(6) ; CHECK-PREP10-NEXT: std 4, 0(6)
; CHECK-P9-NEXT: ori 4, 5, 34463 ; CHECK-PREP10-NEXT: ori 4, 5, 34463
; CHECK-P9-NEXT: std 3, 0(4) ; CHECK-PREP10-NEXT: std 3, 0(4)
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_cst_unalign32__int128___int128:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis 5, 1
; CHECK-P8-NEXT: ori 6, 5, 34471
; CHECK-P8-NEXT: ori 5, 5, 34463
; CHECK-P8-NEXT: std 4, 0(6)
; CHECK-P8-NEXT: std 3, 0(5)
; CHECK-P8-NEXT: blr
entry: entry:
store i128 %str, ptr inttoptr (i64 99999 to ptr), align 16 store i128 %str, ptr inttoptr (i64 99999 to ptr), align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align32__int128___int128(i128 %str) { define dso_local void @st_cst_align32__int128___int128(i128 %str) {
; CHECK-LABEL: st_cst_align32__int128___int128: ; CHECK-LABEL: st_cst_align32__int128___int128:
Show All 15 Lines
; CHECK-P10-NEXT: pli 6, 3567587337 ; CHECK-P10-NEXT: pli 6, 3567587337
; CHECK-P10-NEXT: rldimi 6, 5, 32, 0 ; CHECK-P10-NEXT: rldimi 6, 5, 32, 0
; CHECK-P10-NEXT: std 4, 0(6) ; CHECK-P10-NEXT: std 4, 0(6)
; CHECK-P10-NEXT: pli 4, 3567587329 ; CHECK-P10-NEXT: pli 4, 3567587329
; CHECK-P10-NEXT: rldimi 4, 5, 32, 0 ; CHECK-P10-NEXT: rldimi 4, 5, 32, 0
; CHECK-P10-NEXT: std 3, 0(4) ; CHECK-P10-NEXT: std 3, 0(4)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_cst_unalign64__int128___int128: ; CHECK-PREP10-LABEL: st_cst_unalign64__int128___int128:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: li 5, 29 ; CHECK-PREP10-NEXT: li 5, 29
; CHECK-P9-NEXT: rldic 5, 5, 35, 24 ; CHECK-PREP10-NEXT: rldic 5, 5, 35, 24
; CHECK-P9-NEXT: oris 5, 5, 54437 ; CHECK-PREP10-NEXT: oris 5, 5, 54437
; CHECK-P9-NEXT: ori 6, 5, 4105 ; CHECK-PREP10-NEXT: ori 6, 5, 4105
; CHECK-P9-NEXT: std 4, 0(6) ; CHECK-PREP10-NEXT: std 4, 0(6)
; CHECK-P9-NEXT: ori 4, 5, 4097 ; CHECK-PREP10-NEXT: ori 4, 5, 4097
; CHECK-P9-NEXT: std 3, 0(4) ; CHECK-PREP10-NEXT: std 3, 0(4)
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_cst_unalign64__int128___int128:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li 5, 29
; CHECK-P8-NEXT: rldic 5, 5, 35, 24
; CHECK-P8-NEXT: oris 5, 5, 54437
; CHECK-P8-NEXT: ori 6, 5, 4105
; CHECK-P8-NEXT: ori 5, 5, 4097
; CHECK-P8-NEXT: std 4, 0(6)
; CHECK-P8-NEXT: std 3, 0(5)
; CHECK-P8-NEXT: blr
entry: entry:
store i128 %str, ptr inttoptr (i64 1000000000001 to ptr), align 16 store i128 %str, ptr inttoptr (i64 1000000000001 to ptr), align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align64__int128___int128(i128 %str) { define dso_local void @st_cst_align64__int128___int128(i128 %str) {
; CHECK-P10-LABEL: st_cst_align64__int128___int128: ; CHECK-P10-LABEL: st_cst_align64__int128___int128:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli 5, 232 ; CHECK-P10-NEXT: pli 5, 232
; CHECK-P10-NEXT: pli 6, 3567587336 ; CHECK-P10-NEXT: pli 6, 3567587336
; CHECK-P10-NEXT: rldimi 6, 5, 32, 0 ; CHECK-P10-NEXT: rldimi 6, 5, 32, 0
; CHECK-P10-NEXT: std 4, 0(6) ; CHECK-P10-NEXT: std 4, 0(6)
; CHECK-P10-NEXT: pli 4, 244140625 ; CHECK-P10-NEXT: pli 4, 244140625
; CHECK-P10-NEXT: rldic 4, 4, 12, 24 ; CHECK-P10-NEXT: rldic 4, 4, 12, 24
; CHECK-P10-NEXT: std 3, 0(4) ; CHECK-P10-NEXT: std 3, 0(4)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_cst_align64__int128___int128: ; CHECK-PREP10-LABEL: st_cst_align64__int128___int128:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis 5, 3725 ; CHECK-PREP10-NEXT: lis 5, 3725
; CHECK-P9-NEXT: ori 5, 5, 19025 ; CHECK-PREP10-NEXT: ori 5, 5, 19025
; CHECK-P9-NEXT: rldic 5, 5, 12, 24 ; CHECK-PREP10-NEXT: rldic 5, 5, 12, 24
; CHECK-P9-NEXT: std 3, 0(5) ; CHECK-PREP10-NEXT: std 3, 0(5)
; CHECK-P9-NEXT: li 3, 29 ; CHECK-PREP10-NEXT: li 3, 29
; CHECK-P9-NEXT: rldic 3, 3, 35, 24 ; CHECK-PREP10-NEXT: rldic 3, 3, 35, 24
; CHECK-P9-NEXT: oris 3, 3, 54437 ; CHECK-PREP10-NEXT: oris 3, 3, 54437
; CHECK-P9-NEXT: ori 3, 3, 4104 ; CHECK-PREP10-NEXT: ori 3, 3, 4104
; CHECK-P9-NEXT: std 4, 0(3) ; CHECK-PREP10-NEXT: std 4, 0(3)
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_cst_align64__int128___int128:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li 5, 29
; CHECK-P8-NEXT: lis 6, 3725
; CHECK-P8-NEXT: rldic 5, 5, 35, 24
; CHECK-P8-NEXT: ori 6, 6, 19025
; CHECK-P8-NEXT: oris 5, 5, 54437
; CHECK-P8-NEXT: rldic 6, 6, 12, 24
; CHECK-P8-NEXT: ori 5, 5, 4104
; CHECK-P8-NEXT: std 3, 0(6)
; CHECK-P8-NEXT: std 4, 0(5)
; CHECK-P8-NEXT: blr
entry: entry:
store i128 %str, ptr inttoptr (i64 1000000000000 to ptr), align 4096 store i128 %str, ptr inttoptr (i64 1000000000000 to ptr), align 4096
ret void ret void
} }
shchenzUnsubmitted
Done
ReplyInline Actions

Same with above

shchenz: Same with above

llvm/test/CodeGen/PowerPC/legalize-vaarg.ll

llvm/test/CodeGen/PowerPC/licm-remat.ll

llvm/test/CodeGen/PowerPC/licm-tocReg.ll

llvm/test/CodeGen/PowerPC/load-and-splat.ll

llvm/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll

llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll

llvm/test/CodeGen/PowerPC/memcmp.ll

llvm/test/CodeGen/PowerPC/memset-tail.ll

llvm/test/CodeGen/PowerPC/mergeable-string-pool-large.ll

llvm/test/CodeGen/PowerPC/mergeable-string-pool.ll

llvm/test/CodeGen/PowerPC/mma-acc-memops.ll

llvm/test/CodeGen/PowerPC/mulld.ll

llvm/test/CodeGen/PowerPC/no-ctr-loop-if-exit-in-nested-loop.ll

llvm/test/CodeGen/PowerPC/non-debug-mi-search-frspxsrsp.ll

llvm/test/CodeGen/PowerPC/p8-isel-sched.ll

llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll

llvm/test/CodeGen/PowerPC/peephole-align.ll

llvm/test/CodeGen/PowerPC/pow-025-075-intrinsic-scalar-mass-fast.ll

llvm/test/CodeGen/PowerPC/ppc-32bit-build-vector.ll

llvm/test/CodeGen/PowerPC/ppc-clear-before-return.ll

llvm/test/CodeGen/PowerPC/ppc-ctr-dead-code.ll

llvm/test/CodeGen/PowerPC/ppc-rotate-clear.ll

llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll

llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll

llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll

llvm/test/CodeGen/PowerPC/ppc64-byval-larger-struct.ll

llvm/test/CodeGen/PowerPC/ppc64-byval-multi-store.ll

llvm/test/CodeGen/PowerPC/ppc64-rop-protection-aix.ll

llvm/test/CodeGen/PowerPC/ppc64-rop-protection.ll

llvm/test/CodeGen/PowerPC/ppc64-varargs.ll

llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll

llvm/test/CodeGen/PowerPC/pr25080.ll

llvm/test/CodeGen/PowerPC/pr27078.ll

llvm/test/CodeGen/PowerPC/pr33093.ll

llvm/test/CodeGen/PowerPC/pr33547.ll

llvm/test/CodeGen/PowerPC/pr35402.ll

llvm/test/CodeGen/PowerPC/pr36292.ll

llvm/test/CodeGen/PowerPC/pr45628.ll

llvm/test/CodeGen/PowerPC/pr46759.ll

llvm/test/CodeGen/PowerPC/pr47707.ll

llvm/test/CodeGen/PowerPC/pr47830.ll

llvm/test/CodeGen/PowerPC/pr47891.ll

llvm/test/CodeGen/PowerPC/pr48388.ll

llvm/test/CodeGen/PowerPC/pr48519.ll

llvm/test/CodeGen/PowerPC/pr48527.ll

llvm/test/CodeGen/PowerPC/pr52894-32bit.ll

llvm/test/CodeGen/PowerPC/pr52894.ll

llvm/test/CodeGen/PowerPC/pr61882.ll

llvm/test/CodeGen/PowerPC/recipest.ll

llvm/test/CodeGen/PowerPC/reduce_scalarization.ll

llvm/test/CodeGen/PowerPC/register-pressure-reduction.ll

llvm/test/CodeGen/PowerPC/repeated-fp-divisors.ll

llvm/test/CodeGen/PowerPC/saddo-ssubo.ll

llvm/test/CodeGen/PowerPC/sat-add.ll

llvm/test/CodeGen/PowerPC/scalar-double-ldst.ll

llvm/test/CodeGen/PowerPC/scalar-equal.ll

llvm/test/CodeGen/PowerPC/scalar-float-ldst.ll

llvm/test/CodeGen/PowerPC/scalar-i16-ldst.ll

llvm/test/CodeGen/PowerPC/scalar-i32-ldst.ll

llvm/test/CodeGen/PowerPC/scalar-i64-ldst.ll

llvm/test/CodeGen/PowerPC/scalar-i8-ldst.ll

llvm/test/CodeGen/PowerPC/scalar_cmp.ll

llvm/test/CodeGen/PowerPC/scalar_vector_test_4.ll

llvm/test/CodeGen/PowerPC/scalars-in-altivec-regs.ll

llvm/test/CodeGen/PowerPC/scheduling-mem-dependency.ll

llvm/test/CodeGen/PowerPC/select-constant-xor.ll

llvm/test/CodeGen/PowerPC/select.ll

llvm/test/CodeGen/PowerPC/select_const.ll

llvm/test/CodeGen/PowerPC/setcc-logic.ll

llvm/test/CodeGen/PowerPC/setcc-vector.ll

llvm/test/CodeGen/PowerPC/sext-vector-inreg.ll

llvm/test/CodeGen/PowerPC/sign-ext-atomics.ll

llvm/test/CodeGen/PowerPC/signbit-shift.ll

llvm/test/CodeGen/PowerPC/sms-remark.ll

llvm/test/CodeGen/PowerPC/srem-seteq-illegal-types.ll

llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll

llvm/test/CodeGen/PowerPC/stack-clash-dynamic-alloca.ll

llvm/test/CodeGen/PowerPC/stack-clash-prologue.ll

llvm/test/CodeGen/PowerPC/stack-restore-with-setjmp.ll

llvm/test/CodeGen/PowerPC/store-constant.ll

llvm/test/CodeGen/PowerPC/stwu-sched.ll

llvm/test/CodeGen/PowerPC/swap-reduction.ll

llvm/test/CodeGen/PowerPC/swaps-le-5.ll

llvm/test/CodeGen/PowerPC/swaps-le-6.ll

llvm/test/CodeGen/PowerPC/swaps-le-7.ll

llvm/test/CodeGen/PowerPC/test-vector-insert.ll

llvm/test/CodeGen/PowerPC/testBitReverse.ll

llvm/test/CodeGen/PowerPC/testComparesi32gtu.ll

llvm/test/CodeGen/PowerPC/testComparesi32ltu.ll

Show All 27 Lines
declare signext i32 @fn2(...) local_unnamed_addr #1 declare signext i32 @fn2(...) local_unnamed_addr #1
; Function Attrs: nounwind ; Function Attrs: nounwind
define dso_local i32 @testCompare1(ptr nocapture readonly %arg1) nounwind { define dso_local i32 @testCompare1(ptr nocapture readonly %arg1) nounwind {
; BE-LABEL: testCompare1: ; BE-LABEL: testCompare1:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: mflr r0 ; BE-NEXT: mflr r0
; BE-NEXT: stdu r1, -112(r1) ; BE-NEXT: stdu r1, -112(r1)
; BE-NEXT: std r0, 128(r1)
; BE-NEXT: addis r4, r2, testCompare1@toc@ha ; BE-NEXT: addis r4, r2, testCompare1@toc@ha
; BE-NEXT: lbz r4, testCompare1@toc@l(r4) ; BE-NEXT: std r0, 128(r1)
shchenzUnsubmitted
Done
ReplyInline Actions

This looks positive. We had a request to move the lr store instruction be away from mflr

shchenz: This looks positive. We had a request to move the lr store instruction be away from `mflr`
; BE-NEXT: lbz r3, 0(r3) ; BE-NEXT: lbz r3, 0(r3)
; BE-NEXT: clrlwi r4, r4, 31 ; BE-NEXT: lbz r4, testCompare1@toc@l(r4)
; BE-NEXT: clrlwi r3, r3, 31 ; BE-NEXT: clrlwi r3, r3, 31
; BE-NEXT: clrldi r4, r4, 32 ; BE-NEXT: clrlwi r4, r4, 31
; BE-NEXT: clrldi r3, r3, 32 ; BE-NEXT: clrldi r3, r3, 32
; BE-NEXT: clrldi r4, r4, 32
; BE-NEXT: sub r3, r4, r3 ; BE-NEXT: sub r3, r4, r3
; BE-NEXT: rldicl r3, r3, 1, 63 ; BE-NEXT: rldicl r3, r3, 1, 63
; BE-NEXT: bl fn2 ; BE-NEXT: bl fn2
; BE-NEXT: nop ; BE-NEXT: nop
; BE-NEXT: addi r1, r1, 112 ; BE-NEXT: addi r1, r1, 112
; BE-NEXT: ld r0, 16(r1) ; BE-NEXT: ld r0, 16(r1)
; BE-NEXT: mtlr r0 ; BE-NEXT: mtlr r0
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: testCompare1: ; LE-LABEL: testCompare1:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: mflr r0 ; LE-NEXT: mflr r0
; LE-NEXT: stdu r1, -32(r1) ; LE-NEXT: stdu r1, -32(r1)
; LE-NEXT: std r0, 48(r1)
; LE-NEXT: addis r4, r2, testCompare1@toc@ha ; LE-NEXT: addis r4, r2, testCompare1@toc@ha
; LE-NEXT: lbz r4, testCompare1@toc@l(r4) ; LE-NEXT: std r0, 48(r1)
; LE-NEXT: lbz r3, 0(r3) ; LE-NEXT: lbz r3, 0(r3)
; LE-NEXT: clrlwi r4, r4, 31 ; LE-NEXT: lbz r4, testCompare1@toc@l(r4)
; LE-NEXT: clrlwi r3, r3, 31 ; LE-NEXT: clrlwi r3, r3, 31
; LE-NEXT: clrldi r4, r4, 32 ; LE-NEXT: clrlwi r4, r4, 31
; LE-NEXT: clrldi r3, r3, 32 ; LE-NEXT: clrldi r3, r3, 32
; LE-NEXT: clrldi r4, r4, 32
; LE-NEXT: sub r3, r4, r3 ; LE-NEXT: sub r3, r4, r3
; LE-NEXT: rldicl r3, r3, 1, 63 ; LE-NEXT: rldicl r3, r3, 1, 63
; LE-NEXT: bl fn2 ; LE-NEXT: bl fn2
; LE-NEXT: nop ; LE-NEXT: nop
; LE-NEXT: addi r1, r1, 32 ; LE-NEXT: addi r1, r1, 32
; LE-NEXT: ld r0, 16(r1) ; LE-NEXT: ld r0, 16(r1)
; LE-NEXT: mtlr r0 ; LE-NEXT: mtlr r0
; LE-NEXT: blr ; LE-NEXT: blr
▲ Show 20 Lines • Show All 111 Lines • Show Last 20 Lines

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