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Differential D154181

[x86] Add missing FeatureCMOV in frontend targets.
ClosedPublic

Authored by FreddyYe on Jun 29 2023, 9:19 PM.

Details

Reviewers
pengfei
LuoYuanke
RKSimon
erichkeane
craig.topper
skan
Commits
rGa9256a2e0450: [x86] Add missing FeatureCMOV in frontend targets.
Summary

The missing info is gathered from X86.td.

Diff Detail

Event Timeline

FreddyYe created this revision.Jun 29 2023, 9:19 PM
Herald added a project: Restricted Project. · View Herald TranscriptJun 29 2023, 9:19 PM
Herald added subscribers: pengfei, hiraditya. · View Herald Transcript
FreddyYe requested review of this revision.Jun 29 2023, 9:19 PM
Herald added projects: Restricted Project, Restricted Project. · View Herald TranscriptJun 29 2023, 9:19 PM
Herald added subscribers: llvm-commits, cfe-commits. · View Herald Transcript
FreddyYe added reviewers: pengfei, LuoYuanke, RKSimon, erichkeane, craig.topper, skan.Jun 29 2023, 9:19 PM
FreddyYe mentioned this in D151696: [X86] Remove CPU_SPECIFIC* MACROs and add getCPUDispatchMangling.
craig.topper added inline comments.Jun 29 2023, 9:39 PM
llvm/lib/TargetParser/X86TargetParser.cpp
325

I don't think i686 is supposed to have CMOV. There are some "6th generation" CPUs from Via maybe that don't have cmov.

craig.topper added inline comments.Jun 29 2023, 9:41 PM
llvm/lib/TargetParser/X86TargetParser.cpp
325

Nevermind. I guess we have it enabled for i686. So if I am remembering the Via CPUs correctly, the damage is already done.

craig.topper accepted this revision.Jun 29 2023, 9:45 PM

LGTM

This revision is now accepted and ready to land.Jun 29 2023, 9:45 PM
This revision was landed with ongoing or failed builds.Jun 29 2023, 10:19 PM
Closed by commit rGa9256a2e0450: [x86] Add missing FeatureCMOV in frontend targets. (authored by FreddyYe). · Explain Why
This revision was automatically updated to reflect the committed changes.
FreddyYe added a commit: rGa9256a2e0450: [x86] Add missing FeatureCMOV in frontend targets..
FreddyYe added a comment.Jun 29 2023, 10:20 PM

Thanks review!

Harbormaster completed remote builds in B242322: Diff 536102.Jun 29 2023, 11:34 PM

Revision Contents

PathSize
clang/
test/
CodeGen/
2 lines
22 lines
4 lines
2 lines
llvm/
lib/
TargetParser/
6 lines

Diff 536111

clang/test/CodeGen/attr-target-clones.c

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// WINDOWS: declare dso_local i32 @foo_used_no_defn.sse4.2.0() // WINDOWS: declare dso_local i32 @foo_used_no_defn.sse4.2.0()
// CHECK: attributes #[[SSE42]] = // CHECK: attributes #[[SSE42]] =
// CHECK-SAME: "target-features"="+crc32,+cx8,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87" // CHECK-SAME: "target-features"="+crc32,+cx8,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87"
// CHECK: attributes #[[DEF]] = // CHECK: attributes #[[DEF]] =
// Don't bother checking features, we verified it is the same as a normal function. // Don't bother checking features, we verified it is the same as a normal function.
// CHECK: attributes #[[SB]] = // CHECK: attributes #[[SB]] =
// CHECK-SAME: "target-features"="+avx,+crc32,+cx16,+cx8,+fxsr,+mmx,+pclmul,+popcnt,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt" // CHECK-SAME: "target-features"="+avx,+cmov,+crc32,+cx16,+cx8,+fxsr,+mmx,+pclmul,+popcnt,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt"

clang/test/CodeGen/attr-target-x86.c

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// CHECK: narwhal{{.*}} #4 // CHECK: narwhal{{.*}} #4
// CHECK: bar{{.*}} #0 // CHECK: bar{{.*}} #0
// CHECK: qux{{.*}} #1 // CHECK: qux{{.*}} #1
// CHECK: qax{{.*}} #5 // CHECK: qax{{.*}} #5
// CHECK: qq{{.*}} #6 // CHECK: qq{{.*}} #6
// CHECK: lake{{.*}} #7 // CHECK: lake{{.*}} #7
// CHECK: use_before_def{{.*}} #7 // CHECK: use_before_def{{.*}} #7
// CHECK: walrus{{.*}} #8 // CHECK: walrus{{.*}} #8
// CHECK: #0 = {{.*}}"target-cpu"="i686" "target-features"="+cx8,+x87" "tune-cpu"="i686" // CHECK: #0 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87" "tune-cpu"="i686"
// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" "target-features"="+avx,+crc32,+cx16,+cx8,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt" // CHECK: #1 = {{.*}}"target-cpu"="ivybridge" "target-features"="+avx,+cmov,+crc32,+cx16,+cx8,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt"
// CHECK-NOT: tune-cpu // CHECK-NOT: tune-cpu
// CHECK: #2 = {{.*}}"target-cpu"="i686" "target-features"="+cx8,+x87,-aes,-avx,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512fp16,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint8,-f16c,-fma,-fma4,-gfni,-kl,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-vaes,-vpclmulqdq,-widekl,-xop" "tune-cpu"="i686" // CHECK: #2 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-aes,-avx,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512fp16,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint8,-f16c,-fma,-fma4,-gfni,-kl,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-vaes,-vpclmulqdq,-widekl,-xop" "tune-cpu"="i686"
// CHECK: #3 = {{.*}}"target-cpu"="i686" "target-features"="+crc32,+cx8,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87" "tune-cpu"="i686" // CHECK: #3 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+crc32,+cx8,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87" "tune-cpu"="i686"
// CHECK: #4 = {{.*}}"target-cpu"="i686" "target-features"="+cx8,+x87,-avx,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512fp16,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint8,-f16c,-fma,-fma4,-sse4.1,-sse4.2,-vaes,-vpclmulqdq,-xop" "tune-cpu"="i686" // CHECK: #4 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-avx,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512fp16,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint8,-f16c,-fma,-fma4,-sse4.1,-sse4.2,-vaes,-vpclmulqdq,-xop" "tune-cpu"="i686"
// CHECK: #5 = {{.*}}"target-cpu"="ivybridge" "target-features"="+avx,+crc32,+cx16,+cx8,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt,-aes,-vaes" // CHECK: #5 = {{.*}}"target-cpu"="ivybridge" "target-features"="+avx,+cmov,+crc32,+cx16,+cx8,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt,-aes,-vaes"
// CHECK-NOT: tune-cpu // CHECK-NOT: tune-cpu
// CHECK: #6 = {{.*}}"target-cpu"="i686" "target-features"="+cx8,+x87,-3dnow,-3dnowa,-mmx" // CHECK: #6 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-3dnow,-3dnowa,-mmx"
// CHECK: #7 = {{.*}}"target-cpu"="lakemont" "target-features"="+cx8,+mmx" // CHECK: #7 = {{.*}}"target-cpu"="lakemont" "target-features"="+cx8,+mmx"
// CHECK-NOT: tune-cpu // CHECK-NOT: tune-cpu
// CHECK: #8 = {{.*}}"target-cpu"="i686" "target-features"="+cx8,+x87" "tune-cpu"="sandybridge" // CHECK: #8 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87" "tune-cpu"="sandybridge"
// CHECK: "target-cpu"="x86-64-v2" // CHECK: "target-cpu"="x86-64-v2"
// CHECK-SAME: "target-features"="+crc32,+cx16,+cx8,+fxsr,+mmx,+popcnt,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87" // CHECK-SAME: "target-features"="+cmov,+crc32,+cx16,+cx8,+fxsr,+mmx,+popcnt,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87"
// CHECK: "target-cpu"="x86-64-v3" // CHECK: "target-cpu"="x86-64-v3"
// CHECK-SAME: "target-features"="+avx,+avx2,+bmi,+bmi2,+crc32,+cx16,+cx8,+f16c,+fma,+fxsr,+lzcnt,+mmx,+movbe,+popcnt,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave" // CHECK-SAME: "target-features"="+avx,+avx2,+bmi,+bmi2,+cmov,+crc32,+cx16,+cx8,+f16c,+fma,+fxsr,+lzcnt,+mmx,+movbe,+popcnt,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave"
// CHECK: "target-cpu"="x86-64-v4" // CHECK: "target-cpu"="x86-64-v4"
// CHECK-SAME: "target-features"="+avx,+avx2,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512vl,+bmi,+bmi2,+crc32,+cx16,+cx8,+f16c,+fma,+fxsr,+lzcnt,+mmx,+movbe,+popcnt,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave" // CHECK-SAME: "target-features"="+avx,+avx2,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512vl,+bmi,+bmi2,+cmov,+crc32,+cx16,+cx8,+f16c,+fma,+fxsr,+lzcnt,+mmx,+movbe,+popcnt,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave"

clang/test/CodeGen/attr-target-x87-softfp.c

// RUN: %clang_cc1 -triple x86_64-linux-gnu -target-cpu x86-64 -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=HARD // RUN: %clang_cc1 -triple x86_64-linux-gnu -target-cpu x86-64 -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=HARD
// RUN: %clang_cc1 -msoft-float -triple x86_64-linux-gnu -target-cpu x86-64 -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT // RUN: %clang_cc1 -msoft-float -triple x86_64-linux-gnu -target-cpu x86-64 -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT
int __attribute__((target("x87"))) foo(int a) { return 4; } int __attribute__((target("x87"))) foo(int a) { return 4; }
int __attribute__((target("no-x87"))) bar(int a) { return 4; } int __attribute__((target("no-x87"))) bar(int a) { return 4; }
// CHECK: foo{{.*}} #0 // CHECK: foo{{.*}} #0
// CHECK: bar{{.*}} #1 // CHECK: bar{{.*}} #1
// CHECK: #0 = {{.*}}"target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" // CHECK: #0 = {{.*}}"target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87"
// HARD-NOT: "use-soft-float" // HARD-NOT: "use-soft-float"
// SOFT: "use-soft-float"="true" // SOFT: "use-soft-float"="true"
// CHECK: #1 = {{.*}}"target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,-x87" // CHECK: #1 = {{.*}}"target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,-x87"
// HARD-NOT: "use-soft-float" // HARD-NOT: "use-soft-float"
// SOFT: "use-soft-float"="true" // SOFT: "use-soft-float"="true"

clang/test/CodeGen/tune-cpu.c

// RUN: %clang_cc1 -triple i686-linux-gnu -target-cpu i686 -tune-cpu nehalem -emit-llvm %s -o - | FileCheck %s // RUN: %clang_cc1 -triple i686-linux-gnu -target-cpu i686 -tune-cpu nehalem -emit-llvm %s -o - | FileCheck %s
int baz(int a) { return 4; } int baz(int a) { return 4; }
// CHECK: baz{{.*}} #0 // CHECK: baz{{.*}} #0
// CHECK: #0 = {{.*}}"target-cpu"="i686" "target-features"="+cx8,+x87" "tune-cpu"="nehalem" // CHECK: #0 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87" "tune-cpu"="nehalem"

llvm/lib/TargetParser/X86TargetParser.cpp

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#include "llvm/TargetParser/X86TargetParser.def" #include "llvm/TargetParser/X86TargetParser.def"
// Pentium with MMX. // Pentium with MMX.
constexpr FeatureBitset FeaturesPentiumMMX = constexpr FeatureBitset FeaturesPentiumMMX =
FeatureX87 | FeatureCMPXCHG8B | FeatureMMX; FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
// Pentium 2 and 3. // Pentium 2 and 3.
constexpr FeatureBitset FeaturesPentium2 = constexpr FeatureBitset FeaturesPentium2 =
FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR; FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR | FeatureCMOV;
constexpr FeatureBitset FeaturesPentium3 = FeaturesPentium2 | FeatureSSE; constexpr FeatureBitset FeaturesPentium3 = FeaturesPentium2 | FeatureSSE;
// Pentium 4 CPUs // Pentium 4 CPUs
constexpr FeatureBitset FeaturesPentium4 = FeaturesPentium3 | FeatureSSE2; constexpr FeatureBitset FeaturesPentium4 = FeaturesPentium3 | FeatureSSE2;
constexpr FeatureBitset FeaturesPrescott = FeaturesPentium4 | FeatureSSE3; constexpr FeatureBitset FeaturesPrescott = FeaturesPentium4 | FeatureSSE3;
constexpr FeatureBitset FeaturesNocona = constexpr FeatureBitset FeaturesNocona =
FeaturesPrescott | Feature64BIT | FeatureCMPXCHG16B; FeaturesPrescott | Feature64BIT | FeatureCMPXCHG16B;
▲ Show 20 Lines • Show All 178 Lines • ▼ Show 20 Linesconstexpr ProcInfo Processors[] = {
{ {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX }, { {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX },
{ {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | Feature3DNOW }, { {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | Feature3DNOW },
{ {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | Feature3DNOW }, { {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | Feature3DNOW },
// i586-generation processors, P5 microarchitecture based. // i586-generation processors, P5 microarchitecture based.
{ {"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B }, { {"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B },
{ {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B }, { {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B },
{ {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX }, { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX },
// i686-generation processors, P6 / Pentium M microarchitecture based. // i686-generation processors, P6 / Pentium M microarchitecture based.
{ {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureX87 | FeatureCMPXCHG8B }, { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B },
{ {"i686"}, CK_i686, ~0U, FeatureX87 | FeatureCMPXCHG8B }, { {"i686"}, CK_i686, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B },
craig.topperUnsubmitted
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I don't think i686 is supposed to have CMOV. There are some "6th generation" CPUs from Via maybe that don't have cmov.

craig.topper: I don't think i686 is supposed to have CMOV. There are some "6th generation" CPUs from Via…
craig.topperUnsubmitted
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Nevermind. I guess we have it enabled for i686. So if I am remembering the Via CPUs correctly, the damage is already done.

craig.topper: Nevermind. I guess we have it enabled for i686. So if I am remembering the Via CPUs correctly…
{ {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2 }, { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2 },
{ {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3 }, { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3 },
{ {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3 }, { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3 },
{ {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4 }, { {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4 },
{ {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3 }, { {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3 },
{ {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott }, { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott },
// Netburst microarchitecture based processors. // Netburst microarchitecture based processors.
{ {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4 }, { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4 },
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