[PowerPC] disable ppc-use-absolute-jumptables for AIX

[tingwang]

Summary

ppc-use-absolute-jumptables is not workable on AIX due to jump table encoding and PIC requirement, and AIX only supports relative jump table entries right now. Disable the flag for AIX.

[tingwang]

Update test case after commit NFC patch.

[shchenz]

This indeed is a bug on AIX (which has PIC as default). Relative jump table in the data section but no add in the text section, so the target addresses would be wrong.

Thanks for catching this bug.

llvm/test/CodeGen/PowerPC/absol-jump-table-enabled.ll

73

This change seems problematic to me. PIC is a functionality option while -ppc-use-absolute-jumptables=true is an optimization option (save the add instruction?), so if -ppc-use-absolute-jumptables=true and --relocation-model=pic are both true, we should use relative jump table which matches PIC requirement.

[tingwang]

llvm/test/CodeGen/PowerPC/absol-jump-table-enabled.ll

73

I don't take relative jump table as a necessary condition for PIC, for example check attached case_xlc.c when compiled by xlc using -qpic=small (which is equivalent to -fpic according to the migration guide) generates absolute address for jump table entries, use ldx to load the entry, and then jump to the address without add.

case_xlc.c2 KBDownload

[shchenz]

add @joerg who helped to add PIC mode jump table in https://reviews.llvm.org/D26336

llvm/test/CodeGen/PowerPC/absol-jump-table-enabled.ll

73

XLC don't use add, but the contents in the jump table are not block addresses. They are the sum of the function address and the offsets of the branch targets in that function.

[tingwang]

In D154048#4467834, @shchenz wrote:

add @joerg who helped to add PIC mode jump table in https://reviews.llvm.org/D26336

Thank you for the info. Now I see the factor on AIX: xlc put jump tables in data section (which is writable) with R_POS relocation. Loader will update those entries. While in LLVM right now, jump tables are emitted in text section. Now for absolute BlockAddress, even if linker added R_POS relocation for those entries, loader cannot do update because that's text section, and it generates error like following:

0509-141   Relocation entry 0 (at address 1000003E0)
                   has an invalid l_rsecnm field.

The fix is wrong. I will update patch later.

[tingwang]

Disable the flag on AIX.

However the issue remains on at least ppc64le. I'm not sure of the purpose of this flag, so just expose the issue and leave it here.

[tingwang]

Not necessary.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

 }
 
 // For 64-bit PowerPC, prefer the more compact relative encodings.
 // This trades 32 bits per jump table entry for one or two instructions
 // on the jump site.
 unsigned PPCTargetLowering::getJumpTableEncoding() const {
   if (isJumpTableRelative())
     return MachineJumpTableInfo::EK_LabelDifference32;
-
+  if (UseAbsoluteJumpTables)
+    return MachineJumpTableInfo::EK_BlockAddress;
   return TargetLowering::getJumpTableEncoding();
 }
 
 bool PPCTargetLowering::isJumpTableRelative() const {
   if (UseAbsoluteJumpTables)
     return false;
   if (Subtarget.isPPC64() || Subtarget.isAIXABI())
     return true;

llvm/test/CodeGen/PowerPC/absol-jump-table-enabled.ll

 ; CHECK-LE:       rldic r[[REG:[0-9]+]], r[[REG]], 3, 29
 ; CHECK-LE:       ldx r[[REG]], r[[REG]], r[[REG1:[0-9]+]]
 ; CHECK-LE:       mtctr r[[REG]]
 ; CHECK-LE:       bctr
 ; CHECK-LE:       blr
 ;
 ; CHECK-BE-LABEL: jumpTableTest:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE:       rldic r[[REG:[0-9]+]], r[[REG]], 2, 30
-; CHECK-BE:       lwax r[[REG]], r[[REG]], r[[REG1:[0-9]+]]
+; CHECK-BE:       rldic r[[REG:[0-9]+]], r[[REG]], 3, 29
+; CHECK-BE:       ldx r[[REG]], r[[REG]], r[[REG1:[0-9]+]]
 ; CHECK-BE:       mtctr r[[REG]]
 ; CHECK-BE:       bctr
 ; CHECK-BE:       blr
 ;
 ; CHECK-AIX-LABEL: jumpTableTest:
 ; CHECK-AIX:       # %bb.0: # %entry
-; CHECK-AIX:       rldic r[[REG:[0-9]+]], r[[REG]], 2, 30
-; CHECK-AIX:       lwax r[[REG]], r[[REG]], r[[REG1:[0-9]+]]
+; CHECK-AIX:       rldic r[[REG:[0-9]+]], r[[REG]], 3, 29
+; CHECK-AIX:       ldx r[[REG]], r[[REG]], r[[REG1:[0-9]+]]
 ; CHECK-AIX:       mtctr r[[REG]]
 ; CHECK-AIX:       bctr
 ; CHECK-AIX:       blr
 ;
 ; CHECK-A-PIC-LE-LABEL:       .LJTI0_0:
-; CHECK-A-PIC-LE:             .long   .LBB0_6-.LJTI0_0
+; CHECK-A-PIC-LE:             .quad   .LBB0_6
 ;
 ; CHECK-R-PIC-LE-LABEL:       .LJTI0_0:
 ; CHECK-R-PIC-LE:             .long   .LBB0_6-.LJTI0_0
 ;
 ; CHECK-A-PIC-BE-LABEL:       .LJTI0_0:
-; CHECK-A-PIC-BE:             .long   .LBB0_9-.LJTI0_0
+; CHECK-A-PIC-BE:             .quad   .LBB0_9
 ;
 ; CHECK-R-PIC-BE-LABEL:       .LJTI0_0:
 ; CHECK-R-PIC-BE:             .long   .LBB0_9-.LJTI0_0
 ;
 ; CHECK-A-PIC-AIX-LABEL:      L..JTI0_0:
-; CHECK-A-PIC-AIX:            .vbyte  4, L..BB0_9-L..JTI0_0
+; CHECK-A-PIC-AIX:            .vbyte  8, L..BB0_9
 ;
 ; CHECK-R-PIC-AIX-LABEL:      L..JTI0_0:
 ; CHECK-R-PIC-AIX:            .vbyte  4, L..BB0_9-L..JTI0_0
 ;
 ; CHECK-A-STATIC-LE-LABEL:    .LJTI0_0:
 ; CHECK-A-STATIC-LE:          .quad   .LBB0_6
 ;
 ; CHECK-R-STATIC-LE-LABEL:    .LJTI0_0:

llvm/test/CodeGen/PowerPC/pcrel-jump-table.ll

 ; CHECK-A-LE:       # %bb.1: # %entry
 ; CHECK-A-LE-NEXT:    rldic r4, r4
 ; CHECK-A-LE-NEXT:    paddi r5, 0, .LJTI0_0@PCREL, 1
 ; CHECK-A-LE-NEXT:    ldx r4, r4, r5
 ; CHECK-A-LE-NEXT:    mtctr r4
 ; CHECK-A-LE-NEXT:    bctr
 ; CHECK-A-BE-LABEL: jumptable:
 ; CHECK-A-BE:       # %bb.1: # %entry
-; CHECK-A-BE-NEXT:    paddi r5, 0, .LJTI0_0@PCREL, 1
 ; CHECK-A-BE-NEXT:    rldic r4, r4
-; CHECK-A-BE-NEXT:    lwax r4, r4, r5
+; CHECK-A-BE-NEXT:    paddi r5, 0, .LJTI0_0@PCREL, 1
+; CHECK-A-BE-NEXT:    ldx r4, r4, r5
 ; CHECK-A-BE-NEXT:    mtctr r4
 ; CHECK-A-BE-NEXT:    bctr
 
-
 entry:
   switch i32 %param, label %sw.default [
     i32 1, label %return
     i32 2, label %sw.bb1
     i32 3, label %sw.bb2
     i32 4, label %sw.bb3
     i32 20, label %sw.bb4
   ]