[RISCV] Don't include X1 in the X0_PD register pair

[asb]

Summary

Zdinx on RV32 defines the D instructions as taking even register pairs, and specifies that if using X0 when as a destination then X1 won't be written, and if using X0 as a source then the value is still all 0s (i.e. X1 isn't read). Therefore, it's incorrect to model X0_PD as having X1 as a subregister. This will also be the case for register pairs in Zacas and the P extension (and this patch takes the same approach as D95588 does).

This patch introduces a dummy register that is solely used as a subreg alongside X0 in X0_PD. An earlier version of the patch had a minor effect on register allocation in some tests, which is now avoided by:

1. Adding RISCV::DUMMY_REG_PAIR_WITH_X0 to RISCVRegisterInfo::getReservedRegs
2. Defining a new register class that includes DUMMY_REG_PAIR_WITH_X0

[craig.topper]

I don't have any better ideas. The test change is kind of weird.

[asb]

In D153974#4461536, @craig.topper wrote:

I don't have any better ideas. The test change is kind of weird.

From tracing through, I think (at least from looking for the likely divergence in a -debug trace) the issue is a change in the regPressureSetLimit for GPRs (going from 28 to 29). The PGPR regpressure limit goes from 14 to 13 and GPRC_with_PGPR changes name to PGPR_with_GPRC and goes from 20 to 19.

@MatzeB does this sound like a possible bug in the register pressure code (or indeed, us doing something wrong), or is this just expected change when altering the register set?

[craig.topper]

Do we need to reserve the new register in RISCVRegisterInfo::getReservedRegs?

[asb]

In D153974#4493649, @craig.topper wrote:

Do we need to reserve the new register in RISCVRegisterInfo::getReservedRegs?

Good suggestion. We might need to, but unfortunately that has no impact on the changed test case.

[craig.topper]

In D153974#4494029, @asb wrote:

In D153974#4493649, @craig.topper wrote:

Do we need to reserve the new register in RISCVRegisterInfo::getReservedRegs?

Good suggestion. We might need to, but unfortunately that has no impact on the changed test case.

Marking the register reserved and adding this to RISCVRegisterInfo.td recovers the tests.

def GPRAll : GPRRegisterClass<(add GPR, DUMMY_REG_PAIR_WITH_X0)>;

[asb]

Updated to incorporate suggested fixes from @craig.topper that means unwanted codegen changes are avoided.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

def VMV0 : RegisterClass<"RISCV", VMaskVTs, 64, (add V0)> {
   let Size = 64;
 }
 
 let RegInfos = XLenRI in {
 def GPRF16  : RegisterClass<"RISCV", [f16], 16, (add GPR)>;
 def GPRF32  : RegisterClass<"RISCV", [f32], 32, (add GPR)>;
 } // RegInfos = XLenRI
 
+// Dummy zero register for use in the register pair containing X0 (as X1 is
+// not read to or written when the X0 register pair is used).
+def DUMMY_REG_PAIR_WITH_X0 : RISCVReg<0, "0">;
+
 let RegAltNameIndices = [ABIRegAltName] in {
-  foreach I = 0-15 in {
+  def X0_PD : RISCVRegWithSubRegs<0, X0.AsmName,
+                                     [X0, DUMMY_REG_PAIR_WITH_X0],
+                                     X0.AltNames> {
+    let SubRegIndices = [sub_32, sub_32_hi];
+    let CoveredBySubRegs = 1;
+  }
+  foreach I = 1-15 in {
     defvar Index = !shl(I, 1);
     defvar Reg = !cast<Register>("X"#Index);
     defvar RegP1 = !cast<Register>("X"#!add(Index,1));
     def X#Index#_PD : RISCVRegWithSubRegs<Index, Reg.AsmName,
                                           [Reg, RegP1],
                                           Reg.AltNames> {
       let SubRegIndices = [sub_32, sub_32_hi];
       let CoveredBySubRegs = 1;

llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll

 ; RV64I-NEXT:    lbu a4, 30(a0)
 ; RV64I-NEXT:    lbu a0, 29(a0)
 ; RV64I-NEXT:    lbu a1, 0(a1)
 ; RV64I-NEXT:    sb a3, 87(sp)
 ; RV64I-NEXT:    sb a4, 86(sp)
 ; RV64I-NEXT:    sb a0, 85(sp)
 ; RV64I-NEXT:    sb a5, 84(sp)
 ; RV64I-NEXT:    sb a6, 83(sp)
-; RV64I-NEXT:    sb a7, 82(sp)
 ; RV64I-NEXT:    sb zero, 119(sp)
 ; RV64I-NEXT:    sb zero, 118(sp)
 ; RV64I-NEXT:    sb zero, 117(sp)
 ; RV64I-NEXT:    sb zero, 116(sp)
 ; RV64I-NEXT:    sb zero, 115(sp)
 ; RV64I-NEXT:    sb zero, 114(sp)
 ; RV64I-NEXT:    sb zero, 113(sp)
 ; RV64I-NEXT:    sb zero, 112(sp)

 ; RV64I-NEXT:    sb zero, 95(sp)
 ; RV64I-NEXT:    sb zero, 94(sp)
 ; RV64I-NEXT:    sb zero, 93(sp)
 ; RV64I-NEXT:    sb zero, 92(sp)
 ; RV64I-NEXT:    sb zero, 91(sp)
 ; RV64I-NEXT:    sb zero, 90(sp)
 ; RV64I-NEXT:    sb zero, 89(sp)
 ; RV64I-NEXT:    sb zero, 88(sp)
+; RV64I-NEXT:    sb a7, 82(sp)
 ; RV64I-NEXT:    sb t0, 81(sp)
 ; RV64I-NEXT:    sb ra, 80(sp)
 ; RV64I-NEXT:    sb s11, 79(sp)
 ; RV64I-NEXT:    sb s10, 78(sp)
 ; RV64I-NEXT:    sb s9, 77(sp)
 ; RV64I-NEXT:    sb s8, 76(sp)
 ; RV64I-NEXT:    sb s7, 75(sp)
 ; RV64I-NEXT:    sb s6, 74(sp)

 ; RV32I-NEXT:    lbu a4, 30(a0)
 ; RV32I-NEXT:    lbu a0, 29(a0)
 ; RV32I-NEXT:    lbu a1, 0(a1)
 ; RV32I-NEXT:    sb a3, 59(sp)
 ; RV32I-NEXT:    sb a4, 58(sp)
 ; RV32I-NEXT:    sb a0, 57(sp)
 ; RV32I-NEXT:    sb a5, 56(sp)
 ; RV32I-NEXT:    sb a6, 55(sp)
-; RV32I-NEXT:    sb a7, 54(sp)
 ; RV32I-NEXT:    sb zero, 91(sp)
 ; RV32I-NEXT:    sb zero, 90(sp)
 ; RV32I-NEXT:    sb zero, 89(sp)
 ; RV32I-NEXT:    sb zero, 88(sp)
 ; RV32I-NEXT:    sb zero, 87(sp)
 ; RV32I-NEXT:    sb zero, 86(sp)
 ; RV32I-NEXT:    sb zero, 85(sp)
 ; RV32I-NEXT:    sb zero, 84(sp)

 ; RV32I-NEXT:    sb zero, 67(sp)
 ; RV32I-NEXT:    sb zero, 66(sp)
 ; RV32I-NEXT:    sb zero, 65(sp)
 ; RV32I-NEXT:    sb zero, 64(sp)
 ; RV32I-NEXT:    sb zero, 63(sp)
 ; RV32I-NEXT:    sb zero, 62(sp)
 ; RV32I-NEXT:    sb zero, 61(sp)
 ; RV32I-NEXT:    sb zero, 60(sp)
+; RV32I-NEXT:    sb a7, 54(sp)
 ; RV32I-NEXT:    sb t0, 53(sp)
 ; RV32I-NEXT:    sb ra, 52(sp)
 ; RV32I-NEXT:    sb s11, 51(sp)
 ; RV32I-NEXT:    sb s10, 50(sp)
 ; RV32I-NEXT:    sb s9, 49(sp)
 ; RV32I-NEXT:    sb s8, 48(sp)
 ; RV32I-NEXT:    sb s7, 47(sp)
 ; RV32I-NEXT:    sb s6, 46(sp)

 ; RV64I-NEXT:    lbu a4, 30(a0)
 ; RV64I-NEXT:    lbu a0, 29(a0)
 ; RV64I-NEXT:    lbu a1, 0(a1)
 ; RV64I-NEXT:    sb a3, 119(sp)
 ; RV64I-NEXT:    sb a4, 118(sp)
 ; RV64I-NEXT:    sb a0, 117(sp)
 ; RV64I-NEXT:    sb a5, 116(sp)
 ; RV64I-NEXT:    sb a6, 115(sp)
-; RV64I-NEXT:    sb a7, 114(sp)
 ; RV64I-NEXT:    sb zero, 87(sp)
 ; RV64I-NEXT:    sb zero, 86(sp)
 ; RV64I-NEXT:    sb zero, 85(sp)
 ; RV64I-NEXT:    sb zero, 84(sp)
 ; RV64I-NEXT:    sb zero, 83(sp)
 ; RV64I-NEXT:    sb zero, 82(sp)
 ; RV64I-NEXT:    sb zero, 81(sp)
 ; RV64I-NEXT:    sb zero, 80(sp)

 ; RV64I-NEXT:    sb zero, 63(sp)
 ; RV64I-NEXT:    sb zero, 62(sp)
 ; RV64I-NEXT:    sb zero, 61(sp)
 ; RV64I-NEXT:    sb zero, 60(sp)
 ; RV64I-NEXT:    sb zero, 59(sp)
 ; RV64I-NEXT:    sb zero, 58(sp)
 ; RV64I-NEXT:    sb zero, 57(sp)
 ; RV64I-NEXT:    sb zero, 56(sp)
+; RV64I-NEXT:    sb a7, 114(sp)
 ; RV64I-NEXT:    sb t0, 113(sp)
 ; RV64I-NEXT:    sb ra, 112(sp)
 ; RV64I-NEXT:    sb s11, 111(sp)
 ; RV64I-NEXT:    sb s10, 110(sp)
 ; RV64I-NEXT:    sb s9, 109(sp)
 ; RV64I-NEXT:    sb s8, 108(sp)
 ; RV64I-NEXT:    sb s7, 107(sp)
 ; RV64I-NEXT:    sb s6, 106(sp)

 ; RV32I-NEXT:    lbu a4, 30(a0)
 ; RV32I-NEXT:    lbu a0, 29(a0)
 ; RV32I-NEXT:    lbu a1, 0(a1)
 ; RV32I-NEXT:    sb a3, 91(sp)
 ; RV32I-NEXT:    sb a4, 90(sp)
 ; RV32I-NEXT:    sb a0, 89(sp)
 ; RV32I-NEXT:    sb a5, 88(sp)
 ; RV32I-NEXT:    sb a6, 87(sp)
-; RV32I-NEXT:    sb a7, 86(sp)
 ; RV32I-NEXT:    sb zero, 59(sp)
 ; RV32I-NEXT:    sb zero, 58(sp)
 ; RV32I-NEXT:    sb zero, 57(sp)
 ; RV32I-NEXT:    sb zero, 56(sp)
 ; RV32I-NEXT:    sb zero, 55(sp)
 ; RV32I-NEXT:    sb zero, 54(sp)
 ; RV32I-NEXT:    sb zero, 53(sp)
 ; RV32I-NEXT:    sb zero, 52(sp)

 ; RV32I-NEXT:    sb zero, 35(sp)
 ; RV32I-NEXT:    sb zero, 34(sp)
 ; RV32I-NEXT:    sb zero, 33(sp)
 ; RV32I-NEXT:    sb zero, 32(sp)
 ; RV32I-NEXT:    sb zero, 31(sp)
 ; RV32I-NEXT:    sb zero, 30(sp)
 ; RV32I-NEXT:    sb zero, 29(sp)
 ; RV32I-NEXT:    sb zero, 28(sp)
+; RV32I-NEXT:    sb a7, 86(sp)
 ; RV32I-NEXT:    sb t0, 85(sp)
 ; RV32I-NEXT:    sb ra, 84(sp)
 ; RV32I-NEXT:    sb s11, 83(sp)
 ; RV32I-NEXT:    sb s10, 82(sp)
 ; RV32I-NEXT:    sb s9, 81(sp)
 ; RV32I-NEXT:    sb s8, 80(sp)
 ; RV32I-NEXT:    sb s7, 79(sp)
 ; RV32I-NEXT:    sb s6, 78(sp)

 ; RV64I-NEXT:    lbu a3, 29(a0)
 ; RV64I-NEXT:    lbu a0, 28(a0)
 ; RV64I-NEXT:    lbu t1, 0(t1)
 ; RV64I-NEXT:    sb a1, 86(sp)
 ; RV64I-NEXT:    sb a3, 85(sp)
 ; RV64I-NEXT:    sb a0, 84(sp)
 ; RV64I-NEXT:    sb a4, 83(sp)
 ; RV64I-NEXT:    sb a5, 82(sp)
-; RV64I-NEXT:    sb a6, 81(sp)
 ; RV64I-NEXT:    sb t0, 87(sp)
 ; RV64I-NEXT:    slli t0, t0, 56
+; RV64I-NEXT:    sb a6, 81(sp)
 ; RV64I-NEXT:    sb a7, 80(sp)
 ; RV64I-NEXT:    sb ra, 79(sp)
 ; RV64I-NEXT:    sb s11, 78(sp)
 ; RV64I-NEXT:    sb s10, 77(sp)
 ; RV64I-NEXT:    sb s9, 76(sp)
 ; RV64I-NEXT:    sb s8, 75(sp)
 ; RV64I-NEXT:    sb s7, 74(sp)
 ; RV64I-NEXT:    sb s6, 73(sp)

 ; RV32I-NEXT:    lbu a3, 29(a0)
 ; RV32I-NEXT:    lbu a0, 28(a0)
 ; RV32I-NEXT:    lbu t1, 0(t1)
 ; RV32I-NEXT:    sb a1, 58(sp)
 ; RV32I-NEXT:    sb a3, 57(sp)
 ; RV32I-NEXT:    sb a0, 56(sp)
 ; RV32I-NEXT:    sb a4, 55(sp)
 ; RV32I-NEXT:    sb a5, 54(sp)
-; RV32I-NEXT:    sb a6, 53(sp)
 ; RV32I-NEXT:    sb t0, 59(sp)
 ; RV32I-NEXT:    slli t0, t0, 24
+; RV32I-NEXT:    sb a6, 53(sp)
 ; RV32I-NEXT:    sb a7, 52(sp)
 ; RV32I-NEXT:    sb ra, 51(sp)
 ; RV32I-NEXT:    sb s11, 50(sp)
 ; RV32I-NEXT:    sb s10, 49(sp)
 ; RV32I-NEXT:    sb s9, 48(sp)
 ; RV32I-NEXT:    sb s8, 47(sp)
 ; RV32I-NEXT:    sb s7, 46(sp)
 ; RV32I-NEXT:    sb s6, 45(sp)

llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll

 ; RV64I-NEXT:    lbu s1, 13(a0)
 ; RV64I-NEXT:    lbu s2, 14(a0)
 ; RV64I-NEXT:    lbu s3, 15(a0)
 ; RV64I-NEXT:    lbu s4, 16(a0)
 ; RV64I-NEXT:    lbu s5, 17(a0)
 ; RV64I-NEXT:    lbu s6, 18(a0)
 ; RV64I-NEXT:    lbu s7, 19(a0)
 ; RV64I-NEXT:    lbu s8, 20(a0)
-; RV64I-NEXT:    lbu s9, 1(a1)
-; RV64I-NEXT:    lbu s10, 0(a1)
-; RV64I-NEXT:    lbu s11, 2(a1)
-; RV64I-NEXT:    lbu ra, 3(a1)
-; RV64I-NEXT:    slli s9, s9, 8
-; RV64I-NEXT:    or s9, s9, s10
-; RV64I-NEXT:    slli s11, s11, 16
-; RV64I-NEXT:    slli ra, ra, 24
-; RV64I-NEXT:    lbu s10, 5(a1)
-; RV64I-NEXT:    or s11, ra, s11
-; RV64I-NEXT:    or s9, s11, s9
-; RV64I-NEXT:    lbu s11, 4(a1)
+; RV64I-NEXT:    lbu s9, 21(a0)
+; RV64I-NEXT:    lbu s10, 1(a1)
+; RV64I-NEXT:    lbu s11, 0(a1)
+; RV64I-NEXT:    lbu ra, 2(a1)
+; RV64I-NEXT:    lbu a3, 3(a1)
 ; RV64I-NEXT:    slli s10, s10, 8
+; RV64I-NEXT:    or s10, s10, s11
+; RV64I-NEXT:    slli ra, ra, 16
+; RV64I-NEXT:    slli a3, a3, 24
+; RV64I-NEXT:    lbu s11, 5(a1)
+; RV64I-NEXT:    or a3, a3, ra
+; RV64I-NEXT:    or a3, a3, s10
+; RV64I-NEXT:    lbu s10, 4(a1)
+; RV64I-NEXT:    slli s11, s11, 8
 ; RV64I-NEXT:    lbu ra, 6(a1)
 ; RV64I-NEXT:    lbu a1, 7(a1)
-; RV64I-NEXT:    or s10, s10, s11
-; RV64I-NEXT:    lbu s11, 21(a0)
+; RV64I-NEXT:    or s10, s11, s10
+; RV64I-NEXT:    lbu s11, 22(a0)
 ; RV64I-NEXT:    slli ra, ra, 16
 ; RV64I-NEXT:    slli a1, a1, 24
 ; RV64I-NEXT:    or a1, a1, ra
-; RV64I-NEXT:    lbu ra, 22(a0)
+; RV64I-NEXT:    lbu ra, 23(a0)
 ; RV64I-NEXT:    or a1, a1, s10
-; RV64I-NEXT:    lbu s10, 23(a0)
+; RV64I-NEXT:    lbu s10, 24(a0)
 ; RV64I-NEXT:    slli a1, a1, 32
-; RV64I-NEXT:    or t0, a1, s9
-; RV64I-NEXT:    lbu s9, 24(a0)
+; RV64I-NEXT:    or t0, a1, a3
 ; RV64I-NEXT:    lbu a7, 25(a0)
 ; RV64I-NEXT:    lbu a6, 26(a0)
 ; RV64I-NEXT:    lbu a5, 27(a0)
 ; RV64I-NEXT:    lbu a1, 31(a0)
 ; RV64I-NEXT:    lbu a3, 30(a0)
 ; RV64I-NEXT:    lbu a4, 29(a0)
 ; RV64I-NEXT:    lbu a0, 28(a0)
 ; RV64I-NEXT:    sb a1, 87(sp)
 ; RV64I-NEXT:    sb a3, 86(sp)
 ; RV64I-NEXT:    sb a4, 85(sp)
 ; RV64I-NEXT:    sb a0, 84(sp)
 ; RV64I-NEXT:    sb a5, 83(sp)
 ; RV64I-NEXT:    sb a6, 82(sp)
 ; RV64I-NEXT:    sb a7, 81(sp)
-; RV64I-NEXT:    sb s9, 80(sp)
-; RV64I-NEXT:    sb s10, 79(sp)
-; RV64I-NEXT:    sb ra, 78(sp)
-; RV64I-NEXT:    sb s11, 77(sp)
+; RV64I-NEXT:    sb s10, 80(sp)
+; RV64I-NEXT:    sb ra, 79(sp)
+; RV64I-NEXT:    sb s11, 78(sp)
+; RV64I-NEXT:    sb s9, 77(sp)
 ; RV64I-NEXT:    sb s8, 76(sp)
 ; RV64I-NEXT:    sb s7, 75(sp)
 ; RV64I-NEXT:    sb s6, 74(sp)
 ; RV64I-NEXT:    sb s5, 73(sp)
 ; RV64I-NEXT:    sb s4, 72(sp)
 ; RV64I-NEXT:    sb s3, 71(sp)
 ; RV64I-NEXT:    sb s2, 70(sp)
 ; RV64I-NEXT:    sb s1, 69(sp)

 ; RV32I-NEXT:    lbu s0, 12(a0)
 ; RV32I-NEXT:    lbu s1, 13(a0)
 ; RV32I-NEXT:    lbu s2, 14(a0)
 ; RV32I-NEXT:    lbu s3, 15(a0)
 ; RV32I-NEXT:    lbu s4, 16(a0)
 ; RV32I-NEXT:    lbu s5, 17(a0)
 ; RV32I-NEXT:    lbu s6, 18(a0)
 ; RV32I-NEXT:    lbu s7, 19(a0)
-; RV32I-NEXT:    lbu s8, 1(a1)
-; RV32I-NEXT:    lbu s9, 20(a0)
+; RV32I-NEXT:    lbu s8, 20(a0)
+; RV32I-NEXT:    lbu s9, 1(a1)
 ; RV32I-NEXT:    lbu s10, 21(a0)
-; RV32I-NEXT:    lbu s11, 0(a1)
-; RV32I-NEXT:    slli s8, s8, 8
-; RV32I-NEXT:    lbu ra, 2(a1)
-; RV32I-NEXT:    lbu a1, 3(a1)
-; RV32I-NEXT:    or s8, s8, s11
 ; RV32I-NEXT:    lbu s11, 22(a0)
-; RV32I-NEXT:    slli ra, ra, 16
-; RV32I-NEXT:    slli a1, a1, 24
-; RV32I-NEXT:    or a1, a1, ra
+; RV32I-NEXT:    lbu ra, 0(a1)
+; RV32I-NEXT:    slli s9, s9, 8
+; RV32I-NEXT:    lbu a3, 2(a1)
+; RV32I-NEXT:    lbu a1, 3(a1)
+; RV32I-NEXT:    or s9, s9, ra
 ; RV32I-NEXT:    lbu ra, 23(a0)
-; RV32I-NEXT:    or t0, a1, s8
-; RV32I-NEXT:    lbu s8, 24(a0)
-; RV32I-NEXT:    lbu a7, 25(a0)
+; RV32I-NEXT:    slli a3, a3, 16
+; RV32I-NEXT:    slli a1, a1, 24
+; RV32I-NEXT:    or a1, a1, a3
+; RV32I-NEXT:    lbu a7, 24(a0)
+; RV32I-NEXT:    or t0, a1, s9
+; RV32I-NEXT:    lbu s9, 25(a0)
 ; RV32I-NEXT:    lbu a6, 26(a0)
 ; RV32I-NEXT:    lbu a5, 27(a0)
 ; RV32I-NEXT:    lbu a1, 31(a0)
 ; RV32I-NEXT:    lbu a3, 30(a0)
 ; RV32I-NEXT:    lbu a4, 29(a0)
 ; RV32I-NEXT:    lbu a0, 28(a0)
 ; RV32I-NEXT:    sb a1, 59(sp)
 ; RV32I-NEXT:    sb a3, 58(sp)
 ; RV32I-NEXT:    sb a4, 57(sp)
 ; RV32I-NEXT:    sb a0, 56(sp)
 ; RV32I-NEXT:    sb a5, 55(sp)
 ; RV32I-NEXT:    sb a6, 54(sp)
-; RV32I-NEXT:    sb a7, 53(sp)
-; RV32I-NEXT:    sb s8, 52(sp)
+; RV32I-NEXT:    sb s9, 53(sp)
+; RV32I-NEXT:    sb a7, 52(sp)
 ; RV32I-NEXT:    sb ra, 51(sp)
 ; RV32I-NEXT:    sb s11, 50(sp)
 ; RV32I-NEXT:    sb s10, 49(sp)
-; RV32I-NEXT:    sb s9, 48(sp)
+; RV32I-NEXT:    sb s8, 48(sp)
 ; RV32I-NEXT:    sb s7, 47(sp)
 ; RV32I-NEXT:    sb s6, 46(sp)
 ; RV32I-NEXT:    sb s5, 45(sp)
 ; RV32I-NEXT:    sb s4, 44(sp)
 ; RV32I-NEXT:    sb zero, 91(sp)
 ; RV32I-NEXT:    sb zero, 90(sp)
 ; RV32I-NEXT:    sb zero, 89(sp)
 ; RV32I-NEXT:    sb zero, 88(sp)

 ; RV64I-NEXT:    lbu s1, 13(a0)
 ; RV64I-NEXT:    lbu s2, 14(a0)
 ; RV64I-NEXT:    lbu s3, 15(a0)
 ; RV64I-NEXT:    lbu s4, 16(a0)
 ; RV64I-NEXT:    lbu s5, 17(a0)
 ; RV64I-NEXT:    lbu s6, 18(a0)
 ; RV64I-NEXT:    lbu s7, 19(a0)
 ; RV64I-NEXT:    lbu s8, 20(a0)
-; RV64I-NEXT:    lbu s9, 1(a1)
-; RV64I-NEXT:    lbu s10, 0(a1)
-; RV64I-NEXT:    lbu s11, 2(a1)
-; RV64I-NEXT:    lbu ra, 3(a1)
-; RV64I-NEXT:    slli s9, s9, 8
-; RV64I-NEXT:    or s9, s9, s10
-; RV64I-NEXT:    slli s11, s11, 16
-; RV64I-NEXT:    slli ra, ra, 24
-; RV64I-NEXT:    lbu s10, 5(a1)
-; RV64I-NEXT:    or s11, ra, s11
-; RV64I-NEXT:    or s9, s11, s9
-; RV64I-NEXT:    lbu s11, 4(a1)
+; RV64I-NEXT:    lbu s9, 21(a0)
+; RV64I-NEXT:    lbu s10, 1(a1)
+; RV64I-NEXT:    lbu s11, 0(a1)
+; RV64I-NEXT:    lbu ra, 2(a1)
+; RV64I-NEXT:    lbu a3, 3(a1)
 ; RV64I-NEXT:    slli s10, s10, 8
+; RV64I-NEXT:    or s10, s10, s11
+; RV64I-NEXT:    slli ra, ra, 16
+; RV64I-NEXT:    slli a3, a3, 24
+; RV64I-NEXT:    lbu s11, 5(a1)
+; RV64I-NEXT:    or a3, a3, ra
+; RV64I-NEXT:    or a3, a3, s10
+; RV64I-NEXT:    lbu s10, 4(a1)
+; RV64I-NEXT:    slli s11, s11, 8
 ; RV64I-NEXT:    lbu ra, 6(a1)
 ; RV64I-NEXT:    lbu a1, 7(a1)
-; RV64I-NEXT:    or s10, s10, s11
-; RV64I-NEXT:    lbu s11, 21(a0)
+; RV64I-NEXT:    or s10, s11, s10
+; RV64I-NEXT:    lbu s11, 22(a0)
 ; RV64I-NEXT:    slli ra, ra, 16
 ; RV64I-NEXT:    slli a1, a1, 24
 ; RV64I-NEXT:    or a1, a1, ra
-; RV64I-NEXT:    lbu ra, 22(a0)
+; RV64I-NEXT:    lbu ra, 23(a0)
 ; RV64I-NEXT:    or a1, a1, s10
-; RV64I-NEXT:    lbu s10, 23(a0)
+; RV64I-NEXT:    lbu s10, 24(a0)
 ; RV64I-NEXT:    slli a1, a1, 32
-; RV64I-NEXT:    or t0, a1, s9
-; RV64I-NEXT:    lbu s9, 24(a0)
+; RV64I-NEXT:    or t0, a1, a3
 ; RV64I-NEXT:    lbu a7, 25(a0)
 ; RV64I-NEXT:    lbu a6, 26(a0)
 ; RV64I-NEXT:    lbu a5, 27(a0)
 ; RV64I-NEXT:    lbu a1, 31(a0)
 ; RV64I-NEXT:    lbu a3, 30(a0)
 ; RV64I-NEXT:    lbu a4, 29(a0)
 ; RV64I-NEXT:    lbu a0, 28(a0)
 ; RV64I-NEXT:    sb a1, 119(sp)
 ; RV64I-NEXT:    sb a3, 118(sp)
 ; RV64I-NEXT:    sb a4, 117(sp)
 ; RV64I-NEXT:    sb a0, 116(sp)
 ; RV64I-NEXT:    sb a5, 115(sp)
 ; RV64I-NEXT:    sb a6, 114(sp)
 ; RV64I-NEXT:    sb a7, 113(sp)
-; RV64I-NEXT:    sb s9, 112(sp)
-; RV64I-NEXT:    sb s10, 111(sp)
-; RV64I-NEXT:    sb ra, 110(sp)
-; RV64I-NEXT:    sb s11, 109(sp)
+; RV64I-NEXT:    sb s10, 112(sp)
+; RV64I-NEXT:    sb ra, 111(sp)
+; RV64I-NEXT:    sb s11, 110(sp)
+; RV64I-NEXT:    sb s9, 109(sp)
 ; RV64I-NEXT:    sb s8, 108(sp)
 ; RV64I-NEXT:    sb s7, 107(sp)
 ; RV64I-NEXT:    sb s6, 106(sp)
 ; RV64I-NEXT:    sb s5, 105(sp)
 ; RV64I-NEXT:    sb s4, 104(sp)
 ; RV64I-NEXT:    sb s3, 103(sp)
 ; RV64I-NEXT:    sb s2, 102(sp)
 ; RV64I-NEXT:    sb s1, 101(sp)

 ; RV32I-NEXT:    lbu s0, 12(a0)
 ; RV32I-NEXT:    lbu s1, 13(a0)
 ; RV32I-NEXT:    lbu s2, 14(a0)
 ; RV32I-NEXT:    lbu s3, 15(a0)
 ; RV32I-NEXT:    lbu s4, 16(a0)
 ; RV32I-NEXT:    lbu s5, 17(a0)
 ; RV32I-NEXT:    lbu s6, 18(a0)
 ; RV32I-NEXT:    lbu s7, 19(a0)
-; RV32I-NEXT:    lbu s8, 1(a1)
-; RV32I-NEXT:    lbu s9, 20(a0)
+; RV32I-NEXT:    lbu s8, 20(a0)
+; RV32I-NEXT:    lbu s9, 1(a1)
 ; RV32I-NEXT:    lbu s10, 21(a0)
-; RV32I-NEXT:    lbu s11, 0(a1)
-; RV32I-NEXT:    slli s8, s8, 8
-; RV32I-NEXT:    lbu ra, 2(a1)
-; RV32I-NEXT:    lbu a1, 3(a1)
-; RV32I-NEXT:    or s8, s8, s11
 ; RV32I-NEXT:    lbu s11, 22(a0)
-; RV32I-NEXT:    slli ra, ra, 16
-; RV32I-NEXT:    slli a1, a1, 24
-; RV32I-NEXT:    or a1, a1, ra
+; RV32I-NEXT:    lbu ra, 0(a1)
+; RV32I-NEXT:    slli s9, s9, 8
+; RV32I-NEXT:    lbu a3, 2(a1)
+; RV32I-NEXT:    lbu a1, 3(a1)
+; RV32I-NEXT:    or s9, s9, ra
 ; RV32I-NEXT:    lbu ra, 23(a0)
-; RV32I-NEXT:    or t0, a1, s8
-; RV32I-NEXT:    lbu s8, 24(a0)
-; RV32I-NEXT:    lbu a7, 25(a0)
+; RV32I-NEXT:    slli a3, a3, 16
+; RV32I-NEXT:    slli a1, a1, 24
+; RV32I-NEXT:    or a1, a1, a3
+; RV32I-NEXT:    lbu a7, 24(a0)
+; RV32I-NEXT:    or t0, a1, s9
+; RV32I-NEXT:    lbu s9, 25(a0)
 ; RV32I-NEXT:    lbu a6, 26(a0)
 ; RV32I-NEXT:    lbu a5, 27(a0)
 ; RV32I-NEXT:    lbu a1, 31(a0)
 ; RV32I-NEXT:    lbu a3, 30(a0)
 ; RV32I-NEXT:    lbu a4, 29(a0)
 ; RV32I-NEXT:    lbu a0, 28(a0)
 ; RV32I-NEXT:    sb a1, 91(sp)
 ; RV32I-NEXT:    sb a3, 90(sp)
 ; RV32I-NEXT:    sb a4, 89(sp)
 ; RV32I-NEXT:    sb a0, 88(sp)
 ; RV32I-NEXT:    sb a5, 87(sp)
 ; RV32I-NEXT:    sb a6, 86(sp)
-; RV32I-NEXT:    sb a7, 85(sp)
-; RV32I-NEXT:    sb s8, 84(sp)
+; RV32I-NEXT:    sb s9, 85(sp)
+; RV32I-NEXT:    sb a7, 84(sp)
 ; RV32I-NEXT:    sb ra, 83(sp)
 ; RV32I-NEXT:    sb s11, 82(sp)
 ; RV32I-NEXT:    sb s10, 81(sp)
-; RV32I-NEXT:    sb s9, 80(sp)
+; RV32I-NEXT:    sb s8, 80(sp)
 ; RV32I-NEXT:    sb s7, 79(sp)
 ; RV32I-NEXT:    sb s6, 78(sp)
 ; RV32I-NEXT:    sb s5, 77(sp)
 ; RV32I-NEXT:    sb s4, 76(sp)
 ; RV32I-NEXT:    sb zero, 59(sp)
 ; RV32I-NEXT:    sb zero, 58(sp)
 ; RV32I-NEXT:    sb zero, 57(sp)
 ; RV32I-NEXT:    sb zero, 56(sp)

 ; RV64I-NEXT:    lbu s1, 12(a0)
 ; RV64I-NEXT:    lbu s2, 13(a0)
 ; RV64I-NEXT:    lbu s3, 14(a0)
 ; RV64I-NEXT:    lbu s4, 15(a0)
 ; RV64I-NEXT:    lbu s5, 16(a0)
 ; RV64I-NEXT:    lbu s6, 17(a0)
 ; RV64I-NEXT:    lbu s7, 18(a0)
 ; RV64I-NEXT:    lbu s8, 19(a0)
-; RV64I-NEXT:    lbu s9, 1(a1)
-; RV64I-NEXT:    lbu s10, 0(a1)
-; RV64I-NEXT:    lbu s11, 2(a1)
-; RV64I-NEXT:    lbu ra, 3(a1)
-; RV64I-NEXT:    slli s9, s9, 8
-; RV64I-NEXT:    or s9, s9, s10
-; RV64I-NEXT:    slli s11, s11, 16
-; RV64I-NEXT:    slli ra, ra, 24
-; RV64I-NEXT:    lbu s10, 5(a1)
-; RV64I-NEXT:    or s11, ra, s11
-; RV64I-NEXT:    or s9, s11, s9
-; RV64I-NEXT:    lbu s11, 4(a1)
+; RV64I-NEXT:    lbu s9, 20(a0)
+; RV64I-NEXT:    lbu s10, 1(a1)
+; RV64I-NEXT:    lbu s11, 0(a1)
+; RV64I-NEXT:    lbu ra, 2(a1)
+; RV64I-NEXT:    lbu a3, 3(a1)
 ; RV64I-NEXT:    slli s10, s10, 8
+; RV64I-NEXT:    or s10, s10, s11
+; RV64I-NEXT:    slli ra, ra, 16
+; RV64I-NEXT:    slli a3, a3, 24
+; RV64I-NEXT:    lbu s11, 5(a1)
+; RV64I-NEXT:    or a3, a3, ra
+; RV64I-NEXT:    or a3, a3, s10
+; RV64I-NEXT:    lbu s10, 4(a1)
+; RV64I-NEXT:    slli s11, s11, 8
 ; RV64I-NEXT:    lbu ra, 6(a1)
 ; RV64I-NEXT:    lbu a1, 7(a1)
-; RV64I-NEXT:    or s10, s10, s11
-; RV64I-NEXT:    lbu s11, 20(a0)
+; RV64I-NEXT:    or s10, s11, s10
+; RV64I-NEXT:    lbu s11, 21(a0)
 ; RV64I-NEXT:    slli ra, ra, 16
 ; RV64I-NEXT:    slli a1, a1, 24
 ; RV64I-NEXT:    or a1, a1, ra
-; RV64I-NEXT:    lbu ra, 21(a0)
+; RV64I-NEXT:    lbu ra, 22(a0)
 ; RV64I-NEXT:    or a1, a1, s10
-; RV64I-NEXT:    lbu s10, 22(a0)
+; RV64I-NEXT:    lbu s10, 23(a0)
 ; RV64I-NEXT:    slli a1, a1, 32
-; RV64I-NEXT:    or t1, a1, s9
-; RV64I-NEXT:    lbu s9, 23(a0)
+; RV64I-NEXT:    or t1, a1, a3
 ; RV64I-NEXT:    lbu a7, 24(a0)
 ; RV64I-NEXT:    lbu a6, 25(a0)
 ; RV64I-NEXT:    lbu a5, 26(a0)
 ; RV64I-NEXT:    lbu a1, 30(a0)
 ; RV64I-NEXT:    lbu a3, 29(a0)
 ; RV64I-NEXT:    lbu a4, 28(a0)
 ; RV64I-NEXT:    lbu a0, 27(a0)
 ; RV64I-NEXT:    sb a1, 86(sp)
 ; RV64I-NEXT:    sb a3, 85(sp)
 ; RV64I-NEXT:    sb a4, 84(sp)
 ; RV64I-NEXT:    sb a0, 83(sp)
 ; RV64I-NEXT:    sb a5, 82(sp)
 ; RV64I-NEXT:    sb a6, 81(sp)
 ; RV64I-NEXT:    sb a7, 80(sp)
-; RV64I-NEXT:    sb s9, 79(sp)
-; RV64I-NEXT:    sb s10, 78(sp)
-; RV64I-NEXT:    sb ra, 77(sp)
-; RV64I-NEXT:    sb s11, 76(sp)
+; RV64I-NEXT:    sb s10, 79(sp)
+; RV64I-NEXT:    sb ra, 78(sp)
+; RV64I-NEXT:    sb s11, 77(sp)
+; RV64I-NEXT:    sb s9, 76(sp)
 ; RV64I-NEXT:    sb s8, 75(sp)
 ; RV64I-NEXT:    sb s7, 74(sp)
 ; RV64I-NEXT:    sb s6, 73(sp)
 ; RV64I-NEXT:    sb s5, 72(sp)
 ; RV64I-NEXT:    sb s4, 71(sp)
 ; RV64I-NEXT:    sb s3, 70(sp)
 ; RV64I-NEXT:    sb s2, 69(sp)
 ; RV64I-NEXT:    sb s1, 68(sp)

 ; RV32I-NEXT:    lbu s1, 11(a0)
 ; RV32I-NEXT:    lbu s2, 12(a0)
 ; RV32I-NEXT:    lbu s3, 13(a0)
 ; RV32I-NEXT:    lbu s4, 14(a0)
 ; RV32I-NEXT:    lbu s5, 15(a0)
 ; RV32I-NEXT:    lbu s6, 16(a0)
 ; RV32I-NEXT:    lbu s7, 17(a0)
 ; RV32I-NEXT:    lbu s8, 18(a0)
-; RV32I-NEXT:    lbu a4, 1(a1)
 ; RV32I-NEXT:    lbu s9, 19(a0)
+; RV32I-NEXT:    lbu a4, 1(a1)
 ; RV32I-NEXT:    lbu s10, 20(a0)
-; RV32I-NEXT:    lbu s11, 0(a1)
+; RV32I-NEXT:    lbu s11, 21(a0)
+; RV32I-NEXT:    lbu ra, 0(a1)
 ; RV32I-NEXT:    slli a4, a4, 8
-; RV32I-NEXT:    lbu ra, 2(a1)
+; RV32I-NEXT:    lbu a3, 2(a1)
 ; RV32I-NEXT:    lbu a1, 3(a1)
-; RV32I-NEXT:    or a4, a4, s11
-; RV32I-NEXT:    lbu s11, 21(a0)
-; RV32I-NEXT:    slli ra, ra, 16
-; RV32I-NEXT:    slli a1, a1, 24
-; RV32I-NEXT:    or a1, a1, ra
+; RV32I-NEXT:    or a4, a4, ra
 ; RV32I-NEXT:    lbu ra, 22(a0)
-; RV32I-NEXT:    or t1, a1, a4
+; RV32I-NEXT:    slli a3, a3, 16
+; RV32I-NEXT:    slli a1, a1, 24
+; RV32I-NEXT:    or a1, a1, a3
 ; RV32I-NEXT:    lbu t0, 23(a0)
+; RV32I-NEXT:    or t1, a1, a4
 ; RV32I-NEXT:    lbu a7, 24(a0)
 ; RV32I-NEXT:    lbu a6, 25(a0)
 ; RV32I-NEXT:    lbu a5, 26(a0)
 ; RV32I-NEXT:    lbu a1, 30(a0)
 ; RV32I-NEXT:    lbu a3, 29(a0)
 ; RV32I-NEXT:    lbu a4, 28(a0)
 ; RV32I-NEXT:    lbu a0, 27(a0)
 ; RV32I-NEXT:    sb a1, 58(sp)

 ; RV32I-NEXT:    lbu a1, 4(a3)
 ; RV32I-NEXT:    lbu a4, 6(a3)
 ; RV32I-NEXT:    lbu a5, 7(a3)
 ; RV32I-NEXT:    slli a0, a0, 8
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    slli a4, a4, 16
 ; RV32I-NEXT:    slli a5, a5, 24
 ; RV32I-NEXT:    or a4, a5, a4
-; RV32I-NEXT:    or t4, a4, a0
+; RV32I-NEXT:    or a5, a4, a0
 ; RV32I-NEXT:    andi a4, t1, 7
 ; RV32I-NEXT:    lbu a0, 9(a3)
 ; RV32I-NEXT:    lbu a1, 8(a3)
-; RV32I-NEXT:    lbu a5, 10(a3)
-; RV32I-NEXT:    lbu a6, 11(a3)
+; RV32I-NEXT:    lbu a6, 10(a3)
+; RV32I-NEXT:    lbu a7, 11(a3)
 ; RV32I-NEXT:    slli a0, a0, 8
 ; RV32I-NEXT:    or a0, a0, a1
-; RV32I-NEXT:    slli a5, a5, 16
-; RV32I-NEXT:    slli a6, a6, 24
-; RV32I-NEXT:    or a1, a6, a5
+; RV32I-NEXT:    slli a6, a6, 16
+; RV32I-NEXT:    slli a7, a7, 24
+; RV32I-NEXT:    or a1, a7, a6
 ; RV32I-NEXT:    or a6, a1, a0
 ; RV32I-NEXT:    slli a0, a6, 1
 ; RV32I-NEXT:    not t0, a4
 ; RV32I-NEXT:    sll a0, a0, t0
 ; RV32I-NEXT:    lbu a1, 1(a3)
-; RV32I-NEXT:    lbu a5, 0(a3)
-; RV32I-NEXT:    lbu a7, 2(a3)
-; RV32I-NEXT:    lbu t1, 3(a3)
+; RV32I-NEXT:    lbu a7, 0(a3)
+; RV32I-NEXT:    lbu t1, 2(a3)
+; RV32I-NEXT:    lbu t2, 3(a3)
 ; RV32I-NEXT:    slli a1, a1, 8
-; RV32I-NEXT:    or a1, a1, a5
-; RV32I-NEXT:    slli a7, a7, 16
-; RV32I-NEXT:    slli t1, t1, 24
-; RV32I-NEXT:    or a5, t1, a7
-; RV32I-NEXT:    or t1, a5, a1
-; RV32I-NEXT:    slli a1, t4, 1
+; RV32I-NEXT:    or a1, a1, a7
+; RV32I-NEXT:    slli t1, t1, 16
+; RV32I-NEXT:    slli t2, t2, 24
+; RV32I-NEXT:    or a7, t2, t1
+; RV32I-NEXT:    or t1, a7, a1
+; RV32I-NEXT:    slli a1, a5, 1
 ; RV32I-NEXT:    xori t2, a4, 31
 ; RV32I-NEXT:    sll a1, a1, t2
-; RV32I-NEXT:    lbu a5, 13(a3)
-; RV32I-NEXT:    lbu a7, 12(a3)
-; RV32I-NEXT:    lbu t3, 14(a3)
+; RV32I-NEXT:    lbu a7, 13(a3)
+; RV32I-NEXT:    lbu t3, 12(a3)
+; RV32I-NEXT:    lbu t4, 14(a3)
 ; RV32I-NEXT:    lbu t5, 15(a3)
-; RV32I-NEXT:    slli a5, a5, 8
-; RV32I-NEXT:    or a5, a5, a7
-; RV32I-NEXT:    slli t3, t3, 16
+; RV32I-NEXT:    slli a7, a7, 8
+; RV32I-NEXT:    or a7, a7, t3
+; RV32I-NEXT:    slli t4, t4, 16
 ; RV32I-NEXT:    slli t5, t5, 24
-; RV32I-NEXT:    or a7, t5, t3
-; RV32I-NEXT:    or t3, a7, a5
-; RV32I-NEXT:    lbu a5, 17(a3)
-; RV32I-NEXT:    lbu a7, 16(a3)
+; RV32I-NEXT:    or t3, t5, t4
+; RV32I-NEXT:    or t3, t3, a7
+; RV32I-NEXT:    lbu a7, 17(a3)
+; RV32I-NEXT:    lbu t4, 16(a3)
 ; RV32I-NEXT:    lbu t5, 18(a3)
 ; RV32I-NEXT:    lbu t6, 19(a3)
-; RV32I-NEXT:    slli a5, a5, 8
-; RV32I-NEXT:    or a5, a5, a7
+; RV32I-NEXT:    slli a7, a7, 8
+; RV32I-NEXT:    or a7, a7, t4
 ; RV32I-NEXT:    slli t5, t5, 16
 ; RV32I-NEXT:    slli t6, t6, 24
-; RV32I-NEXT:    or a7, t6, t5
-; RV32I-NEXT:    or a5, a7, a5
-; RV32I-NEXT:    slli a7, a5, 1
+; RV32I-NEXT:    or t4, t6, t5
+; RV32I-NEXT:    or t4, t4, a7
+; RV32I-NEXT:    slli a7, t4, 1
 ; RV32I-NEXT:    sll a7, a7, t0
 ; RV32I-NEXT:    lbu t5, 21(a3)
 ; RV32I-NEXT:    lbu t6, 20(a3)
 ; RV32I-NEXT:    lbu s0, 22(a3)
 ; RV32I-NEXT:    lbu s1, 23(a3)
 ; RV32I-NEXT:    slli t5, t5, 8
 ; RV32I-NEXT:    or t5, t5, t6
 ; RV32I-NEXT:    slli s0, s0, 16

 ; RV32I-NEXT:    slli s1, s1, 16
 ; RV32I-NEXT:    slli a3, a3, 24
 ; RV32I-NEXT:    or a3, a3, s1
 ; RV32I-NEXT:    slli s1, t5, 1
 ; RV32I-NEXT:    sll s1, s1, t2
 ; RV32I-NEXT:    or a3, a3, s0
 ; RV32I-NEXT:    slli s0, a3, 1
 ; RV32I-NEXT:    sll t2, s0, t2
-; RV32I-NEXT:    srl t4, t4, a4
+; RV32I-NEXT:    srl a5, a5, a4
 ; RV32I-NEXT:    srl t1, t1, a4
 ; RV32I-NEXT:    srl t3, t3, a4
 ; RV32I-NEXT:    srl a6, a6, a4
 ; RV32I-NEXT:    srl t5, t5, a4
-; RV32I-NEXT:    srl a5, a5, a4
+; RV32I-NEXT:    srl t4, t4, a4
 ; RV32I-NEXT:    srl t6, t6, a4
 ; RV32I-NEXT:    sra a3, a3, a4
 ; RV32I-NEXT:    srli a4, t6, 16
 ; RV32I-NEXT:    sb a4, 26(a2)
 ; RV32I-NEXT:    or a4, t6, t2
 ; RV32I-NEXT:    sb t6, 24(a2)
 ; RV32I-NEXT:    srli t2, t6, 8
 ; RV32I-NEXT:    sb t2, 25(a2)
 ; RV32I-NEXT:    srli t2, a3, 24
 ; RV32I-NEXT:    sb t2, 31(a2)
 ; RV32I-NEXT:    srli t2, a3, 16
 ; RV32I-NEXT:    sb t2, 30(a2)
 ; RV32I-NEXT:    sb a3, 28(a2)
 ; RV32I-NEXT:    srli a3, a3, 8
 ; RV32I-NEXT:    sb a3, 29(a2)
-; RV32I-NEXT:    srli a3, a5, 16
+; RV32I-NEXT:    srli a3, t4, 16
 ; RV32I-NEXT:    sb a3, 18(a2)
-; RV32I-NEXT:    or s1, a5, s1
-; RV32I-NEXT:    sb a5, 16(a2)
-; RV32I-NEXT:    srli a5, a5, 8
-; RV32I-NEXT:    sb a5, 17(a2)
-; RV32I-NEXT:    srli a3, t5, 16
-; RV32I-NEXT:    sb a3, 22(a2)
-; RV32I-NEXT:    or a3, t5, t0
+; RV32I-NEXT:    or a3, t4, s1
+; RV32I-NEXT:    sb t4, 16(a2)
+; RV32I-NEXT:    srli t2, t4, 8
+; RV32I-NEXT:    sb t2, 17(a2)
+; RV32I-NEXT:    srli t2, t5, 16
+; RV32I-NEXT:    sb t2, 22(a2)
+; RV32I-NEXT:    or t0, t5, t0
 ; RV32I-NEXT:    sb t5, 20(a2)
-; RV32I-NEXT:    srli a5, t5, 8
-; RV32I-NEXT:    sb a5, 21(a2)
-; RV32I-NEXT:    srli a5, a6, 16
-; RV32I-NEXT:    sb a5, 10(a2)
-; RV32I-NEXT:    or a5, a6, s2
+; RV32I-NEXT:    srli t2, t5, 8
+; RV32I-NEXT:    sb t2, 21(a2)
+; RV32I-NEXT:    srli t2, a6, 16
+; RV32I-NEXT:    sb t2, 10(a2)
+; RV32I-NEXT:    or t2, a6, s2
 ; RV32I-NEXT:    sb a6, 8(a2)
 ; RV32I-NEXT:    srli a6, a6, 8
 ; RV32I-NEXT:    sb a6, 9(a2)
 ; RV32I-NEXT:    srli a6, t3, 16
 ; RV32I-NEXT:    sb a6, 14(a2)
 ; RV32I-NEXT:    or a6, t3, a7
 ; RV32I-NEXT:    sb t3, 12(a2)
 ; RV32I-NEXT:    srli a7, t3, 8
 ; RV32I-NEXT:    sb a7, 13(a2)
 ; RV32I-NEXT:    srli a7, t1, 16
 ; RV32I-NEXT:    sb a7, 2(a2)
 ; RV32I-NEXT:    or a1, t1, a1
 ; RV32I-NEXT:    sb t1, 0(a2)
 ; RV32I-NEXT:    srli a7, t1, 8
 ; RV32I-NEXT:    sb a7, 1(a2)
-; RV32I-NEXT:    srli a7, t4, 16
+; RV32I-NEXT:    srli a7, a5, 16
 ; RV32I-NEXT:    sb a7, 6(a2)
-; RV32I-NEXT:    or a0, t4, a0
-; RV32I-NEXT:    sb t4, 4(a2)
-; RV32I-NEXT:    srli a7, t4, 8
-; RV32I-NEXT:    sb a7, 5(a2)
+; RV32I-NEXT:    or a0, a5, a0
+; RV32I-NEXT:    sb a5, 4(a2)
+; RV32I-NEXT:    srli a5, a5, 8
+; RV32I-NEXT:    sb a5, 5(a2)
 ; RV32I-NEXT:    srli a4, a4, 24
 ; RV32I-NEXT:    sb a4, 27(a2)
-; RV32I-NEXT:    srli s1, s1, 24
-; RV32I-NEXT:    sb s1, 19(a2)
 ; RV32I-NEXT:    srli a3, a3, 24
+; RV32I-NEXT:    sb a3, 19(a2)
+; RV32I-NEXT:    srli a3, t0, 24
 ; RV32I-NEXT:    sb a3, 23(a2)
-; RV32I-NEXT:    srli a5, a5, 24
-; RV32I-NEXT:    sb a5, 11(a2)
+; RV32I-NEXT:    srli a3, t2, 24
+; RV32I-NEXT:    sb a3, 11(a2)
 ; RV32I-NEXT:    srli a3, a6, 24
 ; RV32I-NEXT:    sb a3, 15(a2)
 ; RV32I-NEXT:    srli a1, a1, 24
 ; RV32I-NEXT:    sb a1, 3(a2)
 ; RV32I-NEXT:    srli a0, a0, 24
 ; RV32I-NEXT:    sb a0, 7(a2)
 ; RV32I-NEXT:    lw ra, 140(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 136(sp) # 4-byte Folded Reload