[XCOFF] Force recording a relocation for weak symbol label.

[Esme]

Summary

Currently, if there are multiple definitions of the same symbol declared has weak linkage, the linker may choose the wrong one when they are compiled with integrated-as.
For example

> cat t1.c 
__attribute__((weak))
__attribute__((noinline))
int foo() { return 3; }

int main() { return foo(); }

> cat t2.c
__attribute__((weak))
int foo() {  return 1; }

>  ~/Source/install.opt/bin/ibm-clang t2.c t1.c -fintegrated-as && ./a.out; echo $?
3
> ~/Source/install.opt/bin/ibm-clang t2.c t1.c -fno-integrated-as && ./a.out; echo $?
1

This patch fixes the issue.
If the target symbol is a weak label we must not attempt to resolve the fixup directly. Emit a relocation and leave resolution of the final target address to the linker.

[shchenz]

llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp

182–185

This seems not equal to what we handle for Linux(where we have local entry). On Linux, for non weak functions, they also need a force relocation for usage like compiling a shared library. I've asked help internally.

[shchenz]

LGTM. Thanks for addressing this bug.

llvm/lib/MC/XCOFFObjectWriter.cpp

670

Hmm, ok, seems before this change, we assume R_RBR type relocation is only applied to function sections, so that we only need the virtual address of the section because the target function offset in the section are always 0.

Now, we will generate R_RBR for functions that has no own csect, so using section virtual address is now not enough, we also need to consider about the offset of the function in the "big" csect.

This change makes sense to me.

llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp

182–185

Like what we discussed internally, I think this is enough for AIX.

llvm/lib/MC/XCOFFObjectWriter.cpp

else if (Type == XCOFF::RelocationType::R_TOC ||
     assert((SymASec->getMappingClass() == XCOFF::XMC_PR &&
             ParentSec->getMappingClass() == XCOFF::XMC_PR) &&
            "Only XMC_PR csect may have the R_RBR relocation.");
 
     // The address of the branch instruction should be the sum of section
     // address, fragment offset and Fixup offset.
     uint64_t BRInstrAddress =
         SectionMap[ParentSec]->Address + FixupOffsetInCsect;
-    // The FixedValue should be the difference between SymA csect address and BR
-    // instr address plus any constant value.
-    FixedValue =
-        SectionMap[SymASec]->Address - BRInstrAddress + Target.getConstant();
+    // The FixedValue should be the difference between symbol's virtual address
+    // and BR instr address plus any constant value.
+    FixedValue = getVirtualAddress(SymA, SymASec) - BRInstrAddress +
+                 Target.getConstant();
   } else if (Type == XCOFF::RelocationType::R_REF) {
     // The FixedValue and FixupOffsetInCsect should always be 0 since it
     // specifies a nonrelocating reference.
     FixedValue = 0;
     FixupOffsetInCsect = 0;
   }
 
   XCOFFRelocation Reloc = {Index, FixupOffsetInCsect, SignAndSize, Type};

llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp

 #include "llvm/MC/MCAssembler.h"
 #include "llvm/MC/MCELFObjectWriter.h"
 #include "llvm/MC/MCFixupKindInfo.h"
 #include "llvm/MC/MCMachObjectWriter.h"
 #include "llvm/MC/MCObjectWriter.h"
 #include "llvm/MC/MCSectionMachO.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/MCSymbolELF.h"
+#include "llvm/MC/MCSymbolXCOFF.h"
 #include "llvm/MC/MCValue.h"
 #include "llvm/MC/TargetRegistry.h"
 #include "llvm/Support/ErrorHandling.h"
 using namespace llvm;
 
 static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value) {
   switch (Kind) {
   default:
case PPC::fixup_ppc_br24_notoc:
       if (const MCSymbolRefExpr *A = Target.getSymA()) {
         if (const auto *S = dyn_cast<MCSymbolELF>(&A->getSymbol())) {
           // The "other" values are stored in the last 6 bits of the second
           // byte. The traditional defines for STO values assume the full byte
           // and thus the shift to pack it.
           unsigned Other = S->getOther() << 2;
           if ((Other & ELF::STO_PPC64_LOCAL_MASK) != 0)
             return true;
-        }
+        } else if (const auto *S = dyn_cast<MCSymbolXCOFF>(&A->getSymbol())) {
+          return !Target.isAbsolute() && S->isExternal() &&
+                 S->getStorageClass() == XCOFF::C_WEAKEXT;
       }
       return false;
     }
   }
 
   bool fixupNeedsRelaxation(const MCFixup &Fixup,
                             uint64_t Value,
                             const MCRelaxableFragment *DF,

llvm/test/CodeGen/PowerPC/aix-weak-reloc.ll

+; RUN: llc -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llvm-objdump -dr %t.o | FileCheck --check-prefix=OBJ32 %s
+
+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llvm-objdump -dr %t.o | FileCheck --check-prefix=OBJ64 %s
+
+; Function Attrs: noinline nounwind optnone
+define i32 @main() {
+entry:
+  %retval = alloca i32, align 4
+  store i32 0, ptr %retval, align 4
+  %call = call i32 @foo()
+  ret i32 %call
+}
+
+; Function Attrs: noinline nounwind optnone
+define weak i32 @foo() {
+entry:
+  ret i32 3
+}
+
+; OBJ32:       00000000 <.main>:
+; OBJ32-NEXT:         0: 7c 08 02 a6    mflr 0
+; OBJ32-NEXT:         4: 94 21 ff c0    stwu 1, -64(1)
+; OBJ32-NEXT:         8: 38 60 00 00    li 3, 0
+; OBJ32-NEXT:         c: 90 01 00 48    stw 0, 72(1)
+; OBJ32-NEXT:        10: 90 61 00 3c    stw 3, 60(1)
+; OBJ32-NEXT:        14: 48 00 00 31    bl 0x44 <.foo>
+; OBJ32-NEXT:       00000014:  R_RBR  .foo
+; OBJ32-NEXT:        18: 60 00 00 00    nop
+; OBJ32:       00000044 <.foo>:
+; OBJ32-NEXT:        44: 38 60 00 03    li 3, 3
+; OBJ32-NEXT:        48: 4e 80 00 20    blr
+
+; OBJ64:      0000000000000000 <.main>:
+; OBJ64-NEXT:        0: 7c 08 02 a6   mflr 0
+; OBJ64-NEXT:        4: f8 21 ff 81   stdu 1, -128(1)
+; OBJ64-NEXT:        8: 38 60 00 00   li 3, 0
+; OBJ64-NEXT:        c: f8 01 00 90   std 0, 144(1)
+; OBJ64-NEXT:       10: 90 61 00 7c   stw 3, 124(1)
+; OBJ64-NEXT:       14: 48 00 00 31   bl 0x44 <.foo>
+; OBJ64-NEXT:     0000000000000014:  R_RBR  .foo
+; OBJ64-NEXT:       18: 60 00 00 00   nop
+; OBJ64:      0000000000000044 <.foo>:
+; OBJ64-NEXT:       44: 38 60 00 03   li 3, 3
+; OBJ64-NEXT:       48: 4e 80 00 20   blr