This is an archive of the discontinued LLVM Phabricator instance.

[PowerPC] Optimize TLS initial-exec sequence to use X-Form loads/stores
ClosedPublic

Authored by syzaara on Feb 14 2018, 2:13 PM.

Details

Summary

The TLS sequence for the initial exec access mode currently generates:

addis 4, 2, var_int@got@tprel@ha
ld 4, var_int@got@tprel@l(4)
add 4, 4, var_int@tls
lwz 5, 0(4)

The d-form load can be changed into an x-form load if we check that the input is coming from a special tls add instruction.

addis 3, 2, var_int@got@tprel@ha
ld 3, var_int@got@tprel@l(3)
lwzx 3, 3, var_int@tls

This patch adds new load/store instructions for integer scalar types and selects these instructions when an ISD::LOAD/STORE is fed by PPCISD::ADD_TLS.

Diff Detail

Repository
rL LLVM

Event Timeline

syzaara created this revision.Feb 14 2018, 2:13 PM

Please don't forget the diff context (that is missing with this patch).

lib/Target/PowerPC/PPCISelDAGToDAG.cpp
207 ↗(On Diff #134311)

Add a comment describing what these functions do.

585 ↗(On Diff #134311)

I find this name a little un-intuitive. Seems a little odd to use "output" with a store. Perhaps it might be clearer if the two types were MemVT and RegVT?

587 ↗(On Diff #134311)

This is unnecessarily nested. Please change this to an early exit if != PPCISD::ADD_TLS. Same for the load case below.

614 ↗(On Diff #134311)

This looks like it'll fit on the line above just fine. Perhaps run clang-format on this part of the patch.

lib/Target/PowerPC/PPCInstr64Bit.td
504 ↗(On Diff #134311)

Formatting issue on all these defs - the " should go under the 3.

523 ↗(On Diff #134311)

Why are these marked as cracked instructions?

syzaara updated this revision to Diff 134466.Feb 15 2018, 11:16 AM
nemanjai accepted this revision.Mar 2 2018, 8:19 AM

LGTM.

This revision is now accepted and ready to land.Mar 2 2018, 8:19 AM
This revision was automatically updated to reflect the committed changes.