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Differential D153235

[RISCV] Change the type of argument to clz and ctz from ZiZi/WiWi to iUZi/iUWi
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Authored by Jim on Jun 18 2023, 6:42 PM.

Details

Reviewers
craig.topper
Commits
rG612b7e10a9af: [RISCV] Change the type of argument to clz and ctz from ZiZi/WiWi to iUZi/iUWi
Summary

Input argument of clz and ctz should be unsigned type and return value
should be integer like builtin_clz and builtin_ctz defined in clang/include/clang/Basic/Builtins.def.

Diff Detail

Unit TestsFailed

TimeTest
5,920 mslibcxx CI - Modules > llvm-libc++-shared-cfg-in.libcxx/depr/depr_default_allocator/allocator_members::allocate.cxx2a.pass.cpp
5,950 mslibcxx CI - Modules > llvm-libc++-shared-cfg-in.libcxx/depr/depr_default_allocator/allocator_members::construct.cxx2a.pass.cpp
1,060 mslibcxx CI - Modules > llvm-libc++-shared-cfg-in.libcxx/input_output/filesystems/class_path/path_member/path_native_obs::string_alloc.pass.cpp
180 mslibcxx CI - Modules > llvm-libc++-shared-cfg-in.libcxx/localization/locales/locale/locale_types/locale_facet::no_allocation.pass.cpp
110 mslibcxx CI - Modules > llvm-libc++-shared-cfg-in.libcxx/utilities/utility/mem_res/mem_res_monotonic_buffer/mem_res_monotonic_buffer_mem::allocate_from_underaligned_buffer.pass.cpp
View Full Test Results (113 Failed)

Event Timeline

Jim created this revision.Jun 18 2023, 6:42 PM
Herald added a project: Restricted Project. · View Herald TranscriptJun 18 2023, 6:42 PM
Herald added subscribers: jobnoorman, luke, VincentWu and 26 others. · View Herald Transcript
Jim requested review of this revision.Jun 18 2023, 6:42 PM
Herald added a project: Restricted Project. · View Herald TranscriptJun 18 2023, 6:42 PM
Herald added subscribers: cfe-commits, wangpc, eopXD, MaskRay. · View Herald Transcript
Jim added a reviewer: craig.topper.Jun 18 2023, 6:43 PM
Harbormaster completed remote builds in B239690: Diff 532497.Jun 18 2023, 7:16 PM
craig.topper added inline comments.Jun 19 2023, 12:58 PM
clang/include/clang/Basic/BuiltinsRISCV.def
22

I'd prefer we use UWi instead of ULi. If we ever implement ilp32 on RV64, long will not be xlen bits.

Jim updated this revision to Diff 532790.Jun 19 2023, 10:30 PM

Address comment.

Jim retitled this revision from [RISCV] Change the type of argument to clz and ctz from ZiZi/WiWi to iUi/iULi to [RISCV] Change the type of argument to clz and ctz from ZiZi/WiWi to iUZi/iUWi.Jun 19 2023, 10:31 PM
Jim edited the summary of this revision. (Show Details)
Jim edited the summary of this revision. (Show Details)
Jim marked an inline comment as done.
Harbormaster completed remote builds in B239918: Diff 532790.Jun 19 2023, 11:51 PM
craig.topper accepted this revision.Jun 20 2023, 9:14 AM

LGTM

This revision is now accepted and ready to land.Jun 20 2023, 9:14 AM
craig.topper mentioned this in D153403: [RISCV] Use unsigned types for orc_b builtins..Jun 21 2023, 12:50 AM
This revision was landed with ongoing or failed builds.Jun 25 2023, 10:16 PM
Closed by commit rG612b7e10a9af: [RISCV] Change the type of argument to clz and ctz from ZiZi/WiWi to iUZi/iUWi (authored by Jim). · Explain Why
This revision was automatically updated to reflect the committed changes.
Jim added a commit: rG612b7e10a9af: [RISCV] Change the type of argument to clz and ctz from ZiZi/WiWi to iUZi/iUWi.
craig.topper mentioned this in rGf67dfb3cdb4b: [RISCV] Use unsigned types for orc_b builtins..Jun 25 2023, 10:54 PM

Revision Contents

PathSize
clang/
include/
clang/
Basic/
8 lines
test/
CodeGen/
RISCV/
rvb-intrinsics/
4 lines
8 lines

Diff 532497

clang/include/clang/Basic/BuiltinsRISCV.def

Show All 12 Lines
#if defined(BUILTIN) && !defined(TARGET_BUILTIN) #if defined(BUILTIN) && !defined(TARGET_BUILTIN)
# define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) BUILTIN(ID, TYPE, ATTRS) # define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) BUILTIN(ID, TYPE, ATTRS)
#endif #endif
// Zbb extension // Zbb extension
TARGET_BUILTIN(__builtin_riscv_orc_b_32, "ZiZi", "nc", "zbb") TARGET_BUILTIN(__builtin_riscv_orc_b_32, "ZiZi", "nc", "zbb")
TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "zbb,64bit") TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "zbb,64bit")
TARGET_BUILTIN(__builtin_riscv_clz_32, "ZiZi", "nc", "zbb|xtheadbb") TARGET_BUILTIN(__builtin_riscv_clz_32, "iUi", "nc", "zbb|xtheadbb")
TARGET_BUILTIN(__builtin_riscv_clz_64, "WiWi", "nc", "zbb|xtheadbb,64bit") TARGET_BUILTIN(__builtin_riscv_clz_64, "iULi", "nc", "zbb|xtheadbb,64bit")
craig.topperUnsubmitted
Done
ReplyInline Actions

I'd prefer we use UWi instead of ULi. If we ever implement ilp32 on RV64, long will not be xlen bits.

craig.topper: I'd prefer we use `UWi` instead of `ULi`. If we ever implement ilp32 on RV64, long will not be…
TARGET_BUILTIN(__builtin_riscv_ctz_32, "ZiZi", "nc", "zbb") TARGET_BUILTIN(__builtin_riscv_ctz_32, "iUi", "nc", "zbb")
TARGET_BUILTIN(__builtin_riscv_ctz_64, "WiWi", "nc", "zbb,64bit") TARGET_BUILTIN(__builtin_riscv_ctz_64, "iULi", "nc", "zbb,64bit")
// Zbc or Zbkc extension // Zbc or Zbkc extension
TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "zbc|zbkc") TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "zbc|zbkc")
TARGET_BUILTIN(__builtin_riscv_clmulh, "LiLiLi", "nc", "zbc|zbkc") TARGET_BUILTIN(__builtin_riscv_clmulh, "LiLiLi", "nc", "zbc|zbkc")
TARGET_BUILTIN(__builtin_riscv_clmulr, "LiLiLi", "nc", "zbc") TARGET_BUILTIN(__builtin_riscv_clmulr, "LiLiLi", "nc", "zbc")
// Zbkx // Zbkx
TARGET_BUILTIN(__builtin_riscv_xperm4, "LiLiLi", "nc", "zbkx") TARGET_BUILTIN(__builtin_riscv_xperm4, "LiLiLi", "nc", "zbkx")
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clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c

Show All 16 Lines
// RV32ZBB-LABEL: @clz_32( // RV32ZBB-LABEL: @clz_32(
// RV32ZBB-NEXT: entry: // RV32ZBB-NEXT: entry:
// RV32ZBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // RV32ZBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// RV32ZBB-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 // RV32ZBB-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
// RV32ZBB-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // RV32ZBB-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// RV32ZBB-NEXT: [[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 false) // RV32ZBB-NEXT: [[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 false)
// RV32ZBB-NEXT: ret i32 [[TMP1]] // RV32ZBB-NEXT: ret i32 [[TMP1]]
// //
int clz_32(int a) { int clz_32(unsigned int a) {
return __builtin_riscv_clz_32(a); return __builtin_riscv_clz_32(a);
} }
// RV32ZBB-LABEL: @ctz_32( // RV32ZBB-LABEL: @ctz_32(
// RV32ZBB-NEXT: entry: // RV32ZBB-NEXT: entry:
// RV32ZBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // RV32ZBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// RV32ZBB-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 // RV32ZBB-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
// RV32ZBB-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // RV32ZBB-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// RV32ZBB-NEXT: [[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 false) // RV32ZBB-NEXT: [[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 false)
// RV32ZBB-NEXT: ret i32 [[TMP1]] // RV32ZBB-NEXT: ret i32 [[TMP1]]
// //
int ctz_32(int a) { int ctz_32(unsigned int a) {
return __builtin_riscv_ctz_32(a); return __builtin_riscv_ctz_32(a);
} }
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clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c

Show All 28 Lines
// RV64ZBB-LABEL: @clz_32( // RV64ZBB-LABEL: @clz_32(
// RV64ZBB-NEXT: entry: // RV64ZBB-NEXT: entry:
// RV64ZBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // RV64ZBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// RV64ZBB-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 // RV64ZBB-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
// RV64ZBB-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // RV64ZBB-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// RV64ZBB-NEXT: [[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 false) // RV64ZBB-NEXT: [[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 false)
// RV64ZBB-NEXT: ret i32 [[TMP1]] // RV64ZBB-NEXT: ret i32 [[TMP1]]
// //
int clz_32(int a) { int clz_32(unsigned int a) {
return __builtin_riscv_clz_32(a); return __builtin_riscv_clz_32(a);
} }
// RV64ZBB-LABEL: @clz_64( // RV64ZBB-LABEL: @clz_64(
// RV64ZBB-NEXT: entry: // RV64ZBB-NEXT: entry:
// RV64ZBB-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // RV64ZBB-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// RV64ZBB-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 8 // RV64ZBB-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
// RV64ZBB-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 // RV64ZBB-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
// RV64ZBB-NEXT: [[TMP1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[TMP0]], i1 false) // RV64ZBB-NEXT: [[TMP1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[TMP0]], i1 false)
// RV64ZBB-NEXT: ret i64 [[TMP1]] // RV64ZBB-NEXT: ret i64 [[TMP1]]
// //
long clz_64(long a) { long clz_64(unsigned long a) {
return __builtin_riscv_clz_64(a); return __builtin_riscv_clz_64(a);
} }
// RV64ZBB-LABEL: @ctz_32( // RV64ZBB-LABEL: @ctz_32(
// RV64ZBB-NEXT: entry: // RV64ZBB-NEXT: entry:
// RV64ZBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // RV64ZBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// RV64ZBB-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 // RV64ZBB-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
// RV64ZBB-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // RV64ZBB-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// RV64ZBB-NEXT: [[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 false) // RV64ZBB-NEXT: [[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 false)
// RV64ZBB-NEXT: ret i32 [[TMP1]] // RV64ZBB-NEXT: ret i32 [[TMP1]]
// //
int ctz_32(int a) { int ctz_32(unsigned int a) {
return __builtin_riscv_ctz_32(a); return __builtin_riscv_ctz_32(a);
} }
// RV64ZBB-LABEL: @ctz_64( // RV64ZBB-LABEL: @ctz_64(
// RV64ZBB-NEXT: entry: // RV64ZBB-NEXT: entry:
// RV64ZBB-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // RV64ZBB-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// RV64ZBB-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 8 // RV64ZBB-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
// RV64ZBB-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 // RV64ZBB-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
// RV64ZBB-NEXT: [[TMP1:%.*]] = call i64 @llvm.cttz.i64(i64 [[TMP0]], i1 false) // RV64ZBB-NEXT: [[TMP1:%.*]] = call i64 @llvm.cttz.i64(i64 [[TMP0]], i1 false)
// RV64ZBB-NEXT: ret i64 [[TMP1]] // RV64ZBB-NEXT: ret i64 [[TMP1]]
// //
long ctz_64(long a) { long ctz_64(unsigned long a) {
return __builtin_riscv_ctz_64(a); return __builtin_riscv_ctz_64(a);
} }
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