[RISCV] Use unsigned types for orc_b builtins.

[craig.topper]

Summary

Inspried by D153235, I think bit manipulation makes more
sense on unsigned types.

clang/include/clang/Basic/BuiltinsRISCV.def

 //
 //===----------------------------------------------------------------------===//
 
 #if defined(BUILTIN) && !defined(TARGET_BUILTIN)
 #   define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) BUILTIN(ID, TYPE, ATTRS)
 #endif
 
 // Zbb extension
-TARGET_BUILTIN(__builtin_riscv_orc_b_32, "ZiZi", "nc", "zbb")
-TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "zbb,64bit")
+TARGET_BUILTIN(__builtin_riscv_orc_b_32, "UZiUZi", "nc", "zbb")
+TARGET_BUILTIN(__builtin_riscv_orc_b_64, "UWiUWi", "nc", "zbb,64bit")
 TARGET_BUILTIN(__builtin_riscv_clz_32, "iUZi", "nc", "zbb|xtheadbb")
 TARGET_BUILTIN(__builtin_riscv_clz_64, "iUWi", "nc", "zbb|xtheadbb,64bit")
 TARGET_BUILTIN(__builtin_riscv_ctz_32, "iUZi", "nc", "zbb")
 TARGET_BUILTIN(__builtin_riscv_ctz_64, "iUWi", "nc", "zbb,64bit")
 
 // Zbc or Zbkc extension
 TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "zbc|zbkc")
 TARGET_BUILTIN(__builtin_riscv_clmulh, "LiLiLi", "nc", "zbc|zbkc")

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb-error.c

 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // RUN: %clang_cc1 -triple riscv32 -target-feature +zbb -verify %s -o -
 
-int orc_b_64(int a) {
+unsigned int orc_b_64(unsigned int a) {
   return __builtin_riscv_orc_b_64(a); // expected-error {{builtin requires: 'RV64'}}
 }

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c

 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // RUN: %clang_cc1 -triple riscv32 -target-feature +zbb -emit-llvm %s -o - \
 // RUN:     | FileCheck %s  -check-prefix=RV32ZBB
 
 // RV32ZBB-LABEL: @orc_b_32(
 // RV32ZBB-NEXT:  entry:
 // RV32ZBB-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
 // RV32ZBB-NEXT:    store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
 // RV32ZBB-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
 // RV32ZBB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.orc.b.i32(i32 [[TMP0]])
 // RV32ZBB-NEXT:    ret i32 [[TMP1]]
 //
-int orc_b_32(int a) {
+unsigned int orc_b_32(unsigned int a) {
   return __builtin_riscv_orc_b_32(a);
 }
 
 // RV32ZBB-LABEL: @clz_32(
 // RV32ZBB-NEXT:  entry:
 // RV32ZBB-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
 // RV32ZBB-NEXT:    store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
 // RV32ZBB-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4

 // RV32ZBB-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
 // RV32ZBB-NEXT:    store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
 // RV32ZBB-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
 // RV32ZBB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 false)
 // RV32ZBB-NEXT:    ret i32 [[TMP1]]
 //
 int ctz_32(unsigned int a) {
   return __builtin_riscv_ctz_32(a);
-}
+}
 

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c

 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // RUN: %clang_cc1 -triple riscv64 -target-feature +zbb -emit-llvm %s -o - \
 // RUN:     | FileCheck %s  -check-prefix=RV64ZBB
 
 // RV64ZBB-LABEL: @orc_b_32(
 // RV64ZBB-NEXT:  entry:
 // RV64ZBB-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
 // RV64ZBB-NEXT:    store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
 // RV64ZBB-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
 // RV64ZBB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.orc.b.i32(i32 [[TMP0]])
 // RV64ZBB-NEXT:    ret i32 [[TMP1]]
 //
-int orc_b_32(int a) {
+unsigned int orc_b_32(unsigned int a) {
   return __builtin_riscv_orc_b_32(a);
 }
 
 // RV64ZBB-LABEL: @orc_b_64(
 // RV64ZBB-NEXT:  entry:
 // RV64ZBB-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
 // RV64ZBB-NEXT:    store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
 // RV64ZBB-NEXT:    [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
 // RV64ZBB-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.orc.b.i64(i64 [[TMP0]])
 // RV64ZBB-NEXT:    ret i64 [[TMP1]]
 //
-long orc_b_64(long a) {
+unsigned long orc_b_64(unsigned long a) {
   return __builtin_riscv_orc_b_64(a);
 }
 
 // RV64ZBB-LABEL: @clz_32(
 // RV64ZBB-NEXT:  entry:
 // RV64ZBB-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
 // RV64ZBB-NEXT:    store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
 // RV64ZBB-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4

 // RV64ZBB-NEXT:    [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
 // RV64ZBB-NEXT:    [[TMP1:%.*]] = call i64 @llvm.cttz.i64(i64 [[TMP0]], i1 false)
 // RV64ZBB-NEXT:    store i64 [[TMP1]], ptr [[RETVAL]], align 4
 // RV64ZBB-NEXT:    [[TMP2:%.*]] = load i32, ptr [[RETVAL]], align 4
 // RV64ZBB-NEXT:    ret i32 [[TMP2]]
 //
 int ctz_64(unsigned long a) {
   return __builtin_riscv_ctz_64(a);
-}
+}