[RISCV] Remove fcvt.d.l(u) and fcvt.l(u).d instructions with _IN32X suffix.

[craig.topper]

Summary

_IN32X instructions are for Zdinx on RV32 where doubles are split
across 2 registers.

fcvt.d.l(u) and fcvt.l(u).d are RV64 only instructions so we don't
need _IN32X versions of them.

This existed prior to D152948. I have no looked to see how easy
this is to fix without D152948.

[craig.topper]

Abandoning in favor of D152952

llvm/lib/Target/RISCV/RISCVInstrInfoD.td

 def DExt       : ExtInfo<"", "", [HasStdExtD], FPR32, FPR64, ?>;
 
 def ZdinxExt   : ExtInfo<"_INX", "RVZfinx", [HasStdExtZdinx, IsRV64],
                          FPR32INX, FPR64INX, ?>;
 def Zdinx32Ext : ExtInfo<"_IN32X", "RV32Zdinx", [HasStdExtZdinx, IsRV32],
                          FPR32INX, FPR64IN32X, ?>;
 
 defvar DExts     = [DExt, ZdinxExt, Zdinx32Ext];
+defvar DExtsRV64 = [DExt, ZdinxExt];
 
 //===----------------------------------------------------------------------===//
 // Instructions
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtD] in {
 def FLD : FPLoad_r<0b011, "fld", FPR64, WriteFLD64>;
 
foreach Ext = DExts in {
 
   defm FCVT_D_W : FPUnaryOp_r_m<0b1101001, 0b00000, 0b000, Ext, Ext.F64Ty, GPR,
                                 "fcvt.d.w">,
                   Sched<[WriteFCvtI32ToF64, ReadFCvtI32ToF64]>;
 
   defm FCVT_D_WU : FPUnaryOp_r_m<0b1101001, 0b00001, 0b000, Ext, Ext.F64Ty, GPR,
                                  "fcvt.d.wu">,
                    Sched<[WriteFCvtI32ToF64, ReadFCvtI32ToF64]>;
+} // foreach Ext = DExts
+
+foreach Ext = DExtsRV64 in {
   defm FCVT_L_D : FPUnaryOp_r_frm_m<0b1100001, 0b00010, Ext, GPR, Ext.F64Ty,
                                     "fcvt.l.d", [IsRV64]>,
                   Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]>;
 
   defm FCVT_LU_D : FPUnaryOp_r_frm_m<0b1100001, 0b00011, Ext, GPR, Ext.F64Ty,
                                      "fcvt.lu.d", [IsRV64]>,
                    Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]>;
 
   defm FCVT_D_L : FPUnaryOp_r_frm_m<0b1101001, 0b00010, Ext, Ext.F64Ty, GPR,
                                     "fcvt.d.l", [IsRV64]>,
                   Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]>;
 
   defm FCVT_D_LU : FPUnaryOp_r_frm_m<0b1101001, 0b00011, Ext, Ext.F64Ty, GPR,
                                      "fcvt.d.lu", [IsRV64]>,
                    Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]>;
-} // foreach Ext = DExts
+} // foreach Ext = DExtsRV64
 
 let Predicates = [HasStdExtD, IsRV64], mayRaiseFPException = 0 in
 def FMV_X_D : FPUnaryOp_r<0b1110001, 0b00000, 0b000, GPR, FPR64, "fmv.x.d">,
               Sched<[WriteFMovF64ToI64, ReadFMovF64ToI64]>;
 
 let Predicates = [HasStdExtD, IsRV64], mayRaiseFPException = 0 in
 def FMV_D_X : FPUnaryOp_r<0b1111001, 0b00000, 0b000, FPR64, GPR, "fmv.d.x">,
               Sched<[WriteFMovI64ToF64, ReadFMovI64ToF64]>;