AMDGPU: Use correct lowering for llvm.log2.f32

[arsenm]

Summary

We previously directly codegened to v_log_f32, which is broken for
denormals. The lowering isn't complicated, you simply need to scale
denormal inputs and adjust the result. Note log and log10 are still
not accurate enough, and will be fixed separately.

[rampitec]

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

2463

Don't you need to produce v_log_f16 if denorm handling is not needed?

[arsenm]

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

2463

v_log_f16 is supposed to be fully correct. This is the promoted path for SI/CI that don't have it

[rampitec]

LGTM

[rampitec]

Please let Brian a chance to review too.

[rampitec]

llvm/docs/AMDGPUUsage.rst

963

Typo 0.51ULP?

[arsenm]

llvm/docs/AMDGPUUsage.rst

963

That's what the last 3 public ISA docs say

[rampitec]

llvm/docs/AMDGPUUsage.rst

963

For what I know this does not make any sense. Someones finger must be mistyped. @b-sumner can you comment please?

[rampitec]

llvm/docs/AMDGPUUsage.rst

963

I.e. I understand 0.5ULP. This is half of a bit, when you do not known how to round it: up or down. But what is 1/100 of a bit? Is that like your computation is 100 bits more accurate, but you do not know how to round it?

[foad]

llvm/docs/AMDGPUUsage.rst

963

It's when the true result is something.51 but the hardware rounds it down, or the true result is something.49 but the hardware rounds it up.

I assume for f16 someone exhaustively tested all inputs, measured the largest error from the true result, and decided 0.51 bits was a nice neat upper bound that they could publish.

[rampitec]

llvm/docs/AMDGPUUsage.rst

963

But the representation is in binary, not in decimal. There can be no true result 0.51 decimal to have this rounding problem, it must be 0.51 of a bit. This is the definition of the ULP: 1 bit. We have 0.51 of a bit here.

[rampitec]

llvm/docs/AMDGPUUsage.rst

963

I.e. anything above 0.5ULP is 1ULP to me. If your previous mantissa bit is 1 you round it up, if it is 0 you round it down, or whatever rules you have you can only change a single bit. Your 100th bit which you cannot represent doesn't matter. If you can have a single bit error in the lowest mantissa bit, this is 1ULP.

[foad]

llvm/docs/AMDGPUUsage.rst

963

There is a true infinitely precise mathematical result. The documented error bound is the difference from the true mathematical result, not the difference from the correctly rounded result.

[rampitec]

llvm/docs/AMDGPUUsage.rst

963

We certainly do not have a common ground here, so I am calling for @b-sumner again.

[arsenm]

llvm/docs/AMDGPUUsage.rst

963

I can also just delete the note about the ULP. It's not exactly great to have to repeat the ISA manual on every instruction

963

But yes, the ULP definition is in terms of the true result, not the expected rounded result

[rampitec]

llvm/docs/AMDGPUUsage.rst

963

If that's in the manual we need to fix it.

[rampitec]

llvm/docs/AMDGPUUsage.rst

963

Whatever you think of a true result, I want to understand what is 0.51ULP accuracy of the rounding of it. I.e. I am not certain about some transcendental results [in a given notation]. But up to this point I was pretty much sure about its rounding.

[rampitec]

To proceed I want to see a one single example of a computation giving a wrong result with 0.5ULP rounding, correct result with 0.51ULP rounding [whatever it is], and then again wrong result with 1ULP rounding.

[arsenm]

In D152766#4440496, @rampitec wrote:

To proceed I want to see a one single example of a computation giving a wrong result with 0.5ULP rounding, correct result with 0.51ULP rounding [whatever it is], and then again wrong result with 1ULP rounding.

This has nothing to do with the patch. There's no behavior change here for the f16 intrinsic. We continue to directly pass through to the hardware instructions, and the documentation is simply restating what the ISA manual states. The point of the documentation is stating the f16 case passes through directly and the f32 is a small expansion

[rampitec]

OK, got the explanation from @b-sumner. This looks very unusual, but it is correct.

[JonChesterfield]

In D152766#4442379, @rampitec wrote:

OK, got the explanation from @b-sumner. This looks very unusual, but it is correct.

Please could you summarise it here? Also curious what's going on here

[rampitec]

In D152766#4442408, @JonChesterfield wrote:

In D152766#4442379, @rampitec wrote:

OK, got the explanation from @b-sumner. This looks very unusual, but it is correct.

Please could you summarise it here? Also curious what's going on here

Quote from Brian:

In general, ULP(x) is defined for any real value of x and is roughly the distance from x to the nearest floating point number divided by the distance between the two nearest floating point numbers.

So, statements about a maximum relative error being 0.51 or 3.14159 ULP are quite meaningful.

[arsenm]

89ccfa1b3978fa2c2945dec743401f090a23abec

llvm/docs/AMDGPUUsage.rst

.. table:: AMDGPU LLVM IR Intrinsics
   =========================================  ==========================================================
   :ref:`llvm.get.fpenv.i32 <int_get_fpenv>`  The natural floating-point environment type is i32. This
                                              implemented by extracting relevant bits out of the MODE
                                              register with s_getreg_b32. The first 10 bits are the
                                              core floating-point mode. Bits 12:18 are the exception
                                              mask. On gfx9+, bit 23 is FP16_OVFL. Bitfields not
                                              relevant to floating-point instructions are 0s.
 
+  :ref:`llvm.log2 <int_log2>`                Implemented for float and half (and vectors of float or
+                                             half). Not implemented for double. Hardware provides
+                                             1ULP accuracy for float, and 0.51ULP for half. Float
+                                             instruction does not natively support denormal
+                                             inputs. Backend will optimize out denormal scaling if
+                                             marked with the :ref:`afn <fastmath_afn>` flag.
+
+
   =========================================  ==========================================================
 
 
 .. TODO::
 
    List AMDGPU intrinsics.
 
 LLVM IR Attributes

llvm/docs/LangRef.rst

``arcp``
    argument rather than perform division.
 
 ``contract``
    Allow floating-point contraction (e.g. fusing a multiply followed by an
    addition into a fused multiply-and-add). This does not enable reassociating
    to form arbitrary contractions. For example, ``(a*b) + (c*d) + e`` can not
    be transformed into ``(a*b) + ((c*d) + e)`` to create two fma operations.
 
+.. _fastmath_afn:
+
 ``afn``
    Approximate functions - Allow substitution of approximate calculations for
    functions (sin, log, sqrt, etc). See floating-point intrinsic definitions
    for places where this can apply to LLVM's intrinsic math functions.
 
 ``reassoc``
    Allow reassociation transformations for floating-point instructions.
    This may dramatically change results in floating-point.

 """"""""""
 
 Return the same value as a corresponding libm '``log10``' function but without
 trapping or setting ``errno``.
 
 When specified with the fast-math-flag 'afn', the result may be approximated
 using a less accurate calculation.
 
+
+.. _int_log2:
+
 '``llvm.log2.*``' Intrinsic
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 Syntax:
 """""""
 
 This is an overloaded intrinsic. You can use ``llvm.log2`` on any
 floating-point or vector of floating-point type. Not all targets support

llvm/docs/ReleaseNotes.rst

* New versions of the intrinsics for working with buffer resources have been added.
   the old `llvm.amdgcn.*.[t]buffer.*` intrinsics, except that their `rsrc`
   arguments are represented by a `ptr addrspace(8)` instead of a `<4 x i32>`. This
   improves the interaction between AMDGPU buffer operations and the LLVM memory
   model, and so the non `.ptr` intrinsics are deprecated.
 
 * Added llvm.amdgcn.log.f32 intrinsic. This provides direct access to
   v_log_f32.
 
+* llvm.log2.f32 is now lowered accurately. Use llvm.amdgcn.log.f32 to
+  access the old behavior.
+
 Changes to the ARM Backend
 --------------------------
 
 - The hard-float ABI is now available in Armv8.1-M configurations that
   have integer MVE instructions (and therefore have FP registers) but
   no scalar or vector floating point computation.
 
 - The ``.arm`` directive now aligns code to the next 4-byte boundary, and

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h

protected:
   SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
 
   SDValue LowerFROUNDEVEN(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
+  SDValue LowerFLOG2(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFLOG(SDValue Op, SelectionDAG &DAG,
                     double Log2BaseInverted) const;
   SDValue lowerFEXP(SDValue Op, SelectionDAG &DAG) const;
 
   SDValue LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const;
 
   SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
   SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
 
   setOperationAction({ISD::BR_JT, ISD::BRIND}, MVT::Other, Expand);
 
   // This is totally unsupported, just custom lower to produce an error.
   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
 
   // Library functions.  These default to Expand, but we have instructions
   // for them.
-  setOperationAction({ISD::FCEIL, ISD::FEXP2, ISD::FPOW, ISD::FLOG2, ISD::FABS,
-                      ISD::FFLOOR, ISD::FRINT, ISD::FTRUNC, ISD::FMINNUM,
-                      ISD::FMAXNUM},
+  setOperationAction({ISD::FCEIL, ISD::FEXP2, ISD::FPOW, ISD::FABS, ISD::FFLOOR,
+                      ISD::FRINT, ISD::FTRUNC, ISD::FMINNUM, ISD::FMAXNUM},
                      MVT::f32, Legal);
 
+  setOperationAction(ISD::FLOG2, MVT::f32, Custom);
   setOperationAction(ISD::FROUND, {MVT::f32, MVT::f64}, Custom);
 
   setOperationAction({ISD::FLOG, ISD::FLOG10, ISD::FEXP}, MVT::f32, Custom);
 
   setOperationAction(ISD::FNEARBYINT, {MVT::f16, MVT::f32, MVT::f64}, Custom);
 
   setOperationAction(ISD::FROUNDEVEN, {MVT::f16, MVT::f32, MVT::f64}, Custom);
 
   setOperationAction(ISD::FREM, {MVT::f16, MVT::f32, MVT::f64}, Custom);
 
   if (Subtarget->has16BitInsts())
     setOperationAction(ISD::IS_FPCLASS, {MVT::f16, MVT::f32, MVT::f64}, Legal);
-  else
+  else {
     setOperationAction(ISD::IS_FPCLASS, {MVT::f32, MVT::f64}, Legal);
+    setOperationAction(ISD::FLOG2, MVT::f16, Custom);
+  }
 
   // FIXME: These IS_FPCLASS vector fp types are marked custom so it reaches
   // scalarization code. Can be removed when IS_FPCLASS expand isn't called by
   // default unless marked custom/legal.
   setOperationAction(
       ISD::IS_FPCLASS,
       {MVT::v2f16, MVT::v3f16, MVT::v4f16, MVT::v16f16, MVT::v2f32, MVT::v3f32,
        MVT::v4f32, MVT::v5f32, MVT::v6f32, MVT::v7f32, MVT::v8f32, MVT::v16f32,
SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
   case ISD::FCEIL: return LowerFCEIL(Op, DAG);
   case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
   case ISD::FRINT: return LowerFRINT(Op, DAG);
   case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
   case ISD::FROUNDEVEN:
     return LowerFROUNDEVEN(Op, DAG);
   case ISD::FROUND: return LowerFROUND(Op, DAG);
   case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
+  case ISD::FLOG2:
+    return LowerFLOG2(Op, DAG);
   case ISD::FLOG:
     return LowerFLOG(Op, DAG, numbers::ln2);
   case ISD::FLOG10:
     return LowerFLOG(Op, DAG, numbers::ln2 / numbers::ln10);
   case ISD::FEXP:
     return lowerFEXP(Op, DAG);
   case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
   case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
   case ISD::SIGN_EXTEND_INREG:
     // Different parts of legalization seem to interpret which type of
     // sign_extend_inreg is the one to check for custom lowering. The extended
     // from type is what really matters, but some places check for custom
     // lowering of the result type. This results in trying to use
     // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
     // nothing here and let the illegal result integer be handled normally.
     return;
+  case ISD::FLOG2:
+    if (SDValue Lowered = LowerFLOG2(SDValue(N, 0), DAG))
+      Results.push_back(Lowered);
+    return;
   default:
     return;
   }
 }
 
 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
                                                  SDValue Op,
                                                  SelectionDAG &DAG) const {
SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
   SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
   SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
 
   SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);
   // TODO: Should this propagate fast-math-flags?
   return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
 }
 
+/// Return true if it's known that \p Src can never be an f32 denormal value.
+static bool valueIsKnownNeverF32Denorm(SDValue Src) {
+  switch (Src.getOpcode()) {
+  case ISD::FP_EXTEND:
+    return Src.getOperand(0).getValueType() == MVT::f16;
+  case ISD::FP16_TO_FP:
+    return true;
+  default:
+    return false;
+  }
+
+  llvm_unreachable("covered opcode switch");
+}
+
+SDValue AMDGPUTargetLowering::LowerFLOG2(SDValue Op, SelectionDAG &DAG) const {
+  // v_log_f32 is good enough for OpenCL, except it doesn't handle denormals.
+  // If we have to handle denormals, scale up the input and adjust the result.
+
+  // scaled = x * (is_denormal ? 0x1.0p+32 : 1.0)
+  // log2 = amdgpu_log2 - (is_denormal ? 32.0 : 0.0)
+
+  SDLoc SL(Op);
+  EVT VT = Op.getValueType();
+  SDValue Src = Op.getOperand(0);
+  SDNodeFlags Flags = Op->getFlags();
+
+  if (VT == MVT::f16) {
+    // Nothing in half is a denormal when promoted to f32.
+    assert(!Subtarget->has16BitInsts());
+    SDValue Ext = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src, Flags);
+    SDValue Log = DAG.getNode(AMDGPUISD::LOG, SL, MVT::f32, Ext, Flags);
+    return DAG.getNode(ISD::FP_ROUND, SL, VT, Log,
+                       DAG.getTargetConstant(0, SL, MVT::i32), Flags);
+  }
+
+  bool NeedDenormHandling =
+      !Flags.hasApproximateFuncs() && !DAG.getTarget().Options.UnsafeFPMath &&
+      !DAG.getTarget().Options.ApproxFuncFPMath &&
+      !valueIsKnownNeverF32Denorm(Src) &&
+      DAG.getDenormalMode(VT).Input != DenormalMode::PreserveSign;
+
+  if (!NeedDenormHandling)
+    return DAG.getNode(AMDGPUISD::LOG, SL, VT, Src, Flags);
+
+  const fltSemantics &Semantics = APFloat::IEEEsingle();
+  SDValue SmallestNormal =
+      DAG.getConstantFP(APFloat::getSmallestNormalized(Semantics), SL, VT);
+
+  // Want to scale denormals up, but negatives and 0 work just as well on the
+  // scaled path.
+  SDValue IsLtSmallestNormal = DAG.getSetCC(
+      SL, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT), Src,
+      SmallestNormal, ISD::SETOLT);
+
+  SDValue Scale32 = DAG.getConstantFP(0x1.0p+32, SL, VT);
+  SDValue One = DAG.getConstantFP(1.0, SL, VT);
+  SDValue ScaleFactor =
+      DAG.getNode(ISD::SELECT, SL, VT, IsLtSmallestNormal, Scale32, One, Flags);
+
+  SDValue ScaledInput = DAG.getNode(ISD::FMUL, SL, VT, Src, ScaleFactor, Flags);
+
+  SDValue Log2 = DAG.getNode(AMDGPUISD::LOG, SL, VT, ScaledInput, Flags);
+
+  SDValue ThirtyTwo = DAG.getConstantFP(32.0, SL, VT);
+  SDValue Zero = DAG.getConstantFP(0.0, SL, VT);
+  SDValue ResultOffset =
+      DAG.getNode(ISD::SELECT, SL, VT, IsLtSmallestNormal, ThirtyTwo, Zero);
+  return DAG.getNode(ISD::FSUB, SL, VT, Log2, ResultOffset, Flags);
+}
+
 SDValue AMDGPUTargetLowering::LowerFLOG(SDValue Op, SelectionDAG &DAG,
                                         double Log2BaseInverted) const {
   EVT VT = Op.getValueType();
 
   SDLoc SL(Op);
   SDValue Operand = Op.getOperand(0);
   SDValue Log2Operand = DAG.getNode(ISD::FLOG2, SL, VT, Operand);
   SDValue Log2BaseInvertedOperand = DAG.getConstantFP(Log2BaseInverted, SL, VT);

llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td

 
 def AMDGPUsin : PatFrags<(ops node:$src), [(int_amdgcn_sin node:$src),
                                            (AMDGPUsin_impl node:$src)]>;
 def AMDGPUcos : PatFrags<(ops node:$src), [(int_amdgcn_cos node:$src),
                                            (AMDGPUcos_impl node:$src)]>;
 def AMDGPUfract : PatFrags<(ops node:$src), [(int_amdgcn_fract node:$src),
                                              (AMDGPUfract_impl node:$src)]>;
 def AMDGPUlog : PatFrags<(ops node:$src), [(int_amdgcn_log node:$src),
-                                           (AMDGPUlog_impl node:$src),
-                                           (flog2 node:$src)]>;
+                                           (AMDGPUlog_impl node:$src)]>;
 def AMDGPUlogf16 : PatFrags<(ops node:$src), [(int_amdgcn_log node:$src),
                                               (flog2 node:$src)]>;
 
 
 def AMDGPUfp_class : PatFrags<(ops node:$src0, node:$src1),
   [(int_amdgcn_class node:$src0, node:$src1),
    (AMDGPUfp_class_impl node:$src0, node:$src1)]>;
 

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h

public:
   bool legalizeLoad(LegalizerHelper &Helper, MachineInstr &MI) const;
   bool legalizeStore(LegalizerHelper &Helper, MachineInstr &MI) const;
 
   bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI,
                     MachineIRBuilder &B) const;
 
   bool legalizeAtomicCmpXChg(MachineInstr &MI, MachineRegisterInfo &MRI,
                              MachineIRBuilder &B) const;
+  bool legalizeFlog2(MachineInstr &MI, MachineIRBuilder &B) const;
   bool legalizeFlog(MachineInstr &MI, MachineIRBuilder &B,
                     double Log2BaseInverted) const;
   bool legalizeFExp(MachineInstr &MI, MachineIRBuilder &B) const;
   bool legalizeFPow(MachineInstr &MI, MachineIRBuilder &B) const;
   bool legalizeFFloor(MachineInstr &MI, MachineRegisterInfo &MRI,
                       MachineIRBuilder &B) const;
 
   bool legalizeBuildVector(MachineInstr &MI, MachineRegisterInfo &MRI,

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
 
   getActionDefinitionsBuilder(G_FCMP)
     .legalForCartesianProduct({S1}, ST.has16BitInsts() ? FPTypes16 : FPTypesBase)
     .widenScalarToNextPow2(1)
     .clampScalar(1, S32, S64)
     .scalarize(0);
 
   // FIXME: fpow has a selection pattern that should move to custom lowering.
-  auto &Exp2Ops = getActionDefinitionsBuilder({G_FEXP2, G_FLOG2});
+  auto &Exp2Ops = getActionDefinitionsBuilder(G_FEXP2);
   if (ST.has16BitInsts())
     Exp2Ops.legalFor({S32, S16});
   else
     Exp2Ops.legalFor({S32});
   Exp2Ops.clampScalar(0, MinScalarFPTy, S32);
   Exp2Ops.scalarize(0);
 
   auto &ExpOps = getActionDefinitionsBuilder({G_FEXP, G_FLOG, G_FLOG10, G_FPOW});
   if (ST.has16BitInsts())
     ExpOps.customFor({{S32}, {S16}});
   else
     ExpOps.customFor({S32});
   ExpOps.clampScalar(0, MinScalarFPTy, S32)
         .scalarize(0);
 
   getActionDefinitionsBuilder(G_FPOWI)
     .clampScalar(0, MinScalarFPTy, S32)
     .lower();
 
+  auto &Log2Ops = getActionDefinitionsBuilder(G_FLOG2);
+  Log2Ops.customFor({S32});
+  if (ST.has16BitInsts())
+    Log2Ops.legalFor({S16});
+  else
+    Log2Ops.customFor({S16});
+  Log2Ops.scalarize(0)
+    .lower();
+
   // The 64-bit versions produce 32-bit results, but only on the SALU.
   getActionDefinitionsBuilder(G_CTPOP)
     .legalFor({{S32, S32}, {S32, S64}})
     .clampScalar(0, S32, S32)
     .widenScalarToNextPow2(1, 32)
     .clampScalar(1, S32, S64)
     .scalarize(0)
     .widenScalarToNextPow2(0, 32);
bool AMDGPULegalizerInfo::legalizeCustom(LegalizerHelper &Helper,
   case TargetOpcode::G_UDIVREM:
     return legalizeUnsignedDIV_REM(MI, MRI, B);
   case TargetOpcode::G_SDIV:
   case TargetOpcode::G_SREM:
   case TargetOpcode::G_SDIVREM:
     return legalizeSignedDIV_REM(MI, MRI, B);
   case TargetOpcode::G_ATOMIC_CMPXCHG:
     return legalizeAtomicCmpXChg(MI, MRI, B);
+  case TargetOpcode::G_FLOG2:
+    return legalizeFlog2(MI, B);
   case TargetOpcode::G_FLOG:
     return legalizeFlog(MI, B, numbers::ln2);
   case TargetOpcode::G_FLOG10:
     return legalizeFlog(MI, B, numbers::ln2 / numbers::ln10);
   case TargetOpcode::G_FEXP:
     return legalizeFExp(MI, B);
   case TargetOpcode::G_FPOW:
     return legalizeFPow(MI, B);
B.buildInstr(AMDGPU::G_AMDGPU_ATOMIC_CMPXCHG)
     .addUse(PtrReg)
     .addUse(PackedVal)
     .setMemRefs(MI.memoperands());
 
   MI.eraseFromParent();
   return true;
 }
 
+/// Return true if it's known that \p Src can never be an f32 denormal value.
+static bool valueIsKnownNeverF32Denorm(const MachineRegisterInfo &MRI,
+                                       Register Src) {
+  Register ExtSrc;
+  if (mi_match(Src, MRI, m_GFPExt(m_Reg(ExtSrc))))
+    return MRI.getType(ExtSrc) == LLT::scalar(16);
+  return false;
+}
+
+bool AMDGPULegalizerInfo::legalizeFlog2(MachineInstr &MI,
+                                        MachineIRBuilder &B) const {
+  // v_log_f32 is good enough for OpenCL, except it doesn't handle denormals.
+  // If we have to handle denormals, scale up the input and adjust the result.
+
+  // scaled = x * (is_denormal ? 0x1.0p+32 : 1.0)
+  // log2 = amdgpu_log2 - (is_denormal ? 32.0 : 0.0)
+
+  Register Dst = MI.getOperand(0).getReg();
+  Register Src = MI.getOperand(1).getReg();
+  LLT Ty = B.getMRI()->getType(Dst);
+  unsigned Flags = MI.getFlags();
+
+  const MachineFunction &MF = B.getMF();
+
+  if (Ty == LLT::scalar(16)) {
+    const LLT F32 = LLT::scalar(32);
+    // Nothing in half is a denormal when promoted to f32.
+    auto Ext = B.buildFPExt(F32, Src, Flags);
+    auto Log2 = B.buildIntrinsic(Intrinsic::amdgcn_log, {F32}, false)
+      .addUse(Ext.getReg(0))
+      .setMIFlags(Flags);
+    B.buildFPTrunc(Dst, Log2, Flags);
+    MI.eraseFromParent();
+    return true;
+  }
+
+  assert(Ty == LLT::scalar(32));
+
+  const fltSemantics &Flt = APFloat::IEEEsingle();
+
+  bool NeedDenormHandling =
+      !MI.getFlag(MachineInstr::FmAfn) &&
+      !MF.getTarget().Options.UnsafeFPMath &&
+      !MF.getTarget().Options.ApproxFuncFPMath &&
+      !valueIsKnownNeverF32Denorm(*B.getMRI(), Src) &&
+      MF.getDenormalMode(Flt).Input != DenormalMode::PreserveSign;
+
+  if (!NeedDenormHandling) {
+    B.buildIntrinsic(Intrinsic::amdgcn_log, ArrayRef<Register>{Dst}, false)
+      .addUse(Src)
+      .setMIFlags(Flags);
+    MI.eraseFromParent();
+    return true;
+  }
+
+  auto SmallestNormal =
+      B.buildFConstant(Ty, APFloat::getSmallestNormalized(Flt));
+  auto IsDenormOrZero =
+      B.buildFCmp(CmpInst::FCMP_OLT, LLT::scalar(1), Src, SmallestNormal);
+
+  auto Scale32 = B.buildFConstant(Ty, 0x1.0p+32);
+  auto One = B.buildFConstant(Ty, 1.0);
+  auto ScaleFactor = B.buildSelect(Ty, IsDenormOrZero, Scale32, One, Flags);
+  auto ScaledInput = B.buildFMul(Ty, Src, ScaleFactor, Flags);
+  auto Log2 = B.buildIntrinsic(Intrinsic::amdgcn_log, {Ty}, false)
+    .addUse(ScaledInput.getReg(0))
+    .setMIFlags(Flags);
+
+  auto ThirtyTwo = B.buildFConstant(Ty, 32.0);
+  auto Zero = B.buildFConstant(Ty, 0.0);
+  auto ResultOffset = B.buildSelect(Ty, IsDenormOrZero, ThirtyTwo, Zero, Flags);
+  B.buildFSub(Dst, Log2, ResultOffset, Flags);
+
+  MI.eraseFromParent();
+  return true;
+}
+
 bool AMDGPULegalizerInfo::legalizeFlog(
   MachineInstr &MI, MachineIRBuilder &B, double Log2BaseInverted) const {
   Register Dst = MI.getOperand(0).getReg();
   Register Src = MI.getOperand(1).getReg();
   LLT Ty = B.getMRI()->getType(Dst);
   unsigned Flags = MI.getFlags();
 
   auto Log2Operand = B.buildFLog2(Ty, Src, Flags);

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

case ISD::FABS: {
 
     SDValue Op = DAG.getNode(ISD::AND, SL, MVT::i32,
                              BC,
                              DAG.getConstant(0x7fff7fff, SL, MVT::i32));
     Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2f16, Op));
     return;
   }
   default:
+    AMDGPUTargetLowering::ReplaceNodeResults(N, Results, DAG);
     break;
   }
 }
 
 /// Helper function for LowerBRCOND
 static SDNode *findUser(SDValue Value, unsigned Opcode) {
 
   SDNode *Parent = Value.getNode();
bool SITargetLowering::isCanonicalized(SelectionDAG &DAG, SDValue Op,
   case ISD::FLDEXP:
   case AMDGPUISD::FMUL_LEGACY:
   case AMDGPUISD::FMAD_FTZ:
   case AMDGPUISD::RCP:
   case AMDGPUISD::RSQ:
   case AMDGPUISD::RSQ_CLAMP:
   case AMDGPUISD::RCP_LEGACY:
   case AMDGPUISD::RCP_IFLAG:
+  case AMDGPUISD::LOG:
   case AMDGPUISD::DIV_SCALE:
   case AMDGPUISD::DIV_FMAS:
   case AMDGPUISD::DIV_FIXUP:
   case AMDGPUISD::FRACT:
   case AMDGPUISD::CVT_PKRTZ_F16_F32:
   case AMDGPUISD::CVT_F32_UBYTE0:
   case AMDGPUISD::CVT_F32_UBYTE1:
   case AMDGPUISD::CVT_F32_UBYTE2:

llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -global-isel -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=GFX6 %s
 ; RUN: llc -global-isel -march=amdgcn -mcpu=fiji < %s | FileCheck -check-prefix=GFX8 %s
 ; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
 ; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
 ; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11 %s
 
 define float @v_pow_f32(float %x, float %y) {
 ; GFX6-LABEL: v_pow_f32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_mov_b32_e32 v2, 0x800000
+; GFX6-NEXT:    v_mov_b32_e32 v3, 0x4f800000
+; GFX6-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v2
+; GFX6-NEXT:    v_cndmask_b32_e32 v2, 1.0, v3, vcc
+; GFX6-NEXT:    v_mul_f32_e32 v0, v0, v2
 ; GFX6-NEXT:    v_log_f32_e32 v0, v0
+; GFX6-NEXT:    v_mov_b32_e32 v2, 0x42000000
+; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX6-NEXT:    v_sub_f32_e32 v0, v0, v2
 ; GFX6-NEXT:    v_mul_legacy_f32_e32 v0, v0, v1
 ; GFX6-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX6-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX8-LABEL: v_pow_f32:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_mov_b32_e32 v2, 0x800000
+; GFX8-NEXT:    v_mov_b32_e32 v3, 0x4f800000
+; GFX8-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v2
+; GFX8-NEXT:    v_cndmask_b32_e32 v2, 1.0, v3, vcc
+; GFX8-NEXT:    v_mul_f32_e32 v0, v0, v2
 ; GFX8-NEXT:    v_log_f32_e32 v0, v0
+; GFX8-NEXT:    v_mov_b32_e32 v2, 0x42000000
+; GFX8-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX8-NEXT:    v_sub_f32_e32 v0, v0, v2
 ; GFX8-NEXT:    v_mul_legacy_f32_e32 v0, v0, v1
 ; GFX8-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_pow_f32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v2, 0x800000
+; GFX9-NEXT:    v_mov_b32_e32 v3, 0x4f800000
+; GFX9-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v2
+; GFX9-NEXT:    v_cndmask_b32_e32 v2, 1.0, v3, vcc
+; GFX9-NEXT:    v_mul_f32_e32 v0, v0, v2
 ; GFX9-NEXT:    v_log_f32_e32 v0, v0
+; GFX9-NEXT:    v_mov_b32_e32 v2, 0x42000000
+; GFX9-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX9-NEXT:    v_sub_f32_e32 v0, v0, v2
 ; GFX9-NEXT:    v_mul_legacy_f32_e32 v0, v0, v1
 ; GFX9-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_pow_f32:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_cmp_gt_f32_e64 s4, 0x800000, |v0|
+; GFX10-NEXT:    v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s4
+; GFX10-NEXT:    v_mul_f32_e32 v0, v0, v2
+; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, 0x42000000, s4
 ; GFX10-NEXT:    v_log_f32_e32 v0, v0
+; GFX10-NEXT:    v_sub_f32_e32 v0, v0, v2
 ; GFX10-NEXT:    v_mul_legacy_f32_e32 v0, v0, v1
 ; GFX10-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-LABEL: v_pow_f32:
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT:    v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s0
+; GFX11-NEXT:    v_mul_f32_e32 v0, v0, v2
+; GFX11-NEXT:    v_cndmask_b32_e64 v2, 0, 0x42000000, s0
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
 ; GFX11-NEXT:    v_log_f32_e32 v0, v0
 ; GFX11-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-NEXT:    v_sub_f32_e32 v0, v0, v2
 ; GFX11-NEXT:    v_mul_dx9_zero_f32_e32 v0, v0, v1
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GFX11-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %pow = call float @llvm.pow.f32(float %x, float %y)
   ret float %pow
 }
 
 define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
 ; GFX6-LABEL: v_pow_v2f32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    s_mov_b32 s4, 0x800000
+; GFX6-NEXT:    v_mov_b32_e32 v4, 0x4f800000
+; GFX6-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX6-NEXT:    v_cndmask_b32_e32 v5, 1.0, v4, vcc
+; GFX6-NEXT:    v_mul_f32_e32 v0, v0, v5
+; GFX6-NEXT:    v_mov_b32_e32 v5, 0x42000000
+; GFX6-NEXT:    v_cndmask_b32_e32 v6, 0, v5, vcc
+; GFX6-NEXT:    v_cmp_lt_f32_e64 vcc, |v1|, s4
 ; GFX6-NEXT:    v_log_f32_e32 v0, v0
+; GFX6-NEXT:    v_cndmask_b32_e32 v4, 1.0, v4, vcc
+; GFX6-NEXT:    v_mul_f32_e32 v1, v1, v4
 ; GFX6-NEXT:    v_log_f32_e32 v1, v1
+; GFX6-NEXT:    v_sub_f32_e32 v0, v0, v6
 ; GFX6-NEXT:    v_mul_legacy_f32_e32 v0, v0, v2
+; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v5, vcc
+; GFX6-NEXT:    v_sub_f32_e32 v1, v1, v2
 ; GFX6-NEXT:    v_mul_legacy_f32_e32 v1, v1, v3
 ; GFX6-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX6-NEXT:    v_exp_f32_e32 v1, v1
 ; GFX6-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX8-LABEL: v_pow_v2f32:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    s_mov_b32 s4, 0x800000
+; GFX8-NEXT:    v_mov_b32_e32 v4, 0x4f800000
+; GFX8-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX8-NEXT:    v_cndmask_b32_e32 v5, 1.0, v4, vcc
+; GFX8-NEXT:    v_mul_f32_e32 v0, v0, v5
+; GFX8-NEXT:    v_mov_b32_e32 v5, 0x42000000
+; GFX8-NEXT:    v_cndmask_b32_e32 v6, 0, v5, vcc
+; GFX8-NEXT:    v_cmp_lt_f32_e64 vcc, |v1|, s4
 ; GFX8-NEXT:    v_log_f32_e32 v0, v0
+; GFX8-NEXT:    v_cndmask_b32_e32 v4, 1.0, v4, vcc
+; GFX8-NEXT:    v_mul_f32_e32 v1, v1, v4
 ; GFX8-NEXT:    v_log_f32_e32 v1, v1
+; GFX8-NEXT:    v_sub_f32_e32 v0, v0, v6
 ; GFX8-NEXT:    v_mul_legacy_f32_e32 v0, v0, v2
+; GFX8-NEXT:    v_cndmask_b32_e32 v2, 0, v5, vcc
+; GFX8-NEXT:    v_sub_f32_e32 v1, v1, v2
 ; GFX8-NEXT:    v_mul_legacy_f32_e32 v1, v1, v3
 ; GFX8-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX8-NEXT:    v_exp_f32_e32 v1, v1
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_pow_v2f32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    s_mov_b32 s4, 0x800000
+; GFX9-NEXT:    v_mov_b32_e32 v4, 0x4f800000
+; GFX9-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX9-NEXT:    v_cndmask_b32_e32 v5, 1.0, v4, vcc
+; GFX9-NEXT:    v_mul_f32_e32 v0, v0, v5
+; GFX9-NEXT:    v_mov_b32_e32 v5, 0x42000000
+; GFX9-NEXT:    v_cndmask_b32_e32 v6, 0, v5, vcc
+; GFX9-NEXT:    v_cmp_lt_f32_e64 vcc, |v1|, s4
 ; GFX9-NEXT:    v_log_f32_e32 v0, v0
+; GFX9-NEXT:    v_cndmask_b32_e32 v4, 1.0, v4, vcc
+; GFX9-NEXT:    v_mul_f32_e32 v1, v1, v4
 ; GFX9-NEXT:    v_log_f32_e32 v1, v1
+; GFX9-NEXT:    v_sub_f32_e32 v0, v0, v6
 ; GFX9-NEXT:    v_mul_legacy_f32_e32 v0, v0, v2
+; GFX9-NEXT:    v_cndmask_b32_e32 v2, 0, v5, vcc
+; GFX9-NEXT:    v_sub_f32_e32 v1, v1, v2
 ; GFX9-NEXT:    v_mul_legacy_f32_e32 v1, v1, v3
 ; GFX9-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX9-NEXT:    v_exp_f32_e32 v1, v1
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_pow_v2f32:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_cmp_gt_f32_e64 s4, 0x800000, |v0|
+; GFX10-NEXT:    v_cmp_gt_f32_e64 s5, 0x800000, |v1|
+; GFX10-NEXT:    v_cndmask_b32_e64 v4, 1.0, 0x4f800000, s4
+; GFX10-NEXT:    v_cndmask_b32_e64 v5, 1.0, 0x4f800000, s5
+; GFX10-NEXT:    v_mul_f32_e32 v0, v0, v4
+; GFX10-NEXT:    v_mul_f32_e32 v1, v1, v5
+; GFX10-NEXT:    v_cndmask_b32_e64 v4, 0, 0x42000000, s4
+; GFX10-NEXT:    v_cndmask_b32_e64 v5, 0, 0x42000000, s5
 ; GFX10-NEXT:    v_log_f32_e32 v0, v0
 ; GFX10-NEXT:    v_log_f32_e32 v1, v1
+; GFX10-NEXT:    v_sub_f32_e32 v0, v0, v4
+; GFX10-NEXT:    v_sub_f32_e32 v1, v1, v5
 ; GFX10-NEXT:    v_mul_legacy_f32_e32 v0, v0, v2
 ; GFX10-NEXT:    v_mul_legacy_f32_e32 v1, v1, v3
 ; GFX10-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX10-NEXT:    v_exp_f32_e32 v1, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-LABEL: v_pow_v2f32:
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT:    v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-NEXT:    v_cmp_gt_f32_e64 s1, 0x800000, |v1|
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT:    v_cndmask_b32_e64 v4, 1.0, 0x4f800000, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v5, 1.0, 0x4f800000, s1
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT:    v_dual_mul_f32 v0, v0, v4 :: v_dual_mul_f32 v1, v1, v5
+; GFX11-NEXT:    v_cndmask_b32_e64 v4, 0, 0x42000000, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v5, 0, 0x42000000, s1
 ; GFX11-NEXT:    v_log_f32_e32 v0, v0
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
 ; GFX11-NEXT:    v_log_f32_e32 v1, v1
 ; GFX11-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-NEXT:    v_dual_sub_f32 v0, v0, v4 :: v_dual_sub_f32 v1, v1, v5
 ; GFX11-NEXT:    v_dual_mul_dx9_zero_f32 v0, v0, v2 :: v_dual_mul_dx9_zero_f32 v1, v1, v3
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
 ; GFX11-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX11-NEXT:    v_exp_f32_e32 v1, v1
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %pow = call <2 x float> @llvm.pow.v2f32(<2 x float> %x, <2 x float> %y)
   ret <2 x float> %pow
 }

 ;   %pow = call double @llvm.pow.f64(double %x, double %y)
 ;   ret double %pow
 ; }
 
 define float @v_pow_f32_fabs_lhs(float %x, float %y) {
 ; GFX6-LABEL: v_pow_f32_fabs_lhs:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    v_log_f32_e64 v0, |v0|
+; GFX6-NEXT:    v_mov_b32_e32 v2, 0x800000
+; GFX6-NEXT:    v_mov_b32_e32 v3, 0x4f800000
+; GFX6-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v2
+; GFX6-NEXT:    v_cndmask_b32_e32 v2, 1.0, v3, vcc
+; GFX6-NEXT:    v_mul_f32_e64 v0, |v0|, v2
+; GFX6-NEXT:    v_log_f32_e32 v0, v0
+; GFX6-NEXT:    v_mov_b32_e32 v2, 0x42000000
+; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX6-NEXT:    v_sub_f32_e32 v0, v0, v2
 ; GFX6-NEXT:    v_mul_legacy_f32_e32 v0, v0, v1
 ; GFX6-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX6-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX8-LABEL: v_pow_f32_fabs_lhs:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT:    v_log_f32_e64 v0, |v0|
+; GFX8-NEXT:    v_mov_b32_e32 v2, 0x800000
+; GFX8-NEXT:    v_mov_b32_e32 v3, 0x4f800000
+; GFX8-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v2
+; GFX8-NEXT:    v_cndmask_b32_e32 v2, 1.0, v3, vcc
+; GFX8-NEXT:    v_mul_f32_e64 v0, |v0|, v2
+; GFX8-NEXT:    v_log_f32_e32 v0, v0
+; GFX8-NEXT:    v_mov_b32_e32 v2, 0x42000000
+; GFX8-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX8-NEXT:    v_sub_f32_e32 v0, v0, v2
 ; GFX8-NEXT:    v_mul_legacy_f32_e32 v0, v0, v1
 ; GFX8-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_pow_f32_fabs_lhs:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_log_f32_e64 v0, |v0|
+; GFX9-NEXT:    v_mov_b32_e32 v2, 0x800000
+; GFX9-NEXT:    v_mov_b32_e32 v3, 0x4f800000
+; GFX9-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v2
+; GFX9-NEXT:    v_cndmask_b32_e32 v2, 1.0, v3, vcc
+; GFX9-NEXT:    v_mul_f32_e64 v0, |v0|, v2
+; GFX9-NEXT:    v_log_f32_e32 v0, v0
+; GFX9-NEXT:    v_mov_b32_e32 v2, 0x42000000
+; GFX9-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX9-NEXT:    v_sub_f32_e32 v0, v0, v2
 ; GFX9-NEXT:    v_mul_legacy_f32_e32 v0, v0, v1
 ; GFX9-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_pow_f32_fabs_lhs:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_log_f32_e64 v0, |v0|
+; GFX10-NEXT:    v_cmp_gt_f32_e64 s4, 0x800000, |v0|
+; GFX10-NEXT:    v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s4
+; GFX10-NEXT:    v_mul_f32_e64 v0, |v0|, v2
+; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, 0x42000000, s4
+; GFX10-NEXT:    v_log_f32_e32 v0, v0
+; GFX10-NEXT:    v_sub_f32_e32 v0, v0, v2
 ; GFX10-NEXT:    v_mul_legacy_f32_e32 v0, v0, v1
 ; GFX10-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-LABEL: v_pow_f32_fabs_lhs:
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    v_log_f32_e64 v0, |v0|
+; GFX11-NEXT:    v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s0
+; GFX11-NEXT:    v_mul_f32_e64 v0, |v0|, v2
+; GFX11-NEXT:    v_cndmask_b32_e64 v2, 0, 0x42000000, s0
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_log_f32_e32 v0, v0
 ; GFX11-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-NEXT:    v_sub_f32_e32 v0, v0, v2
 ; GFX11-NEXT:    v_mul_dx9_zero_f32_e32 v0, v0, v1
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GFX11-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %fabs.x = call float @llvm.fabs.f32(float %x)
   %pow = call float @llvm.pow.f32(float %fabs.x, float %y)
   ret float %pow
 }
 
 define float @v_pow_f32_fabs_rhs(float %x, float %y) {
 ; GFX6-LABEL: v_pow_f32_fabs_rhs:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_mov_b32_e32 v2, 0x800000
+; GFX6-NEXT:    v_mov_b32_e32 v3, 0x4f800000
+; GFX6-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v2
+; GFX6-NEXT:    v_cndmask_b32_e32 v2, 1.0, v3, vcc
+; GFX6-NEXT:    v_mul_f32_e32 v0, v0, v2
 ; GFX6-NEXT:    v_log_f32_e32 v0, v0
+; GFX6-NEXT:    v_mov_b32_e32 v2, 0x42000000
+; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX6-NEXT:    v_sub_f32_e32 v0, v0, v2
 ; GFX6-NEXT:    v_mul_legacy_f32_e64 v0, v0, |v1|
 ; GFX6-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX6-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX8-LABEL: v_pow_f32_fabs_rhs:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_mov_b32_e32 v2, 0x800000
+; GFX8-NEXT:    v_mov_b32_e32 v3, 0x4f800000
+; GFX8-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v2
+; GFX8-NEXT:    v_cndmask_b32_e32 v2, 1.0, v3, vcc
+; GFX8-NEXT:    v_mul_f32_e32 v0, v0, v2
 ; GFX8-NEXT:    v_log_f32_e32 v0, v0
+; GFX8-NEXT:    v_mov_b32_e32 v2, 0x42000000
+; GFX8-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX8-NEXT:    v_sub_f32_e32 v0, v0, v2
 ; GFX8-NEXT:    v_mul_legacy_f32_e64 v0, v0, |v1|
 ; GFX8-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_pow_f32_fabs_rhs:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v2, 0x800000
+; GFX9-NEXT:    v_mov_b32_e32 v3, 0x4f800000
+; GFX9-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v2
+; GFX9-NEXT:    v_cndmask_b32_e32 v2, 1.0, v3, vcc
+; GFX9-NEXT:    v_mul_f32_e32 v0, v0, v2
 ; GFX9-NEXT:    v_log_f32_e32 v0, v0
+; GFX9-NEXT:    v_mov_b32_e32 v2, 0x42000000
+; GFX9-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX9-NEXT:    v_sub_f32_e32 v0, v0, v2
 ; GFX9-NEXT:    v_mul_legacy_f32_e64 v0, v0, |v1|
 ; GFX9-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_pow_f32_fabs_rhs:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_cmp_gt_f32_e64 s4, 0x800000, |v0|
+; GFX10-NEXT:    v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s4
+; GFX10-NEXT:    v_mul_f32_e32 v0, v0, v2
+; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, 0x42000000, s4
 ; GFX10-NEXT:    v_log_f32_e32 v0, v0
+; GFX10-NEXT:    v_sub_f32_e32 v0, v0, v2
 ; GFX10-NEXT:    v_mul_legacy_f32_e64 v0, v0, |v1|
 ; GFX10-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-LABEL: v_pow_f32_fabs_rhs:
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT:    v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s0
+; GFX11-NEXT:    v_mul_f32_e32 v0, v0, v2
+; GFX11-NEXT:    v_cndmask_b32_e64 v2, 0, 0x42000000, s0
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
 ; GFX11-NEXT:    v_log_f32_e32 v0, v0
 ; GFX11-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-NEXT:    v_sub_f32_e32 v0, v0, v2
 ; GFX11-NEXT:    v_mul_dx9_zero_f32_e64 v0, v0, |v1|
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GFX11-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %fabs.y = call float @llvm.fabs.f32(float %y)
   %pow = call float @llvm.pow.f32(float %x, float %fabs.y)
   ret float %pow
 }
 
 define float @v_pow_f32_fabs_lhs_rhs(float %x, float %y) {
 ; GFX6-LABEL: v_pow_f32_fabs_lhs_rhs:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    v_log_f32_e64 v0, |v0|
+; GFX6-NEXT:    v_mov_b32_e32 v2, 0x800000
+; GFX6-NEXT:    v_mov_b32_e32 v3, 0x4f800000
+; GFX6-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v2
+; GFX6-NEXT:    v_cndmask_b32_e32 v2, 1.0, v3, vcc
+; GFX6-NEXT:    v_mul_f32_e64 v0, |v0|, v2
+; GFX6-NEXT:    v_log_f32_e32 v0, v0
+; GFX6-NEXT:    v_mov_b32_e32 v2, 0x42000000
+; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX6-NEXT:    v_sub_f32_e32 v0, v0, v2
 ; GFX6-NEXT:    v_mul_legacy_f32_e64 v0, v0, |v1|
 ; GFX6-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX6-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX8-LABEL: v_pow_f32_fabs_lhs_rhs:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT:    v_log_f32_e64 v0, |v0|
+; GFX8-NEXT:    v_mov_b32_e32 v2, 0x800000
+; GFX8-NEXT:    v_mov_b32_e32 v3, 0x4f800000
+; GFX8-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v2
+; GFX8-NEXT:    v_cndmask_b32_e32 v2, 1.0, v3, vcc
+; GFX8-NEXT:    v_mul_f32_e64 v0, |v0|, v2
+; GFX8-NEXT:    v_log_f32_e32 v0, v0
+; GFX8-NEXT:    v_mov_b32_e32 v2, 0x42000000
+; GFX8-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX8-NEXT:    v_sub_f32_e32 v0, v0, v2
 ; GFX8-NEXT:    v_mul_legacy_f32_e64 v0, v0, |v1|
 ; GFX8-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_pow_f32_fabs_lhs_rhs:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_log_f32_e64 v0, |v0|
+; GFX9-NEXT:    v_mov_b32_e32 v2, 0x800000
+; GFX9-NEXT:    v_mov_b32_e32 v3, 0x4f800000
+; GFX9-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v2
+; GFX9-NEXT:    v_cndmask_b32_e32 v2, 1.0, v3, vcc
+; GFX9-NEXT:    v_mul_f32_e64 v0, |v0|, v2
+; GFX9-NEXT:    v_log_f32_e32 v0, v0
+; GFX9-NEXT:    v_mov_b32_e32 v2, 0x42000000
+; GFX9-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX9-NEXT:    v_sub_f32_e32 v0, v0, v2
 ; GFX9-NEXT:    v_mul_legacy_f32_e64 v0, v0, |v1|
 ; GFX9-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_pow_f32_fabs_lhs_rhs:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_log_f32_e64 v0, |v0|
+; GFX10-NEXT:    v_cmp_gt_f32_e64 s4, 0x800000, |v0|
+; GFX10-NEXT:    v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s4
+; GFX10-NEXT:    v_mul_f32_e64 v0, |v0|, v2
+; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, 0x42000000, s4
+; GFX10-NEXT:    v_log_f32_e32 v0, v0
+; GFX10-NEXT:    v_sub_f32_e32 v0, v0, v2
 ; GFX10-NEXT:    v_mul_legacy_f32_e64 v0, v0, |v1|
 ; GFX10-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-LABEL: v_pow_f32_fabs_lhs_rhs:
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    v_log_f32_e64 v0, |v0|
+; GFX11-NEXT:    v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s0
+; GFX11-NEXT:    v_mul_f32_e64 v0, |v0|, v2
+; GFX11-NEXT:    v_cndmask_b32_e64 v2, 0, 0x42000000, s0
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_log_f32_e32 v0, v0
 ; GFX11-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-NEXT:    v_sub_f32_e32 v0, v0, v2
 ; GFX11-NEXT:    v_mul_dx9_zero_f32_e64 v0, v0, |v1|
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GFX11-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %fabs.x = call float @llvm.fabs.f32(float %x)
   %fabs.y = call float @llvm.fabs.f32(float %y)
   %pow = call float @llvm.pow.f32(float %fabs.x, float %fabs.y)
   ret float %pow
 }
 
 define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) {
 ; GFX6-LABEL: v_pow_f32_sgpr_vgpr:
 ; GFX6:       ; %bb.0:
-; GFX6-NEXT:    v_log_f32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GFX6-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GFX6-NEXT:    v_cmp_lt_f32_e64 vcc, |s0|, v1
+; GFX6-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GFX6-NEXT:    v_mul_f32_e32 v1, s0, v1
+; GFX6-NEXT:    v_log_f32_e32 v1, v1
+; GFX6-NEXT:    v_mov_b32_e32 v2, 0x42000000
+; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX6-NEXT:    v_sub_f32_e32 v1, v1, v2
 ; GFX6-NEXT:    v_mul_legacy_f32_e32 v0, v1, v0
 ; GFX6-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX6-NEXT:    ; return to shader part epilog
 ;
 ; GFX8-LABEL: v_pow_f32_sgpr_vgpr:
 ; GFX8:       ; %bb.0:
-; GFX8-NEXT:    v_log_f32_e32 v1, s0
+; GFX8-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GFX8-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GFX8-NEXT:    v_cmp_lt_f32_e64 vcc, |s0|, v1
+; GFX8-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GFX8-NEXT:    v_mul_f32_e32 v1, s0, v1
+; GFX8-NEXT:    v_log_f32_e32 v1, v1
+; GFX8-NEXT:    v_mov_b32_e32 v2, 0x42000000
+; GFX8-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX8-NEXT:    v_sub_f32_e32 v1, v1, v2
 ; GFX8-NEXT:    v_mul_legacy_f32_e32 v0, v1, v0
 ; GFX8-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX8-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: v_pow_f32_sgpr_vgpr:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    v_log_f32_e32 v1, s0
+; GFX9-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GFX9-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GFX9-NEXT:    v_cmp_lt_f32_e64 vcc, |s0|, v1
+; GFX9-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GFX9-NEXT:    v_mul_f32_e32 v1, s0, v1
+; GFX9-NEXT:    v_log_f32_e32 v1, v1
+; GFX9-NEXT:    v_mov_b32_e32 v2, 0x42000000
+; GFX9-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX9-NEXT:    v_sub_f32_e32 v1, v1, v2
 ; GFX9-NEXT:    v_mul_legacy_f32_e32 v0, v1, v0
 ; GFX9-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: v_pow_f32_sgpr_vgpr:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_log_f32_e32 v1, s0
+; GFX10-NEXT:    v_cmp_gt_f32_e64 s1, 0x800000, |s0|
+; GFX10-NEXT:    v_cndmask_b32_e64 v1, 1.0, 0x4f800000, s1
+; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, 0x42000000, s1
+; GFX10-NEXT:    v_mul_f32_e32 v1, s0, v1
+; GFX10-NEXT:    v_log_f32_e32 v1, v1
+; GFX10-NEXT:    v_sub_f32_e32 v1, v1, v2
 ; GFX10-NEXT:    v_mul_legacy_f32_e32 v0, v1, v0
 ; GFX10-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
 ; GFX11-LABEL: v_pow_f32_sgpr_vgpr:
 ; GFX11:       ; %bb.0:
-; GFX11-NEXT:    v_log_f32_e32 v1, s0
+; GFX11-NEXT:    v_cmp_gt_f32_e64 s1, 0x800000, |s0|
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT:    v_cndmask_b32_e64 v1, 1.0, 0x4f800000, s1
+; GFX11-NEXT:    v_cndmask_b32_e64 v2, 0, 0x42000000, s1
+; GFX11-NEXT:    v_mul_f32_e32 v1, s0, v1
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_log_f32_e32 v1, v1
 ; GFX11-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-NEXT:    v_sub_f32_e32 v1, v1, v2
 ; GFX11-NEXT:    v_mul_dx9_zero_f32_e32 v0, v1, v0
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GFX11-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX11-NEXT:    ; return to shader part epilog
   %pow = call float @llvm.pow.f32(float %x, float %y)
   ret float %pow
 }
 
 define amdgpu_ps float @v_pow_f32_vgpr_sgpr(float %x, float inreg %y) {
 ; GFX6-LABEL: v_pow_f32_vgpr_sgpr:
 ; GFX6:       ; %bb.0:
+; GFX6-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GFX6-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GFX6-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v1
+; GFX6-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GFX6-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; GFX6-NEXT:    v_log_f32_e32 v0, v0
+; GFX6-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GFX6-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX6-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; GFX6-NEXT:    v_mul_legacy_f32_e32 v0, s0, v0
 ; GFX6-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX6-NEXT:    ; return to shader part epilog
 ;
 ; GFX8-LABEL: v_pow_f32_vgpr_sgpr:
 ; GFX8:       ; %bb.0:
+; GFX8-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GFX8-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GFX8-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v1
+; GFX8-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GFX8-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; GFX8-NEXT:    v_log_f32_e32 v0, v0
+; GFX8-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GFX8-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX8-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; GFX8-NEXT:    v_mul_legacy_f32_e32 v0, s0, v0
 ; GFX8-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX8-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: v_pow_f32_vgpr_sgpr:
 ; GFX9:       ; %bb.0:
+; GFX9-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GFX9-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GFX9-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v1
+; GFX9-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GFX9-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; GFX9-NEXT:    v_log_f32_e32 v0, v0
+; GFX9-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GFX9-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX9-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; GFX9-NEXT:    v_mul_legacy_f32_e32 v0, s0, v0
 ; GFX9-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: v_pow_f32_vgpr_sgpr:
 ; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_cmp_gt_f32_e64 s1, 0x800000, |v0|
+; GFX10-NEXT:    v_cndmask_b32_e64 v1, 1.0, 0x4f800000, s1
+; GFX10-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, 0x42000000, s1
 ; GFX10-NEXT:    v_log_f32_e32 v0, v0
+; GFX10-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; GFX10-NEXT:    v_mul_legacy_f32_e32 v0, s0, v0
 ; GFX10-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
 ; GFX11-LABEL: v_pow_f32_vgpr_sgpr:
 ; GFX11:       ; %bb.0:
+; GFX11-NEXT:    v_cmp_gt_f32_e64 s1, 0x800000, |v0|
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_cndmask_b32_e64 v1, 1.0, 0x4f800000, s1
+; GFX11-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX11-NEXT:    v_cndmask_b32_e64 v1, 0, 0x42000000, s1
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
 ; GFX11-NEXT:    v_log_f32_e32 v0, v0
 ; GFX11-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; GFX11-NEXT:    v_mul_dx9_zero_f32_e32 v0, s0, v0
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GFX11-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX11-NEXT:    ; return to shader part epilog
   %pow = call float @llvm.pow.f32(float %x, float %y)
   ret float %pow
 }
 
 define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) {
 ; GFX6-LABEL: v_pow_f32_sgpr_sgpr:
 ; GFX6:       ; %bb.0:
-; GFX6-NEXT:    v_log_f32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, 0x800000
+; GFX6-NEXT:    v_mov_b32_e32 v1, 0x4f800000
+; GFX6-NEXT:    v_cmp_lt_f32_e64 vcc, |s0|, v0
+; GFX6-NEXT:    v_cndmask_b32_e32 v0, 1.0, v1, vcc
+; GFX6-NEXT:    v_mul_f32_e32 v0, s0, v0
+; GFX6-NEXT:    v_log_f32_e32 v0, v0
+; GFX6-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GFX6-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX6-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; GFX6-NEXT:    v_mul_legacy_f32_e32 v0, s1, v0
 ; GFX6-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX6-NEXT:    ; return to shader part epilog
 ;
 ; GFX8-LABEL: v_pow_f32_sgpr_sgpr:
 ; GFX8:       ; %bb.0:
-; GFX8-NEXT:    v_log_f32_e32 v0, s0
+; GFX8-NEXT:    v_mov_b32_e32 v0, 0x800000
+; GFX8-NEXT:    v_mov_b32_e32 v1, 0x4f800000
+; GFX8-NEXT:    v_cmp_lt_f32_e64 vcc, |s0|, v0
+; GFX8-NEXT:    v_cndmask_b32_e32 v0, 1.0, v1, vcc
+; GFX8-NEXT:    v_mul_f32_e32 v0, s0, v0
+; GFX8-NEXT:    v_log_f32_e32 v0, v0
+; GFX8-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GFX8-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX8-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; GFX8-NEXT:    v_mul_legacy_f32_e32 v0, s1, v0
 ; GFX8-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX8-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: v_pow_f32_sgpr_sgpr:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    v_log_f32_e32 v0, s0
+; GFX9-NEXT:    v_mov_b32_e32 v0, 0x800000
+; GFX9-NEXT:    v_mov_b32_e32 v1, 0x4f800000
+; GFX9-NEXT:    v_cmp_lt_f32_e64 vcc, |s0|, v0
+; GFX9-NEXT:    v_cndmask_b32_e32 v0, 1.0, v1, vcc
+; GFX9-NEXT:    v_mul_f32_e32 v0, s0, v0
+; GFX9-NEXT:    v_log_f32_e32 v0, v0
+; GFX9-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GFX9-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX9-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; GFX9-NEXT:    v_mul_legacy_f32_e32 v0, s1, v0
 ; GFX9-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: v_pow_f32_sgpr_sgpr:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_log_f32_e32 v0, s0
+; GFX10-NEXT:    v_cmp_gt_f32_e64 s2, 0x800000, |s0|
+; GFX10-NEXT:    v_cndmask_b32_e64 v0, 1.0, 0x4f800000, s2
+; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, 0x42000000, s2
+; GFX10-NEXT:    v_mul_f32_e32 v0, s0, v0
+; GFX10-NEXT:    v_log_f32_e32 v0, v0
+; GFX10-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; GFX10-NEXT:    v_mul_legacy_f32_e32 v0, s1, v0
 ; GFX10-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
 ; GFX11-LABEL: v_pow_f32_sgpr_sgpr:
 ; GFX11:       ; %bb.0:
-; GFX11-NEXT:    v_log_f32_e32 v0, s0
+; GFX11-NEXT:    v_cmp_gt_f32_e64 s2, 0x800000, |s0|
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 1.0, 0x4f800000, s2
+; GFX11-NEXT:    v_cndmask_b32_e64 v1, 0, 0x42000000, s2
+; GFX11-NEXT:    v_mul_f32_e32 v0, s0, v0
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_log_f32_e32 v0, v0
 ; GFX11-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; GFX11-NEXT:    v_mul_dx9_zero_f32_e32 v0, s1, v0
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GFX11-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX11-NEXT:    ; return to shader part epilog
   %pow = call float @llvm.pow.f32(float %x, float %y)
   ret float %pow
 }
 
 define float @v_pow_f32_fneg_lhs(float %x, float %y) {
 ; GFX6-LABEL: v_pow_f32_fneg_lhs:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    v_log_f32_e64 v0, -v0
+; GFX6-NEXT:    v_mov_b32_e32 v2, 0x800000
+; GFX6-NEXT:    v_mov_b32_e32 v3, 0x4f800000
+; GFX6-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v2
+; GFX6-NEXT:    v_cndmask_b32_e32 v2, 1.0, v3, vcc
+; GFX6-NEXT:    v_mul_f32_e64 v0, -v0, v2
+; GFX6-NEXT:    v_log_f32_e32 v0, v0
+; GFX6-NEXT:    v_mov_b32_e32 v2, 0x42000000
+; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX6-NEXT:    v_sub_f32_e32 v0, v0, v2
 ; GFX6-NEXT:    v_mul_legacy_f32_e32 v0, v0, v1
 ; GFX6-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX6-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX8-LABEL: v_pow_f32_fneg_lhs:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT:    v_log_f32_e64 v0, -v0
+; GFX8-NEXT:    v_mov_b32_e32 v2, 0x800000
+; GFX8-NEXT:    v_mov_b32_e32 v3, 0x4f800000
+; GFX8-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v2
+; GFX8-NEXT:    v_cndmask_b32_e32 v2, 1.0, v3, vcc
+; GFX8-NEXT:    v_mul_f32_e64 v0, -v0, v2
+; GFX8-NEXT:    v_log_f32_e32 v0, v0
+; GFX8-NEXT:    v_mov_b32_e32 v2, 0x42000000
+; GFX8-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX8-NEXT:    v_sub_f32_e32 v0, v0, v2
 ; GFX8-NEXT:    v_mul_legacy_f32_e32 v0, v0, v1
 ; GFX8-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_pow_f32_fneg_lhs:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_log_f32_e64 v0, -v0
+; GFX9-NEXT:    v_mov_b32_e32 v2, 0x800000
+; GFX9-NEXT:    v_mov_b32_e32 v3, 0x4f800000
+; GFX9-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v2
+; GFX9-NEXT:    v_cndmask_b32_e32 v2, 1.0, v3, vcc
+; GFX9-NEXT:    v_mul_f32_e64 v0, -v0, v2
+; GFX9-NEXT:    v_log_f32_e32 v0, v0
+; GFX9-NEXT:    v_mov_b32_e32 v2, 0x42000000
+; GFX9-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX9-NEXT:    v_sub_f32_e32 v0, v0, v2
 ; GFX9-NEXT:    v_mul_legacy_f32_e32 v0, v0, v1
 ; GFX9-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_pow_f32_fneg_lhs:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_log_f32_e64 v0, -v0
+; GFX10-NEXT:    v_cmp_gt_f32_e64 s4, 0x800000, |v0|
+; GFX10-NEXT:    v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s4
+; GFX10-NEXT:    v_mul_f32_e64 v0, -v0, v2
+; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, 0x42000000, s4
+; GFX10-NEXT:    v_log_f32_e32 v0, v0
+; GFX10-NEXT:    v_sub_f32_e32 v0, v0, v2
 ; GFX10-NEXT:    v_mul_legacy_f32_e32 v0, v0, v1
 ; GFX10-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-LABEL: v_pow_f32_fneg_lhs:
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    v_log_f32_e64 v0, -v0
+; GFX11-NEXT:    v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s0
+; GFX11-NEXT:    v_mul_f32_e64 v0, -v0, v2
+; GFX11-NEXT:    v_cndmask_b32_e64 v2, 0, 0x42000000, s0
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_log_f32_e32 v0, v0
 ; GFX11-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-NEXT:    v_sub_f32_e32 v0, v0, v2
 ; GFX11-NEXT:    v_mul_dx9_zero_f32_e32 v0, v0, v1
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GFX11-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %neg.x = fneg float %x
   %pow = call float @llvm.pow.f32(float %neg.x, float %y)
   ret float %pow
 }
 
 define float @v_pow_f32_fneg_rhs(float %x, float %y) {
 ; GFX6-LABEL: v_pow_f32_fneg_rhs:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_mov_b32_e32 v2, 0x800000
+; GFX6-NEXT:    v_mov_b32_e32 v3, 0x4f800000
+; GFX6-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v2
+; GFX6-NEXT:    v_cndmask_b32_e32 v2, 1.0, v3, vcc
+; GFX6-NEXT:    v_mul_f32_e32 v0, v0, v2
 ; GFX6-NEXT:    v_log_f32_e32 v0, v0
+; GFX6-NEXT:    v_mov_b32_e32 v2, 0x42000000
+; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX6-NEXT:    v_sub_f32_e32 v0, v0, v2
 ; GFX6-NEXT:    v_mul_legacy_f32_e64 v0, v0, -v1
 ; GFX6-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX6-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX8-LABEL: v_pow_f32_fneg_rhs:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_mov_b32_e32 v2, 0x800000
+; GFX8-NEXT:    v_mov_b32_e32 v3, 0x4f800000
+; GFX8-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v2
+; GFX8-NEXT:    v_cndmask_b32_e32 v2, 1.0, v3, vcc
+; GFX8-NEXT:    v_mul_f32_e32 v0, v0, v2
 ; GFX8-NEXT:    v_log_f32_e32 v0, v0
+; GFX8-NEXT:    v_mov_b32_e32 v2, 0x42000000
+; GFX8-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX8-NEXT:    v_sub_f32_e32 v0, v0, v2
 ; GFX8-NEXT:    v_mul_legacy_f32_e64 v0, v0, -v1
 ; GFX8-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_pow_f32_fneg_rhs:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v2, 0x800000
+; GFX9-NEXT:    v_mov_b32_e32 v3, 0x4f800000
+; GFX9-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v2
+; GFX9-NEXT:    v_cndmask_b32_e32 v2, 1.0, v3, vcc
+; GFX9-NEXT:    v_mul_f32_e32 v0, v0, v2
 ; GFX9-NEXT:    v_log_f32_e32 v0, v0
+; GFX9-NEXT:    v_mov_b32_e32 v2, 0x42000000
+; GFX9-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX9-NEXT:    v_sub_f32_e32 v0, v0, v2
 ; GFX9-NEXT:    v_mul_legacy_f32_e64 v0, v0, -v1
 ; GFX9-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_pow_f32_fneg_rhs:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_cmp_gt_f32_e64 s4, 0x800000, |v0|
+; GFX10-NEXT:    v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s4
+; GFX10-NEXT:    v_mul_f32_e32 v0, v0, v2
+; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, 0x42000000, s4
 ; GFX10-NEXT:    v_log_f32_e32 v0, v0
+; GFX10-NEXT:    v_sub_f32_e32 v0, v0, v2
 ; GFX10-NEXT:    v_mul_legacy_f32_e64 v0, v0, -v1
 ; GFX10-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-LABEL: v_pow_f32_fneg_rhs:
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT:    v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s0
+; GFX11-NEXT:    v_mul_f32_e32 v0, v0, v2
+; GFX11-NEXT:    v_cndmask_b32_e64 v2, 0, 0x42000000, s0
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
 ; GFX11-NEXT:    v_log_f32_e32 v0, v0
 ; GFX11-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-NEXT:    v_sub_f32_e32 v0, v0, v2
 ; GFX11-NEXT:    v_mul_dx9_zero_f32_e64 v0, v0, -v1
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GFX11-NEXT:    v_exp_f32_e32 v0, v0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %neg.y = fneg float %y
   %pow = call float @llvm.pow.f32(float %x, float %neg.y)
   ret float %pow
 }

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck %s
 
 ---
 name: test_flog_s32
 body: |
   bb.0:
     liveins: $vgpr0
 
     ; CHECK-LABEL: name: test_flog_s32
     ; CHECK: liveins: $vgpr0
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
-    ; CHECK-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[COPY]]
-    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FE62E4300000000
-    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FLOG2_]], [[C]]
-    ; CHECK-NEXT: $vgpr0 = COPY [[FMUL]](s32)
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+    ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY]]
+    ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C]]
+    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
+    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[SELECT]]
+    ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32)
+    ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01
+    ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+    ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
+    ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[INT]], [[SELECT1]]
+    ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FE62E4300000000
+    ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FSUB]], [[C5]]
+    ; CHECK-NEXT: $vgpr0 = COPY [[FMUL1]](s32)
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = G_FLOG %0
     $vgpr0 = COPY %1
 ...
 
 ---
 name: test_flog_s32_flags
 body: |
   bb.0:
     liveins: $vgpr0
 
     ; CHECK-LABEL: name: test_flog_s32_flags
     ; CHECK: liveins: $vgpr0
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
-    ; CHECK-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = nnan G_FLOG2 [[COPY]]
-    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FE62E4300000000
-    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[FLOG2_]], [[C]]
-    ; CHECK-NEXT: $vgpr0 = COPY [[FMUL]](s32)
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+    ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = nnan G_FABS [[COPY]]
+    ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C]]
+    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
+    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[SELECT]]
+    ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32)
+    ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01
+    ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+    ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
+    ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = nnan G_FSUB [[INT]], [[SELECT1]]
+    ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FE62E4300000000
+    ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = nnan G_FMUL [[FSUB]], [[C5]]
+    ; CHECK-NEXT: $vgpr0 = COPY [[FMUL1]](s32)
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = nnan G_FLOG %0
     $vgpr0 = COPY %1
 ...
 
 ---
 name: test_flog_v2s32
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1
 
     ; CHECK-LABEL: name: test_flog_v2s32
     ; CHECK: liveins: $vgpr0_vgpr1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
     ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
-    ; CHECK-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[UV]]
-    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FE62E4300000000
-    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FLOG2_]], [[C]]
-    ; CHECK-NEXT: [[FLOG2_1:%[0-9]+]]:_(s32) = G_FLOG2 [[UV1]]
-    ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FLOG2_1]], [[C]]
-    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FMUL]](s32), [[FMUL1]](s32)
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+    ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[UV]]
+    ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C]]
+    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
+    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[SELECT]]
+    ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32)
+    ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01
+    ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+    ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
+    ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[INT]], [[SELECT1]]
+    ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FE62E4300000000
+    ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FSUB]], [[C5]]
+    ; CHECK-NEXT: [[FABS1:%[0-9]+]]:_(s32) = G_FABS [[UV1]]
+    ; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS1]](s32), [[C]]
+    ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C1]], [[C2]]
+    ; CHECK-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[SELECT2]]
+    ; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL2]](s32)
+    ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C3]], [[C4]]
+    ; CHECK-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[INT1]], [[SELECT3]]
+    ; CHECK-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[FSUB1]], [[C5]]
+    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FMUL1]](s32), [[FMUL3]](s32)
     ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
     %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
     %1:_(<2 x s32>) = G_FLOG %0
     $vgpr0_vgpr1 = COPY %1
 ...
 
 ---
 name: test_flog_v3s32
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1_vgpr2
 
     ; CHECK-LABEL: name: test_flog_v3s32
     ; CHECK: liveins: $vgpr0_vgpr1_vgpr2
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
     ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
-    ; CHECK-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[UV]]
-    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FE62E4300000000
-    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FLOG2_]], [[C]]
-    ; CHECK-NEXT: [[FLOG2_1:%[0-9]+]]:_(s32) = G_FLOG2 [[UV1]]
-    ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FLOG2_1]], [[C]]
-    ; CHECK-NEXT: [[FLOG2_2:%[0-9]+]]:_(s32) = G_FLOG2 [[UV2]]
-    ; CHECK-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FLOG2_2]], [[C]]
-    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FMUL]](s32), [[FMUL1]](s32), [[FMUL2]](s32)
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+    ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[UV]]
+    ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C]]
+    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
+    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[SELECT]]
+    ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32)
+    ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01
+    ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+    ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
+    ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[INT]], [[SELECT1]]
+    ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FE62E4300000000
+    ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FSUB]], [[C5]]
+    ; CHECK-NEXT: [[FABS1:%[0-9]+]]:_(s32) = G_FABS [[UV1]]
+    ; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS1]](s32), [[C]]
+    ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C1]], [[C2]]
+    ; CHECK-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[SELECT2]]
+    ; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL2]](s32)
+    ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C3]], [[C4]]
+    ; CHECK-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[INT1]], [[SELECT3]]
+    ; CHECK-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[FSUB1]], [[C5]]
+    ; CHECK-NEXT: [[FABS2:%[0-9]+]]:_(s32) = G_FABS [[UV2]]
+    ; CHECK-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS2]](s32), [[C]]
+    ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[FCMP2]](s1), [[C1]], [[C2]]
+    ; CHECK-NEXT: [[FMUL4:%[0-9]+]]:_(s32) = G_FMUL [[UV2]], [[SELECT4]]
+    ; CHECK-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL4]](s32)
+    ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[FCMP2]](s1), [[C3]], [[C4]]
+    ; CHECK-NEXT: [[FSUB2:%[0-9]+]]:_(s32) = G_FSUB [[INT2]], [[SELECT5]]
+    ; CHECK-NEXT: [[FMUL5:%[0-9]+]]:_(s32) = G_FMUL [[FSUB2]], [[C5]]
+    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FMUL1]](s32), [[FMUL3]](s32), [[FMUL5]](s32)
     ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
     %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
     %1:_(<3 x  s32>) = G_FLOG %0
     $vgpr0_vgpr1_vgpr2 = COPY %1
 ...
 
 ---
 name: test_flog_s16
 body: |
   bb.0:
     liveins: $vgpr0
 
     ; CHECK-LABEL: name: test_flog_s16
     ; CHECK: liveins: $vgpr0
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
     ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
-    ; CHECK-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[FPEXT]]
+    ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT]](s32)
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FE62E4300000000
-    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FLOG2_]], [[C]]
+    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[C]]
     ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL]](s32)
     ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
     ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
     %0:_(s32) = COPY $vgpr0
     %1:_(s16) = G_TRUNC %0
     %2:_(s16) = G_FLOG %1
     %3:_(s32) = G_ANYEXT %2
     $vgpr0 = COPY %3
bb.0:
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
     ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
     ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
     ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
     ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
     ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
-    ; CHECK-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[FPEXT]]
+    ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT]](s32)
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FE62E4300000000
-    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FLOG2_]], [[C1]]
+    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[C1]]
     ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL]](s32)
     ; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
-    ; CHECK-NEXT: [[FLOG2_1:%[0-9]+]]:_(s32) = G_FLOG2 [[FPEXT1]]
-    ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FLOG2_1]], [[C1]]
+    ; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT1]](s32)
+    ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[INT1]], [[C1]]
     ; CHECK-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL1]](s32)
     ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC]](s16)
     ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC1]](s16)
     ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)
     ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
     ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
     ; CHECK-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
     %0:_(<2 x s16>) = COPY $vgpr0
     %1:_(<2 x s16>) = G_FLOG %0
     $vgpr0 = COPY %1
 
 ...

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog10.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck %s
 
 ---
 name: test_flog10_s32
 body: |
   bb.0:
     liveins: $vgpr0
 
     ; CHECK-LABEL: name: test_flog10_s32
     ; CHECK: liveins: $vgpr0
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
-    ; CHECK-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[COPY]]
-    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FD3441360000000
-    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FLOG2_]], [[C]]
-    ; CHECK-NEXT: $vgpr0 = COPY [[FMUL]](s32)
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+    ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C]]
+    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
+    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[SELECT]]
+    ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32)
+    ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01
+    ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+    ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
+    ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[INT]], [[SELECT1]]
+    ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FD3441360000000
+    ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FSUB]], [[C5]]
+    ; CHECK-NEXT: $vgpr0 = COPY [[FMUL1]](s32)
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = G_FLOG10 %0
     $vgpr0 = COPY %1
 ...
 
 ---
 name: test_flog10_s32_flags
 body: |
   bb.0:
     liveins: $vgpr0
 
     ; CHECK-LABEL: name: test_flog10_s32_flags
     ; CHECK: liveins: $vgpr0
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
-    ; CHECK-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = nnan G_FLOG2 [[COPY]]
-    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FD3441360000000
-    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[FLOG2_]], [[C]]
-    ; CHECK-NEXT: $vgpr0 = COPY [[FMUL]](s32)
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+    ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C]]
+    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
+    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[SELECT]]
+    ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32)
+    ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01
+    ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+    ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
+    ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = nnan G_FSUB [[INT]], [[SELECT1]]
+    ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FD3441360000000
+    ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = nnan G_FMUL [[FSUB]], [[C5]]
+    ; CHECK-NEXT: $vgpr0 = COPY [[FMUL1]](s32)
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = nnan G_FLOG10 %0
     $vgpr0 = COPY %1
 ...
 
 ---
 name: test_flog10_v2s32
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1
 
     ; CHECK-LABEL: name: test_flog10_v2s32
     ; CHECK: liveins: $vgpr0_vgpr1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
     ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
-    ; CHECK-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[UV]]
-    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FD3441360000000
-    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FLOG2_]], [[C]]
-    ; CHECK-NEXT: [[FLOG2_1:%[0-9]+]]:_(s32) = G_FLOG2 [[UV1]]
-    ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FLOG2_1]], [[C]]
-    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FMUL]](s32), [[FMUL1]](s32)
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+    ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C]]
+    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
+    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[SELECT]]
+    ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32)
+    ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01
+    ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+    ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
+    ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[INT]], [[SELECT1]]
+    ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FD3441360000000
+    ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FSUB]], [[C5]]
+    ; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s32), [[C]]
+    ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C1]], [[C2]]
+    ; CHECK-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[SELECT2]]
+    ; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL2]](s32)
+    ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C3]], [[C4]]
+    ; CHECK-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[INT1]], [[SELECT3]]
+    ; CHECK-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[FSUB1]], [[C5]]
+    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FMUL1]](s32), [[FMUL3]](s32)
     ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
     %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
     %1:_(<2 x s32>) = G_FLOG10 %0
     $vgpr0_vgpr1 = COPY %1
 ...
 
 ---
 name: test_flog10_v3s32
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1_vgpr2
 
     ; CHECK-LABEL: name: test_flog10_v3s32
     ; CHECK: liveins: $vgpr0_vgpr1_vgpr2
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
     ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
-    ; CHECK-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[UV]]
-    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FD3441360000000
-    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FLOG2_]], [[C]]
-    ; CHECK-NEXT: [[FLOG2_1:%[0-9]+]]:_(s32) = G_FLOG2 [[UV1]]
-    ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FLOG2_1]], [[C]]
-    ; CHECK-NEXT: [[FLOG2_2:%[0-9]+]]:_(s32) = G_FLOG2 [[UV2]]
-    ; CHECK-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FLOG2_2]], [[C]]
-    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FMUL]](s32), [[FMUL1]](s32), [[FMUL2]](s32)
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+    ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C]]
+    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
+    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[SELECT]]
+    ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32)
+    ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01
+    ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+    ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
+    ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[INT]], [[SELECT1]]
+    ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FD3441360000000
+    ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FSUB]], [[C5]]
+    ; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s32), [[C]]
+    ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C1]], [[C2]]
+    ; CHECK-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[SELECT2]]
+    ; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL2]](s32)
+    ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C3]], [[C4]]
+    ; CHECK-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[INT1]], [[SELECT3]]
+    ; CHECK-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[FSUB1]], [[C5]]
+    ; CHECK-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV2]](s32), [[C]]
+    ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[FCMP2]](s1), [[C1]], [[C2]]
+    ; CHECK-NEXT: [[FMUL4:%[0-9]+]]:_(s32) = G_FMUL [[UV2]], [[SELECT4]]
+    ; CHECK-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL4]](s32)
+    ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[FCMP2]](s1), [[C3]], [[C4]]
+    ; CHECK-NEXT: [[FSUB2:%[0-9]+]]:_(s32) = G_FSUB [[INT2]], [[SELECT5]]
+    ; CHECK-NEXT: [[FMUL5:%[0-9]+]]:_(s32) = G_FMUL [[FSUB2]], [[C5]]
+    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FMUL1]](s32), [[FMUL3]](s32), [[FMUL5]](s32)
     ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
     %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
     %1:_(<3 x  s32>) = G_FLOG10 %0
     $vgpr0_vgpr1_vgpr2 = COPY %1
 ...
 
 ---
 name: test_flog10_s16
 body: |
   bb.0:
     liveins: $vgpr0
 
     ; CHECK-LABEL: name: test_flog10_s16
     ; CHECK: liveins: $vgpr0
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
     ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
-    ; CHECK-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[FPEXT]]
+    ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT]](s32)
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FD3441360000000
-    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FLOG2_]], [[C]]
+    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[C]]
     ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL]](s32)
     ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
     ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
     %0:_(s32) = COPY $vgpr0
     %1:_(s16) = G_TRUNC %0
     %2:_(s16) = G_FLOG10 %1
     %3:_(s32) = G_ANYEXT %2
     $vgpr0 = COPY %3
bb.0:
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
     ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
     ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
     ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
     ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
     ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
-    ; CHECK-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[FPEXT]]
+    ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT]](s32)
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FD3441360000000
-    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FLOG2_]], [[C1]]
+    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[C1]]
     ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL]](s32)
     ; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
-    ; CHECK-NEXT: [[FLOG2_1:%[0-9]+]]:_(s32) = G_FLOG2 [[FPEXT1]]
-    ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FLOG2_1]], [[C1]]
+    ; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT1]](s32)
+    ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[INT1]], [[C1]]
     ; CHECK-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL1]](s32)
     ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC]](s16)
     ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC1]](s16)
     ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)
     ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
     ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
     ; CHECK-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
     %0:_(<2 x s16>) = COPY $vgpr0
     %1:_(<2 x s16>) = G_FLOG10 %0
     $vgpr0 = COPY %1
 
 ...

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog2.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck %s
 
 ---
 name: test_flog2_s32
 body: |
   bb.0:
     liveins: $vgpr0
 
     ; CHECK-LABEL: name: test_flog2_s32
     ; CHECK: liveins: $vgpr0
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
-    ; CHECK-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[COPY]]
-    ; CHECK-NEXT: $vgpr0 = COPY [[FLOG2_]](s32)
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+    ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY]]
+    ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C]]
+    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
+    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[SELECT]]
+    ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32)
+    ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01
+    ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+    ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
+    ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[INT]], [[SELECT1]]
+    ; CHECK-NEXT: $vgpr0 = COPY [[FSUB]](s32)
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = G_FLOG2 %0
     $vgpr0 = COPY %1
 ...
 
 ---
 name: test_flog2_v2s32
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1
 
     ; CHECK-LABEL: name: test_flog2_v2s32
     ; CHECK: liveins: $vgpr0_vgpr1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
     ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
-    ; CHECK-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[UV]]
-    ; CHECK-NEXT: [[FLOG2_1:%[0-9]+]]:_(s32) = G_FLOG2 [[UV1]]
-    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FLOG2_]](s32), [[FLOG2_1]](s32)
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+    ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[UV]]
+    ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C]]
+    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
+    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[SELECT]]
+    ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32)
+    ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01
+    ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+    ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
+    ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[INT]], [[SELECT1]]
+    ; CHECK-NEXT: [[FABS1:%[0-9]+]]:_(s32) = G_FABS [[UV1]]
+    ; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS1]](s32), [[C]]
+    ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C1]], [[C2]]
+    ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[SELECT2]]
+    ; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL1]](s32)
+    ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C3]], [[C4]]
+    ; CHECK-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[INT1]], [[SELECT3]]
+    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FSUB]](s32), [[FSUB1]](s32)
     ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
     %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
     %1:_(<2 x s32>) = G_FLOG2 %0
     $vgpr0_vgpr1 = COPY %1
 ...
 
 ---
 name: test_flog2_v3s32
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1_vgpr2
 
     ; CHECK-LABEL: name: test_flog2_v3s32
     ; CHECK: liveins: $vgpr0_vgpr1_vgpr2
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
     ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
-    ; CHECK-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[UV]]
-    ; CHECK-NEXT: [[FLOG2_1:%[0-9]+]]:_(s32) = G_FLOG2 [[UV1]]
-    ; CHECK-NEXT: [[FLOG2_2:%[0-9]+]]:_(s32) = G_FLOG2 [[UV2]]
-    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FLOG2_]](s32), [[FLOG2_1]](s32), [[FLOG2_2]](s32)
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+    ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[UV]]
+    ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C]]
+    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
+    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[SELECT]]
+    ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32)
+    ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01
+    ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+    ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
+    ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[INT]], [[SELECT1]]
+    ; CHECK-NEXT: [[FABS1:%[0-9]+]]:_(s32) = G_FABS [[UV1]]
+    ; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS1]](s32), [[C]]
+    ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C1]], [[C2]]
+    ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[SELECT2]]
+    ; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL1]](s32)
+    ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C3]], [[C4]]
+    ; CHECK-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[INT1]], [[SELECT3]]
+    ; CHECK-NEXT: [[FABS2:%[0-9]+]]:_(s32) = G_FABS [[UV2]]
+    ; CHECK-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS2]](s32), [[C]]
+    ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[FCMP2]](s1), [[C1]], [[C2]]
+    ; CHECK-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[UV2]], [[SELECT4]]
+    ; CHECK-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL2]](s32)
+    ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[FCMP2]](s1), [[C3]], [[C4]]
+    ; CHECK-NEXT: [[FSUB2:%[0-9]+]]:_(s32) = G_FSUB [[INT2]], [[SELECT5]]
+    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FSUB]](s32), [[FSUB1]](s32), [[FSUB2]](s32)
     ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
     %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
     %1:_(<3 x  s32>) = G_FLOG2 %0
     $vgpr0_vgpr1_vgpr2 = COPY %1
 ...

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir

body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     ; GFX6-LABEL: name: test_fpow_s32
     ; GFX6: liveins: $vgpr0, $vgpr1
     ; GFX6-NEXT: {{  $}}
     ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
-    ; GFX6-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[COPY]]
-    ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_]](s32), [[COPY1]](s32)
-    ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[INT]]
+    ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+    ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY]]
+    ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C]]
+    ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+    ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+    ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
+    ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[SELECT]]
+    ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32)
+    ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01
+    ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+    ; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
+    ; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[INT]], [[SELECT1]]
+    ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB]](s32), [[COPY1]](s32)
+    ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[INT1]]
     ; GFX6-NEXT: $vgpr0 = COPY [[FEXP2_]](s32)
     ; GFX9-LABEL: name: test_fpow_s32
     ; GFX9: liveins: $vgpr0, $vgpr1
     ; GFX9-NEXT: {{  $}}
     ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
-    ; GFX9-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[COPY]]
-    ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_]](s32), [[COPY1]](s32)
-    ; GFX9-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[INT]]
+    ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+    ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY]]
+    ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C]]
+    ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+    ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+    ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
+    ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[SELECT]]
+    ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32)
+    ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01
+    ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+    ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
+    ; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[INT]], [[SELECT1]]
+    ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB]](s32), [[COPY1]](s32)
+    ; GFX9-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[INT1]]
     ; GFX9-NEXT: $vgpr0 = COPY [[FEXP2_]](s32)
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = COPY $vgpr1
     %2:_(s32) = G_FPOW %0, %1
     $vgpr0 = COPY %2
 ...
 
 ---
 name: test_fpow_v2s32
 body: |
   bb.0.entry:
     liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
 
     ; GFX6-LABEL: name: test_fpow_v2s32
     ; GFX6: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
     ; GFX6-NEXT: {{  $}}
     ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
     ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
     ; GFX6-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
     ; GFX6-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
-    ; GFX6-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[UV]]
-    ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_]](s32), [[UV2]](s32)
-    ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[INT]]
-    ; GFX6-NEXT: [[FLOG2_1:%[0-9]+]]:_(s32) = G_FLOG2 [[UV1]]
-    ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_1]](s32), [[UV3]](s32)
-    ; GFX6-NEXT: [[FEXP2_1:%[0-9]+]]:_(s32) = G_FEXP2 [[INT1]]
+    ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+    ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[UV]]
+    ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C]]
+    ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+    ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+    ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
+    ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[SELECT]]
+    ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32)
+    ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01
+    ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+    ; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
+    ; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[INT]], [[SELECT1]]
+    ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB]](s32), [[UV2]](s32)
+    ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[INT1]]
+    ; GFX6-NEXT: [[FABS1:%[0-9]+]]:_(s32) = G_FABS [[UV1]]
+    ; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS1]](s32), [[C]]
+    ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C1]], [[C2]]
+    ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[SELECT2]]
+    ; GFX6-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL1]](s32)
+    ; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C3]], [[C4]]
+    ; GFX6-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[INT2]], [[SELECT3]]
+    ; GFX6-NEXT: [[INT3:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB1]](s32), [[UV3]](s32)
+    ; GFX6-NEXT: [[FEXP2_1:%[0-9]+]]:_(s32) = G_FEXP2 [[INT3]]
     ; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FEXP2_]](s32), [[FEXP2_1]](s32)
     ; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
     ; GFX9-LABEL: name: test_fpow_v2s32
     ; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
     ; GFX9-NEXT: {{  $}}
     ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
     ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
     ; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
     ; GFX9-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
-    ; GFX9-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[UV]]
-    ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_]](s32), [[UV2]](s32)
-    ; GFX9-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[INT]]
-    ; GFX9-NEXT: [[FLOG2_1:%[0-9]+]]:_(s32) = G_FLOG2 [[UV1]]
-    ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_1]](s32), [[UV3]](s32)
-    ; GFX9-NEXT: [[FEXP2_1:%[0-9]+]]:_(s32) = G_FEXP2 [[INT1]]
+    ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+    ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[UV]]
+    ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C]]
+    ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+    ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+    ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
+    ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[SELECT]]
+    ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32)
+    ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01
+    ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+    ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
+    ; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[INT]], [[SELECT1]]
+    ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB]](s32), [[UV2]](s32)
+    ; GFX9-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[INT1]]
+    ; GFX9-NEXT: [[FABS1:%[0-9]+]]:_(s32) = G_FABS [[UV1]]
+    ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS1]](s32), [[C]]
+    ; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C1]], [[C2]]
+    ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[SELECT2]]
+    ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL1]](s32)
+    ; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C3]], [[C4]]
+    ; GFX9-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[INT2]], [[SELECT3]]
+    ; GFX9-NEXT: [[INT3:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB1]](s32), [[UV3]](s32)
+    ; GFX9-NEXT: [[FEXP2_1:%[0-9]+]]:_(s32) = G_FEXP2 [[INT3]]
     ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FEXP2_]](s32), [[FEXP2_1]](s32)
     ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
     %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
     %1:_(<2 x s32>) = COPY $vgpr2_vgpr3
     %2:_(<2 x s32>) = G_FPOW %0, %1
     $vgpr0_vgpr1 = COPY %2
 ...
 
 ---
 name: test_fpow_v3s32
 body: |
   bb.0.entry:
     liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
 
     ; GFX6-LABEL: name: test_fpow_v3s32
     ; GFX6: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
     ; GFX6-NEXT: {{  $}}
     ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
     ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
     ; GFX6-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
     ; GFX6-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
-    ; GFX6-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[UV]]
-    ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_]](s32), [[UV3]](s32)
-    ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[INT]]
-    ; GFX6-NEXT: [[FLOG2_1:%[0-9]+]]:_(s32) = G_FLOG2 [[UV1]]
-    ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_1]](s32), [[UV4]](s32)
-    ; GFX6-NEXT: [[FEXP2_1:%[0-9]+]]:_(s32) = G_FEXP2 [[INT1]]
-    ; GFX6-NEXT: [[FLOG2_2:%[0-9]+]]:_(s32) = G_FLOG2 [[UV2]]
-    ; GFX6-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_2]](s32), [[UV5]](s32)
-    ; GFX6-NEXT: [[FEXP2_2:%[0-9]+]]:_(s32) = G_FEXP2 [[INT2]]
+    ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+    ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[UV]]
+    ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C]]
+    ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+    ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+    ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
+    ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[SELECT]]
+    ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32)
+    ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01
+    ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+    ; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
+    ; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[INT]], [[SELECT1]]
+    ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB]](s32), [[UV3]](s32)
+    ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[INT1]]
+    ; GFX6-NEXT: [[FABS1:%[0-9]+]]:_(s32) = G_FABS [[UV1]]
+    ; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS1]](s32), [[C]]
+    ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C1]], [[C2]]
+    ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[SELECT2]]
+    ; GFX6-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL1]](s32)
+    ; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C3]], [[C4]]
+    ; GFX6-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[INT2]], [[SELECT3]]
+    ; GFX6-NEXT: [[INT3:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB1]](s32), [[UV4]](s32)
+    ; GFX6-NEXT: [[FEXP2_1:%[0-9]+]]:_(s32) = G_FEXP2 [[INT3]]
+    ; GFX6-NEXT: [[FABS2:%[0-9]+]]:_(s32) = G_FABS [[UV2]]
+    ; GFX6-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS2]](s32), [[C]]
+    ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[FCMP2]](s1), [[C1]], [[C2]]
+    ; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[UV2]], [[SELECT4]]
+    ; GFX6-NEXT: [[INT4:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL2]](s32)
+    ; GFX6-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[FCMP2]](s1), [[C3]], [[C4]]
+    ; GFX6-NEXT: [[FSUB2:%[0-9]+]]:_(s32) = G_FSUB [[INT4]], [[SELECT5]]
+    ; GFX6-NEXT: [[INT5:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB2]](s32), [[UV5]](s32)
+    ; GFX6-NEXT: [[FEXP2_2:%[0-9]+]]:_(s32) = G_FEXP2 [[INT5]]
     ; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FEXP2_]](s32), [[FEXP2_1]](s32), [[FEXP2_2]](s32)
     ; GFX6-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
     ; GFX9-LABEL: name: test_fpow_v3s32
     ; GFX9: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
     ; GFX9-NEXT: {{  $}}
     ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
     ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
     ; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
     ; GFX9-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
-    ; GFX9-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[UV]]
-    ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_]](s32), [[UV3]](s32)
-    ; GFX9-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[INT]]
-    ; GFX9-NEXT: [[FLOG2_1:%[0-9]+]]:_(s32) = G_FLOG2 [[UV1]]
-    ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_1]](s32), [[UV4]](s32)
-    ; GFX9-NEXT: [[FEXP2_1:%[0-9]+]]:_(s32) = G_FEXP2 [[INT1]]
-    ; GFX9-NEXT: [[FLOG2_2:%[0-9]+]]:_(s32) = G_FLOG2 [[UV2]]
-    ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_2]](s32), [[UV5]](s32)
-    ; GFX9-NEXT: [[FEXP2_2:%[0-9]+]]:_(s32) = G_FEXP2 [[INT2]]
+    ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+    ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[UV]]
+    ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C]]
+    ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+    ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+    ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
+    ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[SELECT]]
+    ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32)
+    ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01
+    ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+    ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
+    ; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[INT]], [[SELECT1]]
+    ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB]](s32), [[UV3]](s32)
+    ; GFX9-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[INT1]]
+    ; GFX9-NEXT: [[FABS1:%[0-9]+]]:_(s32) = G_FABS [[UV1]]
+    ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS1]](s32), [[C]]
+    ; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C1]], [[C2]]
+    ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[SELECT2]]
+    ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL1]](s32)
+    ; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C3]], [[C4]]
+    ; GFX9-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[INT2]], [[SELECT3]]
+    ; GFX9-NEXT: [[INT3:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB1]](s32), [[UV4]](s32)
+    ; GFX9-NEXT: [[FEXP2_1:%[0-9]+]]:_(s32) = G_FEXP2 [[INT3]]
+    ; GFX9-NEXT: [[FABS2:%[0-9]+]]:_(s32) = G_FABS [[UV2]]
+    ; GFX9-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS2]](s32), [[C]]
+    ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[FCMP2]](s1), [[C1]], [[C2]]
+    ; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[UV2]], [[SELECT4]]
+    ; GFX9-NEXT: [[INT4:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL2]](s32)
+    ; GFX9-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[FCMP2]](s1), [[C3]], [[C4]]
+    ; GFX9-NEXT: [[FSUB2:%[0-9]+]]:_(s32) = G_FSUB [[INT4]], [[SELECT5]]
+    ; GFX9-NEXT: [[INT5:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB2]](s32), [[UV5]](s32)
+    ; GFX9-NEXT: [[FEXP2_2:%[0-9]+]]:_(s32) = G_FEXP2 [[INT5]]
     ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FEXP2_]](s32), [[FEXP2_1]](s32), [[FEXP2_2]](s32)
     ; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
     %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
     %1:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
     %2:_(<3 x s32>) = G_FPOW %0, %1
     $vgpr0_vgpr1_vgpr2 = COPY %2
 ...
 
 ---
 name: test_fpow_s32_flags
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     ; GFX6-LABEL: name: test_fpow_s32_flags
     ; GFX6: liveins: $vgpr0, $vgpr1
     ; GFX6-NEXT: {{  $}}
     ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
-    ; GFX6-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = nnan nsz G_FLOG2 [[COPY]]
-    ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_]](s32), [[COPY1]](s32)
-    ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = nnan nsz G_FEXP2 [[INT]]
+    ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+    ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(s32) = nnan nsz G_FABS [[COPY]]
+    ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C]]
+    ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+    ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+    ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = nnan nsz G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
+    ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan nsz G_FMUL [[COPY]], [[SELECT]]
+    ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32)
+    ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01
+    ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+    ; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = nnan nsz G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
+    ; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(s32) = nnan nsz G_FSUB [[INT]], [[SELECT1]]
+    ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(s32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB]](s32), [[COPY1]](s32)
+    ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = nnan nsz G_FEXP2 [[INT1]]
     ; GFX6-NEXT: $vgpr0 = COPY [[FEXP2_]](s32)
     ; GFX9-LABEL: name: test_fpow_s32_flags
     ; GFX9: liveins: $vgpr0, $vgpr1
     ; GFX9-NEXT: {{  $}}
     ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
-    ; GFX9-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = nnan nsz G_FLOG2 [[COPY]]
-    ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_]](s32), [[COPY1]](s32)
-    ; GFX9-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = nnan nsz G_FEXP2 [[INT]]
+    ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+    ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(s32) = nnan nsz G_FABS [[COPY]]
+    ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C]]
+    ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+    ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+    ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = nnan nsz G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
+    ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan nsz G_FMUL [[COPY]], [[SELECT]]
+    ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32)
+    ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01
+    ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+    ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = nnan nsz G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
+    ; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(s32) = nnan nsz G_FSUB [[INT]], [[SELECT1]]
+    ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(s32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB]](s32), [[COPY1]](s32)
+    ; GFX9-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = nnan nsz G_FEXP2 [[INT1]]
     ; GFX9-NEXT: $vgpr0 = COPY [[FEXP2_]](s32)
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = COPY $vgpr1
     %2:_(s32) = nnan nsz G_FPOW %0, %1
     $vgpr0 = COPY %2
 ...
 
 ---
 name: test_fpow_s16
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     ; GFX6-LABEL: name: test_fpow_s16
     ; GFX6: liveins: $vgpr0, $vgpr1
     ; GFX6-NEXT: {{  $}}
     ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
     ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
     ; GFX6-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
     ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
     ; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
-    ; GFX6-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[FPEXT]]
-    ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_]](s32), [[FPEXT1]](s32)
-    ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[INT]]
+    ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT]](s32)
+    ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[INT]](s32), [[FPEXT1]](s32)
+    ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[INT1]]
     ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FEXP2_]](s32)
     ; GFX6-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
     ; GFX6-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
     ; GFX9-LABEL: name: test_fpow_s16
     ; GFX9: liveins: $vgpr0, $vgpr1
     ; GFX9-NEXT: {{  $}}
     ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
bb.0:
     ; GFX6-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
     ; GFX6-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
     ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
     ; GFX6-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](s32)
     ; GFX6-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
     ; GFX6-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
     ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
     ; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC2]](s16)
-    ; GFX6-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[FPEXT]]
-    ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_]](s32), [[FPEXT1]](s32)
-    ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[INT]]
+    ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT]](s32)
+    ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[INT]](s32), [[FPEXT1]](s32)
+    ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[INT1]]
     ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FEXP2_]](s32)
     ; GFX6-NEXT: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
     ; GFX6-NEXT: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC3]](s16)
-    ; GFX6-NEXT: [[FLOG2_1:%[0-9]+]]:_(s32) = G_FLOG2 [[FPEXT2]]
-    ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_1]](s32), [[FPEXT3]](s32)
-    ; GFX6-NEXT: [[FEXP2_1:%[0-9]+]]:_(s32) = G_FEXP2 [[INT1]]
+    ; GFX6-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT2]](s32)
+    ; GFX6-NEXT: [[INT3:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[INT2]](s32), [[FPEXT3]](s32)
+    ; GFX6-NEXT: [[FEXP2_1:%[0-9]+]]:_(s32) = G_FEXP2 [[INT3]]
     ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FEXP2_1]](s32)
     ; GFX6-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC]](s16)
     ; GFX6-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC1]](s16)
     ; GFX6-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)
     ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
     ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
     ; GFX6-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
     ; GFX9-LABEL: name: test_fpow_v2s16
bb.0:
     ; GFX6-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
     ; GFX6-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
     ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
     ; GFX6-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](s32)
     ; GFX6-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
     ; GFX6-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
     ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
     ; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC2]](s16)
-    ; GFX6-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = nnan nsz G_FLOG2 [[FPEXT]]
-    ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_]](s32), [[FPEXT1]](s32)
-    ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = nnan nsz G_FEXP2 [[INT]]
+    ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT]](s32)
+    ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(s32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[INT]](s32), [[FPEXT1]](s32)
+    ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = nnan nsz G_FEXP2 [[INT1]]
     ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FEXP2_]](s32)
     ; GFX6-NEXT: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
     ; GFX6-NEXT: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC3]](s16)
-    ; GFX6-NEXT: [[FLOG2_1:%[0-9]+]]:_(s32) = nnan nsz G_FLOG2 [[FPEXT2]]
-    ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(s32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_1]](s32), [[FPEXT3]](s32)
-    ; GFX6-NEXT: [[FEXP2_1:%[0-9]+]]:_(s32) = nnan nsz G_FEXP2 [[INT1]]
+    ; GFX6-NEXT: [[INT2:%[0-9]+]]:_(s32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT2]](s32)
+    ; GFX6-NEXT: [[INT3:%[0-9]+]]:_(s32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[INT2]](s32), [[FPEXT3]](s32)
+    ; GFX6-NEXT: [[FEXP2_1:%[0-9]+]]:_(s32) = nnan nsz G_FEXP2 [[INT3]]
     ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FEXP2_1]](s32)
     ; GFX6-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC]](s16)
     ; GFX6-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC1]](s16)
     ; GFX6-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)
     ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
     ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
     ; GFX6-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
     ; GFX9-LABEL: name: test_fpow_v2s16_flags

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpowi.mir

bb.0:
     ; GFX6-LABEL: name: test_fpowi_s16_s32_flags
     ; GFX6: liveins: $vgpr0, $vgpr1
     ; GFX6-NEXT: {{  $}}
     ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
     ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
     ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
     ; GFX6-NEXT: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[COPY1]](s32)
-    ; GFX6-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = nnan G_FLOG2 [[FPEXT]]
-    ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_]](s32), [[SITOFP]](s32)
-    ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = nnan G_FEXP2 [[INT]]
+    ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT]](s32)
+    ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[INT]](s32), [[SITOFP]](s32)
+    ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = nnan G_FEXP2 [[INT1]]
     ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FEXP2_]](s32)
     ; GFX6-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
     ; GFX6-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
     ; GFX9-LABEL: name: test_fpowi_s16_s32_flags
     ; GFX9: liveins: $vgpr0, $vgpr1
     ; GFX9-NEXT: {{  $}}
     ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
bb.0:
     liveins: $vgpr0, $vgpr1
 
     ; GFX6-LABEL: name: test_fpowi_s32_s32_flags
     ; GFX6: liveins: $vgpr0, $vgpr1
     ; GFX6-NEXT: {{  $}}
     ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
     ; GFX6-NEXT: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[COPY1]](s32)
-    ; GFX6-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = nnan G_FLOG2 [[COPY]]
-    ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_]](s32), [[SITOFP]](s32)
-    ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = nnan G_FEXP2 [[INT]]
+    ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+    ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(s32) = nnan G_FABS [[COPY]]
+    ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C]]
+    ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+    ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+    ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
+    ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[SELECT]]
+    ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32)
+    ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01
+    ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+    ; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
+    ; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(s32) = nnan G_FSUB [[INT]], [[SELECT1]]
+    ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB]](s32), [[SITOFP]](s32)
+    ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = nnan G_FEXP2 [[INT1]]
     ; GFX6-NEXT: $vgpr0 = COPY [[FEXP2_]](s32)
     ; GFX9-LABEL: name: test_fpowi_s32_s32_flags
     ; GFX9: liveins: $vgpr0, $vgpr1
     ; GFX9-NEXT: {{  $}}
     ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
     ; GFX9-NEXT: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[COPY1]](s32)
-    ; GFX9-NEXT: [[FLOG2_:%[0-9]+]]:_(s32) = nnan G_FLOG2 [[COPY]]
-    ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_]](s32), [[SITOFP]](s32)
-    ; GFX9-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = nnan G_FEXP2 [[INT]]
+    ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+    ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(s32) = nnan G_FABS [[COPY]]
+    ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C]]
+    ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+    ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+    ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
+    ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[SELECT]]
+    ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32)
+    ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01
+    ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+    ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
+    ; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(s32) = nnan G_FSUB [[INT]], [[SELECT1]]
+    ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB]](s32), [[SITOFP]](s32)
+    ; GFX9-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = nnan G_FEXP2 [[INT1]]
     ; GFX9-NEXT: $vgpr0 = COPY [[FEXP2_]](s32)
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = COPY $vgpr1
     %2:_(s32) = nnan G_FPOWI %0, %1
     $vgpr0 = COPY %2
 ...

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll

; GFX8-NEXT:    s_setpc_b64 s[30:31]
   %res.cast = bitcast half %res to i16
   ret i16 %res.cast
 }
 
 define float @v_powi_f32(float %l, i32 %r) {
 ; GCN-LABEL: v_powi_f32:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v1
+; GCN-NEXT:    v_mov_b32_e32 v2, 0x800000
+; GCN-NEXT:    v_mov_b32_e32 v3, 0x4f800000
+; GCN-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v2
+; GCN-NEXT:    v_cndmask_b32_e32 v2, 1.0, v3, vcc
+; GCN-NEXT:    v_mul_f32_e32 v0, v0, v2
 ; GCN-NEXT:    v_log_f32_e32 v0, v0
+; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v1
+; GCN-NEXT:    v_mov_b32_e32 v2, 0x42000000
+; GCN-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
+; GCN-NEXT:    v_sub_f32_e32 v0, v0, v2
 ; GCN-NEXT:    v_mul_legacy_f32_e32 v0, v0, v1
 ; GCN-NEXT:    v_exp_f32_e32 v0, v0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
   %res = call float @llvm.powi.f32.i32(float %l, i32 %r)
   ret float %res
 }
 
 define float @v_powi_0_f32(float %l) {
; GCN-NEXT:    s_setpc_b64 s[30:31]
   %res = call float @llvm.powi.f32.i32(float %l, i32 1)
   ret float %res
 }
 
 define float @v_powi_neg1_f32(float %l) {
 ; GCN-LABEL: v_powi_neg1_f32:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, v0
+; GCN-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v1
+; GCN-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GCN-NEXT:    v_log_f32_e32 v0, v0
+; GCN-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; GCN-NEXT:    v_mul_legacy_f32_e32 v0, -1.0, v0
 ; GCN-NEXT:    v_exp_f32_e32 v0, v0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
   %res = call float @llvm.powi.f32.i32(float %l, i32 -1)
   ret float %res
 }
 
 define float @v_powi_2_f32(float %l) {
 ; GCN-LABEL: v_powi_2_f32:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, v0
+; GCN-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v1
+; GCN-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GCN-NEXT:    v_log_f32_e32 v0, v0
+; GCN-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; GCN-NEXT:    v_mul_legacy_f32_e32 v0, 2.0, v0
 ; GCN-NEXT:    v_exp_f32_e32 v0, v0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
   %res = call float @llvm.powi.f32.i32(float %l, i32 2)
   ret float %res
 }
 
 define float @v_powi_neg2_f32(float %l) {
 ; GCN-LABEL: v_powi_neg2_f32:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, v0
+; GCN-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v1
+; GCN-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GCN-NEXT:    v_log_f32_e32 v0, v0
+; GCN-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; GCN-NEXT:    v_mul_legacy_f32_e32 v0, -2.0, v0
 ; GCN-NEXT:    v_exp_f32_e32 v0, v0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
   %res = call float @llvm.powi.f32.i32(float %l, i32 -2)
   ret float %res
 }
 
 define float @v_powi_4_f32(float %l) {
 ; GCN-LABEL: v_powi_4_f32:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, v0
+; GCN-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v1
+; GCN-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GCN-NEXT:    v_log_f32_e32 v0, v0
+; GCN-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; GCN-NEXT:    v_mul_legacy_f32_e32 v0, 4.0, v0
 ; GCN-NEXT:    v_exp_f32_e32 v0, v0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
   %res = call float @llvm.powi.f32.i32(float %l, i32 4)
   ret float %res
 }
 
 define float @v_powi_8_f32(float %l) {
 ; GCN-LABEL: v_powi_8_f32:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, v0
+; GCN-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v1
+; GCN-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GCN-NEXT:    v_log_f32_e32 v0, v0
+; GCN-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; GCN-NEXT:    v_mul_legacy_f32_e32 v0, 0x41000000, v0
 ; GCN-NEXT:    v_exp_f32_e32 v0, v0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
   %res = call float @llvm.powi.f32.i32(float %l, i32 8)
   ret float %res
 }
 
 define float @v_powi_16_f32(float %l) {
 ; GCN-LABEL: v_powi_16_f32:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, v0
+; GCN-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v1
+; GCN-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GCN-NEXT:    v_log_f32_e32 v0, v0
+; GCN-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; GCN-NEXT:    v_mul_legacy_f32_e32 v0, 0x41800000, v0
 ; GCN-NEXT:    v_exp_f32_e32 v0, v0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
   %res = call float @llvm.powi.f32.i32(float %l, i32 16)
   ret float %res
 }
 
 define float @v_powi_128_f32(float %l) {
 ; GCN-LABEL: v_powi_128_f32:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, v0
+; GCN-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v1
+; GCN-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GCN-NEXT:    v_log_f32_e32 v0, v0
+; GCN-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; GCN-NEXT:    v_mul_legacy_f32_e32 v0, 0x43000000, v0
 ; GCN-NEXT:    v_exp_f32_e32 v0, v0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
   %res = call float @llvm.powi.f32.i32(float %l, i32 128)
   ret float %res
 }
 
 define float @v_powi_neg128_f32(float %l) {
 ; GCN-LABEL: v_powi_neg128_f32:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, v0
+; GCN-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v1
+; GCN-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GCN-NEXT:    v_log_f32_e32 v0, v0
+; GCN-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; GCN-NEXT:    v_mul_legacy_f32_e32 v0, 0xc3000000, v0
 ; GCN-NEXT:    v_exp_f32_e32 v0, v0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
   %res = call float @llvm.powi.f32.i32(float %l, i32 -128)
   ret float %res
 }
 
 ; FIXME: f64 broken

llvm/test/CodeGen/AMDGPU/llvm.log.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc -global-isel=0 -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,SI,GCN-SDAG,SI-SDAG %s
 ; RUN: llc -global-isel=1 -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,SI,GCN-GISEL,SI-GISEL %s
 ; RUN: llc -global-isel=0 -march=amdgcn -mcpu=tonga < %s | FileCheck  -check-prefixes=GCN,VI,GCN-SDAG,VI-SDAG %s
 ; RUN: llc -global-isel=1 -march=amdgcn -mcpu=tonga < %s | FileCheck  -check-prefixes=GCN,VI,GCN-GISEL,VI-GISEL %s
 ; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX900,GCN-SDAG,GFX900-SDAG %s
 ; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX900,GCN-GISEL,GFX900-GISEL %s
 
 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s
 ; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s
 
 define amdgpu_kernel void @s_log_f32(ptr addrspace(1) %out, float %in) {
-; SI-LABEL: s_log_f32:
-; SI:       ; %bb.0:
-; SI-NEXT:    s_load_dword s2, s[0:1], 0xb
-; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; SI-NEXT:    s_mov_b32 s3, 0xf000
-; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    v_log_f32_e32 v0, s2
-; SI-NEXT:    s_mov_b32 s2, -1
-; SI-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
-; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
-; SI-NEXT:    s_endpgm
+; SI-SDAG-LABEL: s_log_f32:
+; SI-SDAG:       ; %bb.0:
+; SI-SDAG-NEXT:    s_load_dword s2, s[0:1], 0xb
+; SI-SDAG-NEXT:    v_mov_b32_e32 v0, 0x800000
+; SI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; SI-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SI-SDAG-NEXT:    s_mov_b32 s3, 0xf000
+; SI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
+; SI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s2, v0
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; SI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x4f800000
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
+; SI-SDAG-NEXT:    v_mul_f32_e32 v1, s2, v1
+; SI-SDAG-NEXT:    v_log_f32_e32 v1, v1
+; SI-SDAG-NEXT:    s_mov_b32 s2, -1
+; SI-SDAG-NEXT:    v_sub_f32_e32 v0, v1, v0
+; SI-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; SI-SDAG-NEXT:    buffer_store_dword v0, off, s[0:3], 0
+; SI-SDAG-NEXT:    s_endpgm
 ;
-; VI-LABEL: s_log_f32:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
-; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_log_f32_e32 v0, s2
-; VI-NEXT:    v_mul_f32_e32 v2, 0x3f317218, v0
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    flat_store_dword v[0:1], v2
-; VI-NEXT:    s_endpgm
+; SI-GISEL-LABEL: s_log_f32:
+; SI-GISEL:       ; %bb.0:
+; SI-GISEL-NEXT:    s_load_dword s2, s[0:1], 0xb
+; SI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SI-GISEL-NEXT:    v_mov_b32_e32 v0, 0x800000
+; SI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x4f800000
+; SI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, s2, v0
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v0, 1.0, v1, vcc
+; SI-GISEL-NEXT:    v_mul_f32_e32 v0, s2, v0
+; SI-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT:    s_mov_b32 s2, -1
+; SI-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; SI-GISEL-NEXT:    buffer_store_dword v0, off, s[0:3], 0
+; SI-GISEL-NEXT:    s_endpgm
+;
+; VI-SDAG-LABEL: s_log_f32:
+; VI-SDAG:       ; %bb.0:
+; VI-SDAG-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; VI-SDAG-NEXT:    v_mov_b32_e32 v0, 0x800000
+; VI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; VI-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; VI-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; VI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
+; VI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s2, v0
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, s2, v1
+; VI-SDAG-NEXT:    v_log_f32_e32 v1, v1
+; VI-SDAG-NEXT:    v_sub_f32_e32 v0, v1, v0
+; VI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3f317218, v0
+; VI-SDAG-NEXT:    v_mov_b32_e32 v0, s0
+; VI-SDAG-NEXT:    v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT:    flat_store_dword v[0:1], v2
+; VI-SDAG-NEXT:    s_endpgm
+;
+; VI-GISEL-LABEL: s_log_f32:
+; VI-GISEL:       ; %bb.0:
+; VI-GISEL-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; VI-GISEL-NEXT:    v_mov_b32_e32 v0, 0x800000
+; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x4f800000
+; VI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, s2, v0
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, 1.0, v1, vcc
+; VI-GISEL-NEXT:    v_mul_f32_e32 v0, s2, v0
+; VI-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT:    v_mul_f32_e32 v2, 0x3f317218, v0
+; VI-GISEL-NEXT:    v_mov_b32_e32 v0, s0
+; VI-GISEL-NEXT:    v_mov_b32_e32 v1, s1
+; VI-GISEL-NEXT:    flat_store_dword v[0:1], v2
+; VI-GISEL-NEXT:    s_endpgm
 ;
 ; GFX900-SDAG-LABEL: s_log_f32:
 ; GFX900-SDAG:       ; %bb.0:
-; GFX900-SDAG-NEXT:    s_load_dword s4, s[0:1], 0x2c
-; GFX900-SDAG-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
-; GFX900-SDAG-NEXT:    v_mov_b32_e32 v1, 0
+; GFX900-SDAG-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v0, 0x800000
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GFX900-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX900-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX900-SDAG-NEXT:    v_log_f32_e32 v0, s4
+; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v1, 0x4f800000
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, s2, v1
+; GFX900-SDAG-NEXT:    v_log_f32_e32 v1, v1
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v0, v1, v0
 ; GFX900-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
-; GFX900-SDAG-NEXT:    global_store_dword v1, v0, s[2:3]
+; GFX900-SDAG-NEXT:    global_store_dword v2, v0, s[0:1]
 ; GFX900-SDAG-NEXT:    s_endpgm
 ;
 ; GFX900-GISEL-LABEL: s_log_f32:
 ; GFX900-GISEL:       ; %bb.0:
 ; GFX900-GISEL-NEXT:    s_load_dword s2, s[0:1], 0x2c
-; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v0, 0x800000
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; GFX900-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX900-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX900-GISEL-NEXT:    v_log_f32_e32 v0, s2
+; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v0, 1.0, v1, vcc
+; GFX900-GISEL-NEXT:    v_mul_f32_e32 v0, s2, v0
+; GFX900-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX900-GISEL-NEXT:    global_store_dword v1, v0, s[0:1]
 ; GFX900-GISEL-NEXT:    s_endpgm
 ;
 ; R600-LABEL: s_log_f32:
 ; R600:       ; %bb.0:
-; R600-NEXT:    ALU 3, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT:    ALU 11, @4, KC0[CB0:0-32], KC1[]
 ; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ; R600-NEXT:    ALU clause starting at 4:
-; R600-NEXT:     LOG_IEEE * T0.X, KC0[2].Z,
-; R600-NEXT:     MUL_IEEE T0.X, PS, literal.x,
+; R600-NEXT:     SETGT * T0.W, literal.x, KC0[2].Z,
+; R600-NEXT:    8388608(1.175494e-38), 0(0.000000e+00)
+; R600-NEXT:     CNDE * T1.W, PV.W, 1.0, literal.x,
+; R600-NEXT:    1333788672(4.294967e+09), 0(0.000000e+00)
+; R600-NEXT:     MUL_IEEE T1.W, KC0[2].Z, PV.W,
+; R600-NEXT:     CNDE * T0.W, T0.W, 0.0, literal.x,
+; R600-NEXT:    1107296256(3.200000e+01), 0(0.000000e+00)
+; R600-NEXT:     LOG_IEEE * T0.X, PV.W,
+; R600-NEXT:     ADD * T0.W, PS, -T0.W,
+; R600-NEXT:     MUL_IEEE T0.X, PV.W, literal.x,
 ; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.y,
 ; R600-NEXT:    1060205080(6.931472e-01), 2(2.802597e-45)
 ;
 ; CM-LABEL: s_log_f32:
 ; CM:       ; %bb.0:
-; CM-NEXT:    ALU 7, @4, KC0[CB0:0-32], KC1[]
+; CM-NEXT:    ALU 15, @4, KC0[CB0:0-32], KC1[]
 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
 ; CM-NEXT:    ALU clause starting at 4:
-; CM-NEXT:     LOG_IEEE T0.X, KC0[2].Z,
-; CM-NEXT:     LOG_IEEE T0.Y (MASKED), KC0[2].Z,
-; CM-NEXT:     LOG_IEEE T0.Z (MASKED), KC0[2].Z,
-; CM-NEXT:     LOG_IEEE * T0.W (MASKED), KC0[2].Z,
-; CM-NEXT:     MUL_IEEE * T0.X, PV.X, literal.x,
+; CM-NEXT:     SETGT * T0.W, literal.x, KC0[2].Z,
+; CM-NEXT:    8388608(1.175494e-38), 0(0.000000e+00)
+; CM-NEXT:     CNDE * T1.W, PV.W, 1.0, literal.x,
+; CM-NEXT:    1333788672(4.294967e+09), 0(0.000000e+00)
+; CM-NEXT:     CNDE T0.Z, T0.W, 0.0, literal.x,
+; CM-NEXT:     MUL_IEEE * T0.W, KC0[2].Z, PV.W,
+; CM-NEXT:    1107296256(3.200000e+01), 0(0.000000e+00)
+; CM-NEXT:     LOG_IEEE T0.X, T0.W,
+; CM-NEXT:     LOG_IEEE T0.Y (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE T0.Z (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE * T0.W (MASKED), T0.W,
+; CM-NEXT:     ADD * T0.W, PV.X, -T0.Z,
+; CM-NEXT:     MUL_IEEE * T0.X, PV.W, literal.x,
 ; CM-NEXT:    1060205080(6.931472e-01), 0(0.000000e+00)
 ; CM-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
   %result = call float @llvm.log.f32(float %in)
   store float %result, ptr addrspace(1) %out
   ret void
 }
 
 ; FIXME: We should be able to merge these packets together on Cayman so we
 ; have a maximum of 4 instructions.
 define amdgpu_kernel void @s_log_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
 ; SI-SDAG-LABEL: s_log_v2f32:
 ; SI-SDAG:       ; %bb.0:
 ; SI-SDAG-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; SI-SDAG-NEXT:    v_mov_b32_e32 v0, 0x800000
+; SI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; SI-SDAG-NEXT:    v_mov_b32_e32 v3, 0x4f800000
 ; SI-SDAG-NEXT:    s_mov_b32 s7, 0xf000
-; SI-SDAG-NEXT:    s_mov_b32 s6, -1
 ; SI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-SDAG-NEXT:    v_log_f32_e32 v0, s3
-; SI-SDAG-NEXT:    v_log_f32_e32 v2, s2
+; SI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s3, v0
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v2, 0, v1, vcc
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v4, 1.0, v3, vcc
+; SI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s2, v0
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v3, vcc
+; SI-SDAG-NEXT:    v_mul_f32_e32 v4, s3, v4
+; SI-SDAG-NEXT:    v_mul_f32_e32 v1, s2, v1
+; SI-SDAG-NEXT:    v_log_f32_e32 v4, v4
+; SI-SDAG-NEXT:    v_log_f32_e32 v3, v1
+; SI-SDAG-NEXT:    s_mov_b32 s6, -1
 ; SI-SDAG-NEXT:    s_mov_b32 s4, s0
+; SI-SDAG-NEXT:    v_sub_f32_e32 v1, v4, v2
+; SI-SDAG-NEXT:    v_sub_f32_e32 v0, v3, v0
 ; SI-SDAG-NEXT:    s_mov_b32 s5, s1
-; SI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317218, v0
-; SI-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v2
+; SI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317218, v1
+; SI-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
 ; SI-SDAG-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; SI-SDAG-NEXT:    s_endpgm
 ;
 ; SI-GISEL-LABEL: s_log_v2f32:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; SI-GISEL-NEXT:    s_mov_b32 s4, 0x800000
+; SI-GISEL-NEXT:    v_mov_b32_e32 v0, 0x4f800000
+; SI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
 ; SI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-GISEL-NEXT:    v_log_f32_e32 v0, s2
-; SI-GISEL-NEXT:    v_log_f32_e32 v1, s3
+; SI-GISEL-NEXT:    v_mov_b32_e32 v2, s2
+; SI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v2
+; SI-GISEL-NEXT:    v_mov_b32_e32 v4, s3
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v2, 1.0, v0, vcc
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v3, 0, v1, vcc
+; SI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v4
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v0, 1.0, v0, vcc
+; SI-GISEL-NEXT:    v_mul_f32_e32 v2, s2, v2
+; SI-GISEL-NEXT:    v_mul_f32_e32 v0, s3, v0
+; SI-GISEL-NEXT:    v_log_f32_e32 v2, v2
+; SI-GISEL-NEXT:    v_log_f32_e32 v4, v0
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; SI-GISEL-NEXT:    s_mov_b32 s2, -1
-; SI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT:    v_sub_f32_e32 v0, v2, v3
+; SI-GISEL-NEXT:    v_sub_f32_e32 v1, v4, v1
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3f317218, v1
+; SI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
 ; SI-GISEL-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; SI-GISEL-NEXT:    s_endpgm
 ;
 ; VI-SDAG-LABEL: s_log_v2f32:
 ; VI-SDAG:       ; %bb.0:
 ; VI-SDAG-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; VI-SDAG-NEXT:    v_mov_b32_e32 v0, 0x800000
+; VI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; VI-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
 ; VI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT:    v_log_f32_e32 v0, s3
-; VI-SDAG-NEXT:    v_log_f32_e32 v2, s2
-; VI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317218, v0
-; VI-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v2
+; VI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s3, v0
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v3, 0, v1, vcc
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v4, 1.0, v2, vcc
+; VI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s2, v0
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; VI-SDAG-NEXT:    v_mul_f32_e32 v4, s3, v4
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, s2, v1
+; VI-SDAG-NEXT:    v_log_f32_e32 v4, v4
+; VI-SDAG-NEXT:    v_log_f32_e32 v2, v1
+; VI-SDAG-NEXT:    v_sub_f32_e32 v1, v4, v3
+; VI-SDAG-NEXT:    v_sub_f32_e32 v0, v2, v0
 ; VI-SDAG-NEXT:    v_mov_b32_e32 v3, s1
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317218, v1
+; VI-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
 ; VI-SDAG-NEXT:    v_mov_b32_e32 v2, s0
 ; VI-SDAG-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
 ; VI-SDAG-NEXT:    s_endpgm
 ;
 ; VI-GISEL-LABEL: s_log_v2f32:
 ; VI-GISEL:       ; %bb.0:
 ; VI-GISEL-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; VI-GISEL-NEXT:    s_mov_b32 s4, 0x800000
+; VI-GISEL-NEXT:    v_mov_b32_e32 v0, 0x4f800000
+; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
 ; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT:    v_log_f32_e32 v0, s2
-; VI-GISEL-NEXT:    v_log_f32_e32 v1, s3
+; VI-GISEL-NEXT:    v_mov_b32_e32 v2, s2
+; VI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v2
+; VI-GISEL-NEXT:    v_mov_b32_e32 v4, s3
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v2, 1.0, v0, vcc
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v3, 0, v1, vcc
+; VI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v4
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, 1.0, v0, vcc
+; VI-GISEL-NEXT:    v_mul_f32_e32 v2, s2, v2
+; VI-GISEL-NEXT:    v_mul_f32_e32 v0, s3, v0
+; VI-GISEL-NEXT:    v_log_f32_e32 v2, v2
+; VI-GISEL-NEXT:    v_log_f32_e32 v4, v0
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT:    v_sub_f32_e32 v0, v2, v3
+; VI-GISEL-NEXT:    v_sub_f32_e32 v1, v4, v1
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT:    v_mov_b32_e32 v2, s0
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3f317218, v1
+; VI-GISEL-NEXT:    v_mov_b32_e32 v2, s0
 ; VI-GISEL-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
 ; VI-GISEL-NEXT:    s_endpgm
 ;
 ; GFX900-SDAG-LABEL: s_log_v2f32:
 ; GFX900-SDAG:       ; %bb.0:
 ; GFX900-SDAG-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
-; GFX900-SDAG-NEXT:    v_mov_b32_e32 v3, 0
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v0, 0x800000
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v5, 0
 ; GFX900-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX900-SDAG-NEXT:    v_log_f32_e32 v0, s3
-; GFX900-SDAG-NEXT:    v_log_f32_e32 v2, s2
-; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317218, v0
-; GFX900-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v2
-; GFX900-SDAG-NEXT:    global_store_dwordx2 v3, v[0:1], s[0:1]
+; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s3, v0
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v3, 0, v1, vcc
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v4, 1.0, v2, vcc
+; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v4, s3, v4
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, s2, v1
+; GFX900-SDAG-NEXT:    v_log_f32_e32 v4, v4
+; GFX900-SDAG-NEXT:    v_log_f32_e32 v2, v1
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v1, v4, v3
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v0, v2, v0
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317218, v1
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; GFX900-SDAG-NEXT:    global_store_dwordx2 v5, v[0:1], s[0:1]
 ; GFX900-SDAG-NEXT:    s_endpgm
 ;
 ; GFX900-GISEL-LABEL: s_log_v2f32:
 ; GFX900-GISEL:       ; %bb.0:
 ; GFX900-GISEL-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
-; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0
+; GFX900-GISEL-NEXT:    s_mov_b32 s4, 0x800000
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v0, 0x4f800000
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
 ; GFX900-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX900-GISEL-NEXT:    v_log_f32_e32 v0, s2
-; GFX900-GISEL-NEXT:    v_log_f32_e32 v1, s3
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, s2
+; GFX900-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v2
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v4, s3
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v2, 1.0, v0, vcc
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v3, 0, v1, vcc
+; GFX900-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v4
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v0, 1.0, v0, vcc
+; GFX900-GISEL-NEXT:    v_mul_f32_e32 v2, s2, v2
+; GFX900-GISEL-NEXT:    v_mul_f32_e32 v0, s3, v0
+; GFX900-GISEL-NEXT:    v_log_f32_e32 v2, v2
+; GFX900-GISEL-NEXT:    v_log_f32_e32 v4, v0
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v0, v2, v3
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v1, v4, v1
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3f317218, v1
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX900-GISEL-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
 ; GFX900-GISEL-NEXT:    s_endpgm
 ;
 ; R600-LABEL: s_log_v2f32:
 ; R600:       ; %bb.0:
-; R600-NEXT:    ALU 6, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT:    ALU 21, @4, KC0[CB0:0-32], KC1[]
 ; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ; R600-NEXT:    ALU clause starting at 4:
-; R600-NEXT:     LOG_IEEE * T0.X, KC0[3].X,
-; R600-NEXT:     MUL_IEEE T0.Y, PS, literal.x,
-; R600-NEXT:     LOG_IEEE * T0.X, KC0[2].W,
+; R600-NEXT:     SETGT T0.W, literal.x, KC0[3].X,
+; R600-NEXT:     SETGT * T1.W, literal.x, KC0[2].W,
+; R600-NEXT:    8388608(1.175494e-38), 0(0.000000e+00)
+; R600-NEXT:     CNDE * T2.W, PV.W, 1.0, literal.x,
+; R600-NEXT:    1333788672(4.294967e+09), 0(0.000000e+00)
+; R600-NEXT:     MUL_IEEE T2.W, KC0[3].X, PV.W,
+; R600-NEXT:     CNDE * T3.W, T1.W, 1.0, literal.x,
+; R600-NEXT:    1333788672(4.294967e+09), 0(0.000000e+00)
+; R600-NEXT:     MUL_IEEE T0.Z, KC0[2].W, PS,
+; R600-NEXT:     CNDE T0.W, T0.W, 0.0, literal.x,
+; R600-NEXT:     LOG_IEEE * T0.X, PV.W,
+; R600-NEXT:    1107296256(3.200000e+01), 0(0.000000e+00)
+; R600-NEXT:     CNDE T1.Z, T1.W, 0.0, literal.x,
+; R600-NEXT:     ADD T0.W, PS, -PV.W,
+; R600-NEXT:     LOG_IEEE * T0.X, PV.Z,
+; R600-NEXT:    1107296256(3.200000e+01), 0(0.000000e+00)
+; R600-NEXT:     MUL_IEEE T0.Y, PV.W, literal.x,
+; R600-NEXT:     ADD * T0.W, PS, -PV.Z,
 ; R600-NEXT:    1060205080(6.931472e-01), 0(0.000000e+00)
-; R600-NEXT:     MUL_IEEE T0.X, PS, literal.x,
+; R600-NEXT:     MUL_IEEE T0.X, PV.W, literal.x,
 ; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.y,
 ; R600-NEXT:    1060205080(6.931472e-01), 2(2.802597e-45)
 ;
 ; CM-LABEL: s_log_v2f32:
 ; CM:       ; %bb.0:
-; CM-NEXT:    ALU 13, @4, KC0[CB0:0-32], KC1[]
+; CM-NEXT:    ALU 27, @4, KC0[CB0:0-32], KC1[]
 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0, T1.X
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
 ; CM-NEXT:    ALU clause starting at 4:
-; CM-NEXT:     LOG_IEEE T0.X, KC0[3].X,
-; CM-NEXT:     LOG_IEEE T0.Y (MASKED), KC0[3].X,
-; CM-NEXT:     LOG_IEEE T0.Z (MASKED), KC0[3].X,
-; CM-NEXT:     LOG_IEEE * T0.W (MASKED), KC0[3].X,
-; CM-NEXT:     MUL_IEEE * T0.Y, PV.X, literal.x,
+; CM-NEXT:     SETGT * T0.W, literal.x, KC0[3].X,
+; CM-NEXT:    8388608(1.175494e-38), 0(0.000000e+00)
+; CM-NEXT:     CNDE T0.Z, PV.W, 1.0, literal.x,
+; CM-NEXT:     SETGT * T1.W, literal.y, KC0[2].W,
+; CM-NEXT:    1333788672(4.294967e+09), 8388608(1.175494e-38)
+; CM-NEXT:     CNDE T0.Y, PV.W, 1.0, literal.x,
+; CM-NEXT:     CNDE T1.Z, T0.W, 0.0, literal.y,
+; CM-NEXT:     MUL_IEEE * T0.W, KC0[3].X, PV.Z,
+; CM-NEXT:    1333788672(4.294967e+09), 1107296256(3.200000e+01)
+; CM-NEXT:     LOG_IEEE T0.X, T0.W,
+; CM-NEXT:     LOG_IEEE T0.Y (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE T0.Z (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE * T0.W (MASKED), T0.W,
+; CM-NEXT:     CNDE T1.Y, T1.W, 0.0, literal.x,
+; CM-NEXT:     ADD T0.Z, PV.X, -T1.Z,
+; CM-NEXT:     MUL_IEEE * T0.W, KC0[2].W, T0.Y,
+; CM-NEXT:    1107296256(3.200000e+01), 0(0.000000e+00)
+; CM-NEXT:     LOG_IEEE T0.X, T0.W,
+; CM-NEXT:     LOG_IEEE T0.Y (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE T0.Z (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE * T0.W (MASKED), T0.W,
+; CM-NEXT:     MUL_IEEE T0.Y, T0.Z, literal.x,
+; CM-NEXT:     ADD * T0.W, PV.X, -T1.Y,
 ; CM-NEXT:    1060205080(6.931472e-01), 0(0.000000e+00)
-; CM-NEXT:     LOG_IEEE T0.X, KC0[2].W,
-; CM-NEXT:     LOG_IEEE T0.Y (MASKED), KC0[2].W,
-; CM-NEXT:     LOG_IEEE T0.Z (MASKED), KC0[2].W,
-; CM-NEXT:     LOG_IEEE * T0.W (MASKED), KC0[2].W,
-; CM-NEXT:     MUL_IEEE * T0.X, PV.X, literal.x,
+; CM-NEXT:     MUL_IEEE * T0.X, PV.W, literal.x,
 ; CM-NEXT:    1060205080(6.931472e-01), 0(0.000000e+00)
 ; CM-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
   %result = call <2 x float> @llvm.log.v2f32(<2 x float> %in)
   store <2 x float> %result, ptr addrspace(1) %out
   ret void
 }
 
 define amdgpu_kernel void @s_log_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
 ; SI-SDAG-LABEL: s_log_v3f32:
 ; SI-SDAG:       ; %bb.0:
 ; SI-SDAG-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xd
+; SI-SDAG-NEXT:    v_mov_b32_e32 v0, 0x800000
+; SI-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; SI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
 ; SI-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
+; SI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s5, v0
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v4, 1.0, v2, vcc
+; SI-SDAG-NEXT:    v_mul_f32_e32 v4, s5, v4
+; SI-SDAG-NEXT:    v_log_f32_e32 v4, v4
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v3, 0, v1, vcc
+; SI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v5, 1.0, v2, vcc
+; SI-SDAG-NEXT:    v_sub_f32_e32 v3, v4, v3
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v4, 0, v1, vcc
+; SI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s6, v0
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v0, 1.0, v2, vcc
+; SI-SDAG-NEXT:    v_mul_f32_e32 v0, s6, v0
+; SI-SDAG-NEXT:    v_mul_f32_e32 v5, s4, v5
+; SI-SDAG-NEXT:    v_log_f32_e32 v2, v0
+; SI-SDAG-NEXT:    v_log_f32_e32 v5, v5
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v6, 0, v1, vcc
 ; SI-SDAG-NEXT:    s_mov_b32 s3, 0xf000
+; SI-SDAG-NEXT:    v_sub_f32_e32 v2, v2, v6
 ; SI-SDAG-NEXT:    s_mov_b32 s2, -1
-; SI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-SDAG-NEXT:    v_log_f32_e32 v0, s5
-; SI-SDAG-NEXT:    v_log_f32_e32 v2, s4
-; SI-SDAG-NEXT:    v_log_f32_e32 v3, s6
-; SI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317218, v0
-; SI-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v2
-; SI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3f317218, v3
+; SI-SDAG-NEXT:    v_sub_f32_e32 v0, v5, v4
+; SI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3f317218, v2
+; SI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317218, v3
+; SI-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
 ; SI-SDAG-NEXT:    buffer_store_dword v2, off, s[0:3], 0 offset:8
 ; SI-SDAG-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; SI-SDAG-NEXT:    s_endpgm
 ;
 ; SI-GISEL-LABEL: s_log_v3f32:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xd
 ; SI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; SI-GISEL-NEXT:    s_mov_b32 s2, -1
-; SI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT:    s_mov_b32 s2, 0x800000
+; SI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x4f800000
+; SI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x42000000
 ; SI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-GISEL-NEXT:    v_log_f32_e32 v0, s4
-; SI-GISEL-NEXT:    v_log_f32_e32 v1, s5
-; SI-GISEL-NEXT:    v_log_f32_e32 v2, s6
+; SI-GISEL-NEXT:    v_mov_b32_e32 v0, s4
+; SI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s2, v0
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v0, 1.0, v1, vcc
+; SI-GISEL-NEXT:    v_mul_f32_e32 v0, s4, v0
+; SI-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v4, 0, v3, vcc
+; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x800000
+; SI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v4
+; SI-GISEL-NEXT:    v_mov_b32_e32 v4, s5
+; SI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s2, v4
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v4, 1.0, v1, vcc
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v5, 0, v3, vcc
+; SI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, s6, v2
+; SI-GISEL-NEXT:    v_mul_f32_e32 v4, s5, v4
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
+; SI-GISEL-NEXT:    v_log_f32_e32 v4, v4
+; SI-GISEL-NEXT:    v_mul_f32_e32 v1, s6, v1
+; SI-GISEL-NEXT:    v_log_f32_e32 v2, v1
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v3, 0, v3, vcc
+; SI-GISEL-NEXT:    v_sub_f32_e32 v1, v4, v5
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3f317218, v1
+; SI-GISEL-NEXT:    v_sub_f32_e32 v2, v2, v3
+; SI-GISEL-NEXT:    s_mov_b32 s2, -1
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v2, 0x3f317218, v2
 ; SI-GISEL-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; SI-GISEL-NEXT:    buffer_store_dword v2, off, s[0:3], 0 offset:8
 ; SI-GISEL-NEXT:    s_endpgm
 ;
 ; VI-SDAG-LABEL: s_log_v3f32:
 ; VI-SDAG:       ; %bb.0:
 ; VI-SDAG-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
+; VI-SDAG-NEXT:    v_mov_b32_e32 v0, 0x800000
+; VI-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; VI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
 ; VI-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; VI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT:    v_log_f32_e32 v0, s6
-; VI-SDAG-NEXT:    v_log_f32_e32 v3, s4
-; VI-SDAG-NEXT:    v_log_f32_e32 v1, s5
-; VI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3f317218, v0
-; VI-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v3
+; VI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s6, v0
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v4, 1.0, v2, vcc
+; VI-SDAG-NEXT:    v_mul_f32_e32 v4, s6, v4
+; VI-SDAG-NEXT:    v_log_f32_e32 v4, v4
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v3, 0, v1, vcc
+; VI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s5, v0
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v5, 0, v1, vcc
+; VI-SDAG-NEXT:    v_sub_f32_e32 v3, v4, v3
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v4, 1.0, v2, vcc
+; VI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; VI-SDAG-NEXT:    v_mul_f32_e32 v4, s5, v4
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, s4, v1
+; VI-SDAG-NEXT:    v_log_f32_e32 v4, v4
+; VI-SDAG-NEXT:    v_log_f32_e32 v6, v1
+; VI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3f317218, v3
+; VI-SDAG-NEXT:    v_sub_f32_e32 v1, v4, v5
+; VI-SDAG-NEXT:    v_sub_f32_e32 v0, v6, v0
 ; VI-SDAG-NEXT:    v_mov_b32_e32 v4, s1
 ; VI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317218, v1
+; VI-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
 ; VI-SDAG-NEXT:    v_mov_b32_e32 v3, s0
 ; VI-SDAG-NEXT:    flat_store_dwordx3 v[3:4], v[0:2]
 ; VI-SDAG-NEXT:    s_endpgm
 ;
 ; VI-GISEL-LABEL: s_log_v3f32:
 ; VI-GISEL:       ; %bb.0:
 ; VI-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
 ; VI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; VI-GISEL-NEXT:    s_mov_b32 s2, 0x800000
+; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x4f800000
+; VI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x42000000
 ; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT:    v_log_f32_e32 v0, s4
-; VI-GISEL-NEXT:    v_log_f32_e32 v1, s5
-; VI-GISEL-NEXT:    v_log_f32_e32 v2, s6
-; VI-GISEL-NEXT:    v_mov_b32_e32 v4, s1
+; VI-GISEL-NEXT:    v_mov_b32_e32 v0, s4
+; VI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s2, v0
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, 1.0, v1, vcc
+; VI-GISEL-NEXT:    v_mul_f32_e32 v0, s4, v0
+; VI-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v4, 0, v3, vcc
+; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x800000
+; VI-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v4
+; VI-GISEL-NEXT:    v_mov_b32_e32 v4, s5
+; VI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s2, v4
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v4, 1.0, v1, vcc
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v5, 0, v3, vcc
+; VI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, s6, v2
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
+; VI-GISEL-NEXT:    v_mul_f32_e32 v4, s5, v4
+; VI-GISEL-NEXT:    v_mul_f32_e32 v1, s6, v1
+; VI-GISEL-NEXT:    v_log_f32_e32 v4, v4
+; VI-GISEL-NEXT:    v_log_f32_e32 v2, v1
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v3, 0, v3, vcc
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; VI-GISEL-NEXT:    v_sub_f32_e32 v1, v4, v5
+; VI-GISEL-NEXT:    v_sub_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT:    v_mov_b32_e32 v4, s1
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3f317218, v1
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v2, 0x3f317218, v2
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v3, s0
 ; VI-GISEL-NEXT:    flat_store_dwordx3 v[3:4], v[0:2]
 ; VI-GISEL-NEXT:    s_endpgm
 ;
 ; GFX900-SDAG-LABEL: s_log_v3f32:
 ; GFX900-SDAG:       ; %bb.0:
 ; GFX900-SDAG-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
-; GFX900-SDAG-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
-; GFX900-SDAG-NEXT:    v_mov_b32_e32 v4, 0
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v0, 0x800000
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GFX900-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX900-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX900-SDAG-NEXT:    v_log_f32_e32 v0, s6
-; GFX900-SDAG-NEXT:    v_log_f32_e32 v1, s5
-; GFX900-SDAG-NEXT:    v_log_f32_e32 v3, s4
-; GFX900-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3f317218, v0
+; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s6, v0
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v4, 1.0, v2, vcc
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v4, s6, v4
+; GFX900-SDAG-NEXT:    v_log_f32_e32 v4, v4
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v3, 0, v1, vcc
+; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s5, v0
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v6, 1.0, v2, vcc
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v3, v4, v3
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v4, 0, v1, vcc
+; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v6, s5, v6
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, s4, v1
+; GFX900-SDAG-NEXT:    v_log_f32_e32 v6, v6
+; GFX900-SDAG-NEXT:    v_log_f32_e32 v7, v1
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v5, 0
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3f317218, v3
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v1, v6, v4
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v0, v7, v0
 ; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317218, v1
-; GFX900-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v3
-; GFX900-SDAG-NEXT:    global_store_dwordx3 v4, v[0:2], s[2:3]
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; GFX900-SDAG-NEXT:    global_store_dwordx3 v5, v[0:2], s[0:1]
 ; GFX900-SDAG-NEXT:    s_endpgm
 ;
 ; GFX900-GISEL-LABEL: s_log_v3f32:
 ; GFX900-GISEL:       ; %bb.0:
 ; GFX900-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
-; GFX900-GISEL-NEXT:    v_mov_b32_e32 v3, 0
-; GFX900-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX900-GISEL-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX900-GISEL-NEXT:    s_mov_b32 s0, 0x800000
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0x4f800000
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v3, 0x42000000
 ; GFX900-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX900-GISEL-NEXT:    v_log_f32_e32 v0, s4
-; GFX900-GISEL-NEXT:    v_log_f32_e32 v1, s5
-; GFX900-GISEL-NEXT:    v_log_f32_e32 v2, s6
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v0, s4
+; GFX900-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s0, v0
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v0, 1.0, v1, vcc
+; GFX900-GISEL-NEXT:    v_mul_f32_e32 v0, s4, v0
+; GFX900-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v4, 0, v3, vcc
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x800000
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v4
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v4, s5
+; GFX900-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s0, v4
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v4, 1.0, v1, vcc
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v5, 0, v3, vcc
+; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, s6, v2
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
+; GFX900-GISEL-NEXT:    v_mul_f32_e32 v4, s5, v4
+; GFX900-GISEL-NEXT:    v_mul_f32_e32 v1, s6, v1
+; GFX900-GISEL-NEXT:    v_log_f32_e32 v4, v4
+; GFX900-GISEL-NEXT:    v_log_f32_e32 v2, v1
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v3, 0, v3, vcc
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v1, v4, v5
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v2, v2, v3
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3f317218, v1
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v2, 0x3f317218, v2
-; GFX900-GISEL-NEXT:    global_store_dwordx3 v3, v[0:2], s[0:1]
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v3, 0
+; GFX900-GISEL-NEXT:    global_store_dwordx3 v3, v[0:2], s[2:3]
 ; GFX900-GISEL-NEXT:    s_endpgm
 ;
 ; R600-LABEL: s_log_v3f32:
 ; R600:       ; %bb.0:
-; R600-NEXT:    ALU 13, @4, KC0[CB0:0-32], KC1[]
-; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T3.X, T2.X, 0
+; R600-NEXT:    ALU 33, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T2.X, T3.X, 0
 ; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    ALU clause starting at 4:
-; R600-NEXT:     LOG_IEEE * T0.X, KC0[3].Z,
-; R600-NEXT:     MUL_IEEE T0.Y, PS, literal.x,
-; R600-NEXT:     LOG_IEEE * T0.X, KC0[3].Y,
+; R600-NEXT:     SETGT T0.W, literal.x, KC0[3].Z,
+; R600-NEXT:     SETGT * T1.W, literal.x, KC0[3].Y,
+; R600-NEXT:    8388608(1.175494e-38), 0(0.000000e+00)
+; R600-NEXT:     CNDE * T2.W, PV.W, 1.0, literal.x,
+; R600-NEXT:    1333788672(4.294967e+09), 0(0.000000e+00)
+; R600-NEXT:     MUL_IEEE T2.W, KC0[3].Z, PV.W,
+; R600-NEXT:     CNDE * T3.W, T1.W, 1.0, literal.x,
+; R600-NEXT:    1333788672(4.294967e+09), 0(0.000000e+00)
+; R600-NEXT:     MUL_IEEE T0.Y, KC0[3].Y, PS,
+; R600-NEXT:     CNDE T0.Z, T0.W, 0.0, literal.x,
+; R600-NEXT:     SETGT T0.W, literal.y, KC0[3].W,
+; R600-NEXT:     LOG_IEEE * T0.X, PV.W,
+; R600-NEXT:    1107296256(3.200000e+01), 8388608(1.175494e-38)
+; R600-NEXT:     CNDE T1.Y, T1.W, 0.0, literal.x,
+; R600-NEXT:     CNDE T1.Z, PV.W, 1.0, literal.y,
+; R600-NEXT:     ADD T1.W, PS, -PV.Z,
+; R600-NEXT:     LOG_IEEE * T0.X, PV.Y,
+; R600-NEXT:    1107296256(3.200000e+01), 1333788672(4.294967e+09)
+; R600-NEXT:     MUL_IEEE T0.Y, PV.W, literal.x,
+; R600-NEXT:     MUL_IEEE T1.W, KC0[3].W, PV.Z,
+; R600-NEXT:     ADD * T2.W, PS, -PV.Y,
 ; R600-NEXT:    1060205080(6.931472e-01), 0(0.000000e+00)
 ; R600-NEXT:     MUL_IEEE T0.X, PS, literal.x,
-; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.y,
-; R600-NEXT:    1060205080(6.931472e-01), 2(2.802597e-45)
-; R600-NEXT:     ADD_INT * T0.W, KC0[2].Y, literal.x,
-; R600-NEXT:    8(1.121039e-44), 0(0.000000e+00)
-; R600-NEXT:     LSHR T2.X, PV.W, literal.x,
-; R600-NEXT:     LOG_IEEE * T0.Z, KC0[3].W,
+; R600-NEXT:     CNDE T0.W, T0.W, 0.0, literal.y,
+; R600-NEXT:     LOG_IEEE * T0.Z, PV.W,
+; R600-NEXT:    1060205080(6.931472e-01), 1107296256(3.200000e+01)
+; R600-NEXT:     LSHR T1.X, KC0[2].Y, literal.x,
+; R600-NEXT:     ADD * T0.W, PS, -PV.W,
+; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
+; R600-NEXT:     MUL_IEEE T2.X, PV.W, literal.x,
+; R600-NEXT:     ADD_INT * T0.W, KC0[2].Y, literal.y,
+; R600-NEXT:    1060205080(6.931472e-01), 8(1.121039e-44)
+; R600-NEXT:     LSHR * T3.X, PV.W, literal.x,
 ; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
-; R600-NEXT:     MUL_IEEE * T3.X, PS, literal.x,
-; R600-NEXT:    1060205080(6.931472e-01), 0(0.000000e+00)
 ;
 ; CM-LABEL: s_log_v3f32:
 ; CM:       ; %bb.0:
-; CM-NEXT:    ALU 22, @4, KC0[CB0:0-32], KC1[]
-; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T2, T3.X
-; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X
+; CM-NEXT:    ALU 40, @4, KC0[CB0:0-32], KC1[]
+; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0, T3.X
+; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T2.X, T1.X
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    ALU clause starting at 4:
-; CM-NEXT:     ADD_INT * T0.W, KC0[2].Y, literal.x,
-; CM-NEXT:    8(1.121039e-44), 0(0.000000e+00)
-; CM-NEXT:     LSHR * T0.X, PV.W, literal.x,
-; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
-; CM-NEXT:     LOG_IEEE T0.X (MASKED), KC0[3].Z,
-; CM-NEXT:     LOG_IEEE T0.Y, KC0[3].Z,
-; CM-NEXT:     LOG_IEEE T0.Z (MASKED), KC0[3].Z,
-; CM-NEXT:     LOG_IEEE * T0.W (MASKED), KC0[3].Z,
-; CM-NEXT:     LOG_IEEE T0.X (MASKED), KC0[3].W,
-; CM-NEXT:     LOG_IEEE T0.Y (MASKED), KC0[3].W,
-; CM-NEXT:     LOG_IEEE T0.Z, KC0[3].W,
-; CM-NEXT:     LOG_IEEE * T0.W (MASKED), KC0[3].W,
-; CM-NEXT:     MUL_IEEE T1.X, PV.Z, literal.x,
-; CM-NEXT:     MUL_IEEE * T2.Y, T0.Y, literal.x,
-; CM-NEXT:    1060205080(6.931472e-01), 0(0.000000e+00)
-; CM-NEXT:     LOG_IEEE T0.X (MASKED), KC0[3].Y,
-; CM-NEXT:     LOG_IEEE T0.Y, KC0[3].Y,
-; CM-NEXT:     LOG_IEEE T0.Z (MASKED), KC0[3].Y,
-; CM-NEXT:     LOG_IEEE * T0.W (MASKED), KC0[3].Y,
-; CM-NEXT:     MUL_IEEE * T2.X, PV.Y, literal.x,
+; CM-NEXT:     SETGT * T0.W, literal.x, KC0[3].W,
+; CM-NEXT:    8388608(1.175494e-38), 0(0.000000e+00)
+; CM-NEXT:     CNDE T0.Y, PV.W, 1.0, literal.x,
+; CM-NEXT:     SETGT T0.Z, literal.y, KC0[3].Z,
+; CM-NEXT:     SETGT * T1.W, literal.y, KC0[3].Y,
+; CM-NEXT:    1333788672(4.294967e+09), 8388608(1.175494e-38)
+; CM-NEXT:     CNDE T0.X, PV.W, 0.0, literal.x,
+; CM-NEXT:     CNDE T1.Y, PV.Z, 1.0, literal.y,
+; CM-NEXT:     CNDE T1.Z, T0.W, 0.0, literal.x,
+; CM-NEXT:     MUL_IEEE * T0.W, KC0[3].W, PV.Y,
+; CM-NEXT:    1107296256(3.200000e+01), 1333788672(4.294967e+09)
+; CM-NEXT:     LOG_IEEE T0.X (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE T0.Y, T0.W,
+; CM-NEXT:     LOG_IEEE T0.Z (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE * T0.W (MASKED), T0.W,
+; CM-NEXT:     CNDE T1.X, T1.W, 1.0, literal.x,
+; CM-NEXT:     CNDE T2.Y, T0.Z, 0.0, literal.y,
+; CM-NEXT:     ADD T0.Z, PV.Y, -T1.Z,
+; CM-NEXT:     MUL_IEEE * T0.W, KC0[3].Z, T1.Y,
+; CM-NEXT:    1333788672(4.294967e+09), 1107296256(3.200000e+01)
+; CM-NEXT:     LOG_IEEE T0.X (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE T0.Y, T0.W,
+; CM-NEXT:     LOG_IEEE T0.Z (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE * T0.W (MASKED), T0.W,
+; CM-NEXT:     MUL_IEEE T2.X, T0.Z, literal.x,
+; CM-NEXT:     ADD T0.Y, PV.Y, -T2.Y,
+; CM-NEXT:     ADD_INT T0.Z, KC0[2].Y, literal.y,
+; CM-NEXT:     MUL_IEEE * T0.W, KC0[3].Y, T1.X,
+; CM-NEXT:    1060205080(6.931472e-01), 8(1.121039e-44)
+; CM-NEXT:     LOG_IEEE T0.X (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE T0.Y (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE T0.Z (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE * T0.W, T0.W,
+; CM-NEXT:     LSHR T1.X, T0.Z, literal.x,
+; CM-NEXT:     MUL_IEEE T0.Y, T0.Y, literal.y,
+; CM-NEXT:     ADD * T0.W, PV.W, -T0.X,
+; CM-NEXT:    2(2.802597e-45), 1060205080(6.931472e-01)
+; CM-NEXT:     MUL_IEEE * T0.X, PV.W, literal.x,
 ; CM-NEXT:    1060205080(6.931472e-01), 0(0.000000e+00)
 ; CM-NEXT:     LSHR * T3.X, KC0[2].Y, literal.x,
 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
   %result = call <3 x float> @llvm.log.v3f32(<3 x float> %in)
   store <3 x float> %result, ptr addrspace(1) %out
   ret void
 }
 
 ; FIXME: We should be able to merge these packets together on Cayman so we
 ; have a maximum of 4 instructions.
 define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
 ; SI-SDAG-LABEL: s_log_v4f32:
 ; SI-SDAG:       ; %bb.0:
 ; SI-SDAG-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xd
 ; SI-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SI-SDAG-NEXT:    v_mov_b32_e32 v0, 0x800000
+; SI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; SI-SDAG-NEXT:    v_mov_b32_e32 v4, 0x4f800000
+; SI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
+; SI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s7, v0
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v2, 0, v1, vcc
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v3, 1.0, v4, vcc
+; SI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s6, v0
+; SI-SDAG-NEXT:    v_mul_f32_e32 v3, s7, v3
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v6, 1.0, v4, vcc
+; SI-SDAG-NEXT:    v_log_f32_e32 v3, v3
+; SI-SDAG-NEXT:    v_mul_f32_e32 v6, s6, v6
+; SI-SDAG-NEXT:    v_log_f32_e32 v6, v6
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v5, 0, v1, vcc
+; SI-SDAG-NEXT:    v_sub_f32_e32 v2, v3, v2
+; SI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s5, v0
+; SI-SDAG-NEXT:    v_mul_f32_e32 v3, 0x3f317218, v2
+; SI-SDAG-NEXT:    v_sub_f32_e32 v2, v6, v5
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v5, 0, v1, vcc
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v6, 1.0, v4, vcc
+; SI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v4, vcc
+; SI-SDAG-NEXT:    v_mul_f32_e32 v6, s5, v6
+; SI-SDAG-NEXT:    v_mul_f32_e32 v1, s4, v1
+; SI-SDAG-NEXT:    v_log_f32_e32 v6, v6
+; SI-SDAG-NEXT:    v_log_f32_e32 v4, v1
 ; SI-SDAG-NEXT:    s_mov_b32 s3, 0xf000
 ; SI-SDAG-NEXT:    s_mov_b32 s2, -1
-; SI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-SDAG-NEXT:    v_log_f32_e32 v0, s7
-; SI-SDAG-NEXT:    v_log_f32_e32 v1, s6
-; SI-SDAG-NEXT:    v_log_f32_e32 v4, s5
-; SI-SDAG-NEXT:    v_log_f32_e32 v5, s4
-; SI-SDAG-NEXT:    v_mul_f32_e32 v3, 0x3f317218, v0
-; SI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3f317218, v1
-; SI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317218, v4
-; SI-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v5
+; SI-SDAG-NEXT:    v_sub_f32_e32 v1, v6, v5
+; SI-SDAG-NEXT:    v_sub_f32_e32 v0, v4, v0
+; SI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3f317218, v2
+; SI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317218, v1
+; SI-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
 ; SI-SDAG-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
 ; SI-SDAG-NEXT:    s_endpgm
 ;
 ; SI-GISEL-LABEL: s_log_v4f32:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xd
 ; SI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; SI-GISEL-NEXT:    s_mov_b32 s2, -1
-; SI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT:    s_mov_b32 s2, 0x800000
+; SI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x4f800000
+; SI-GISEL-NEXT:    v_mov_b32_e32 v4, 0x42000000
 ; SI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-GISEL-NEXT:    v_log_f32_e32 v0, s4
-; SI-GISEL-NEXT:    v_log_f32_e32 v1, s5
-; SI-GISEL-NEXT:    v_log_f32_e32 v2, s6
-; SI-GISEL-NEXT:    v_log_f32_e32 v3, s7
+; SI-GISEL-NEXT:    v_mov_b32_e32 v0, s4
+; SI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s2, v0
+; SI-GISEL-NEXT:    v_mov_b32_e32 v5, s5
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v0, 1.0, v3, vcc
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v4, vcc
+; SI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s2, v5
+; SI-GISEL-NEXT:    v_mul_f32_e32 v0, s4, v0
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v5, 1.0, v3, vcc
+; SI-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT:    v_mul_f32_e32 v5, s5, v5
+; SI-GISEL-NEXT:    v_log_f32_e32 v5, v5
+; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x800000
+; SI-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v4, vcc
+; SI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, s6, v2
+; SI-GISEL-NEXT:    v_sub_f32_e32 v1, v5, v1
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v5, 1.0, v3, vcc
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v6, 0, v4, vcc
+; SI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, s7, v2
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v2, 1.0, v3, vcc
+; SI-GISEL-NEXT:    v_mul_f32_e32 v5, s6, v5
+; SI-GISEL-NEXT:    v_mul_f32_e32 v2, s7, v2
+; SI-GISEL-NEXT:    v_log_f32_e32 v5, v5
+; SI-GISEL-NEXT:    v_log_f32_e32 v3, v2
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v4, 0, v4, vcc
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; SI-GISEL-NEXT:    v_sub_f32_e32 v2, v5, v6
+; SI-GISEL-NEXT:    v_sub_f32_e32 v3, v3, v4
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3f317218, v1
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v2, 0x3f317218, v2
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3f317218, v3
+; SI-GISEL-NEXT:    s_mov_b32 s2, -1
+; SI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
 ; SI-GISEL-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
 ; SI-GISEL-NEXT:    s_endpgm
 ;
 ; VI-SDAG-LABEL: s_log_v4f32:
 ; VI-SDAG:       ; %bb.0:
 ; VI-SDAG-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
+; VI-SDAG-NEXT:    v_mov_b32_e32 v0, 0x800000
+; VI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; VI-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
 ; VI-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; VI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT:    v_log_f32_e32 v0, s7
-; VI-SDAG-NEXT:    v_log_f32_e32 v1, s6
-; VI-SDAG-NEXT:    v_log_f32_e32 v4, s5
-; VI-SDAG-NEXT:    v_log_f32_e32 v5, s4
-; VI-SDAG-NEXT:    v_mul_f32_e32 v3, 0x3f317218, v0
-; VI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3f317218, v1
-; VI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317218, v4
-; VI-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v5
+; VI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s7, v0
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v3, 0, v1, vcc
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v4, 1.0, v2, vcc
+; VI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s6, v0
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v6, 1.0, v2, vcc
+; VI-SDAG-NEXT:    v_mul_f32_e32 v4, s7, v4
+; VI-SDAG-NEXT:    v_mul_f32_e32 v6, s6, v6
+; VI-SDAG-NEXT:    v_log_f32_e32 v4, v4
+; VI-SDAG-NEXT:    v_log_f32_e32 v6, v6
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v5, 0, v1, vcc
+; VI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s5, v0
+; VI-SDAG-NEXT:    v_sub_f32_e32 v3, v4, v3
+; VI-SDAG-NEXT:    v_sub_f32_e32 v4, v6, v5
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v5, 0, v1, vcc
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v6, 1.0, v2, vcc
+; VI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; VI-SDAG-NEXT:    v_mul_f32_e32 v6, s5, v6
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, s4, v1
+; VI-SDAG-NEXT:    v_log_f32_e32 v6, v6
+; VI-SDAG-NEXT:    v_log_f32_e32 v7, v1
+; VI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3f317218, v4
+; VI-SDAG-NEXT:    v_mul_f32_e32 v3, 0x3f317218, v3
+; VI-SDAG-NEXT:    v_sub_f32_e32 v1, v6, v5
+; VI-SDAG-NEXT:    v_sub_f32_e32 v0, v7, v0
 ; VI-SDAG-NEXT:    v_mov_b32_e32 v5, s1
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317218, v1
+; VI-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
 ; VI-SDAG-NEXT:    v_mov_b32_e32 v4, s0
 ; VI-SDAG-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
 ; VI-SDAG-NEXT:    s_endpgm
 ;
 ; VI-GISEL-LABEL: s_log_v4f32:
 ; VI-GISEL:       ; %bb.0:
 ; VI-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
 ; VI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; VI-GISEL-NEXT:    s_mov_b32 s2, 0x800000
+; VI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x4f800000
+; VI-GISEL-NEXT:    v_mov_b32_e32 v4, 0x42000000
 ; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT:    v_log_f32_e32 v0, s4
-; VI-GISEL-NEXT:    v_log_f32_e32 v1, s5
-; VI-GISEL-NEXT:    v_log_f32_e32 v2, s6
-; VI-GISEL-NEXT:    v_log_f32_e32 v3, s7
-; VI-GISEL-NEXT:    v_mov_b32_e32 v5, s1
+; VI-GISEL-NEXT:    v_mov_b32_e32 v0, s4
+; VI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s2, v0
+; VI-GISEL-NEXT:    v_mov_b32_e32 v5, s5
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, 1.0, v3, vcc
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v4, vcc
+; VI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s2, v5
+; VI-GISEL-NEXT:    v_mul_f32_e32 v0, s4, v0
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v5, 1.0, v3, vcc
+; VI-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT:    v_mul_f32_e32 v5, s5, v5
+; VI-GISEL-NEXT:    v_log_f32_e32 v5, v5
+; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x800000
+; VI-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v4, vcc
+; VI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, s6, v2
+; VI-GISEL-NEXT:    v_sub_f32_e32 v1, v5, v1
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v5, 1.0, v3, vcc
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v6, 0, v4, vcc
+; VI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, s7, v2
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v2, 1.0, v3, vcc
+; VI-GISEL-NEXT:    v_mul_f32_e32 v5, s6, v5
+; VI-GISEL-NEXT:    v_mul_f32_e32 v2, s7, v2
+; VI-GISEL-NEXT:    v_log_f32_e32 v5, v5
+; VI-GISEL-NEXT:    v_log_f32_e32 v3, v2
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v4, 0, v4, vcc
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; VI-GISEL-NEXT:    v_sub_f32_e32 v2, v5, v6
+; VI-GISEL-NEXT:    v_sub_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT:    v_mov_b32_e32 v5, s1
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3f317218, v1
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v2, 0x3f317218, v2
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3f317218, v3
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v4, s0
 ; VI-GISEL-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
 ; VI-GISEL-NEXT:    s_endpgm
 ;
 ; GFX900-SDAG-LABEL: s_log_v4f32:
 ; GFX900-SDAG:       ; %bb.0:
 ; GFX900-SDAG-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
 ; GFX900-SDAG-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
-; GFX900-SDAG-NEXT:    v_mov_b32_e32 v4, 0
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v0, 0x800000
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v4, 0x4f800000
 ; GFX900-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX900-SDAG-NEXT:    v_log_f32_e32 v0, s7
-; GFX900-SDAG-NEXT:    v_log_f32_e32 v1, s6
-; GFX900-SDAG-NEXT:    v_log_f32_e32 v5, s5
-; GFX900-SDAG-NEXT:    v_log_f32_e32 v6, s4
-; GFX900-SDAG-NEXT:    v_mul_f32_e32 v3, 0x3f317218, v0
-; GFX900-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3f317218, v1
-; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317218, v5
-; GFX900-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v6
-; GFX900-SDAG-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3]
+; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s7, v0
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v2, 0, v1, vcc
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v3, 1.0, v4, vcc
+; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s6, v0
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v3, s7, v3
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v6, 1.0, v4, vcc
+; GFX900-SDAG-NEXT:    v_log_f32_e32 v3, v3
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v6, s6, v6
+; GFX900-SDAG-NEXT:    v_log_f32_e32 v6, v6
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v5, 0, v1, vcc
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v2, v3, v2
+; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s5, v0
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v3, 0x3f317218, v2
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v2, v6, v5
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v5, 0, v1, vcc
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v6, 1.0, v4, vcc
+; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v4, vcc
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v6, s5, v6
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, s4, v1
+; GFX900-SDAG-NEXT:    v_log_f32_e32 v6, v6
+; GFX900-SDAG-NEXT:    v_log_f32_e32 v4, v1
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v7, 0
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3f317218, v2
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v1, v6, v5
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v0, v4, v0
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317218, v1
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; GFX900-SDAG-NEXT:    global_store_dwordx4 v7, v[0:3], s[2:3]
 ; GFX900-SDAG-NEXT:    s_endpgm
 ;
 ; GFX900-GISEL-LABEL: s_log_v4f32:
 ; GFX900-GISEL:       ; %bb.0:
 ; GFX900-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
 ; GFX900-GISEL-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
-; GFX900-GISEL-NEXT:    v_mov_b32_e32 v4, 0
+; GFX900-GISEL-NEXT:    s_mov_b32 s0, 0x800000
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v3, 0x4f800000
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v4, 0x42000000
 ; GFX900-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX900-GISEL-NEXT:    v_log_f32_e32 v0, s4
-; GFX900-GISEL-NEXT:    v_log_f32_e32 v1, s5
-; GFX900-GISEL-NEXT:    v_log_f32_e32 v2, s6
-; GFX900-GISEL-NEXT:    v_log_f32_e32 v3, s7
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v0, s4
+; GFX900-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s0, v0
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v5, s5
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v0, 1.0, v3, vcc
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v4, vcc
+; GFX900-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s0, v5
+; GFX900-GISEL-NEXT:    v_mul_f32_e32 v0, s4, v0
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v5, 1.0, v3, vcc
+; GFX900-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT:    v_mul_f32_e32 v5, s5, v5
+; GFX900-GISEL-NEXT:    v_log_f32_e32 v5, v5
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x800000
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v4, vcc
+; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, s6, v2
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v1, v5, v1
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v5, 1.0, v3, vcc
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v6, 0, v4, vcc
+; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, s7, v2
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v2, 1.0, v3, vcc
+; GFX900-GISEL-NEXT:    v_mul_f32_e32 v5, s6, v5
+; GFX900-GISEL-NEXT:    v_mul_f32_e32 v2, s7, v2
+; GFX900-GISEL-NEXT:    v_log_f32_e32 v5, v5
+; GFX900-GISEL-NEXT:    v_log_f32_e32 v3, v2
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v4, 0, v4, vcc
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v2, v5, v6
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v3, v3, v4
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3f317218, v1
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v2, 0x3f317218, v2
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3f317218, v3
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX900-GISEL-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3]
 ; GFX900-GISEL-NEXT:    s_endpgm
 ;
 ; R600-LABEL: s_log_v4f32:
 ; R600:       ; %bb.0:
-; R600-NEXT:    ALU 12, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT:    ALU 38, @4, KC0[CB0:0-32], KC1[]
 ; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ; R600-NEXT:    ALU clause starting at 4:
-; R600-NEXT:     LOG_IEEE * T0.X, KC0[4].X,
-; R600-NEXT:     MUL_IEEE T0.W, PS, literal.x,
-; R600-NEXT:     LOG_IEEE * T0.X, KC0[3].W,
-; R600-NEXT:    1060205080(6.931472e-01), 0(0.000000e+00)
-; R600-NEXT:     MUL_IEEE T0.Z, PS, literal.x,
-; R600-NEXT:     LOG_IEEE * T0.X, KC0[3].Z,
+; R600-NEXT:     SETGT T0.W, literal.x, KC0[4].X,
+; R600-NEXT:     SETGT * T1.W, literal.x, KC0[3].W,
+; R600-NEXT:    8388608(1.175494e-38), 0(0.000000e+00)
+; R600-NEXT:     CNDE * T2.W, PV.W, 1.0, literal.x,
+; R600-NEXT:    1333788672(4.294967e+09), 0(0.000000e+00)
+; R600-NEXT:     MUL_IEEE T0.Z, KC0[4].X, PV.W,
+; R600-NEXT:     SETGT T2.W, literal.x, KC0[3].Z,
+; R600-NEXT:     CNDE * T3.W, T1.W, 1.0, literal.y,
+; R600-NEXT:    8388608(1.175494e-38), 1333788672(4.294967e+09)
+; R600-NEXT:     MUL_IEEE T0.X, KC0[3].W, PS,
+; R600-NEXT:     SETGT T0.Y, literal.x, KC0[3].Y,
+; R600-NEXT:     CNDE T1.Z, T0.W, 0.0, literal.y,
+; R600-NEXT:     CNDE T0.W, PV.W, 1.0, literal.z,
+; R600-NEXT:     LOG_IEEE * T0.Z, PV.Z,
+; R600-NEXT:    8388608(1.175494e-38), 1107296256(3.200000e+01)
+; R600-NEXT:    1333788672(4.294967e+09), 0(0.000000e+00)
+; R600-NEXT:     MUL_IEEE T1.X, KC0[3].Z, PV.W,
+; R600-NEXT:     ADD T1.Y, PS, -PV.Z,
+; R600-NEXT:     CNDE T0.Z, T1.W, 0.0, literal.x,
+; R600-NEXT:     CNDE T0.W, PV.Y, 1.0, literal.y,
+; R600-NEXT:     LOG_IEEE * T0.X, PV.X,
+; R600-NEXT:    1107296256(3.200000e+01), 1333788672(4.294967e+09)
+; R600-NEXT:     MUL_IEEE T2.X, KC0[3].Y, PV.W,
+; R600-NEXT:     CNDE T2.Y, T2.W, 0.0, literal.x,
+; R600-NEXT:     ADD T0.Z, PS, -PV.Z,
+; R600-NEXT:     MUL_IEEE T0.W, PV.Y, literal.y,
+; R600-NEXT:     LOG_IEEE * T0.X, PV.X,
+; R600-NEXT:    1107296256(3.200000e+01), 1060205080(6.931472e-01)
+; R600-NEXT:     CNDE T1.Y, T0.Y, 0.0, literal.x,
+; R600-NEXT:     MUL_IEEE T0.Z, PV.Z, literal.y,
+; R600-NEXT:     ADD T1.W, PS, -PV.Y,
+; R600-NEXT:     LOG_IEEE * T0.X, PV.X,
+; R600-NEXT:    1107296256(3.200000e+01), 1060205080(6.931472e-01)
+; R600-NEXT:     MUL_IEEE T0.Y, PV.W, literal.x,
+; R600-NEXT:     ADD * T1.W, PS, -PV.Y,
 ; R600-NEXT:    1060205080(6.931472e-01), 0(0.000000e+00)
-; R600-NEXT:     MUL_IEEE T0.Y, PS, literal.x,
-; R600-NEXT:     LOG_IEEE * T0.X, KC0[3].Y,
-; R600-NEXT:    1060205080(6.931472e-01), 0(0.000000e+00)
-; R600-NEXT:     MUL_IEEE T0.X, PS, literal.x,
+; R600-NEXT:     MUL_IEEE T0.X, PV.W, literal.x,
 ; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.y,
 ; R600-NEXT:    1060205080(6.931472e-01), 2(2.802597e-45)
 ;
 ; CM-LABEL: s_log_v4f32:
 ; CM:       ; %bb.0:
-; CM-NEXT:    ALU 25, @4, KC0[CB0:0-32], KC1[]
-; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0, T1.X
+; CM-NEXT:    ALU 50, @4, KC0[CB0:0-32], KC1[]
+; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T1, T0.X
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
 ; CM-NEXT:    ALU clause starting at 4:
-; CM-NEXT:     LOG_IEEE T0.X, KC0[4].X,
-; CM-NEXT:     LOG_IEEE T0.Y (MASKED), KC0[4].X,
-; CM-NEXT:     LOG_IEEE T0.Z (MASKED), KC0[4].X,
-; CM-NEXT:     LOG_IEEE * T0.W (MASKED), KC0[4].X,
-; CM-NEXT:     MUL_IEEE * T0.W, PV.X, literal.x,
+; CM-NEXT:     SETGT T0.Z, literal.x, KC0[4].X,
+; CM-NEXT:     SETGT * T0.W, literal.x, KC0[3].Y,
+; CM-NEXT:    8388608(1.175494e-38), 0(0.000000e+00)
+; CM-NEXT:     CNDE T0.Y, PV.W, 1.0, literal.x,
+; CM-NEXT:     CNDE T1.Z, PV.Z, 1.0, literal.x,
+; CM-NEXT:     SETGT * T1.W, literal.y, KC0[3].W,
+; CM-NEXT:    1333788672(4.294967e+09), 8388608(1.175494e-38)
+; CM-NEXT:     CNDE T0.X, PV.W, 1.0, literal.x,
+; CM-NEXT:     SETGT T1.Y, literal.y, KC0[3].Z,
+; CM-NEXT:     CNDE T0.Z, T0.Z, 0.0, literal.z,
+; CM-NEXT:     MUL_IEEE * T2.W, KC0[4].X, PV.Z,
+; CM-NEXT:    1333788672(4.294967e+09), 8388608(1.175494e-38)
+; CM-NEXT:    1107296256(3.200000e+01), 0(0.000000e+00)
+; CM-NEXT:     LOG_IEEE T1.X, T2.W,
+; CM-NEXT:     LOG_IEEE T1.Y (MASKED), T2.W,
+; CM-NEXT:     LOG_IEEE T1.Z (MASKED), T2.W,
+; CM-NEXT:     LOG_IEEE * T1.W (MASKED), T2.W,
+; CM-NEXT:     ADD T1.X, PV.X, -T0.Z,
+; CM-NEXT:     CNDE T2.Y, T1.Y, 1.0, literal.x,
+; CM-NEXT:     CNDE T0.Z, T1.W, 0.0, literal.y,
+; CM-NEXT:     MUL_IEEE * T1.W, KC0[3].W, T0.X,
+; CM-NEXT:    1333788672(4.294967e+09), 1107296256(3.200000e+01)
+; CM-NEXT:     LOG_IEEE T0.X, T1.W,
+; CM-NEXT:     LOG_IEEE T0.Y (MASKED), T1.W,
+; CM-NEXT:     LOG_IEEE T0.Z (MASKED), T1.W,
+; CM-NEXT:     LOG_IEEE * T0.W (MASKED), T1.W,
+; CM-NEXT:     ADD T0.X, PV.X, -T0.Z,
+; CM-NEXT:     CNDE T1.Y, T1.Y, 0.0, literal.x,
+; CM-NEXT:     MUL_IEEE T0.Z, KC0[3].Z, T2.Y,
+; CM-NEXT:     MUL_IEEE * T1.W, T1.X, literal.y,
+; CM-NEXT:    1107296256(3.200000e+01), 1060205080(6.931472e-01)
+; CM-NEXT:     LOG_IEEE T0.X (MASKED), T0.Z,
+; CM-NEXT:     LOG_IEEE T0.Y (MASKED), T0.Z,
+; CM-NEXT:     LOG_IEEE T0.Z, T0.Z,
+; CM-NEXT:     LOG_IEEE * T0.W (MASKED), T0.Z,
+; CM-NEXT:     CNDE T1.X, T0.W, 0.0, literal.x,
+; CM-NEXT:     ADD T1.Y, PV.Z, -T1.Y,
+; CM-NEXT:     MUL_IEEE T1.Z, T0.X, literal.y,
+; CM-NEXT:     MUL_IEEE * T0.W, KC0[3].Y, T0.Y, BS:VEC_021/SCL_122
+; CM-NEXT:    1107296256(3.200000e+01), 1060205080(6.931472e-01)
+; CM-NEXT:     LOG_IEEE T0.X, T0.W,
+; CM-NEXT:     LOG_IEEE T0.Y (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE T0.Z (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE * T0.W (MASKED), T0.W,
+; CM-NEXT:     MUL_IEEE T1.Y, T1.Y, literal.x,
+; CM-NEXT:     ADD * T0.W, PV.X, -T1.X,
 ; CM-NEXT:    1060205080(6.931472e-01), 0(0.000000e+00)
-; CM-NEXT:     LOG_IEEE T0.X, KC0[3].W,
-; CM-NEXT:     LOG_IEEE T0.Y (MASKED), KC0[3].W,
-; CM-NEXT:     LOG_IEEE T0.Z (MASKED), KC0[3].W,
-; CM-NEXT:     LOG_IEEE * T0.W (MASKED), KC0[3].W,
-; CM-NEXT:     MUL_IEEE * T0.Z, PV.X, literal.x,
+; CM-NEXT:     MUL_IEEE * T1.X, PV.W, literal.x,
 ; CM-NEXT:    1060205080(6.931472e-01), 0(0.000000e+00)
-; CM-NEXT:     LOG_IEEE T0.X, KC0[3].Z,
-; CM-NEXT:     LOG_IEEE T0.Y (MASKED), KC0[3].Z,
-; CM-NEXT:     LOG_IEEE T0.Z (MASKED), KC0[3].Z,
-; CM-NEXT:     LOG_IEEE * T0.W (MASKED), KC0[3].Z,
-; CM-NEXT:     MUL_IEEE * T0.Y, PV.X, literal.x,
-; CM-NEXT:    1060205080(6.931472e-01), 0(0.000000e+00)
-; CM-NEXT:     LOG_IEEE T0.X, KC0[3].Y,
-; CM-NEXT:     LOG_IEEE T0.Y (MASKED), KC0[3].Y,
-; CM-NEXT:     LOG_IEEE T0.Z (MASKED), KC0[3].Y,
-; CM-NEXT:     LOG_IEEE * T0.W (MASKED), KC0[3].Y,
-; CM-NEXT:     MUL_IEEE * T0.X, PV.X, literal.x,
-; CM-NEXT:    1060205080(6.931472e-01), 0(0.000000e+00)
-; CM-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
+; CM-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
   %result = call <4 x float> @llvm.log.v4f32(<4 x float> %in)
   store <4 x float> %result, ptr addrspace(1) %out
   ret void
 }
 
 define float @v_log_f32(float %in) {
-; GCN-LABEL: v_log_f32:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, v0
-; GCN-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log_f32:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x800000
+; GCN-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log_f32:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log_f32:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log_f32:
 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %result = call float @llvm.log.f32(float %in)
   ret float %result
 }
 
 define float @v_log_fabs_f32(float %in) {
-; GCN-LABEL: v_log_fabs_f32:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e64 v0, |v0|
-; GCN-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log_fabs_f32:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x800000
+; GCN-SDAG-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e64 v0, |v0|, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log_fabs_f32:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-GISEL-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v1
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-GISEL-NEXT:    v_mul_f32_e64 v0, |v0|, v1
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log_fabs_f32:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log_fabs_f32:
 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %fabs = call float @llvm.fabs.f32(float %in)
   %result = call float @llvm.log.f32(float %fabs)
   ret float %result
 }
 
 define float @v_log_fneg_fabs_f32(float %in) {
-; GCN-LABEL: v_log_fneg_fabs_f32:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e64 v0, -|v0|
-; GCN-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log_fneg_fabs_f32:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x80800000
+; GCN-SDAG-NEXT:    v_cmp_gt_f32_e64 vcc, |v0|, s4
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e64 v0, -|v0|, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log_fneg_fabs_f32:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-GISEL-NEXT:    v_cmp_lt_f32_e64 vcc, -|v0|, v1
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-GISEL-NEXT:    v_mul_f32_e64 v0, -|v0|, v1
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log_fneg_fabs_f32:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log_fneg_fabs_f32:
 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %fabs = call float @llvm.fabs.f32(float %in)
   %fneg.fabs = fneg float %fabs
   %result = call float @llvm.log.f32(float %fneg.fabs)
   ret float %result
 }
 
 define float @v_log_fneg_f32(float %in) {
-; GCN-LABEL: v_log_fneg_f32:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e64 v0, -v0
-; GCN-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log_fneg_f32:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x80800000
+; GCN-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s4, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e64 v0, -v0, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log_fneg_f32:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-GISEL-NEXT:    v_cmp_lt_f32_e64 vcc, -v0, v1
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-GISEL-NEXT:    v_mul_f32_e64 v0, -v0, v1
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log_fneg_f32:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log_fneg_f32:
 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %fneg = fneg float %in
   %result = call float @llvm.log.f32(float %fneg)
   ret float %result
 }
 
 define float @v_log_f32_fast(float %in) {
-; GCN-LABEL: v_log_f32_fast:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, v0
-; GCN-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log_f32_fast:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x800000
+; GCN-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log_f32_fast:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log_f32_fast:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log_f32_fast:
 ; CM:       ; %bb.0:

 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %result = call float @llvm.log.f32(float %in)
   ret float %result
 }
 
 define float @v_log_f32_ninf(float %in) {
-; GCN-LABEL: v_log_f32_ninf:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, v0
-; GCN-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log_f32_ninf:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x800000
+; GCN-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log_f32_ninf:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log_f32_ninf:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log_f32_ninf:
 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %result = call ninf float @llvm.log.f32(float %in)
   ret float %result
 }
 
 define float @v_log_f32_afn(float %in) {
-; GCN-LABEL: v_log_f32_afn:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, v0
-; GCN-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log_f32_afn:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x800000
+; GCN-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log_f32_afn:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log_f32_afn:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log_f32_afn:
 ; CM:       ; %bb.0:

 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %result = call afn float @llvm.log.f32(float %in)
   ret float %result
 }
 
 define float @v_log_f32_afn_dynamic(float %in) #1 {
-; GCN-LABEL: v_log_f32_afn_dynamic:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, v0
-; GCN-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log_f32_afn_dynamic:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x800000
+; GCN-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log_f32_afn_dynamic:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log_f32_afn_dynamic:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log_f32_afn_dynamic:
 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %result = call afn float @llvm.log.f32(float %in)
   ret float %result
 }
 
 define float @v_fabs_log_f32_afn(float %in) {
-; GCN-LABEL: v_fabs_log_f32_afn:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e64 v0, |v0|
-; GCN-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_fabs_log_f32_afn:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x800000
+; GCN-SDAG-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e64 v0, |v0|, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_fabs_log_f32_afn:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_log_f32_e64 v0, |v0|
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_fabs_log_f32_afn:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_fabs_log_f32_afn:
 ; CM:       ; %bb.0:

 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %result = call float @llvm.log.f32(float %in)
   ret float %result
 }
 
 define float @v_log_f32_nnan(float %in) {
-; GCN-LABEL: v_log_f32_nnan:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, v0
-; GCN-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log_f32_nnan:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x800000
+; GCN-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log_f32_nnan:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log_f32_nnan:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log_f32_nnan:
 ; CM:       ; %bb.0:

 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %result = call nnan float @llvm.log.f32(float %in)
   ret float %result
 }
 
 define float @v_log_f32_nnan_dynamic(float %in) #1 {
-; GCN-LABEL: v_log_f32_nnan_dynamic:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, v0
-; GCN-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log_f32_nnan_dynamic:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x800000
+; GCN-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log_f32_nnan_dynamic:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log_f32_nnan_dynamic:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log_f32_nnan_dynamic:
 ; CM:       ; %bb.0:

 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %result = call ninf float @llvm.log.f32(float %in)
   ret float %result
 }
 
 define float @v_log_f32_ninf_dynamic(float %in) #1 {
-; GCN-LABEL: v_log_f32_ninf_dynamic:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, v0
-; GCN-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log_f32_ninf_dynamic:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x800000
+; GCN-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log_f32_ninf_dynamic:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log_f32_ninf_dynamic:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log_f32_ninf_dynamic:
 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %result = call ninf float @llvm.log.f32(float %in)
   ret float %result
 }
 
 define float @v_log_f32_nnan_ninf(float %in) {
-; GCN-LABEL: v_log_f32_nnan_ninf:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, v0
-; GCN-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log_f32_nnan_ninf:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x800000
+; GCN-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log_f32_nnan_ninf:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log_f32_nnan_ninf:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log_f32_nnan_ninf:
 ; CM:       ; %bb.0:

 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %result = call nnan ninf float @llvm.log.f32(float %in)
   ret float %result
 }
 
 define float @v_log_f32_nnan_ninf_dynamic(float %in) #1 {
-; GCN-LABEL: v_log_f32_nnan_ninf_dynamic:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, v0
-; GCN-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log_f32_nnan_ninf_dynamic:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x800000
+; GCN-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log_f32_nnan_ninf_dynamic:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log_f32_nnan_ninf_dynamic:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log_f32_nnan_ninf_dynamic:
 ; CM:       ; %bb.0:

 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %result = call fast float @llvm.log.f32(float %in)
   ret float %result
 }
 
 define float @v_log_f32_dynamic_mode(float %in) #1 {
-; GCN-LABEL: v_log_f32_dynamic_mode:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, v0
-; GCN-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log_f32_dynamic_mode:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x800000
+; GCN-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log_f32_dynamic_mode:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log_f32_dynamic_mode:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log_f32_dynamic_mode:
 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %result = call float @llvm.log.f32(float %in)
   ret float %result
 }
 
 define float @v_log_f32_undef() {
-; GCN-LABEL: v_log_f32_undef:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, s4
-; GCN-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log_f32_undef:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, s4
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log_f32_undef:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v0, 0x800000
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x4f800000
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v1, s4, v1
+; GCN-GISEL-NEXT:    v_mul_f32_e64 v2, s4, 1.0
+; GCN-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, s4, v0
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log_f32_undef:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log_f32_undef:
 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %result = call float @llvm.log.f32(float undef)
   ret float %result
 }
 
 define float @v_log_f32_0() {
 ; GCN-SDAG-LABEL: v_log_f32_0:
 ; GCN-SDAG:       ; %bb.0:
 ; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-SDAG-NEXT:    v_log_f32_e32 v0, 0
+; GCN-SDAG-NEXT:    v_add_f32_e32 v0, 0xc2000000, v0
 ; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
 ; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GCN-GISEL-LABEL: v_log_f32_0:
 ; GCN-GISEL:       ; %bb.0:
 ; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-GISEL-NEXT:    v_mov_b32_e32 v0, 0x3f317218
-; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, 0xff800000, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v0, 0x800000
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x4f800000
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v1, 0, v1
+; GCN-GISEL-NEXT:    v_mul_f32_e64 v2, 0, 1.0
+; GCN-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, 0, v0
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
 ; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log_f32_0:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log_f32_0:

 }
 
 define float @v_log_f32_from_fpext_math_f16(i16 %src0.i, i16 %src1.i) {
 ; SI-SDAG-LABEL: v_log_f32_from_fpext_math_f16:
 ; SI-SDAG:       ; %bb.0:
 ; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-SDAG-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; SI-SDAG-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; SI-SDAG-NEXT:    s_mov_b32 s4, 0x800000
 ; SI-SDAG-NEXT:    v_add_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x4f800000
+; SI-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
+; SI-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; SI-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; SI-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
 ; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-GISEL-LABEL: v_log_f32_from_fpext_math_f16:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-GISEL-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; SI-GISEL-NEXT:    v_cvt_f32_f16_e32 v1, v1
; CM-NEXT:    PAD
   %result = call float @llvm.log.f32(float %fpext)
   ret float %result
 }
 
 define float @v_log_f32_from_fpext_bf16(bfloat %src) {
 ; GCN-SDAG-LABEL: v_log_f32_from_fpext_bf16:
 ; GCN-SDAG:       ; %bb.0:
 ; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x800000
+; GCN-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v2
 ; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317218, v0
 ; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GCN-GISEL-LABEL: v_log_f32_from_fpext_bf16:
 ; GCN-GISEL:       ; %bb.0:
 ; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-GISEL-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0

 declare half @llvm.fabs.f16(half) #2
 declare half @llvm.log.f16(half) #2
 declare <2 x half> @llvm.log.v2f16(<2 x half>) #2
 declare <2 x half> @llvm.fabs.v2f16(<2 x half>) #2
 
 attributes #0 = { "denormal-fp-math-f32"="ieee,preserve-sign" }
 attributes #1 = { "denormal-fp-math-f32"="dynamic,dynamic" }
 attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; SI: {{.*}}

llvm/test/CodeGen/AMDGPU/llvm.log10.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc -global-isel=0 -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,SI,GCN-SDAG,SI-SDAG %s
 ; RUN: llc -global-isel=1 -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,SI,GCN-GISEL,SI-GISEL %s
 ; RUN: llc -global-isel=0 -march=amdgcn -mcpu=tonga < %s | FileCheck  -check-prefixes=GCN,VI,GCN-SDAG,VI-SDAG %s
 ; RUN: llc -global-isel=1 -march=amdgcn -mcpu=tonga < %s | FileCheck  -check-prefixes=GCN,VI,GCN-GISEL,VI-GISEL %s
 ; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX900,GCN-SDAG,GFX900-SDAG %s
 ; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX900,GCN-GISEL,GFX900-GISEL %s
 
 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s
 ; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s
 
 define amdgpu_kernel void @s_log10_f32(ptr addrspace(1) %out, float %in) {
-; SI-LABEL: s_log10_f32:
-; SI:       ; %bb.0:
-; SI-NEXT:    s_load_dword s2, s[0:1], 0xb
-; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; SI-NEXT:    s_mov_b32 s3, 0xf000
-; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    v_log_f32_e32 v0, s2
-; SI-NEXT:    s_mov_b32 s2, -1
-; SI-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
-; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
-; SI-NEXT:    s_endpgm
+; SI-SDAG-LABEL: s_log10_f32:
+; SI-SDAG:       ; %bb.0:
+; SI-SDAG-NEXT:    s_load_dword s2, s[0:1], 0xb
+; SI-SDAG-NEXT:    v_mov_b32_e32 v0, 0x800000
+; SI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; SI-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SI-SDAG-NEXT:    s_mov_b32 s3, 0xf000
+; SI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
+; SI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s2, v0
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; SI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x4f800000
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
+; SI-SDAG-NEXT:    v_mul_f32_e32 v1, s2, v1
+; SI-SDAG-NEXT:    v_log_f32_e32 v1, v1
+; SI-SDAG-NEXT:    s_mov_b32 s2, -1
+; SI-SDAG-NEXT:    v_sub_f32_e32 v0, v1, v0
+; SI-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; SI-SDAG-NEXT:    buffer_store_dword v0, off, s[0:3], 0
+; SI-SDAG-NEXT:    s_endpgm
 ;
-; VI-LABEL: s_log10_f32:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
-; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_log_f32_e32 v0, s2
-; VI-NEXT:    v_mul_f32_e32 v2, 0x3e9a209b, v0
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    flat_store_dword v[0:1], v2
-; VI-NEXT:    s_endpgm
+; SI-GISEL-LABEL: s_log10_f32:
+; SI-GISEL:       ; %bb.0:
+; SI-GISEL-NEXT:    s_load_dword s2, s[0:1], 0xb
+; SI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SI-GISEL-NEXT:    v_mov_b32_e32 v0, 0x800000
+; SI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x4f800000
+; SI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, s2, v0
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v0, 1.0, v1, vcc
+; SI-GISEL-NEXT:    v_mul_f32_e32 v0, s2, v0
+; SI-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT:    s_mov_b32 s2, -1
+; SI-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; SI-GISEL-NEXT:    buffer_store_dword v0, off, s[0:3], 0
+; SI-GISEL-NEXT:    s_endpgm
+;
+; VI-SDAG-LABEL: s_log10_f32:
+; VI-SDAG:       ; %bb.0:
+; VI-SDAG-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; VI-SDAG-NEXT:    v_mov_b32_e32 v0, 0x800000
+; VI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; VI-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; VI-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; VI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
+; VI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s2, v0
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, s2, v1
+; VI-SDAG-NEXT:    v_log_f32_e32 v1, v1
+; VI-SDAG-NEXT:    v_sub_f32_e32 v0, v1, v0
+; VI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3e9a209b, v0
+; VI-SDAG-NEXT:    v_mov_b32_e32 v0, s0
+; VI-SDAG-NEXT:    v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT:    flat_store_dword v[0:1], v2
+; VI-SDAG-NEXT:    s_endpgm
+;
+; VI-GISEL-LABEL: s_log10_f32:
+; VI-GISEL:       ; %bb.0:
+; VI-GISEL-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; VI-GISEL-NEXT:    v_mov_b32_e32 v0, 0x800000
+; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x4f800000
+; VI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, s2, v0
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, 1.0, v1, vcc
+; VI-GISEL-NEXT:    v_mul_f32_e32 v0, s2, v0
+; VI-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT:    v_mul_f32_e32 v2, 0x3e9a209b, v0
+; VI-GISEL-NEXT:    v_mov_b32_e32 v0, s0
+; VI-GISEL-NEXT:    v_mov_b32_e32 v1, s1
+; VI-GISEL-NEXT:    flat_store_dword v[0:1], v2
+; VI-GISEL-NEXT:    s_endpgm
 ;
 ; GFX900-SDAG-LABEL: s_log10_f32:
 ; GFX900-SDAG:       ; %bb.0:
-; GFX900-SDAG-NEXT:    s_load_dword s4, s[0:1], 0x2c
-; GFX900-SDAG-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
-; GFX900-SDAG-NEXT:    v_mov_b32_e32 v1, 0
+; GFX900-SDAG-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v0, 0x800000
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GFX900-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX900-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX900-SDAG-NEXT:    v_log_f32_e32 v0, s4
+; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v1, 0x4f800000
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, s2, v1
+; GFX900-SDAG-NEXT:    v_log_f32_e32 v1, v1
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v0, v1, v0
 ; GFX900-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
-; GFX900-SDAG-NEXT:    global_store_dword v1, v0, s[2:3]
+; GFX900-SDAG-NEXT:    global_store_dword v2, v0, s[0:1]
 ; GFX900-SDAG-NEXT:    s_endpgm
 ;
 ; GFX900-GISEL-LABEL: s_log10_f32:
 ; GFX900-GISEL:       ; %bb.0:
 ; GFX900-GISEL-NEXT:    s_load_dword s2, s[0:1], 0x2c
-; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v0, 0x800000
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; GFX900-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX900-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX900-GISEL-NEXT:    v_log_f32_e32 v0, s2
+; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v0, 1.0, v1, vcc
+; GFX900-GISEL-NEXT:    v_mul_f32_e32 v0, s2, v0
+; GFX900-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX900-GISEL-NEXT:    global_store_dword v1, v0, s[0:1]
 ; GFX900-GISEL-NEXT:    s_endpgm
 ;
 ; R600-LABEL: s_log10_f32:
 ; R600:       ; %bb.0:
-; R600-NEXT:    ALU 3, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT:    ALU 11, @4, KC0[CB0:0-32], KC1[]
 ; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ; R600-NEXT:    ALU clause starting at 4:
-; R600-NEXT:     LOG_IEEE * T0.X, KC0[2].Z,
-; R600-NEXT:     MUL_IEEE T0.X, PS, literal.x,
+; R600-NEXT:     SETGT * T0.W, literal.x, KC0[2].Z,
+; R600-NEXT:    8388608(1.175494e-38), 0(0.000000e+00)
+; R600-NEXT:     CNDE * T1.W, PV.W, 1.0, literal.x,
+; R600-NEXT:    1333788672(4.294967e+09), 0(0.000000e+00)
+; R600-NEXT:     MUL_IEEE T1.W, KC0[2].Z, PV.W,
+; R600-NEXT:     CNDE * T0.W, T0.W, 0.0, literal.x,
+; R600-NEXT:    1107296256(3.200000e+01), 0(0.000000e+00)
+; R600-NEXT:     LOG_IEEE * T0.X, PV.W,
+; R600-NEXT:     ADD * T0.W, PS, -T0.W,
+; R600-NEXT:     MUL_IEEE T0.X, PV.W, literal.x,
 ; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.y,
 ; R600-NEXT:    1050288283(3.010300e-01), 2(2.802597e-45)
 ;
 ; CM-LABEL: s_log10_f32:
 ; CM:       ; %bb.0:
-; CM-NEXT:    ALU 7, @4, KC0[CB0:0-32], KC1[]
+; CM-NEXT:    ALU 15, @4, KC0[CB0:0-32], KC1[]
 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
 ; CM-NEXT:    ALU clause starting at 4:
-; CM-NEXT:     LOG_IEEE T0.X, KC0[2].Z,
-; CM-NEXT:     LOG_IEEE T0.Y (MASKED), KC0[2].Z,
-; CM-NEXT:     LOG_IEEE T0.Z (MASKED), KC0[2].Z,
-; CM-NEXT:     LOG_IEEE * T0.W (MASKED), KC0[2].Z,
-; CM-NEXT:     MUL_IEEE * T0.X, PV.X, literal.x,
+; CM-NEXT:     SETGT * T0.W, literal.x, KC0[2].Z,
+; CM-NEXT:    8388608(1.175494e-38), 0(0.000000e+00)
+; CM-NEXT:     CNDE * T1.W, PV.W, 1.0, literal.x,
+; CM-NEXT:    1333788672(4.294967e+09), 0(0.000000e+00)
+; CM-NEXT:     CNDE T0.Z, T0.W, 0.0, literal.x,
+; CM-NEXT:     MUL_IEEE * T0.W, KC0[2].Z, PV.W,
+; CM-NEXT:    1107296256(3.200000e+01), 0(0.000000e+00)
+; CM-NEXT:     LOG_IEEE T0.X, T0.W,
+; CM-NEXT:     LOG_IEEE T0.Y (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE T0.Z (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE * T0.W (MASKED), T0.W,
+; CM-NEXT:     ADD * T0.W, PV.X, -T0.Z,
+; CM-NEXT:     MUL_IEEE * T0.X, PV.W, literal.x,
 ; CM-NEXT:    1050288283(3.010300e-01), 0(0.000000e+00)
 ; CM-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
   %result = call float @llvm.log10.f32(float %in)
   store float %result, ptr addrspace(1) %out
   ret void
 }
 
 ; FIXME: We should be able to merge these packets together on Cayman so we
 ; have a maximum of 4 instructions.
 define amdgpu_kernel void @s_log10_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
 ; SI-SDAG-LABEL: s_log10_v2f32:
 ; SI-SDAG:       ; %bb.0:
 ; SI-SDAG-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; SI-SDAG-NEXT:    v_mov_b32_e32 v0, 0x800000
+; SI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; SI-SDAG-NEXT:    v_mov_b32_e32 v3, 0x4f800000
 ; SI-SDAG-NEXT:    s_mov_b32 s7, 0xf000
-; SI-SDAG-NEXT:    s_mov_b32 s6, -1
 ; SI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-SDAG-NEXT:    v_log_f32_e32 v0, s3
-; SI-SDAG-NEXT:    v_log_f32_e32 v2, s2
+; SI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s3, v0
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v2, 0, v1, vcc
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v4, 1.0, v3, vcc
+; SI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s2, v0
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v3, vcc
+; SI-SDAG-NEXT:    v_mul_f32_e32 v4, s3, v4
+; SI-SDAG-NEXT:    v_mul_f32_e32 v1, s2, v1
+; SI-SDAG-NEXT:    v_log_f32_e32 v4, v4
+; SI-SDAG-NEXT:    v_log_f32_e32 v3, v1
+; SI-SDAG-NEXT:    s_mov_b32 s6, -1
 ; SI-SDAG-NEXT:    s_mov_b32 s4, s0
+; SI-SDAG-NEXT:    v_sub_f32_e32 v1, v4, v2
+; SI-SDAG-NEXT:    v_sub_f32_e32 v0, v3, v0
 ; SI-SDAG-NEXT:    s_mov_b32 s5, s1
-; SI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a209b, v0
-; SI-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v2
+; SI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a209b, v1
+; SI-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
 ; SI-SDAG-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; SI-SDAG-NEXT:    s_endpgm
 ;
 ; SI-GISEL-LABEL: s_log10_v2f32:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; SI-GISEL-NEXT:    s_mov_b32 s4, 0x800000
+; SI-GISEL-NEXT:    v_mov_b32_e32 v0, 0x4f800000
+; SI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
 ; SI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-GISEL-NEXT:    v_log_f32_e32 v0, s2
-; SI-GISEL-NEXT:    v_log_f32_e32 v1, s3
+; SI-GISEL-NEXT:    v_mov_b32_e32 v2, s2
+; SI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v2
+; SI-GISEL-NEXT:    v_mov_b32_e32 v4, s3
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v2, 1.0, v0, vcc
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v3, 0, v1, vcc
+; SI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v4
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v0, 1.0, v0, vcc
+; SI-GISEL-NEXT:    v_mul_f32_e32 v2, s2, v2
+; SI-GISEL-NEXT:    v_mul_f32_e32 v0, s3, v0
+; SI-GISEL-NEXT:    v_log_f32_e32 v2, v2
+; SI-GISEL-NEXT:    v_log_f32_e32 v4, v0
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; SI-GISEL-NEXT:    s_mov_b32 s2, -1
-; SI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT:    v_sub_f32_e32 v0, v2, v3
+; SI-GISEL-NEXT:    v_sub_f32_e32 v1, v4, v1
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3e9a209b, v1
+; SI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
 ; SI-GISEL-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; SI-GISEL-NEXT:    s_endpgm
 ;
 ; VI-SDAG-LABEL: s_log10_v2f32:
 ; VI-SDAG:       ; %bb.0:
 ; VI-SDAG-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; VI-SDAG-NEXT:    v_mov_b32_e32 v0, 0x800000
+; VI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; VI-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
 ; VI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT:    v_log_f32_e32 v0, s3
-; VI-SDAG-NEXT:    v_log_f32_e32 v2, s2
-; VI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a209b, v0
-; VI-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v2
+; VI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s3, v0
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v3, 0, v1, vcc
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v4, 1.0, v2, vcc
+; VI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s2, v0
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; VI-SDAG-NEXT:    v_mul_f32_e32 v4, s3, v4
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, s2, v1
+; VI-SDAG-NEXT:    v_log_f32_e32 v4, v4
+; VI-SDAG-NEXT:    v_log_f32_e32 v2, v1
+; VI-SDAG-NEXT:    v_sub_f32_e32 v1, v4, v3
+; VI-SDAG-NEXT:    v_sub_f32_e32 v0, v2, v0
 ; VI-SDAG-NEXT:    v_mov_b32_e32 v3, s1
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a209b, v1
+; VI-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
 ; VI-SDAG-NEXT:    v_mov_b32_e32 v2, s0
 ; VI-SDAG-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
 ; VI-SDAG-NEXT:    s_endpgm
 ;
 ; VI-GISEL-LABEL: s_log10_v2f32:
 ; VI-GISEL:       ; %bb.0:
 ; VI-GISEL-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; VI-GISEL-NEXT:    s_mov_b32 s4, 0x800000
+; VI-GISEL-NEXT:    v_mov_b32_e32 v0, 0x4f800000
+; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
 ; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT:    v_log_f32_e32 v0, s2
-; VI-GISEL-NEXT:    v_log_f32_e32 v1, s3
+; VI-GISEL-NEXT:    v_mov_b32_e32 v2, s2
+; VI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v2
+; VI-GISEL-NEXT:    v_mov_b32_e32 v4, s3
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v2, 1.0, v0, vcc
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v3, 0, v1, vcc
+; VI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v4
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, 1.0, v0, vcc
+; VI-GISEL-NEXT:    v_mul_f32_e32 v2, s2, v2
+; VI-GISEL-NEXT:    v_mul_f32_e32 v0, s3, v0
+; VI-GISEL-NEXT:    v_log_f32_e32 v2, v2
+; VI-GISEL-NEXT:    v_log_f32_e32 v4, v0
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT:    v_sub_f32_e32 v0, v2, v3
+; VI-GISEL-NEXT:    v_sub_f32_e32 v1, v4, v1
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT:    v_mov_b32_e32 v2, s0
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3e9a209b, v1
+; VI-GISEL-NEXT:    v_mov_b32_e32 v2, s0
 ; VI-GISEL-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
 ; VI-GISEL-NEXT:    s_endpgm
 ;
 ; GFX900-SDAG-LABEL: s_log10_v2f32:
 ; GFX900-SDAG:       ; %bb.0:
 ; GFX900-SDAG-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
-; GFX900-SDAG-NEXT:    v_mov_b32_e32 v3, 0
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v0, 0x800000
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v5, 0
 ; GFX900-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX900-SDAG-NEXT:    v_log_f32_e32 v0, s3
-; GFX900-SDAG-NEXT:    v_log_f32_e32 v2, s2
-; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a209b, v0
-; GFX900-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v2
-; GFX900-SDAG-NEXT:    global_store_dwordx2 v3, v[0:1], s[0:1]
+; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s3, v0
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v3, 0, v1, vcc
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v4, 1.0, v2, vcc
+; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v4, s3, v4
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, s2, v1
+; GFX900-SDAG-NEXT:    v_log_f32_e32 v4, v4
+; GFX900-SDAG-NEXT:    v_log_f32_e32 v2, v1
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v1, v4, v3
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v0, v2, v0
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a209b, v1
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GFX900-SDAG-NEXT:    global_store_dwordx2 v5, v[0:1], s[0:1]
 ; GFX900-SDAG-NEXT:    s_endpgm
 ;
 ; GFX900-GISEL-LABEL: s_log10_v2f32:
 ; GFX900-GISEL:       ; %bb.0:
 ; GFX900-GISEL-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
-; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0
+; GFX900-GISEL-NEXT:    s_mov_b32 s4, 0x800000
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v0, 0x4f800000
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
 ; GFX900-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX900-GISEL-NEXT:    v_log_f32_e32 v0, s2
-; GFX900-GISEL-NEXT:    v_log_f32_e32 v1, s3
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, s2
+; GFX900-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v2
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v4, s3
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v2, 1.0, v0, vcc
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v3, 0, v1, vcc
+; GFX900-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v4
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v0, 1.0, v0, vcc
+; GFX900-GISEL-NEXT:    v_mul_f32_e32 v2, s2, v2
+; GFX900-GISEL-NEXT:    v_mul_f32_e32 v0, s3, v0
+; GFX900-GISEL-NEXT:    v_log_f32_e32 v2, v2
+; GFX900-GISEL-NEXT:    v_log_f32_e32 v4, v0
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v0, v2, v3
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v1, v4, v1
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3e9a209b, v1
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX900-GISEL-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
 ; GFX900-GISEL-NEXT:    s_endpgm
 ;
 ; R600-LABEL: s_log10_v2f32:
 ; R600:       ; %bb.0:
-; R600-NEXT:    ALU 6, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT:    ALU 21, @4, KC0[CB0:0-32], KC1[]
 ; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ; R600-NEXT:    ALU clause starting at 4:
-; R600-NEXT:     LOG_IEEE * T0.X, KC0[3].X,
-; R600-NEXT:     MUL_IEEE T0.Y, PS, literal.x,
-; R600-NEXT:     LOG_IEEE * T0.X, KC0[2].W,
+; R600-NEXT:     SETGT T0.W, literal.x, KC0[3].X,
+; R600-NEXT:     SETGT * T1.W, literal.x, KC0[2].W,
+; R600-NEXT:    8388608(1.175494e-38), 0(0.000000e+00)
+; R600-NEXT:     CNDE * T2.W, PV.W, 1.0, literal.x,
+; R600-NEXT:    1333788672(4.294967e+09), 0(0.000000e+00)
+; R600-NEXT:     MUL_IEEE T2.W, KC0[3].X, PV.W,
+; R600-NEXT:     CNDE * T3.W, T1.W, 1.0, literal.x,
+; R600-NEXT:    1333788672(4.294967e+09), 0(0.000000e+00)
+; R600-NEXT:     MUL_IEEE T0.Z, KC0[2].W, PS,
+; R600-NEXT:     CNDE T0.W, T0.W, 0.0, literal.x,
+; R600-NEXT:     LOG_IEEE * T0.X, PV.W,
+; R600-NEXT:    1107296256(3.200000e+01), 0(0.000000e+00)
+; R600-NEXT:     CNDE T1.Z, T1.W, 0.0, literal.x,
+; R600-NEXT:     ADD T0.W, PS, -PV.W,
+; R600-NEXT:     LOG_IEEE * T0.X, PV.Z,
+; R600-NEXT:    1107296256(3.200000e+01), 0(0.000000e+00)
+; R600-NEXT:     MUL_IEEE T0.Y, PV.W, literal.x,
+; R600-NEXT:     ADD * T0.W, PS, -PV.Z,
 ; R600-NEXT:    1050288283(3.010300e-01), 0(0.000000e+00)
-; R600-NEXT:     MUL_IEEE T0.X, PS, literal.x,
+; R600-NEXT:     MUL_IEEE T0.X, PV.W, literal.x,
 ; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.y,
 ; R600-NEXT:    1050288283(3.010300e-01), 2(2.802597e-45)
 ;
 ; CM-LABEL: s_log10_v2f32:
 ; CM:       ; %bb.0:
-; CM-NEXT:    ALU 13, @4, KC0[CB0:0-32], KC1[]
+; CM-NEXT:    ALU 27, @4, KC0[CB0:0-32], KC1[]
 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0, T1.X
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
 ; CM-NEXT:    ALU clause starting at 4:
-; CM-NEXT:     LOG_IEEE T0.X, KC0[3].X,
-; CM-NEXT:     LOG_IEEE T0.Y (MASKED), KC0[3].X,
-; CM-NEXT:     LOG_IEEE T0.Z (MASKED), KC0[3].X,
-; CM-NEXT:     LOG_IEEE * T0.W (MASKED), KC0[3].X,
-; CM-NEXT:     MUL_IEEE * T0.Y, PV.X, literal.x,
+; CM-NEXT:     SETGT * T0.W, literal.x, KC0[3].X,
+; CM-NEXT:    8388608(1.175494e-38), 0(0.000000e+00)
+; CM-NEXT:     CNDE T0.Z, PV.W, 1.0, literal.x,
+; CM-NEXT:     SETGT * T1.W, literal.y, KC0[2].W,
+; CM-NEXT:    1333788672(4.294967e+09), 8388608(1.175494e-38)
+; CM-NEXT:     CNDE T0.Y, PV.W, 1.0, literal.x,
+; CM-NEXT:     CNDE T1.Z, T0.W, 0.0, literal.y,
+; CM-NEXT:     MUL_IEEE * T0.W, KC0[3].X, PV.Z,
+; CM-NEXT:    1333788672(4.294967e+09), 1107296256(3.200000e+01)
+; CM-NEXT:     LOG_IEEE T0.X, T0.W,
+; CM-NEXT:     LOG_IEEE T0.Y (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE T0.Z (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE * T0.W (MASKED), T0.W,
+; CM-NEXT:     CNDE T1.Y, T1.W, 0.0, literal.x,
+; CM-NEXT:     ADD T0.Z, PV.X, -T1.Z,
+; CM-NEXT:     MUL_IEEE * T0.W, KC0[2].W, T0.Y,
+; CM-NEXT:    1107296256(3.200000e+01), 0(0.000000e+00)
+; CM-NEXT:     LOG_IEEE T0.X, T0.W,
+; CM-NEXT:     LOG_IEEE T0.Y (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE T0.Z (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE * T0.W (MASKED), T0.W,
+; CM-NEXT:     MUL_IEEE T0.Y, T0.Z, literal.x,
+; CM-NEXT:     ADD * T0.W, PV.X, -T1.Y,
 ; CM-NEXT:    1050288283(3.010300e-01), 0(0.000000e+00)
-; CM-NEXT:     LOG_IEEE T0.X, KC0[2].W,
-; CM-NEXT:     LOG_IEEE T0.Y (MASKED), KC0[2].W,
-; CM-NEXT:     LOG_IEEE T0.Z (MASKED), KC0[2].W,
-; CM-NEXT:     LOG_IEEE * T0.W (MASKED), KC0[2].W,
-; CM-NEXT:     MUL_IEEE * T0.X, PV.X, literal.x,
+; CM-NEXT:     MUL_IEEE * T0.X, PV.W, literal.x,
 ; CM-NEXT:    1050288283(3.010300e-01), 0(0.000000e+00)
 ; CM-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
   %result = call <2 x float> @llvm.log10.v2f32(<2 x float> %in)
   store <2 x float> %result, ptr addrspace(1) %out
   ret void
 }
 
 define amdgpu_kernel void @s_log10_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
 ; SI-SDAG-LABEL: s_log10_v3f32:
 ; SI-SDAG:       ; %bb.0:
 ; SI-SDAG-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xd
+; SI-SDAG-NEXT:    v_mov_b32_e32 v0, 0x800000
+; SI-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; SI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
 ; SI-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
+; SI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s5, v0
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v4, 1.0, v2, vcc
+; SI-SDAG-NEXT:    v_mul_f32_e32 v4, s5, v4
+; SI-SDAG-NEXT:    v_log_f32_e32 v4, v4
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v3, 0, v1, vcc
+; SI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v5, 1.0, v2, vcc
+; SI-SDAG-NEXT:    v_sub_f32_e32 v3, v4, v3
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v4, 0, v1, vcc
+; SI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s6, v0
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v0, 1.0, v2, vcc
+; SI-SDAG-NEXT:    v_mul_f32_e32 v0, s6, v0
+; SI-SDAG-NEXT:    v_mul_f32_e32 v5, s4, v5
+; SI-SDAG-NEXT:    v_log_f32_e32 v2, v0
+; SI-SDAG-NEXT:    v_log_f32_e32 v5, v5
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v6, 0, v1, vcc
 ; SI-SDAG-NEXT:    s_mov_b32 s3, 0xf000
+; SI-SDAG-NEXT:    v_sub_f32_e32 v2, v2, v6
 ; SI-SDAG-NEXT:    s_mov_b32 s2, -1
-; SI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-SDAG-NEXT:    v_log_f32_e32 v0, s5
-; SI-SDAG-NEXT:    v_log_f32_e32 v2, s4
-; SI-SDAG-NEXT:    v_log_f32_e32 v3, s6
-; SI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a209b, v0
-; SI-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v2
-; SI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3e9a209b, v3
+; SI-SDAG-NEXT:    v_sub_f32_e32 v0, v5, v4
+; SI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3e9a209b, v2
+; SI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a209b, v3
+; SI-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
 ; SI-SDAG-NEXT:    buffer_store_dword v2, off, s[0:3], 0 offset:8
 ; SI-SDAG-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; SI-SDAG-NEXT:    s_endpgm
 ;
 ; SI-GISEL-LABEL: s_log10_v3f32:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xd
 ; SI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; SI-GISEL-NEXT:    s_mov_b32 s2, -1
-; SI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT:    s_mov_b32 s2, 0x800000
+; SI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x4f800000
+; SI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x42000000
 ; SI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-GISEL-NEXT:    v_log_f32_e32 v0, s4
-; SI-GISEL-NEXT:    v_log_f32_e32 v1, s5
-; SI-GISEL-NEXT:    v_log_f32_e32 v2, s6
+; SI-GISEL-NEXT:    v_mov_b32_e32 v0, s4
+; SI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s2, v0
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v0, 1.0, v1, vcc
+; SI-GISEL-NEXT:    v_mul_f32_e32 v0, s4, v0
+; SI-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v4, 0, v3, vcc
+; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x800000
+; SI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v4
+; SI-GISEL-NEXT:    v_mov_b32_e32 v4, s5
+; SI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s2, v4
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v4, 1.0, v1, vcc
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v5, 0, v3, vcc
+; SI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, s6, v2
+; SI-GISEL-NEXT:    v_mul_f32_e32 v4, s5, v4
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
+; SI-GISEL-NEXT:    v_log_f32_e32 v4, v4
+; SI-GISEL-NEXT:    v_mul_f32_e32 v1, s6, v1
+; SI-GISEL-NEXT:    v_log_f32_e32 v2, v1
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v3, 0, v3, vcc
+; SI-GISEL-NEXT:    v_sub_f32_e32 v1, v4, v5
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3e9a209b, v1
+; SI-GISEL-NEXT:    v_sub_f32_e32 v2, v2, v3
+; SI-GISEL-NEXT:    s_mov_b32 s2, -1
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v2, 0x3e9a209b, v2
 ; SI-GISEL-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; SI-GISEL-NEXT:    buffer_store_dword v2, off, s[0:3], 0 offset:8
 ; SI-GISEL-NEXT:    s_endpgm
 ;
 ; VI-SDAG-LABEL: s_log10_v3f32:
 ; VI-SDAG:       ; %bb.0:
 ; VI-SDAG-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
+; VI-SDAG-NEXT:    v_mov_b32_e32 v0, 0x800000
+; VI-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; VI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
 ; VI-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; VI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT:    v_log_f32_e32 v0, s6
-; VI-SDAG-NEXT:    v_log_f32_e32 v3, s4
-; VI-SDAG-NEXT:    v_log_f32_e32 v1, s5
-; VI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3e9a209b, v0
-; VI-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v3
+; VI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s6, v0
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v4, 1.0, v2, vcc
+; VI-SDAG-NEXT:    v_mul_f32_e32 v4, s6, v4
+; VI-SDAG-NEXT:    v_log_f32_e32 v4, v4
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v3, 0, v1, vcc
+; VI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s5, v0
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v5, 0, v1, vcc
+; VI-SDAG-NEXT:    v_sub_f32_e32 v3, v4, v3
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v4, 1.0, v2, vcc
+; VI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; VI-SDAG-NEXT:    v_mul_f32_e32 v4, s5, v4
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, s4, v1
+; VI-SDAG-NEXT:    v_log_f32_e32 v4, v4
+; VI-SDAG-NEXT:    v_log_f32_e32 v6, v1
+; VI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3e9a209b, v3
+; VI-SDAG-NEXT:    v_sub_f32_e32 v1, v4, v5
+; VI-SDAG-NEXT:    v_sub_f32_e32 v0, v6, v0
 ; VI-SDAG-NEXT:    v_mov_b32_e32 v4, s1
 ; VI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a209b, v1
+; VI-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
 ; VI-SDAG-NEXT:    v_mov_b32_e32 v3, s0
 ; VI-SDAG-NEXT:    flat_store_dwordx3 v[3:4], v[0:2]
 ; VI-SDAG-NEXT:    s_endpgm
 ;
 ; VI-GISEL-LABEL: s_log10_v3f32:
 ; VI-GISEL:       ; %bb.0:
 ; VI-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
 ; VI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; VI-GISEL-NEXT:    s_mov_b32 s2, 0x800000
+; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x4f800000
+; VI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x42000000
 ; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT:    v_log_f32_e32 v0, s4
-; VI-GISEL-NEXT:    v_log_f32_e32 v1, s5
-; VI-GISEL-NEXT:    v_log_f32_e32 v2, s6
-; VI-GISEL-NEXT:    v_mov_b32_e32 v4, s1
+; VI-GISEL-NEXT:    v_mov_b32_e32 v0, s4
+; VI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s2, v0
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, 1.0, v1, vcc
+; VI-GISEL-NEXT:    v_mul_f32_e32 v0, s4, v0
+; VI-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v4, 0, v3, vcc
+; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x800000
+; VI-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v4
+; VI-GISEL-NEXT:    v_mov_b32_e32 v4, s5
+; VI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s2, v4
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v4, 1.0, v1, vcc
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v5, 0, v3, vcc
+; VI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, s6, v2
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
+; VI-GISEL-NEXT:    v_mul_f32_e32 v4, s5, v4
+; VI-GISEL-NEXT:    v_mul_f32_e32 v1, s6, v1
+; VI-GISEL-NEXT:    v_log_f32_e32 v4, v4
+; VI-GISEL-NEXT:    v_log_f32_e32 v2, v1
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v3, 0, v3, vcc
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; VI-GISEL-NEXT:    v_sub_f32_e32 v1, v4, v5
+; VI-GISEL-NEXT:    v_sub_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT:    v_mov_b32_e32 v4, s1
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3e9a209b, v1
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v2, 0x3e9a209b, v2
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v3, s0
 ; VI-GISEL-NEXT:    flat_store_dwordx3 v[3:4], v[0:2]
 ; VI-GISEL-NEXT:    s_endpgm
 ;
 ; GFX900-SDAG-LABEL: s_log10_v3f32:
 ; GFX900-SDAG:       ; %bb.0:
 ; GFX900-SDAG-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
-; GFX900-SDAG-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
-; GFX900-SDAG-NEXT:    v_mov_b32_e32 v4, 0
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v0, 0x800000
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GFX900-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX900-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX900-SDAG-NEXT:    v_log_f32_e32 v0, s6
-; GFX900-SDAG-NEXT:    v_log_f32_e32 v1, s5
-; GFX900-SDAG-NEXT:    v_log_f32_e32 v3, s4
-; GFX900-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3e9a209b, v0
+; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s6, v0
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v4, 1.0, v2, vcc
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v4, s6, v4
+; GFX900-SDAG-NEXT:    v_log_f32_e32 v4, v4
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v3, 0, v1, vcc
+; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s5, v0
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v6, 1.0, v2, vcc
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v3, v4, v3
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v4, 0, v1, vcc
+; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v6, s5, v6
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, s4, v1
+; GFX900-SDAG-NEXT:    v_log_f32_e32 v6, v6
+; GFX900-SDAG-NEXT:    v_log_f32_e32 v7, v1
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v5, 0
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3e9a209b, v3
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v1, v6, v4
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v0, v7, v0
 ; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a209b, v1
-; GFX900-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v3
-; GFX900-SDAG-NEXT:    global_store_dwordx3 v4, v[0:2], s[2:3]
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GFX900-SDAG-NEXT:    global_store_dwordx3 v5, v[0:2], s[0:1]
 ; GFX900-SDAG-NEXT:    s_endpgm
 ;
 ; GFX900-GISEL-LABEL: s_log10_v3f32:
 ; GFX900-GISEL:       ; %bb.0:
 ; GFX900-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
-; GFX900-GISEL-NEXT:    v_mov_b32_e32 v3, 0
-; GFX900-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX900-GISEL-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX900-GISEL-NEXT:    s_mov_b32 s0, 0x800000
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0x4f800000
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v3, 0x42000000
 ; GFX900-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX900-GISEL-NEXT:    v_log_f32_e32 v0, s4
-; GFX900-GISEL-NEXT:    v_log_f32_e32 v1, s5
-; GFX900-GISEL-NEXT:    v_log_f32_e32 v2, s6
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v0, s4
+; GFX900-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s0, v0
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v0, 1.0, v1, vcc
+; GFX900-GISEL-NEXT:    v_mul_f32_e32 v0, s4, v0
+; GFX900-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v4, 0, v3, vcc
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x800000
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v4
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v4, s5
+; GFX900-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s0, v4
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v4, 1.0, v1, vcc
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v5, 0, v3, vcc
+; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, s6, v2
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
+; GFX900-GISEL-NEXT:    v_mul_f32_e32 v4, s5, v4
+; GFX900-GISEL-NEXT:    v_mul_f32_e32 v1, s6, v1
+; GFX900-GISEL-NEXT:    v_log_f32_e32 v4, v4
+; GFX900-GISEL-NEXT:    v_log_f32_e32 v2, v1
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v3, 0, v3, vcc
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v1, v4, v5
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v2, v2, v3
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3e9a209b, v1
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v2, 0x3e9a209b, v2
-; GFX900-GISEL-NEXT:    global_store_dwordx3 v3, v[0:2], s[0:1]
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v3, 0
+; GFX900-GISEL-NEXT:    global_store_dwordx3 v3, v[0:2], s[2:3]
 ; GFX900-GISEL-NEXT:    s_endpgm
 ;
 ; R600-LABEL: s_log10_v3f32:
 ; R600:       ; %bb.0:
-; R600-NEXT:    ALU 13, @4, KC0[CB0:0-32], KC1[]
-; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T3.X, T2.X, 0
+; R600-NEXT:    ALU 33, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T2.X, T3.X, 0
 ; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    ALU clause starting at 4:
-; R600-NEXT:     LOG_IEEE * T0.X, KC0[3].Z,
-; R600-NEXT:     MUL_IEEE T0.Y, PS, literal.x,
-; R600-NEXT:     LOG_IEEE * T0.X, KC0[3].Y,
+; R600-NEXT:     SETGT T0.W, literal.x, KC0[3].Z,
+; R600-NEXT:     SETGT * T1.W, literal.x, KC0[3].Y,
+; R600-NEXT:    8388608(1.175494e-38), 0(0.000000e+00)
+; R600-NEXT:     CNDE * T2.W, PV.W, 1.0, literal.x,
+; R600-NEXT:    1333788672(4.294967e+09), 0(0.000000e+00)
+; R600-NEXT:     MUL_IEEE T2.W, KC0[3].Z, PV.W,
+; R600-NEXT:     CNDE * T3.W, T1.W, 1.0, literal.x,
+; R600-NEXT:    1333788672(4.294967e+09), 0(0.000000e+00)
+; R600-NEXT:     MUL_IEEE T0.Y, KC0[3].Y, PS,
+; R600-NEXT:     CNDE T0.Z, T0.W, 0.0, literal.x,
+; R600-NEXT:     SETGT T0.W, literal.y, KC0[3].W,
+; R600-NEXT:     LOG_IEEE * T0.X, PV.W,
+; R600-NEXT:    1107296256(3.200000e+01), 8388608(1.175494e-38)
+; R600-NEXT:     CNDE T1.Y, T1.W, 0.0, literal.x,
+; R600-NEXT:     CNDE T1.Z, PV.W, 1.0, literal.y,
+; R600-NEXT:     ADD T1.W, PS, -PV.Z,
+; R600-NEXT:     LOG_IEEE * T0.X, PV.Y,
+; R600-NEXT:    1107296256(3.200000e+01), 1333788672(4.294967e+09)
+; R600-NEXT:     MUL_IEEE T0.Y, PV.W, literal.x,
+; R600-NEXT:     MUL_IEEE T1.W, KC0[3].W, PV.Z,
+; R600-NEXT:     ADD * T2.W, PS, -PV.Y,
 ; R600-NEXT:    1050288283(3.010300e-01), 0(0.000000e+00)
 ; R600-NEXT:     MUL_IEEE T0.X, PS, literal.x,
-; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.y,
-; R600-NEXT:    1050288283(3.010300e-01), 2(2.802597e-45)
-; R600-NEXT:     ADD_INT * T0.W, KC0[2].Y, literal.x,
-; R600-NEXT:    8(1.121039e-44), 0(0.000000e+00)
-; R600-NEXT:     LSHR T2.X, PV.W, literal.x,
-; R600-NEXT:     LOG_IEEE * T0.Z, KC0[3].W,
+; R600-NEXT:     CNDE T0.W, T0.W, 0.0, literal.y,
+; R600-NEXT:     LOG_IEEE * T0.Z, PV.W,
+; R600-NEXT:    1050288283(3.010300e-01), 1107296256(3.200000e+01)
+; R600-NEXT:     LSHR T1.X, KC0[2].Y, literal.x,
+; R600-NEXT:     ADD * T0.W, PS, -PV.W,
+; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
+; R600-NEXT:     MUL_IEEE T2.X, PV.W, literal.x,
+; R600-NEXT:     ADD_INT * T0.W, KC0[2].Y, literal.y,
+; R600-NEXT:    1050288283(3.010300e-01), 8(1.121039e-44)
+; R600-NEXT:     LSHR * T3.X, PV.W, literal.x,
 ; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
-; R600-NEXT:     MUL_IEEE * T3.X, PS, literal.x,
-; R600-NEXT:    1050288283(3.010300e-01), 0(0.000000e+00)
 ;
 ; CM-LABEL: s_log10_v3f32:
 ; CM:       ; %bb.0:
-; CM-NEXT:    ALU 22, @4, KC0[CB0:0-32], KC1[]
-; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T2, T3.X
-; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X
+; CM-NEXT:    ALU 40, @4, KC0[CB0:0-32], KC1[]
+; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0, T3.X
+; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T2.X, T1.X
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    ALU clause starting at 4:
-; CM-NEXT:     ADD_INT * T0.W, KC0[2].Y, literal.x,
-; CM-NEXT:    8(1.121039e-44), 0(0.000000e+00)
-; CM-NEXT:     LSHR * T0.X, PV.W, literal.x,
-; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
-; CM-NEXT:     LOG_IEEE T0.X (MASKED), KC0[3].Z,
-; CM-NEXT:     LOG_IEEE T0.Y, KC0[3].Z,
-; CM-NEXT:     LOG_IEEE T0.Z (MASKED), KC0[3].Z,
-; CM-NEXT:     LOG_IEEE * T0.W (MASKED), KC0[3].Z,
-; CM-NEXT:     LOG_IEEE T0.X (MASKED), KC0[3].W,
-; CM-NEXT:     LOG_IEEE T0.Y (MASKED), KC0[3].W,
-; CM-NEXT:     LOG_IEEE T0.Z, KC0[3].W,
-; CM-NEXT:     LOG_IEEE * T0.W (MASKED), KC0[3].W,
-; CM-NEXT:     MUL_IEEE T1.X, PV.Z, literal.x,
-; CM-NEXT:     MUL_IEEE * T2.Y, T0.Y, literal.x,
-; CM-NEXT:    1050288283(3.010300e-01), 0(0.000000e+00)
-; CM-NEXT:     LOG_IEEE T0.X (MASKED), KC0[3].Y,
-; CM-NEXT:     LOG_IEEE T0.Y, KC0[3].Y,
-; CM-NEXT:     LOG_IEEE T0.Z (MASKED), KC0[3].Y,
-; CM-NEXT:     LOG_IEEE * T0.W (MASKED), KC0[3].Y,
-; CM-NEXT:     MUL_IEEE * T2.X, PV.Y, literal.x,
+; CM-NEXT:     SETGT * T0.W, literal.x, KC0[3].W,
+; CM-NEXT:    8388608(1.175494e-38), 0(0.000000e+00)
+; CM-NEXT:     CNDE T0.Y, PV.W, 1.0, literal.x,
+; CM-NEXT:     SETGT T0.Z, literal.y, KC0[3].Z,
+; CM-NEXT:     SETGT * T1.W, literal.y, KC0[3].Y,
+; CM-NEXT:    1333788672(4.294967e+09), 8388608(1.175494e-38)
+; CM-NEXT:     CNDE T0.X, PV.W, 0.0, literal.x,
+; CM-NEXT:     CNDE T1.Y, PV.Z, 1.0, literal.y,
+; CM-NEXT:     CNDE T1.Z, T0.W, 0.0, literal.x,
+; CM-NEXT:     MUL_IEEE * T0.W, KC0[3].W, PV.Y,
+; CM-NEXT:    1107296256(3.200000e+01), 1333788672(4.294967e+09)
+; CM-NEXT:     LOG_IEEE T0.X (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE T0.Y, T0.W,
+; CM-NEXT:     LOG_IEEE T0.Z (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE * T0.W (MASKED), T0.W,
+; CM-NEXT:     CNDE T1.X, T1.W, 1.0, literal.x,
+; CM-NEXT:     CNDE T2.Y, T0.Z, 0.0, literal.y,
+; CM-NEXT:     ADD T0.Z, PV.Y, -T1.Z,
+; CM-NEXT:     MUL_IEEE * T0.W, KC0[3].Z, T1.Y,
+; CM-NEXT:    1333788672(4.294967e+09), 1107296256(3.200000e+01)
+; CM-NEXT:     LOG_IEEE T0.X (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE T0.Y, T0.W,
+; CM-NEXT:     LOG_IEEE T0.Z (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE * T0.W (MASKED), T0.W,
+; CM-NEXT:     MUL_IEEE T2.X, T0.Z, literal.x,
+; CM-NEXT:     ADD T0.Y, PV.Y, -T2.Y,
+; CM-NEXT:     ADD_INT T0.Z, KC0[2].Y, literal.y,
+; CM-NEXT:     MUL_IEEE * T0.W, KC0[3].Y, T1.X,
+; CM-NEXT:    1050288283(3.010300e-01), 8(1.121039e-44)
+; CM-NEXT:     LOG_IEEE T0.X (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE T0.Y (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE T0.Z (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE * T0.W, T0.W,
+; CM-NEXT:     LSHR T1.X, T0.Z, literal.x,
+; CM-NEXT:     MUL_IEEE T0.Y, T0.Y, literal.y,
+; CM-NEXT:     ADD * T0.W, PV.W, -T0.X,
+; CM-NEXT:    2(2.802597e-45), 1050288283(3.010300e-01)
+; CM-NEXT:     MUL_IEEE * T0.X, PV.W, literal.x,
 ; CM-NEXT:    1050288283(3.010300e-01), 0(0.000000e+00)
 ; CM-NEXT:     LSHR * T3.X, KC0[2].Y, literal.x,
 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
   %result = call <3 x float> @llvm.log10.v3f32(<3 x float> %in)
   store <3 x float> %result, ptr addrspace(1) %out
   ret void
 }
 
 ; FIXME: We should be able to merge these packets together on Cayman so we
 ; have a maximum of 4 instructions.
 define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
 ; SI-SDAG-LABEL: s_log10_v4f32:
 ; SI-SDAG:       ; %bb.0:
 ; SI-SDAG-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xd
 ; SI-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SI-SDAG-NEXT:    v_mov_b32_e32 v0, 0x800000
+; SI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; SI-SDAG-NEXT:    v_mov_b32_e32 v4, 0x4f800000
+; SI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
+; SI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s7, v0
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v2, 0, v1, vcc
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v3, 1.0, v4, vcc
+; SI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s6, v0
+; SI-SDAG-NEXT:    v_mul_f32_e32 v3, s7, v3
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v6, 1.0, v4, vcc
+; SI-SDAG-NEXT:    v_log_f32_e32 v3, v3
+; SI-SDAG-NEXT:    v_mul_f32_e32 v6, s6, v6
+; SI-SDAG-NEXT:    v_log_f32_e32 v6, v6
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v5, 0, v1, vcc
+; SI-SDAG-NEXT:    v_sub_f32_e32 v2, v3, v2
+; SI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s5, v0
+; SI-SDAG-NEXT:    v_mul_f32_e32 v3, 0x3e9a209b, v2
+; SI-SDAG-NEXT:    v_sub_f32_e32 v2, v6, v5
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v5, 0, v1, vcc
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v6, 1.0, v4, vcc
+; SI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v4, vcc
+; SI-SDAG-NEXT:    v_mul_f32_e32 v6, s5, v6
+; SI-SDAG-NEXT:    v_mul_f32_e32 v1, s4, v1
+; SI-SDAG-NEXT:    v_log_f32_e32 v6, v6
+; SI-SDAG-NEXT:    v_log_f32_e32 v4, v1
 ; SI-SDAG-NEXT:    s_mov_b32 s3, 0xf000
 ; SI-SDAG-NEXT:    s_mov_b32 s2, -1
-; SI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-SDAG-NEXT:    v_log_f32_e32 v0, s7
-; SI-SDAG-NEXT:    v_log_f32_e32 v1, s6
-; SI-SDAG-NEXT:    v_log_f32_e32 v4, s5
-; SI-SDAG-NEXT:    v_log_f32_e32 v5, s4
-; SI-SDAG-NEXT:    v_mul_f32_e32 v3, 0x3e9a209b, v0
-; SI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3e9a209b, v1
-; SI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a209b, v4
-; SI-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v5
+; SI-SDAG-NEXT:    v_sub_f32_e32 v1, v6, v5
+; SI-SDAG-NEXT:    v_sub_f32_e32 v0, v4, v0
+; SI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3e9a209b, v2
+; SI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a209b, v1
+; SI-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
 ; SI-SDAG-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
 ; SI-SDAG-NEXT:    s_endpgm
 ;
 ; SI-GISEL-LABEL: s_log10_v4f32:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xd
 ; SI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; SI-GISEL-NEXT:    s_mov_b32 s2, -1
-; SI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT:    s_mov_b32 s2, 0x800000
+; SI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x4f800000
+; SI-GISEL-NEXT:    v_mov_b32_e32 v4, 0x42000000
 ; SI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-GISEL-NEXT:    v_log_f32_e32 v0, s4
-; SI-GISEL-NEXT:    v_log_f32_e32 v1, s5
-; SI-GISEL-NEXT:    v_log_f32_e32 v2, s6
-; SI-GISEL-NEXT:    v_log_f32_e32 v3, s7
+; SI-GISEL-NEXT:    v_mov_b32_e32 v0, s4
+; SI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s2, v0
+; SI-GISEL-NEXT:    v_mov_b32_e32 v5, s5
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v0, 1.0, v3, vcc
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v4, vcc
+; SI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s2, v5
+; SI-GISEL-NEXT:    v_mul_f32_e32 v0, s4, v0
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v5, 1.0, v3, vcc
+; SI-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT:    v_mul_f32_e32 v5, s5, v5
+; SI-GISEL-NEXT:    v_log_f32_e32 v5, v5
+; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x800000
+; SI-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v4, vcc
+; SI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, s6, v2
+; SI-GISEL-NEXT:    v_sub_f32_e32 v1, v5, v1
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v5, 1.0, v3, vcc
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v6, 0, v4, vcc
+; SI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, s7, v2
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v2, 1.0, v3, vcc
+; SI-GISEL-NEXT:    v_mul_f32_e32 v5, s6, v5
+; SI-GISEL-NEXT:    v_mul_f32_e32 v2, s7, v2
+; SI-GISEL-NEXT:    v_log_f32_e32 v5, v5
+; SI-GISEL-NEXT:    v_log_f32_e32 v3, v2
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v4, 0, v4, vcc
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; SI-GISEL-NEXT:    v_sub_f32_e32 v2, v5, v6
+; SI-GISEL-NEXT:    v_sub_f32_e32 v3, v3, v4
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3e9a209b, v1
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v2, 0x3e9a209b, v2
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3e9a209b, v3
+; SI-GISEL-NEXT:    s_mov_b32 s2, -1
+; SI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
 ; SI-GISEL-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
 ; SI-GISEL-NEXT:    s_endpgm
 ;
 ; VI-SDAG-LABEL: s_log10_v4f32:
 ; VI-SDAG:       ; %bb.0:
 ; VI-SDAG-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
+; VI-SDAG-NEXT:    v_mov_b32_e32 v0, 0x800000
+; VI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; VI-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
 ; VI-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; VI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT:    v_log_f32_e32 v0, s7
-; VI-SDAG-NEXT:    v_log_f32_e32 v1, s6
-; VI-SDAG-NEXT:    v_log_f32_e32 v4, s5
-; VI-SDAG-NEXT:    v_log_f32_e32 v5, s4
-; VI-SDAG-NEXT:    v_mul_f32_e32 v3, 0x3e9a209b, v0
-; VI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3e9a209b, v1
-; VI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a209b, v4
-; VI-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v5
+; VI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s7, v0
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v3, 0, v1, vcc
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v4, 1.0, v2, vcc
+; VI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s6, v0
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v6, 1.0, v2, vcc
+; VI-SDAG-NEXT:    v_mul_f32_e32 v4, s7, v4
+; VI-SDAG-NEXT:    v_mul_f32_e32 v6, s6, v6
+; VI-SDAG-NEXT:    v_log_f32_e32 v4, v4
+; VI-SDAG-NEXT:    v_log_f32_e32 v6, v6
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v5, 0, v1, vcc
+; VI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s5, v0
+; VI-SDAG-NEXT:    v_sub_f32_e32 v3, v4, v3
+; VI-SDAG-NEXT:    v_sub_f32_e32 v4, v6, v5
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v5, 0, v1, vcc
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v6, 1.0, v2, vcc
+; VI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; VI-SDAG-NEXT:    v_mul_f32_e32 v6, s5, v6
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, s4, v1
+; VI-SDAG-NEXT:    v_log_f32_e32 v6, v6
+; VI-SDAG-NEXT:    v_log_f32_e32 v7, v1
+; VI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3e9a209b, v4
+; VI-SDAG-NEXT:    v_mul_f32_e32 v3, 0x3e9a209b, v3
+; VI-SDAG-NEXT:    v_sub_f32_e32 v1, v6, v5
+; VI-SDAG-NEXT:    v_sub_f32_e32 v0, v7, v0
 ; VI-SDAG-NEXT:    v_mov_b32_e32 v5, s1
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a209b, v1
+; VI-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
 ; VI-SDAG-NEXT:    v_mov_b32_e32 v4, s0
 ; VI-SDAG-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
 ; VI-SDAG-NEXT:    s_endpgm
 ;
 ; VI-GISEL-LABEL: s_log10_v4f32:
 ; VI-GISEL:       ; %bb.0:
 ; VI-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
 ; VI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; VI-GISEL-NEXT:    s_mov_b32 s2, 0x800000
+; VI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x4f800000
+; VI-GISEL-NEXT:    v_mov_b32_e32 v4, 0x42000000
 ; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT:    v_log_f32_e32 v0, s4
-; VI-GISEL-NEXT:    v_log_f32_e32 v1, s5
-; VI-GISEL-NEXT:    v_log_f32_e32 v2, s6
-; VI-GISEL-NEXT:    v_log_f32_e32 v3, s7
-; VI-GISEL-NEXT:    v_mov_b32_e32 v5, s1
+; VI-GISEL-NEXT:    v_mov_b32_e32 v0, s4
+; VI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s2, v0
+; VI-GISEL-NEXT:    v_mov_b32_e32 v5, s5
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, 1.0, v3, vcc
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v4, vcc
+; VI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s2, v5
+; VI-GISEL-NEXT:    v_mul_f32_e32 v0, s4, v0
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v5, 1.0, v3, vcc
+; VI-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT:    v_mul_f32_e32 v5, s5, v5
+; VI-GISEL-NEXT:    v_log_f32_e32 v5, v5
+; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x800000
+; VI-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v4, vcc
+; VI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, s6, v2
+; VI-GISEL-NEXT:    v_sub_f32_e32 v1, v5, v1
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v5, 1.0, v3, vcc
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v6, 0, v4, vcc
+; VI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, s7, v2
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v2, 1.0, v3, vcc
+; VI-GISEL-NEXT:    v_mul_f32_e32 v5, s6, v5
+; VI-GISEL-NEXT:    v_mul_f32_e32 v2, s7, v2
+; VI-GISEL-NEXT:    v_log_f32_e32 v5, v5
+; VI-GISEL-NEXT:    v_log_f32_e32 v3, v2
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v4, 0, v4, vcc
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; VI-GISEL-NEXT:    v_sub_f32_e32 v2, v5, v6
+; VI-GISEL-NEXT:    v_sub_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT:    v_mov_b32_e32 v5, s1
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3e9a209b, v1
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v2, 0x3e9a209b, v2
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3e9a209b, v3
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v4, s0
 ; VI-GISEL-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
 ; VI-GISEL-NEXT:    s_endpgm
 ;
 ; GFX900-SDAG-LABEL: s_log10_v4f32:
 ; GFX900-SDAG:       ; %bb.0:
 ; GFX900-SDAG-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
 ; GFX900-SDAG-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
-; GFX900-SDAG-NEXT:    v_mov_b32_e32 v4, 0
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v0, 0x800000
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v4, 0x4f800000
 ; GFX900-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX900-SDAG-NEXT:    v_log_f32_e32 v0, s7
-; GFX900-SDAG-NEXT:    v_log_f32_e32 v1, s6
-; GFX900-SDAG-NEXT:    v_log_f32_e32 v5, s5
-; GFX900-SDAG-NEXT:    v_log_f32_e32 v6, s4
-; GFX900-SDAG-NEXT:    v_mul_f32_e32 v3, 0x3e9a209b, v0
-; GFX900-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3e9a209b, v1
-; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a209b, v5
-; GFX900-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v6
-; GFX900-SDAG-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3]
+; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s7, v0
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v2, 0, v1, vcc
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v3, 1.0, v4, vcc
+; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s6, v0
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v3, s7, v3
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v6, 1.0, v4, vcc
+; GFX900-SDAG-NEXT:    v_log_f32_e32 v3, v3
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v6, s6, v6
+; GFX900-SDAG-NEXT:    v_log_f32_e32 v6, v6
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v5, 0, v1, vcc
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v2, v3, v2
+; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s5, v0
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v3, 0x3e9a209b, v2
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v2, v6, v5
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v5, 0, v1, vcc
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v6, 1.0, v4, vcc
+; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v4, vcc
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v6, s5, v6
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, s4, v1
+; GFX900-SDAG-NEXT:    v_log_f32_e32 v6, v6
+; GFX900-SDAG-NEXT:    v_log_f32_e32 v4, v1
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v7, 0
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3e9a209b, v2
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v1, v6, v5
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v0, v4, v0
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a209b, v1
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GFX900-SDAG-NEXT:    global_store_dwordx4 v7, v[0:3], s[2:3]
 ; GFX900-SDAG-NEXT:    s_endpgm
 ;
 ; GFX900-GISEL-LABEL: s_log10_v4f32:
 ; GFX900-GISEL:       ; %bb.0:
 ; GFX900-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
 ; GFX900-GISEL-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
-; GFX900-GISEL-NEXT:    v_mov_b32_e32 v4, 0
+; GFX900-GISEL-NEXT:    s_mov_b32 s0, 0x800000
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v3, 0x4f800000
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v4, 0x42000000
 ; GFX900-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX900-GISEL-NEXT:    v_log_f32_e32 v0, s4
-; GFX900-GISEL-NEXT:    v_log_f32_e32 v1, s5
-; GFX900-GISEL-NEXT:    v_log_f32_e32 v2, s6
-; GFX900-GISEL-NEXT:    v_log_f32_e32 v3, s7
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v0, s4
+; GFX900-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s0, v0
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v5, s5
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v0, 1.0, v3, vcc
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v4, vcc
+; GFX900-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s0, v5
+; GFX900-GISEL-NEXT:    v_mul_f32_e32 v0, s4, v0
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v5, 1.0, v3, vcc
+; GFX900-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT:    v_mul_f32_e32 v5, s5, v5
+; GFX900-GISEL-NEXT:    v_log_f32_e32 v5, v5
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x800000
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v4, vcc
+; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, s6, v2
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v1, v5, v1
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v5, 1.0, v3, vcc
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v6, 0, v4, vcc
+; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, s7, v2
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v2, 1.0, v3, vcc
+; GFX900-GISEL-NEXT:    v_mul_f32_e32 v5, s6, v5
+; GFX900-GISEL-NEXT:    v_mul_f32_e32 v2, s7, v2
+; GFX900-GISEL-NEXT:    v_log_f32_e32 v5, v5
+; GFX900-GISEL-NEXT:    v_log_f32_e32 v3, v2
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v4, 0, v4, vcc
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v2, v5, v6
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v3, v3, v4
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3e9a209b, v1
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v2, 0x3e9a209b, v2
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3e9a209b, v3
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX900-GISEL-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3]
 ; GFX900-GISEL-NEXT:    s_endpgm
 ;
 ; R600-LABEL: s_log10_v4f32:
 ; R600:       ; %bb.0:
-; R600-NEXT:    ALU 12, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT:    ALU 38, @4, KC0[CB0:0-32], KC1[]
 ; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ; R600-NEXT:    ALU clause starting at 4:
-; R600-NEXT:     LOG_IEEE * T0.X, KC0[4].X,
-; R600-NEXT:     MUL_IEEE T0.W, PS, literal.x,
-; R600-NEXT:     LOG_IEEE * T0.X, KC0[3].W,
-; R600-NEXT:    1050288283(3.010300e-01), 0(0.000000e+00)
-; R600-NEXT:     MUL_IEEE T0.Z, PS, literal.x,
-; R600-NEXT:     LOG_IEEE * T0.X, KC0[3].Z,
+; R600-NEXT:     SETGT T0.W, literal.x, KC0[4].X,
+; R600-NEXT:     SETGT * T1.W, literal.x, KC0[3].W,
+; R600-NEXT:    8388608(1.175494e-38), 0(0.000000e+00)
+; R600-NEXT:     CNDE * T2.W, PV.W, 1.0, literal.x,
+; R600-NEXT:    1333788672(4.294967e+09), 0(0.000000e+00)
+; R600-NEXT:     MUL_IEEE T0.Z, KC0[4].X, PV.W,
+; R600-NEXT:     SETGT T2.W, literal.x, KC0[3].Z,
+; R600-NEXT:     CNDE * T3.W, T1.W, 1.0, literal.y,
+; R600-NEXT:    8388608(1.175494e-38), 1333788672(4.294967e+09)
+; R600-NEXT:     MUL_IEEE T0.X, KC0[3].W, PS,
+; R600-NEXT:     SETGT T0.Y, literal.x, KC0[3].Y,
+; R600-NEXT:     CNDE T1.Z, T0.W, 0.0, literal.y,
+; R600-NEXT:     CNDE T0.W, PV.W, 1.0, literal.z,
+; R600-NEXT:     LOG_IEEE * T0.Z, PV.Z,
+; R600-NEXT:    8388608(1.175494e-38), 1107296256(3.200000e+01)
+; R600-NEXT:    1333788672(4.294967e+09), 0(0.000000e+00)
+; R600-NEXT:     MUL_IEEE T1.X, KC0[3].Z, PV.W,
+; R600-NEXT:     ADD T1.Y, PS, -PV.Z,
+; R600-NEXT:     CNDE T0.Z, T1.W, 0.0, literal.x,
+; R600-NEXT:     CNDE T0.W, PV.Y, 1.0, literal.y,
+; R600-NEXT:     LOG_IEEE * T0.X, PV.X,
+; R600-NEXT:    1107296256(3.200000e+01), 1333788672(4.294967e+09)
+; R600-NEXT:     MUL_IEEE T2.X, KC0[3].Y, PV.W,
+; R600-NEXT:     CNDE T2.Y, T2.W, 0.0, literal.x,
+; R600-NEXT:     ADD T0.Z, PS, -PV.Z,
+; R600-NEXT:     MUL_IEEE T0.W, PV.Y, literal.y,
+; R600-NEXT:     LOG_IEEE * T0.X, PV.X,
+; R600-NEXT:    1107296256(3.200000e+01), 1050288283(3.010300e-01)
+; R600-NEXT:     CNDE T1.Y, T0.Y, 0.0, literal.x,
+; R600-NEXT:     MUL_IEEE T0.Z, PV.Z, literal.y,
+; R600-NEXT:     ADD T1.W, PS, -PV.Y,
+; R600-NEXT:     LOG_IEEE * T0.X, PV.X,
+; R600-NEXT:    1107296256(3.200000e+01), 1050288283(3.010300e-01)
+; R600-NEXT:     MUL_IEEE T0.Y, PV.W, literal.x,
+; R600-NEXT:     ADD * T1.W, PS, -PV.Y,
 ; R600-NEXT:    1050288283(3.010300e-01), 0(0.000000e+00)
-; R600-NEXT:     MUL_IEEE T0.Y, PS, literal.x,
-; R600-NEXT:     LOG_IEEE * T0.X, KC0[3].Y,
-; R600-NEXT:    1050288283(3.010300e-01), 0(0.000000e+00)
-; R600-NEXT:     MUL_IEEE T0.X, PS, literal.x,
+; R600-NEXT:     MUL_IEEE T0.X, PV.W, literal.x,
 ; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.y,
 ; R600-NEXT:    1050288283(3.010300e-01), 2(2.802597e-45)
 ;
 ; CM-LABEL: s_log10_v4f32:
 ; CM:       ; %bb.0:
-; CM-NEXT:    ALU 25, @4, KC0[CB0:0-32], KC1[]
-; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0, T1.X
+; CM-NEXT:    ALU 50, @4, KC0[CB0:0-32], KC1[]
+; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T1, T0.X
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
 ; CM-NEXT:    ALU clause starting at 4:
-; CM-NEXT:     LOG_IEEE T0.X, KC0[4].X,
-; CM-NEXT:     LOG_IEEE T0.Y (MASKED), KC0[4].X,
-; CM-NEXT:     LOG_IEEE T0.Z (MASKED), KC0[4].X,
-; CM-NEXT:     LOG_IEEE * T0.W (MASKED), KC0[4].X,
-; CM-NEXT:     MUL_IEEE * T0.W, PV.X, literal.x,
+; CM-NEXT:     SETGT T0.Z, literal.x, KC0[4].X,
+; CM-NEXT:     SETGT * T0.W, literal.x, KC0[3].Y,
+; CM-NEXT:    8388608(1.175494e-38), 0(0.000000e+00)
+; CM-NEXT:     CNDE T0.Y, PV.W, 1.0, literal.x,
+; CM-NEXT:     CNDE T1.Z, PV.Z, 1.0, literal.x,
+; CM-NEXT:     SETGT * T1.W, literal.y, KC0[3].W,
+; CM-NEXT:    1333788672(4.294967e+09), 8388608(1.175494e-38)
+; CM-NEXT:     CNDE T0.X, PV.W, 1.0, literal.x,
+; CM-NEXT:     SETGT T1.Y, literal.y, KC0[3].Z,
+; CM-NEXT:     CNDE T0.Z, T0.Z, 0.0, literal.z,
+; CM-NEXT:     MUL_IEEE * T2.W, KC0[4].X, PV.Z,
+; CM-NEXT:    1333788672(4.294967e+09), 8388608(1.175494e-38)
+; CM-NEXT:    1107296256(3.200000e+01), 0(0.000000e+00)
+; CM-NEXT:     LOG_IEEE T1.X, T2.W,
+; CM-NEXT:     LOG_IEEE T1.Y (MASKED), T2.W,
+; CM-NEXT:     LOG_IEEE T1.Z (MASKED), T2.W,
+; CM-NEXT:     LOG_IEEE * T1.W (MASKED), T2.W,
+; CM-NEXT:     ADD T1.X, PV.X, -T0.Z,
+; CM-NEXT:     CNDE T2.Y, T1.Y, 1.0, literal.x,
+; CM-NEXT:     CNDE T0.Z, T1.W, 0.0, literal.y,
+; CM-NEXT:     MUL_IEEE * T1.W, KC0[3].W, T0.X,
+; CM-NEXT:    1333788672(4.294967e+09), 1107296256(3.200000e+01)
+; CM-NEXT:     LOG_IEEE T0.X, T1.W,
+; CM-NEXT:     LOG_IEEE T0.Y (MASKED), T1.W,
+; CM-NEXT:     LOG_IEEE T0.Z (MASKED), T1.W,
+; CM-NEXT:     LOG_IEEE * T0.W (MASKED), T1.W,
+; CM-NEXT:     ADD T0.X, PV.X, -T0.Z,
+; CM-NEXT:     CNDE T1.Y, T1.Y, 0.0, literal.x,
+; CM-NEXT:     MUL_IEEE T0.Z, KC0[3].Z, T2.Y,
+; CM-NEXT:     MUL_IEEE * T1.W, T1.X, literal.y,
+; CM-NEXT:    1107296256(3.200000e+01), 1050288283(3.010300e-01)
+; CM-NEXT:     LOG_IEEE T0.X (MASKED), T0.Z,
+; CM-NEXT:     LOG_IEEE T0.Y (MASKED), T0.Z,
+; CM-NEXT:     LOG_IEEE T0.Z, T0.Z,
+; CM-NEXT:     LOG_IEEE * T0.W (MASKED), T0.Z,
+; CM-NEXT:     CNDE T1.X, T0.W, 0.0, literal.x,
+; CM-NEXT:     ADD T1.Y, PV.Z, -T1.Y,
+; CM-NEXT:     MUL_IEEE T1.Z, T0.X, literal.y,
+; CM-NEXT:     MUL_IEEE * T0.W, KC0[3].Y, T0.Y, BS:VEC_021/SCL_122
+; CM-NEXT:    1107296256(3.200000e+01), 1050288283(3.010300e-01)
+; CM-NEXT:     LOG_IEEE T0.X, T0.W,
+; CM-NEXT:     LOG_IEEE T0.Y (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE T0.Z (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE * T0.W (MASKED), T0.W,
+; CM-NEXT:     MUL_IEEE T1.Y, T1.Y, literal.x,
+; CM-NEXT:     ADD * T0.W, PV.X, -T1.X,
 ; CM-NEXT:    1050288283(3.010300e-01), 0(0.000000e+00)
-; CM-NEXT:     LOG_IEEE T0.X, KC0[3].W,
-; CM-NEXT:     LOG_IEEE T0.Y (MASKED), KC0[3].W,
-; CM-NEXT:     LOG_IEEE T0.Z (MASKED), KC0[3].W,
-; CM-NEXT:     LOG_IEEE * T0.W (MASKED), KC0[3].W,
-; CM-NEXT:     MUL_IEEE * T0.Z, PV.X, literal.x,
+; CM-NEXT:     MUL_IEEE * T1.X, PV.W, literal.x,
 ; CM-NEXT:    1050288283(3.010300e-01), 0(0.000000e+00)
-; CM-NEXT:     LOG_IEEE T0.X, KC0[3].Z,
-; CM-NEXT:     LOG_IEEE T0.Y (MASKED), KC0[3].Z,
-; CM-NEXT:     LOG_IEEE T0.Z (MASKED), KC0[3].Z,
-; CM-NEXT:     LOG_IEEE * T0.W (MASKED), KC0[3].Z,
-; CM-NEXT:     MUL_IEEE * T0.Y, PV.X, literal.x,
-; CM-NEXT:    1050288283(3.010300e-01), 0(0.000000e+00)
-; CM-NEXT:     LOG_IEEE T0.X, KC0[3].Y,
-; CM-NEXT:     LOG_IEEE T0.Y (MASKED), KC0[3].Y,
-; CM-NEXT:     LOG_IEEE T0.Z (MASKED), KC0[3].Y,
-; CM-NEXT:     LOG_IEEE * T0.W (MASKED), KC0[3].Y,
-; CM-NEXT:     MUL_IEEE * T0.X, PV.X, literal.x,
-; CM-NEXT:    1050288283(3.010300e-01), 0(0.000000e+00)
-; CM-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
+; CM-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
   %result = call <4 x float> @llvm.log10.v4f32(<4 x float> %in)
   store <4 x float> %result, ptr addrspace(1) %out
   ret void
 }
 
 define float @v_log10_f32(float %in) {
-; GCN-LABEL: v_log10_f32:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, v0
-; GCN-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log10_f32:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x800000
+; GCN-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log10_f32:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log10_f32:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log10_f32:
 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %result = call float @llvm.log10.f32(float %in)
   ret float %result
 }
 
 define float @v_log10_fabs_f32(float %in) {
-; GCN-LABEL: v_log10_fabs_f32:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e64 v0, |v0|
-; GCN-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log10_fabs_f32:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x800000
+; GCN-SDAG-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e64 v0, |v0|, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log10_fabs_f32:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-GISEL-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v1
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-GISEL-NEXT:    v_mul_f32_e64 v0, |v0|, v1
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log10_fabs_f32:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log10_fabs_f32:
 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %fabs = call float @llvm.fabs.f32(float %in)
   %result = call float @llvm.log10.f32(float %fabs)
   ret float %result
 }
 
 define float @v_log10_fneg_fabs_f32(float %in) {
-; GCN-LABEL: v_log10_fneg_fabs_f32:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e64 v0, -|v0|
-; GCN-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log10_fneg_fabs_f32:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x80800000
+; GCN-SDAG-NEXT:    v_cmp_gt_f32_e64 vcc, |v0|, s4
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e64 v0, -|v0|, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log10_fneg_fabs_f32:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-GISEL-NEXT:    v_cmp_lt_f32_e64 vcc, -|v0|, v1
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-GISEL-NEXT:    v_mul_f32_e64 v0, -|v0|, v1
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log10_fneg_fabs_f32:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log10_fneg_fabs_f32:
 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %fabs = call float @llvm.fabs.f32(float %in)
   %fneg.fabs = fneg float %fabs
   %result = call float @llvm.log10.f32(float %fneg.fabs)
   ret float %result
 }
 
 define float @v_log10_fneg_f32(float %in) {
-; GCN-LABEL: v_log10_fneg_f32:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e64 v0, -v0
-; GCN-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log10_fneg_f32:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x80800000
+; GCN-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s4, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e64 v0, -v0, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log10_fneg_f32:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-GISEL-NEXT:    v_cmp_lt_f32_e64 vcc, -v0, v1
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-GISEL-NEXT:    v_mul_f32_e64 v0, -v0, v1
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log10_fneg_f32:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log10_fneg_f32:
 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %fneg = fneg float %in
   %result = call float @llvm.log10.f32(float %fneg)
   ret float %result
 }
 
 define float @v_log10_f32_fast(float %in) {
-; GCN-LABEL: v_log10_f32_fast:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, v0
-; GCN-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log10_f32_fast:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x800000
+; GCN-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log10_f32_fast:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log10_f32_fast:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log10_f32_fast:
 ; CM:       ; %bb.0:

 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %result = call float @llvm.log10.f32(float %in)
   ret float %result
 }
 
 define float @v_log10_f32_ninf(float %in) {
-; GCN-LABEL: v_log10_f32_ninf:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, v0
-; GCN-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log10_f32_ninf:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x800000
+; GCN-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log10_f32_ninf:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log10_f32_ninf:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log10_f32_ninf:
 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %result = call ninf float @llvm.log10.f32(float %in)
   ret float %result
 }
 
 define float @v_log10_f32_afn(float %in) {
-; GCN-LABEL: v_log10_f32_afn:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, v0
-; GCN-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log10_f32_afn:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x800000
+; GCN-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log10_f32_afn:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log10_f32_afn:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log10_f32_afn:
 ; CM:       ; %bb.0:

 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %result = call afn float @llvm.log10.f32(float %in)
   ret float %result
 }
 
 define float @v_log10_f32_afn_dynamic(float %in) #1 {
-; GCN-LABEL: v_log10_f32_afn_dynamic:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, v0
-; GCN-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log10_f32_afn_dynamic:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x800000
+; GCN-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log10_f32_afn_dynamic:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log10_f32_afn_dynamic:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log10_f32_afn_dynamic:
 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %result = call afn float @llvm.log10.f32(float %in)
   ret float %result
 }
 
 define float @v_fabs_log10_f32_afn(float %in) {
-; GCN-LABEL: v_fabs_log10_f32_afn:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e64 v0, |v0|
-; GCN-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_fabs_log10_f32_afn:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x800000
+; GCN-SDAG-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e64 v0, |v0|, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_fabs_log10_f32_afn:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_log_f32_e64 v0, |v0|
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_fabs_log10_f32_afn:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_fabs_log10_f32_afn:
 ; CM:       ; %bb.0:

 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %result = call float @llvm.log10.f32(float %in)
   ret float %result
 }
 
 define float @v_log10_f32_nnan(float %in) {
-; GCN-LABEL: v_log10_f32_nnan:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, v0
-; GCN-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log10_f32_nnan:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x800000
+; GCN-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log10_f32_nnan:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log10_f32_nnan:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log10_f32_nnan:
 ; CM:       ; %bb.0:

 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %result = call nnan float @llvm.log10.f32(float %in)
   ret float %result
 }
 
 define float @v_log10_f32_nnan_dynamic(float %in) #1 {
-; GCN-LABEL: v_log10_f32_nnan_dynamic:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, v0
-; GCN-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log10_f32_nnan_dynamic:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x800000
+; GCN-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log10_f32_nnan_dynamic:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log10_f32_nnan_dynamic:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log10_f32_nnan_dynamic:
 ; CM:       ; %bb.0:

 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %result = call ninf float @llvm.log10.f32(float %in)
   ret float %result
 }
 
 define float @v_log10_f32_ninf_dynamic(float %in) #1 {
-; GCN-LABEL: v_log10_f32_ninf_dynamic:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, v0
-; GCN-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log10_f32_ninf_dynamic:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x800000
+; GCN-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log10_f32_ninf_dynamic:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log10_f32_ninf_dynamic:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log10_f32_ninf_dynamic:
 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %result = call ninf float @llvm.log10.f32(float %in)
   ret float %result
 }
 
 define float @v_log10_f32_nnan_ninf(float %in) {
-; GCN-LABEL: v_log10_f32_nnan_ninf:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, v0
-; GCN-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log10_f32_nnan_ninf:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x800000
+; GCN-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log10_f32_nnan_ninf:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log10_f32_nnan_ninf:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log10_f32_nnan_ninf:
 ; CM:       ; %bb.0:

 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %result = call nnan ninf float @llvm.log10.f32(float %in)
   ret float %result
 }
 
 define float @v_log10_f32_nnan_ninf_dynamic(float %in) #1 {
-; GCN-LABEL: v_log10_f32_nnan_ninf_dynamic:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, v0
-; GCN-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log10_f32_nnan_ninf_dynamic:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x800000
+; GCN-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log10_f32_nnan_ninf_dynamic:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log10_f32_nnan_ninf_dynamic:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log10_f32_nnan_ninf_dynamic:
 ; CM:       ; %bb.0:

 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %result = call fast float @llvm.log10.f32(float %in)
   ret float %result
 }
 
 define float @v_log10_f32_dynamic_mode(float %in) #1 {
-; GCN-LABEL: v_log10_f32_dynamic_mode:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, v0
-; GCN-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log10_f32_dynamic_mode:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x800000
+; GCN-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log10_f32_dynamic_mode:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log10_f32_dynamic_mode:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log10_f32_dynamic_mode:
 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %result = call float @llvm.log10.f32(float %in)
   ret float %result
 }
 
 define float @v_log10_f32_undef() {
-; GCN-LABEL: v_log10_f32_undef:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, s4
-; GCN-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log10_f32_undef:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, s4
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log10_f32_undef:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v0, 0x800000
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x4f800000
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v1, s4, v1
+; GCN-GISEL-NEXT:    v_mul_f32_e64 v2, s4, 1.0
+; GCN-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, s4, v0
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log10_f32_undef:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log10_f32_undef:
 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %result = call float @llvm.log10.f32(float undef)
   ret float %result
 }
 
 define float @v_log10_f32_0() {
 ; GCN-SDAG-LABEL: v_log10_f32_0:
 ; GCN-SDAG:       ; %bb.0:
 ; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-SDAG-NEXT:    v_log_f32_e32 v0, 0
+; GCN-SDAG-NEXT:    v_add_f32_e32 v0, 0xc2000000, v0
 ; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
 ; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GCN-GISEL-LABEL: v_log10_f32_0:
 ; GCN-GISEL:       ; %bb.0:
 ; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-GISEL-NEXT:    v_mov_b32_e32 v0, 0x3e9a209b
-; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, 0xff800000, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v0, 0x800000
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x4f800000
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v1, 0, v1
+; GCN-GISEL-NEXT:    v_mul_f32_e64 v2, 0, 1.0
+; GCN-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, 0, v0
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
 ; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log10_f32_0:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log10_f32_0:

 }
 
 define float @v_log10_f32_from_fpext_math_f16(i16 %src0.i, i16 %src1.i) {
 ; SI-SDAG-LABEL: v_log10_f32_from_fpext_math_f16:
 ; SI-SDAG:       ; %bb.0:
 ; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-SDAG-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; SI-SDAG-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; SI-SDAG-NEXT:    s_mov_b32 s4, 0x800000
 ; SI-SDAG-NEXT:    v_add_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x4f800000
+; SI-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
+; SI-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; SI-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; SI-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
 ; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-GISEL-LABEL: v_log10_f32_from_fpext_math_f16:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-GISEL-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; SI-GISEL-NEXT:    v_cvt_f32_f16_e32 v1, v1
; CM-NEXT:    PAD
   %result = call float @llvm.log10.f32(float %fpext)
   ret float %result
 }
 
 define float @v_log10_f32_from_fpext_bf16(bfloat %src) {
 ; GCN-SDAG-LABEL: v_log10_f32_from_fpext_bf16:
 ; GCN-SDAG:       ; %bb.0:
 ; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x800000
+; GCN-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v2
 ; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209b, v0
 ; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GCN-GISEL-LABEL: v_log10_f32_from_fpext_bf16:
 ; GCN-GISEL:       ; %bb.0:
 ; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-GISEL-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0

 declare half @llvm.fabs.f16(half) #2
 declare half @llvm.log10.f16(half) #2
 declare <2 x half> @llvm.log10.v2f16(<2 x half>) #2
 declare <2 x half> @llvm.fabs.v2f16(<2 x half>) #2
 
 attributes #0 = { "denormal-fp-math-f32"="ieee,preserve-sign" }
 attributes #1 = { "denormal-fp-math-f32"="dynamic,dynamic" }
 attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; SI: {{.*}}

llvm/test/CodeGen/AMDGPU/llvm.log2.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc -global-isel=0 -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,SI,GCN-SDAG,SI-SDAG %s
 ; RUN: llc -global-isel=1 -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,SI,GCN-GISEL,SI-GISEL %s
 ; RUN: llc -global-isel=0 -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,VI,GCN-SDAG,VI-SDAG %s
 ; RUN: llc -global-isel=1 -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,VI,GCN-GISEL,VI-GISEL %s
 ; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX900,GCN-SDAG,GFX900-SDAG %s
 ; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX900,GCN-GISEL,GFX900-GISEL %s
 
 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s
 ; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s
 
 define amdgpu_kernel void @s_log2_f32(ptr addrspace(1) %out, float %in) {
-; SI-LABEL: s_log2_f32:
-; SI:       ; %bb.0:
-; SI-NEXT:    s_load_dword s2, s[0:1], 0xb
-; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; SI-NEXT:    s_mov_b32 s3, 0xf000
-; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    v_log_f32_e32 v0, s2
-; SI-NEXT:    s_mov_b32 s2, -1
-; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
-; SI-NEXT:    s_endpgm
+; SI-SDAG-LABEL: s_log2_f32:
+; SI-SDAG:       ; %bb.0:
+; SI-SDAG-NEXT:    s_load_dword s2, s[0:1], 0xb
+; SI-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SI-SDAG-NEXT:    v_mov_b32_e32 v0, 0x800000
+; SI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; SI-SDAG-NEXT:    s_mov_b32 s3, 0xf000
+; SI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
+; SI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s2, v0
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; SI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x4f800000
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
+; SI-SDAG-NEXT:    v_mul_f32_e32 v1, s2, v1
+; SI-SDAG-NEXT:    v_log_f32_e32 v1, v1
+; SI-SDAG-NEXT:    s_mov_b32 s2, -1
+; SI-SDAG-NEXT:    v_sub_f32_e32 v0, v1, v0
+; SI-SDAG-NEXT:    buffer_store_dword v0, off, s[0:3], 0
+; SI-SDAG-NEXT:    s_endpgm
 ;
-; VI-LABEL: s_log2_f32:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
-; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_log_f32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    flat_store_dword v[0:1], v2
-; VI-NEXT:    s_endpgm
+; SI-GISEL-LABEL: s_log2_f32:
+; SI-GISEL:       ; %bb.0:
+; SI-GISEL-NEXT:    s_load_dword s2, s[0:1], 0xb
+; SI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SI-GISEL-NEXT:    v_mov_b32_e32 v0, 0x800000
+; SI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x4f800000
+; SI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, s2, v0
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v0, 1.0, v1, vcc
+; SI-GISEL-NEXT:    v_mul_f32_e32 v0, s2, v0
+; SI-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT:    s_mov_b32 s2, -1
+; SI-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT:    buffer_store_dword v0, off, s[0:3], 0
+; SI-GISEL-NEXT:    s_endpgm
 ;
-; GFX900-LABEL: s_log2_f32:
-; GFX900:       ; %bb.0:
-; GFX900-NEXT:    s_load_dword s4, s[0:1], 0x2c
-; GFX900-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
-; GFX900-NEXT:    v_mov_b32_e32 v1, 0
-; GFX900-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX900-NEXT:    v_log_f32_e32 v0, s4
-; GFX900-NEXT:    global_store_dword v1, v0, s[2:3]
-; GFX900-NEXT:    s_endpgm
+; VI-SDAG-LABEL: s_log2_f32:
+; VI-SDAG:       ; %bb.0:
+; VI-SDAG-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; VI-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; VI-SDAG-NEXT:    v_mov_b32_e32 v0, 0x800000
+; VI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; VI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
+; VI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s2, v0
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x4f800000
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, s2, v1
+; VI-SDAG-NEXT:    v_log_f32_e32 v1, v1
+; VI-SDAG-NEXT:    v_sub_f32_e32 v2, v1, v0
+; VI-SDAG-NEXT:    v_mov_b32_e32 v0, s0
+; VI-SDAG-NEXT:    v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT:    flat_store_dword v[0:1], v2
+; VI-SDAG-NEXT:    s_endpgm
+;
+; VI-GISEL-LABEL: s_log2_f32:
+; VI-GISEL:       ; %bb.0:
+; VI-GISEL-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; VI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; VI-GISEL-NEXT:    v_mov_b32_e32 v0, 0x800000
+; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x4f800000
+; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, s2, v0
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, 1.0, v1, vcc
+; VI-GISEL-NEXT:    v_mul_f32_e32 v0, s2, v0
+; VI-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT:    v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT:    v_mov_b32_e32 v0, s0
+; VI-GISEL-NEXT:    v_mov_b32_e32 v1, s1
+; VI-GISEL-NEXT:    flat_store_dword v[0:1], v2
+; VI-GISEL-NEXT:    s_endpgm
+;
+; GFX900-SDAG-LABEL: s_log2_f32:
+; GFX900-SDAG:       ; %bb.0:
+; GFX900-SDAG-NEXT:    s_load_dword s4, s[0:1], 0x2c
+; GFX900-SDAG-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v0, 0x800000
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v2, 0
+; GFX900-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v1, 0x4f800000
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, s4, v1
+; GFX900-SDAG-NEXT:    v_log_f32_e32 v1, v1
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v0, v1, v0
+; GFX900-SDAG-NEXT:    global_store_dword v2, v0, s[2:3]
+; GFX900-SDAG-NEXT:    s_endpgm
+;
+; GFX900-GISEL-LABEL: s_log2_f32:
+; GFX900-GISEL:       ; %bb.0:
+; GFX900-GISEL-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v0, 0x800000
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0x4f800000
+; GFX900-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX900-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v0, 1.0, v1, vcc
+; GFX900-GISEL-NEXT:    v_mul_f32_e32 v0, s2, v0
+; GFX900-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0
+; GFX900-GISEL-NEXT:    global_store_dword v1, v0, s[0:1]
+; GFX900-GISEL-NEXT:    s_endpgm
 ;
 ; R600-LABEL: s_log2_f32:
 ; R600:       ; %bb.0:
-; R600-NEXT:    ALU 2, @4, KC0[CB0:0-32], KC1[]
-; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
+; R600-NEXT:    ALU 10, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ; R600-NEXT:    ALU clause starting at 4:
-; R600-NEXT:     LSHR T0.X, KC0[2].Y, literal.x,
-; R600-NEXT:     LOG_IEEE * T1.X, KC0[2].Z,
+; R600-NEXT:     SETGT * T0.W, literal.x, KC0[2].Z,
+; R600-NEXT:    8388608(1.175494e-38), 0(0.000000e+00)
+; R600-NEXT:     CNDE * T1.W, PV.W, 1.0, literal.x,
+; R600-NEXT:    1333788672(4.294967e+09), 0(0.000000e+00)
+; R600-NEXT:     MUL_IEEE T1.W, KC0[2].Z, PV.W,
+; R600-NEXT:     CNDE * T0.W, T0.W, 0.0, literal.x,
+; R600-NEXT:    1107296256(3.200000e+01), 0(0.000000e+00)
+; R600-NEXT:     LOG_IEEE * T0.X, PV.W,
+; R600-NEXT:     ADD T0.X, PS, -T0.W,
+; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
 ; CM-LABEL: s_log2_f32:
 ; CM:       ; %bb.0:
-; CM-NEXT:    ALU 5, @4, KC0[CB0:0-32], KC1[]
-; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X
+; CM-NEXT:    ALU 13, @4, KC0[CB0:0-32], KC1[]
+; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
 ; CM-NEXT:    ALU clause starting at 4:
-; CM-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
+; CM-NEXT:     SETGT * T0.W, literal.x, KC0[2].Z,
+; CM-NEXT:    8388608(1.175494e-38), 0(0.000000e+00)
+; CM-NEXT:     CNDE * T1.W, PV.W, 1.0, literal.x,
+; CM-NEXT:    1333788672(4.294967e+09), 0(0.000000e+00)
+; CM-NEXT:     CNDE T0.Z, T0.W, 0.0, literal.x,
+; CM-NEXT:     MUL_IEEE * T0.W, KC0[2].Z, PV.W,
+; CM-NEXT:    1107296256(3.200000e+01), 0(0.000000e+00)
+; CM-NEXT:     LOG_IEEE T0.X, T0.W,
+; CM-NEXT:     LOG_IEEE T0.Y (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE T0.Z (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE * T0.W (MASKED), T0.W,
+; CM-NEXT:     ADD * T0.X, PV.X, -T0.Z,
+; CM-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
-; CM-NEXT:     LOG_IEEE T1.X, KC0[2].Z,
-; CM-NEXT:     LOG_IEEE T1.Y (MASKED), KC0[2].Z,
-; CM-NEXT:     LOG_IEEE T1.Z (MASKED), KC0[2].Z,
-; CM-NEXT:     LOG_IEEE * T1.W (MASKED), KC0[2].Z,
   %result = call float @llvm.log2.f32(float %in)
   store float %result, ptr addrspace(1) %out
   ret void
 }
 
 ; FIXME: We should be able to merge these packets together on Cayman so we
 ; have a maximum of 4 instructions.
 define amdgpu_kernel void @s_log2_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
 ; SI-SDAG-LABEL: s_log2_v2f32:
 ; SI-SDAG:       ; %bb.0:
 ; SI-SDAG-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; SI-SDAG-NEXT:    v_mov_b32_e32 v0, 0x800000
+; SI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; SI-SDAG-NEXT:    v_mov_b32_e32 v3, 0x4f800000
 ; SI-SDAG-NEXT:    s_mov_b32 s7, 0xf000
-; SI-SDAG-NEXT:    s_mov_b32 s6, -1
 ; SI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-SDAG-NEXT:    v_log_f32_e32 v1, s3
-; SI-SDAG-NEXT:    v_log_f32_e32 v0, s2
+; SI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s3, v0
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v2, 0, v1, vcc
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v4, 1.0, v3, vcc
+; SI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s2, v0
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v3, vcc
+; SI-SDAG-NEXT:    v_mul_f32_e32 v4, s3, v4
+; SI-SDAG-NEXT:    v_mul_f32_e32 v1, s2, v1
+; SI-SDAG-NEXT:    v_log_f32_e32 v4, v4
+; SI-SDAG-NEXT:    v_log_f32_e32 v3, v1
+; SI-SDAG-NEXT:    s_mov_b32 s6, -1
 ; SI-SDAG-NEXT:    s_mov_b32 s4, s0
 ; SI-SDAG-NEXT:    s_mov_b32 s5, s1
+; SI-SDAG-NEXT:    v_sub_f32_e32 v1, v4, v2
+; SI-SDAG-NEXT:    v_sub_f32_e32 v0, v3, v0
 ; SI-SDAG-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; SI-SDAG-NEXT:    s_endpgm
 ;
 ; SI-GISEL-LABEL: s_log2_v2f32:
 ; SI-GISEL:       ; %bb.0:
-; SI-GISEL-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; SI-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
+; SI-GISEL-NEXT:    s_mov_b32 s0, 0x800000
+; SI-GISEL-NEXT:    v_mov_b32_e32 v0, 0x4f800000
+; SI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
 ; SI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-GISEL-NEXT:    v_log_f32_e32 v0, s2
-; SI-GISEL-NEXT:    v_log_f32_e32 v1, s3
-; SI-GISEL-NEXT:    s_mov_b32 s2, -1
-; SI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
-; SI-GISEL-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SI-GISEL-NEXT:    v_mov_b32_e32 v2, s6
+; SI-GISEL-NEXT:    v_mov_b32_e32 v3, s7
+; SI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s0, v2
+; SI-GISEL-NEXT:    v_cmp_gt_f32_e64 s[0:1], s0, v3
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v2, 1.0, v0, vcc
+; SI-GISEL-NEXT:    v_cndmask_b32_e64 v0, 1.0, v0, s[0:1]
+; SI-GISEL-NEXT:    v_mul_f32_e32 v2, s6, v2
+; SI-GISEL-NEXT:    v_mul_f32_e32 v0, s7, v0
+; SI-GISEL-NEXT:    v_log_f32_e32 v2, v2
+; SI-GISEL-NEXT:    v_log_f32_e32 v3, v0
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; SI-GISEL-NEXT:    v_cndmask_b32_e64 v1, 0, v1, s[0:1]
+; SI-GISEL-NEXT:    v_sub_f32_e32 v0, v2, v0
+; SI-GISEL-NEXT:    v_sub_f32_e32 v1, v3, v1
+; SI-GISEL-NEXT:    s_mov_b32 s6, -1
+; SI-GISEL-NEXT:    s_mov_b32 s7, 0xf000
+; SI-GISEL-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; SI-GISEL-NEXT:    s_endpgm
 ;
 ; VI-SDAG-LABEL: s_log2_v2f32:
 ; VI-SDAG:       ; %bb.0:
 ; VI-SDAG-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; VI-SDAG-NEXT:    v_mov_b32_e32 v0, 0x800000
+; VI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; VI-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
 ; VI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT:    v_log_f32_e32 v1, s3
-; VI-SDAG-NEXT:    v_log_f32_e32 v0, s2
+; VI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s3, v0
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v3, 0, v1, vcc
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v4, 1.0, v2, vcc
+; VI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s2, v0
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; VI-SDAG-NEXT:    v_mul_f32_e32 v4, s3, v4
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, s2, v1
+; VI-SDAG-NEXT:    v_log_f32_e32 v4, v4
+; VI-SDAG-NEXT:    v_log_f32_e32 v2, v1
+; VI-SDAG-NEXT:    v_sub_f32_e32 v1, v4, v3
+; VI-SDAG-NEXT:    v_sub_f32_e32 v0, v2, v0
 ; VI-SDAG-NEXT:    v_mov_b32_e32 v3, s1
 ; VI-SDAG-NEXT:    v_mov_b32_e32 v2, s0
 ; VI-SDAG-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
 ; VI-SDAG-NEXT:    s_endpgm
 ;
 ; VI-GISEL-LABEL: s_log2_v2f32:
 ; VI-GISEL:       ; %bb.0:
-; VI-GISEL-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; VI-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
+; VI-GISEL-NEXT:    s_mov_b32 s0, 0x800000
+; VI-GISEL-NEXT:    v_mov_b32_e32 v0, 0x4f800000
+; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
 ; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT:    v_log_f32_e32 v0, s2
-; VI-GISEL-NEXT:    v_log_f32_e32 v1, s3
-; VI-GISEL-NEXT:    v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT:    v_mov_b32_e32 v2, s0
+; VI-GISEL-NEXT:    v_mov_b32_e32 v2, s6
+; VI-GISEL-NEXT:    v_mov_b32_e32 v3, s7
+; VI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s0, v2
+; VI-GISEL-NEXT:    v_cmp_gt_f32_e64 s[0:1], s0, v3
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v2, 1.0, v0, vcc
+; VI-GISEL-NEXT:    v_cndmask_b32_e64 v0, 1.0, v0, s[0:1]
+; VI-GISEL-NEXT:    v_mul_f32_e32 v2, s6, v2
+; VI-GISEL-NEXT:    v_mul_f32_e32 v0, s7, v0
+; VI-GISEL-NEXT:    v_log_f32_e32 v2, v2
+; VI-GISEL-NEXT:    v_log_f32_e32 v3, v0
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-GISEL-NEXT:    v_cndmask_b32_e64 v1, 0, v1, s[0:1]
+; VI-GISEL-NEXT:    v_sub_f32_e32 v0, v2, v0
+; VI-GISEL-NEXT:    v_sub_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT:    v_mov_b32_e32 v2, s4
+; VI-GISEL-NEXT:    v_mov_b32_e32 v3, s5
 ; VI-GISEL-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
 ; VI-GISEL-NEXT:    s_endpgm
 ;
 ; GFX900-SDAG-LABEL: s_log2_v2f32:
 ; GFX900-SDAG:       ; %bb.0:
 ; GFX900-SDAG-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
-; GFX900-SDAG-NEXT:    v_mov_b32_e32 v2, 0
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v0, 0x800000
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v5, 0
 ; GFX900-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX900-SDAG-NEXT:    v_log_f32_e32 v1, s3
-; GFX900-SDAG-NEXT:    v_log_f32_e32 v0, s2
-; GFX900-SDAG-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s3, v0
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v3, 0, v1, vcc
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v4, 1.0, v2, vcc
+; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v4, s3, v4
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, s2, v1
+; GFX900-SDAG-NEXT:    v_log_f32_e32 v4, v4
+; GFX900-SDAG-NEXT:    v_log_f32_e32 v2, v1
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v1, v4, v3
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v0, v2, v0
+; GFX900-SDAG-NEXT:    global_store_dwordx2 v5, v[0:1], s[0:1]
 ; GFX900-SDAG-NEXT:    s_endpgm
 ;
 ; GFX900-GISEL-LABEL: s_log2_v2f32:
 ; GFX900-GISEL:       ; %bb.0:
-; GFX900-GISEL-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
-; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0
+; GFX900-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
+; GFX900-GISEL-NEXT:    s_mov_b32 s0, 0x800000
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v0, 0x4f800000
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
 ; GFX900-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX900-GISEL-NEXT:    v_log_f32_e32 v0, s2
-; GFX900-GISEL-NEXT:    v_log_f32_e32 v1, s3
-; GFX900-GISEL-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, s6
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v3, s7
+; GFX900-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s0, v2
+; GFX900-GISEL-NEXT:    v_cmp_gt_f32_e64 s[0:1], s0, v3
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v2, 1.0, v0, vcc
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e64 v0, 1.0, v0, s[0:1]
+; GFX900-GISEL-NEXT:    v_mul_f32_e32 v2, s6, v2
+; GFX900-GISEL-NEXT:    v_mul_f32_e32 v0, s7, v0
+; GFX900-GISEL-NEXT:    v_log_f32_e32 v2, v2
+; GFX900-GISEL-NEXT:    v_log_f32_e32 v3, v0
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e64 v1, 0, v1, s[0:1]
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v0, v2, v0
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v1, v3, v1
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0
+; GFX900-GISEL-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
 ; GFX900-GISEL-NEXT:    s_endpgm
 ;
 ; R600-LABEL: s_log2_v2f32:
 ; R600:       ; %bb.0:
-; R600-NEXT:    ALU 3, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT:    ALU 18, @4, KC0[CB0:0-32], KC1[]
 ; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ; R600-NEXT:    ALU clause starting at 4:
-; R600-NEXT:     LOG_IEEE * T0.Y, KC0[3].X,
-; R600-NEXT:     LSHR T1.X, KC0[2].Y, literal.x,
-; R600-NEXT:     LOG_IEEE * T0.X, KC0[2].W,
+; R600-NEXT:     SETGT T0.W, literal.x, KC0[3].X,
+; R600-NEXT:     SETGT * T1.W, literal.x, KC0[2].W,
+; R600-NEXT:    8388608(1.175494e-38), 0(0.000000e+00)
+; R600-NEXT:     CNDE * T2.W, PV.W, 1.0, literal.x,
+; R600-NEXT:    1333788672(4.294967e+09), 0(0.000000e+00)
+; R600-NEXT:     MUL_IEEE T2.W, KC0[3].X, PV.W,
+; R600-NEXT:     CNDE * T3.W, T1.W, 1.0, literal.x,
+; R600-NEXT:    1333788672(4.294967e+09), 0(0.000000e+00)
+; R600-NEXT:     MUL_IEEE T0.Z, KC0[2].W, PS,
+; R600-NEXT:     CNDE T0.W, T0.W, 0.0, literal.x,
+; R600-NEXT:     LOG_IEEE * T0.X, PV.W,
+; R600-NEXT:    1107296256(3.200000e+01), 0(0.000000e+00)
+; R600-NEXT:     ADD T0.Y, PS, -PV.W,
+; R600-NEXT:     CNDE T0.W, T1.W, 0.0, literal.x,
+; R600-NEXT:     LOG_IEEE * T0.X, PV.Z,
+; R600-NEXT:    1107296256(3.200000e+01), 0(0.000000e+00)
+; R600-NEXT:     ADD T0.X, PS, -PV.W,
+; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
 ; CM-LABEL: s_log2_v2f32:
 ; CM:       ; %bb.0:
-; CM-NEXT:    ALU 9, @4, KC0[CB0:0-32], KC1[]
+; CM-NEXT:    ALU 23, @4, KC0[CB0:0-32], KC1[]
 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T1, T0.X
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
 ; CM-NEXT:    ALU clause starting at 4:
+; CM-NEXT:     SETGT * T0.W, literal.x, KC0[3].X,
+; CM-NEXT:    8388608(1.175494e-38), 0(0.000000e+00)
+; CM-NEXT:     CNDE T0.Z, PV.W, 1.0, literal.x,
+; CM-NEXT:     SETGT * T1.W, literal.y, KC0[2].W,
+; CM-NEXT:    1333788672(4.294967e+09), 8388608(1.175494e-38)
+; CM-NEXT:     CNDE T0.Y, PV.W, 1.0, literal.x,
+; CM-NEXT:     CNDE T1.Z, T0.W, 0.0, literal.y,
+; CM-NEXT:     MUL_IEEE * T0.W, KC0[3].X, PV.Z,
+; CM-NEXT:    1333788672(4.294967e+09), 1107296256(3.200000e+01)
+; CM-NEXT:     LOG_IEEE T0.X, T0.W,
+; CM-NEXT:     LOG_IEEE T0.Y (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE T0.Z (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE * T0.W (MASKED), T0.W,
+; CM-NEXT:     ADD T1.Y, PV.X, -T1.Z,
+; CM-NEXT:     CNDE T0.Z, T1.W, 0.0, literal.x,
+; CM-NEXT:     MUL_IEEE * T0.W, KC0[2].W, T0.Y,
+; CM-NEXT:    1107296256(3.200000e+01), 0(0.000000e+00)
+; CM-NEXT:     LOG_IEEE T0.X, T0.W,
+; CM-NEXT:     LOG_IEEE T0.Y (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE T0.Z (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE * T0.W (MASKED), T0.W,
+; CM-NEXT:     ADD * T1.X, PV.X, -T0.Z,
 ; CM-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
-; CM-NEXT:     LOG_IEEE T1.X (MASKED), KC0[3].X,
-; CM-NEXT:     LOG_IEEE T1.Y, KC0[3].X,
-; CM-NEXT:     LOG_IEEE T1.Z (MASKED), KC0[3].X,
-; CM-NEXT:     LOG_IEEE * T1.W (MASKED), KC0[3].X,
-; CM-NEXT:     LOG_IEEE T1.X, KC0[2].W,
-; CM-NEXT:     LOG_IEEE T1.Y (MASKED), KC0[2].W,
-; CM-NEXT:     LOG_IEEE T1.Z (MASKED), KC0[2].W,
-; CM-NEXT:     LOG_IEEE * T1.W (MASKED), KC0[2].W,
   %result = call <2 x float> @llvm.log2.v2f32(<2 x float> %in)
   store <2 x float> %result, ptr addrspace(1) %out
   ret void
 }
 
 define amdgpu_kernel void @s_log2_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
 ; SI-SDAG-LABEL: s_log2_v3f32:
 ; SI-SDAG:       ; %bb.0:
 ; SI-SDAG-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xd
 ; SI-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SI-SDAG-NEXT:    v_mov_b32_e32 v0, 0x800000
+; SI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; SI-SDAG-NEXT:    v_mov_b32_e32 v3, 0x4f800000
+; SI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
+; SI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s5, v0
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v2, 0, v1, vcc
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v4, 1.0, v3, vcc
+; SI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v5, 0, v1, vcc
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v6, 1.0, v3, vcc
+; SI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s6, v0
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v0, 1.0, v3, vcc
+; SI-SDAG-NEXT:    v_mul_f32_e32 v4, s5, v4
+; SI-SDAG-NEXT:    v_mul_f32_e32 v0, s6, v0
+; SI-SDAG-NEXT:    v_log_f32_e32 v4, v4
+; SI-SDAG-NEXT:    v_mul_f32_e32 v6, s4, v6
+; SI-SDAG-NEXT:    v_log_f32_e32 v3, v0
+; SI-SDAG-NEXT:    v_log_f32_e32 v6, v6
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v7, 0, v1, vcc
 ; SI-SDAG-NEXT:    s_mov_b32 s3, 0xf000
 ; SI-SDAG-NEXT:    s_mov_b32 s2, -1
-; SI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-SDAG-NEXT:    v_log_f32_e32 v2, s6
-; SI-SDAG-NEXT:    v_log_f32_e32 v1, s5
-; SI-SDAG-NEXT:    v_log_f32_e32 v0, s4
+; SI-SDAG-NEXT:    v_sub_f32_e32 v1, v4, v2
+; SI-SDAG-NEXT:    v_sub_f32_e32 v2, v3, v7
+; SI-SDAG-NEXT:    v_sub_f32_e32 v0, v6, v5
 ; SI-SDAG-NEXT:    buffer_store_dword v2, off, s[0:3], 0 offset:8
 ; SI-SDAG-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; SI-SDAG-NEXT:    s_endpgm
 ;
 ; SI-GISEL-LABEL: s_log2_v3f32:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xd
-; SI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; SI-GISEL-NEXT:    s_mov_b32 s2, -1
-; SI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x9
+; SI-GISEL-NEXT:    s_mov_b32 s0, 0x800000
+; SI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x4f800000
+; SI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x42000000
 ; SI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-GISEL-NEXT:    v_log_f32_e32 v0, s4
-; SI-GISEL-NEXT:    v_log_f32_e32 v1, s5
-; SI-GISEL-NEXT:    v_log_f32_e32 v2, s6
-; SI-GISEL-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; SI-GISEL-NEXT:    buffer_store_dword v2, off, s[0:3], 0 offset:8
+; SI-GISEL-NEXT:    v_mov_b32_e32 v0, s4
+; SI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s0, v0
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v0, 1.0, v1, vcc
+; SI-GISEL-NEXT:    v_mul_f32_e32 v0, s4, v0
+; SI-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v4, 0, v3, vcc
+; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x800000
+; SI-GISEL-NEXT:    s_mov_b32 s10, -1
+; SI-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v4
+; SI-GISEL-NEXT:    v_mov_b32_e32 v4, s5
+; SI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s0, v4
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v4, 1.0, v1, vcc
+; SI-GISEL-NEXT:    v_cmp_lt_f32_e64 s[0:1], s6, v2
+; SI-GISEL-NEXT:    v_mul_f32_e32 v4, s5, v4
+; SI-GISEL-NEXT:    v_cndmask_b32_e64 v1, 1.0, v1, s[0:1]
+; SI-GISEL-NEXT:    v_log_f32_e32 v4, v4
+; SI-GISEL-NEXT:    v_mul_f32_e32 v1, s6, v1
+; SI-GISEL-NEXT:    v_log_f32_e32 v2, v1
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
+; SI-GISEL-NEXT:    v_sub_f32_e32 v1, v4, v1
+; SI-GISEL-NEXT:    v_cndmask_b32_e64 v3, 0, v3, s[0:1]
+; SI-GISEL-NEXT:    s_mov_b32 s11, 0xf000
+; SI-GISEL-NEXT:    v_sub_f32_e32 v2, v2, v3
+; SI-GISEL-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
+; SI-GISEL-NEXT:    buffer_store_dword v2, off, s[8:11], 0 offset:8
 ; SI-GISEL-NEXT:    s_endpgm
 ;
 ; VI-SDAG-LABEL: s_log2_v3f32:
 ; VI-SDAG:       ; %bb.0:
 ; VI-SDAG-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
 ; VI-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; VI-SDAG-NEXT:    v_mov_b32_e32 v0, 0x800000
+; VI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; VI-SDAG-NEXT:    v_mov_b32_e32 v3, 0x4f800000
 ; VI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT:    v_log_f32_e32 v2, s6
-; VI-SDAG-NEXT:    v_log_f32_e32 v1, s5
-; VI-SDAG-NEXT:    v_log_f32_e32 v0, s4
+; VI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s6, v0
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v2, 0, v1, vcc
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v4, 1.0, v3, vcc
+; VI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s5, v0
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v5, 0, v1, vcc
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v6, 1.0, v3, vcc
+; VI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v3, vcc
+; VI-SDAG-NEXT:    v_mul_f32_e32 v4, s6, v4
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, s4, v1
+; VI-SDAG-NEXT:    v_log_f32_e32 v4, v4
+; VI-SDAG-NEXT:    v_mul_f32_e32 v6, s5, v6
+; VI-SDAG-NEXT:    v_log_f32_e32 v3, v1
+; VI-SDAG-NEXT:    v_log_f32_e32 v6, v6
+; VI-SDAG-NEXT:    v_sub_f32_e32 v2, v4, v2
+; VI-SDAG-NEXT:    v_sub_f32_e32 v0, v3, v0
 ; VI-SDAG-NEXT:    v_mov_b32_e32 v4, s1
+; VI-SDAG-NEXT:    v_sub_f32_e32 v1, v6, v5
 ; VI-SDAG-NEXT:    v_mov_b32_e32 v3, s0
 ; VI-SDAG-NEXT:    flat_store_dwordx3 v[3:4], v[0:2]
 ; VI-SDAG-NEXT:    s_endpgm
 ;
 ; VI-GISEL-LABEL: s_log2_v3f32:
 ; VI-GISEL:       ; %bb.0:
 ; VI-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
-; VI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; VI-GISEL-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
+; VI-GISEL-NEXT:    s_mov_b32 s0, 0x800000
+; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x4f800000
+; VI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x42000000
 ; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT:    v_log_f32_e32 v0, s4
-; VI-GISEL-NEXT:    v_log_f32_e32 v1, s5
-; VI-GISEL-NEXT:    v_log_f32_e32 v2, s6
-; VI-GISEL-NEXT:    v_mov_b32_e32 v4, s1
-; VI-GISEL-NEXT:    v_mov_b32_e32 v3, s0
+; VI-GISEL-NEXT:    v_mov_b32_e32 v0, s4
+; VI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s0, v0
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, 1.0, v1, vcc
+; VI-GISEL-NEXT:    v_mul_f32_e32 v0, s4, v0
+; VI-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v4, 0, v3, vcc
+; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x800000
+; VI-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v4
+; VI-GISEL-NEXT:    v_mov_b32_e32 v4, s5
+; VI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s0, v4
+; VI-GISEL-NEXT:    v_cmp_lt_f32_e64 s[0:1], s6, v2
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v4, 1.0, v1, vcc
+; VI-GISEL-NEXT:    v_cndmask_b32_e64 v1, 1.0, v1, s[0:1]
+; VI-GISEL-NEXT:    v_mul_f32_e32 v4, s5, v4
+; VI-GISEL-NEXT:    v_mul_f32_e32 v1, s6, v1
+; VI-GISEL-NEXT:    v_log_f32_e32 v4, v4
+; VI-GISEL-NEXT:    v_log_f32_e32 v2, v1
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
+; VI-GISEL-NEXT:    v_cndmask_b32_e64 v3, 0, v3, s[0:1]
+; VI-GISEL-NEXT:    v_sub_f32_e32 v1, v4, v1
+; VI-GISEL-NEXT:    v_sub_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT:    v_mov_b32_e32 v4, s3
+; VI-GISEL-NEXT:    v_mov_b32_e32 v3, s2
 ; VI-GISEL-NEXT:    flat_store_dwordx3 v[3:4], v[0:2]
 ; VI-GISEL-NEXT:    s_endpgm
 ;
 ; GFX900-SDAG-LABEL: s_log2_v3f32:
 ; GFX900-SDAG:       ; %bb.0:
 ; GFX900-SDAG-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
 ; GFX900-SDAG-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
-; GFX900-SDAG-NEXT:    v_mov_b32_e32 v3, 0
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v0, 0x800000
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v3, 0x4f800000
 ; GFX900-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX900-SDAG-NEXT:    v_log_f32_e32 v2, s6
-; GFX900-SDAG-NEXT:    v_log_f32_e32 v1, s5
-; GFX900-SDAG-NEXT:    v_log_f32_e32 v0, s4
-; GFX900-SDAG-NEXT:    global_store_dwordx3 v3, v[0:2], s[2:3]
+; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s6, v0
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v2, 0, v1, vcc
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v4, 1.0, v3, vcc
+; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s5, v0
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v5, 0, v1, vcc
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v6, 1.0, v3, vcc
+; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v3, vcc
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v4, s6, v4
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v6, s5, v6
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, s4, v1
+; GFX900-SDAG-NEXT:    v_log_f32_e32 v4, v4
+; GFX900-SDAG-NEXT:    v_log_f32_e32 v6, v6
+; GFX900-SDAG-NEXT:    v_log_f32_e32 v3, v1
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v7, 0
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v2, v4, v2
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v1, v6, v5
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v0, v3, v0
+; GFX900-SDAG-NEXT:    global_store_dwordx3 v7, v[0:2], s[2:3]
 ; GFX900-SDAG-NEXT:    s_endpgm
 ;
 ; GFX900-GISEL-LABEL: s_log2_v3f32:
 ; GFX900-GISEL:       ; %bb.0:
 ; GFX900-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
 ; GFX900-GISEL-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
-; GFX900-GISEL-NEXT:    v_mov_b32_e32 v3, 0
+; GFX900-GISEL-NEXT:    s_mov_b32 s0, 0x800000
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0x4f800000
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v3, 0x42000000
 ; GFX900-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX900-GISEL-NEXT:    v_log_f32_e32 v0, s4
-; GFX900-GISEL-NEXT:    v_log_f32_e32 v1, s5
-; GFX900-GISEL-NEXT:    v_log_f32_e32 v2, s6
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v0, s4
+; GFX900-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s0, v0
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v0, 1.0, v1, vcc
+; GFX900-GISEL-NEXT:    v_mul_f32_e32 v0, s4, v0
+; GFX900-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v4, 0, v3, vcc
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x800000
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v4
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v4, s5
+; GFX900-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s0, v4
+; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e64 s[0:1], s6, v2
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v4, 1.0, v1, vcc
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e64 v1, 1.0, v1, s[0:1]
+; GFX900-GISEL-NEXT:    v_mul_f32_e32 v4, s5, v4
+; GFX900-GISEL-NEXT:    v_mul_f32_e32 v1, s6, v1
+; GFX900-GISEL-NEXT:    v_log_f32_e32 v4, v4
+; GFX900-GISEL-NEXT:    v_log_f32_e32 v2, v1
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e64 v3, 0, v3, s[0:1]
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v1, v4, v1
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v2, v2, v3
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v3, 0
 ; GFX900-GISEL-NEXT:    global_store_dwordx3 v3, v[0:2], s[2:3]
 ; GFX900-GISEL-NEXT:    s_endpgm
 ;
 ; R600-LABEL: s_log2_v3f32:
 ; R600:       ; %bb.0:
-; R600-NEXT:    ALU 7, @4, KC0[CB0:0-32], KC1[]
-; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T3.X, T2.X, 0
-; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; R600-NEXT:    ALU 29, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T2.X, T3.X, 0
+; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T1.XY, T0.X, 1
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    ALU clause starting at 4:
-; R600-NEXT:     LOG_IEEE * T0.Y, KC0[3].Z,
-; R600-NEXT:     LSHR T1.X, KC0[2].Y, literal.x,
-; R600-NEXT:     ADD_INT T0.W, KC0[2].Y, literal.y,
-; R600-NEXT:     LOG_IEEE * T0.X, KC0[3].Y,
-; R600-NEXT:    2(2.802597e-45), 8(1.121039e-44)
-; R600-NEXT:     LSHR T2.X, PV.W, literal.x,
-; R600-NEXT:     LOG_IEEE * T3.X, KC0[3].W,
+; R600-NEXT:     SETGT T0.W, literal.x, KC0[3].Z,
+; R600-NEXT:     SETGT * T1.W, literal.x, KC0[3].Y,
+; R600-NEXT:    8388608(1.175494e-38), 0(0.000000e+00)
+; R600-NEXT:     CNDE * T2.W, PV.W, 1.0, literal.x,
+; R600-NEXT:    1333788672(4.294967e+09), 0(0.000000e+00)
+; R600-NEXT:     MUL_IEEE T2.W, KC0[3].Z, PV.W,
+; R600-NEXT:     CNDE * T3.W, T1.W, 1.0, literal.x,
+; R600-NEXT:    1333788672(4.294967e+09), 0(0.000000e+00)
+; R600-NEXT:     MUL_IEEE T0.Y, KC0[3].Y, PS,
+; R600-NEXT:     SETGT T0.Z, literal.x, KC0[3].W,
+; R600-NEXT:     CNDE T0.W, T0.W, 0.0, literal.y,
+; R600-NEXT:     LOG_IEEE * T0.X, PV.W,
+; R600-NEXT:    8388608(1.175494e-38), 1107296256(3.200000e+01)
+; R600-NEXT:     ADD T1.Y, PS, -PV.W,
+; R600-NEXT:     CNDE T1.Z, PV.Z, 1.0, literal.x,
+; R600-NEXT:     CNDE T0.W, T1.W, 0.0, literal.y,
+; R600-NEXT:     LOG_IEEE * T0.X, PV.Y,
+; R600-NEXT:    1333788672(4.294967e+09), 1107296256(3.200000e+01)
+; R600-NEXT:     ADD T1.X, PS, -PV.W,
+; R600-NEXT:     MUL_IEEE T0.W, KC0[3].W, PV.Z,
+; R600-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
+; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
+; R600-NEXT:     CNDE T1.W, T0.Z, 0.0, literal.x,
+; R600-NEXT:     LOG_IEEE * T0.Y, PV.W,
+; R600-NEXT:    1107296256(3.200000e+01), 0(0.000000e+00)
+; R600-NEXT:     ADD T2.X, PS, -PV.W,
+; R600-NEXT:     ADD_INT * T0.W, KC0[2].Y, literal.x,
+; R600-NEXT:    8(1.121039e-44), 0(0.000000e+00)
+; R600-NEXT:     LSHR * T3.X, PV.W, literal.x,
 ; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
 ; CM-LABEL: s_log2_v3f32:
 ; CM:       ; %bb.0:
-; CM-NEXT:    ALU 17, @4, KC0[CB0:0-32], KC1[]
-; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T3, T1.X
-; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T2.X, T0.X
+; CM-NEXT:    ALU 35, @4, KC0[CB0:0-32], KC1[]
+; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0, T3.X
+; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T1.X, T2.X
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    ALU clause starting at 4:
-; CM-NEXT:     ADD_INT * T0.W, KC0[2].Y, literal.x,
-; CM-NEXT:    8(1.121039e-44), 0(0.000000e+00)
-; CM-NEXT:     LSHR * T0.X, PV.W, literal.x,
-; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
-; CM-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
+; CM-NEXT:     SETGT * T0.W, literal.x, KC0[3].W,
+; CM-NEXT:    8388608(1.175494e-38), 0(0.000000e+00)
+; CM-NEXT:     CNDE T0.Y, PV.W, 1.0, literal.x,
+; CM-NEXT:     SETGT T0.Z, literal.y, KC0[3].Z,
+; CM-NEXT:     SETGT * T1.W, literal.y, KC0[3].Y,
+; CM-NEXT:    1333788672(4.294967e+09), 8388608(1.175494e-38)
+; CM-NEXT:     CNDE T0.X, PV.W, 1.0, literal.x,
+; CM-NEXT:     CNDE T1.Y, PV.Z, 1.0, literal.x,
+; CM-NEXT:     CNDE T1.Z, T0.W, 0.0, literal.y,
+; CM-NEXT:     MUL_IEEE * T0.W, KC0[3].W, PV.Y,
+; CM-NEXT:    1333788672(4.294967e+09), 1107296256(3.200000e+01)
+; CM-NEXT:     LOG_IEEE T0.X (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE T0.Y, T0.W,
+; CM-NEXT:     LOG_IEEE T0.Z (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE * T0.W (MASKED), T0.W,
+; CM-NEXT:     ADD T1.X, PV.Y, -T1.Z,
+; CM-NEXT:     CNDE T0.Y, T0.Z, 0.0, literal.x,
+; CM-NEXT:     ADD_INT T0.Z, KC0[2].Y, literal.y,
+; CM-NEXT:     MUL_IEEE * T0.W, KC0[3].Z, T1.Y,
+; CM-NEXT:    1107296256(3.200000e+01), 8(1.121039e-44)
+; CM-NEXT:     LOG_IEEE T0.X (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE T0.Y (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE T0.Z (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE * T0.W, T0.W,
+; CM-NEXT:     LSHR T2.X, T0.Z, literal.x,
+; CM-NEXT:     ADD T0.Y, PV.W, -T0.Y,
+; CM-NEXT:     CNDE T0.Z, T1.W, 0.0, literal.y,
+; CM-NEXT:     MUL_IEEE * T0.W, KC0[3].Y, T0.X,
+; CM-NEXT:    2(2.802597e-45), 1107296256(3.200000e+01)
+; CM-NEXT:     LOG_IEEE T0.X, T0.W,
+; CM-NEXT:     LOG_IEEE T0.Y (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE T0.Z (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE * T0.W (MASKED), T0.W,
+; CM-NEXT:     ADD * T0.X, PV.X, -T0.Z,
+; CM-NEXT:     LSHR * T3.X, KC0[2].Y, literal.x,
 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
-; CM-NEXT:     LOG_IEEE T2.X, KC0[3].W,
-; CM-NEXT:     LOG_IEEE T2.Y (MASKED), KC0[3].W,
-; CM-NEXT:     LOG_IEEE T2.Z (MASKED), KC0[3].W,
-; CM-NEXT:     LOG_IEEE * T2.W (MASKED), KC0[3].W,
-; CM-NEXT:     LOG_IEEE T3.X (MASKED), KC0[3].Z,
-; CM-NEXT:     LOG_IEEE T3.Y, KC0[3].Z,
-; CM-NEXT:     LOG_IEEE T3.Z (MASKED), KC0[3].Z,
-; CM-NEXT:     LOG_IEEE * T3.W (MASKED), KC0[3].Z,
-; CM-NEXT:     LOG_IEEE T3.X, KC0[3].Y,
-; CM-NEXT:     LOG_IEEE T3.Y (MASKED), KC0[3].Y,
-; CM-NEXT:     LOG_IEEE T3.Z (MASKED), KC0[3].Y,
-; CM-NEXT:     LOG_IEEE * T3.W (MASKED), KC0[3].Y,
   %result = call <3 x float> @llvm.log2.v3f32(<3 x float> %in)
   store <3 x float> %result, ptr addrspace(1) %out
   ret void
 }
 
 ; FIXME: We should be able to merge these packets together on Cayman so we
 ; have a maximum of 4 instructions.
 define amdgpu_kernel void @s_log2_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
 ; SI-SDAG-LABEL: s_log2_v4f32:
 ; SI-SDAG:       ; %bb.0:
-; SI-SDAG-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xd
-; SI-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; SI-SDAG-NEXT:    s_mov_b32 s3, 0xf000
-; SI-SDAG-NEXT:    s_mov_b32 s2, -1
+; SI-SDAG-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
+; SI-SDAG-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
+; SI-SDAG-NEXT:    v_mov_b32_e32 v0, 0x800000
+; SI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; SI-SDAG-NEXT:    v_mov_b32_e32 v3, 0x4f800000
+; SI-SDAG-NEXT:    s_mov_b32 s7, 0xf000
 ; SI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-SDAG-NEXT:    v_log_f32_e32 v3, s7
-; SI-SDAG-NEXT:    v_log_f32_e32 v2, s6
-; SI-SDAG-NEXT:    v_log_f32_e32 v1, s5
-; SI-SDAG-NEXT:    v_log_f32_e32 v0, s4
-; SI-SDAG-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; SI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s3, v0
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v2, 0, v1, vcc
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v4, 1.0, v3, vcc
+; SI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s2, v0
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v5, 0, v1, vcc
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v6, 1.0, v3, vcc
+; SI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s1, v0
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v7, 0, v1, vcc
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v8, 1.0, v3, vcc
+; SI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s0, v0
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v3, vcc
+; SI-SDAG-NEXT:    v_mul_f32_e32 v4, s3, v4
+; SI-SDAG-NEXT:    v_mul_f32_e32 v6, s2, v6
+; SI-SDAG-NEXT:    v_mul_f32_e32 v8, s1, v8
+; SI-SDAG-NEXT:    v_mul_f32_e32 v1, s0, v1
+; SI-SDAG-NEXT:    v_log_f32_e32 v4, v4
+; SI-SDAG-NEXT:    v_log_f32_e32 v6, v6
+; SI-SDAG-NEXT:    v_log_f32_e32 v8, v8
+; SI-SDAG-NEXT:    v_log_f32_e32 v9, v1
+; SI-SDAG-NEXT:    s_mov_b32 s6, -1
+; SI-SDAG-NEXT:    v_sub_f32_e32 v3, v4, v2
+; SI-SDAG-NEXT:    v_sub_f32_e32 v2, v6, v5
+; SI-SDAG-NEXT:    v_sub_f32_e32 v1, v8, v7
+; SI-SDAG-NEXT:    v_sub_f32_e32 v0, v9, v0
+; SI-SDAG-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
 ; SI-SDAG-NEXT:    s_endpgm
 ;
 ; SI-GISEL-LABEL: s_log2_v4f32:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xd
-; SI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; SI-GISEL-NEXT:    s_mov_b32 s2, -1
-; SI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x9
+; SI-GISEL-NEXT:    s_mov_b32 s0, 0x800000
+; SI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x4f800000
+; SI-GISEL-NEXT:    v_mov_b32_e32 v4, 0x42000000
 ; SI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-GISEL-NEXT:    v_log_f32_e32 v0, s4
-; SI-GISEL-NEXT:    v_log_f32_e32 v1, s5
-; SI-GISEL-NEXT:    v_log_f32_e32 v2, s6
-; SI-GISEL-NEXT:    v_log_f32_e32 v3, s7
-; SI-GISEL-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; SI-GISEL-NEXT:    v_mov_b32_e32 v0, s4
+; SI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s0, v0
+; SI-GISEL-NEXT:    v_mov_b32_e32 v1, s5
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v0, 1.0, v3, vcc
+; SI-GISEL-NEXT:    v_cmp_gt_f32_e64 s[0:1], s0, v1
+; SI-GISEL-NEXT:    v_mul_f32_e32 v0, s4, v0
+; SI-GISEL-NEXT:    v_cndmask_b32_e64 v1, 1.0, v3, s[0:1]
+; SI-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT:    v_mul_f32_e32 v1, s5, v1
+; SI-GISEL-NEXT:    v_log_f32_e32 v1, v1
+; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x800000
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v5, 0, v4, vcc
+; SI-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v5
+; SI-GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, v4, s[0:1]
+; SI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, s6, v2
+; SI-GISEL-NEXT:    v_cmp_lt_f32_e64 s[0:1], s7, v2
+; SI-GISEL-NEXT:    v_sub_f32_e32 v1, v1, v5
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v5, 1.0, v3, vcc
+; SI-GISEL-NEXT:    v_cndmask_b32_e64 v2, 1.0, v3, s[0:1]
+; SI-GISEL-NEXT:    v_mul_f32_e32 v5, s6, v5
+; SI-GISEL-NEXT:    v_mul_f32_e32 v2, s7, v2
+; SI-GISEL-NEXT:    v_log_f32_e32 v5, v5
+; SI-GISEL-NEXT:    v_log_f32_e32 v3, v2
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v2, 0, v4, vcc
+; SI-GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, v4, s[0:1]
+; SI-GISEL-NEXT:    v_sub_f32_e32 v2, v5, v2
+; SI-GISEL-NEXT:    v_sub_f32_e32 v3, v3, v4
+; SI-GISEL-NEXT:    s_mov_b32 s10, -1
+; SI-GISEL-NEXT:    s_mov_b32 s11, 0xf000
+; SI-GISEL-NEXT:    buffer_store_dwordx4 v[0:3], off, s[8:11], 0
 ; SI-GISEL-NEXT:    s_endpgm
 ;
 ; VI-SDAG-LABEL: s_log2_v4f32:
 ; VI-SDAG:       ; %bb.0:
 ; VI-SDAG-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
 ; VI-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; VI-SDAG-NEXT:    v_mov_b32_e32 v0, 0x800000
+; VI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; VI-SDAG-NEXT:    v_mov_b32_e32 v3, 0x4f800000
 ; VI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT:    v_log_f32_e32 v3, s7
-; VI-SDAG-NEXT:    v_log_f32_e32 v2, s6
-; VI-SDAG-NEXT:    v_log_f32_e32 v1, s5
-; VI-SDAG-NEXT:    v_log_f32_e32 v0, s4
+; VI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s7, v0
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v2, 0, v1, vcc
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v4, 1.0, v3, vcc
+; VI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s6, v0
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v5, 0, v1, vcc
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v6, 1.0, v3, vcc
+; VI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s5, v0
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v7, 0, v1, vcc
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v8, 1.0, v3, vcc
+; VI-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT:    v_mul_f32_e32 v4, s7, v4
+; VI-SDAG-NEXT:    v_mul_f32_e32 v6, s6, v6
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v3, vcc
+; VI-SDAG-NEXT:    v_log_f32_e32 v4, v4
+; VI-SDAG-NEXT:    v_log_f32_e32 v6, v6
+; VI-SDAG-NEXT:    v_mul_f32_e32 v8, s5, v8
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, s4, v1
+; VI-SDAG-NEXT:    v_log_f32_e32 v8, v8
+; VI-SDAG-NEXT:    v_log_f32_e32 v9, v1
+; VI-SDAG-NEXT:    v_sub_f32_e32 v3, v4, v2
+; VI-SDAG-NEXT:    v_sub_f32_e32 v2, v6, v5
 ; VI-SDAG-NEXT:    v_mov_b32_e32 v5, s1
+; VI-SDAG-NEXT:    v_sub_f32_e32 v1, v8, v7
+; VI-SDAG-NEXT:    v_sub_f32_e32 v0, v9, v0
 ; VI-SDAG-NEXT:    v_mov_b32_e32 v4, s0
 ; VI-SDAG-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
 ; VI-SDAG-NEXT:    s_endpgm
 ;
 ; VI-GISEL-LABEL: s_log2_v4f32:
 ; VI-GISEL:       ; %bb.0:
 ; VI-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
-; VI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; VI-GISEL-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
+; VI-GISEL-NEXT:    s_mov_b32 s0, 0x800000
+; VI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x4f800000
+; VI-GISEL-NEXT:    v_mov_b32_e32 v4, 0x42000000
 ; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT:    v_log_f32_e32 v0, s4
-; VI-GISEL-NEXT:    v_log_f32_e32 v1, s5
-; VI-GISEL-NEXT:    v_log_f32_e32 v2, s6
-; VI-GISEL-NEXT:    v_log_f32_e32 v3, s7
-; VI-GISEL-NEXT:    v_mov_b32_e32 v5, s1
-; VI-GISEL-NEXT:    v_mov_b32_e32 v4, s0
+; VI-GISEL-NEXT:    v_mov_b32_e32 v0, s4
+; VI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s0, v0
+; VI-GISEL-NEXT:    v_mov_b32_e32 v1, s5
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, 1.0, v3, vcc
+; VI-GISEL-NEXT:    v_cmp_gt_f32_e64 s[0:1], s0, v1
+; VI-GISEL-NEXT:    v_mul_f32_e32 v0, s4, v0
+; VI-GISEL-NEXT:    v_cndmask_b32_e64 v1, 1.0, v3, s[0:1]
+; VI-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT:    v_mul_f32_e32 v1, s5, v1
+; VI-GISEL-NEXT:    v_log_f32_e32 v1, v1
+; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x800000
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v5, 0, v4, vcc
+; VI-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v5
+; VI-GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, v4, s[0:1]
+; VI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, s6, v2
+; VI-GISEL-NEXT:    v_cmp_lt_f32_e64 s[0:1], s7, v2
+; VI-GISEL-NEXT:    v_sub_f32_e32 v1, v1, v5
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v5, 1.0, v3, vcc
+; VI-GISEL-NEXT:    v_cndmask_b32_e64 v2, 1.0, v3, s[0:1]
+; VI-GISEL-NEXT:    v_mul_f32_e32 v5, s6, v5
+; VI-GISEL-NEXT:    v_mul_f32_e32 v2, s7, v2
+; VI-GISEL-NEXT:    v_log_f32_e32 v5, v5
+; VI-GISEL-NEXT:    v_log_f32_e32 v3, v2
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v2, 0, v4, vcc
+; VI-GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, v4, s[0:1]
+; VI-GISEL-NEXT:    v_sub_f32_e32 v2, v5, v2
+; VI-GISEL-NEXT:    v_sub_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT:    v_mov_b32_e32 v5, s3
+; VI-GISEL-NEXT:    v_mov_b32_e32 v4, s2
 ; VI-GISEL-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
 ; VI-GISEL-NEXT:    s_endpgm
 ;
 ; GFX900-SDAG-LABEL: s_log2_v4f32:
 ; GFX900-SDAG:       ; %bb.0:
 ; GFX900-SDAG-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
 ; GFX900-SDAG-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
-; GFX900-SDAG-NEXT:    v_mov_b32_e32 v4, 0
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v0, 0x800000
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v3, 0x4f800000
 ; GFX900-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX900-SDAG-NEXT:    v_log_f32_e32 v3, s7
-; GFX900-SDAG-NEXT:    v_log_f32_e32 v2, s6
-; GFX900-SDAG-NEXT:    v_log_f32_e32 v1, s5
-; GFX900-SDAG-NEXT:    v_log_f32_e32 v0, s4
+; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s7, v0
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v2, 0, v1, vcc
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v5, 1.0, v3, vcc
+; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s6, v0
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v6, 0, v1, vcc
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v7, 1.0, v3, vcc
+; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s5, v0
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v8, 0, v1, vcc
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v9, 1.0, v3, vcc
+; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v3, vcc
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v5, s7, v5
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v7, s6, v7
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v9, s5, v9
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, s4, v1
+; GFX900-SDAG-NEXT:    v_log_f32_e32 v5, v5
+; GFX900-SDAG-NEXT:    v_log_f32_e32 v7, v7
+; GFX900-SDAG-NEXT:    v_log_f32_e32 v9, v9
+; GFX900-SDAG-NEXT:    v_log_f32_e32 v10, v1
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v4, 0
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v3, v5, v2
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v2, v7, v6
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v1, v9, v8
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v0, v10, v0
 ; GFX900-SDAG-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3]
 ; GFX900-SDAG-NEXT:    s_endpgm
 ;
 ; GFX900-GISEL-LABEL: s_log2_v4f32:
 ; GFX900-GISEL:       ; %bb.0:
 ; GFX900-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
 ; GFX900-GISEL-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
-; GFX900-GISEL-NEXT:    v_mov_b32_e32 v4, 0
+; GFX900-GISEL-NEXT:    s_mov_b32 s0, 0x800000
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v3, 0x4f800000
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v4, 0x42000000
 ; GFX900-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX900-GISEL-NEXT:    v_log_f32_e32 v0, s4
-; GFX900-GISEL-NEXT:    v_log_f32_e32 v1, s5
-; GFX900-GISEL-NEXT:    v_log_f32_e32 v2, s6
-; GFX900-GISEL-NEXT:    v_log_f32_e32 v3, s7
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v0, s4
+; GFX900-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, s0, v0
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, s5
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v0, 1.0, v3, vcc
+; GFX900-GISEL-NEXT:    v_cmp_gt_f32_e64 s[0:1], s0, v1
+; GFX900-GISEL-NEXT:    v_mul_f32_e32 v0, s4, v0
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e64 v1, 1.0, v3, s[0:1]
+; GFX900-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT:    v_mul_f32_e32 v1, s5, v1
+; GFX900-GISEL-NEXT:    v_log_f32_e32 v1, v1
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x800000
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v5, 0, v4, vcc
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v5
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, v4, s[0:1]
+; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, s6, v2
+; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e64 s[0:1], s7, v2
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v1, v1, v5
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v5, 1.0, v3, vcc
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e64 v2, 1.0, v3, s[0:1]
+; GFX900-GISEL-NEXT:    v_mul_f32_e32 v5, s6, v5
+; GFX900-GISEL-NEXT:    v_mul_f32_e32 v2, s7, v2
+; GFX900-GISEL-NEXT:    v_log_f32_e32 v5, v5
+; GFX900-GISEL-NEXT:    v_log_f32_e32 v3, v2
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v2, 0, v4, vcc
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, v4, s[0:1]
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v2, v5, v2
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v3, v3, v4
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX900-GISEL-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3]
 ; GFX900-GISEL-NEXT:    s_endpgm
 ;
 ; R600-LABEL: s_log2_v4f32:
 ; R600:       ; %bb.0:
-; R600-NEXT:    ALU 5, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT:    ALU 33, @4, KC0[CB0:0-32], KC1[]
 ; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ; R600-NEXT:    ALU clause starting at 4:
-; R600-NEXT:     LOG_IEEE * T0.W, KC0[4].X,
-; R600-NEXT:     LOG_IEEE * T0.Z, KC0[3].W,
-; R600-NEXT:     LOG_IEEE * T0.Y, KC0[3].Z,
-; R600-NEXT:     LSHR T1.X, KC0[2].Y, literal.x,
-; R600-NEXT:     LOG_IEEE * T0.X, KC0[3].Y,
+; R600-NEXT:     SETGT T0.W, literal.x, KC0[4].X,
+; R600-NEXT:     SETGT * T1.W, literal.x, KC0[3].W,
+; R600-NEXT:    8388608(1.175494e-38), 0(0.000000e+00)
+; R600-NEXT:     CNDE * T2.W, PV.W, 1.0, literal.x,
+; R600-NEXT:    1333788672(4.294967e+09), 0(0.000000e+00)
+; R600-NEXT:     MUL_IEEE T0.Z, KC0[4].X, PV.W,
+; R600-NEXT:     SETGT T2.W, literal.x, KC0[3].Z,
+; R600-NEXT:     CNDE * T3.W, T1.W, 1.0, literal.y,
+; R600-NEXT:    8388608(1.175494e-38), 1333788672(4.294967e+09)
+; R600-NEXT:     MUL_IEEE T0.X, KC0[3].W, PS,
+; R600-NEXT:     CNDE T0.Y, T0.W, 0.0, literal.x,
+; R600-NEXT:     SETGT T1.Z, literal.y, KC0[3].Y,
+; R600-NEXT:     CNDE T0.W, PV.W, 1.0, literal.z,
+; R600-NEXT:     LOG_IEEE * T0.Z, PV.Z,
+; R600-NEXT:    1107296256(3.200000e+01), 8388608(1.175494e-38)
+; R600-NEXT:    1333788672(4.294967e+09), 0(0.000000e+00)
+; R600-NEXT:     MUL_IEEE T1.X, KC0[3].Z, PV.W,
+; R600-NEXT:     CNDE T1.Y, T1.W, 0.0, literal.x,
+; R600-NEXT:     CNDE T2.Z, PV.Z, 1.0, literal.y,
+; R600-NEXT:     ADD T0.W, PS, -PV.Y,
+; R600-NEXT:     LOG_IEEE * T0.X, PV.X,
+; R600-NEXT:    1107296256(3.200000e+01), 1333788672(4.294967e+09)
+; R600-NEXT:     MUL_IEEE T2.Y, KC0[3].Y, PV.Z,
+; R600-NEXT:     ADD T0.Z, PS, -PV.Y,
+; R600-NEXT:     CNDE T1.W, T2.W, 0.0, literal.x,
+; R600-NEXT:     LOG_IEEE * T0.X, PV.X,
+; R600-NEXT:    1107296256(3.200000e+01), 0(0.000000e+00)
+; R600-NEXT:     ADD T0.Y, PS, -PV.W,
+; R600-NEXT:     CNDE T1.W, T1.Z, 0.0, literal.x,
+; R600-NEXT:     LOG_IEEE * T0.X, PV.Y,
+; R600-NEXT:    1107296256(3.200000e+01), 0(0.000000e+00)
+; R600-NEXT:     ADD T0.X, PS, -PV.W,
+; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
 ; CM-LABEL: s_log2_v4f32:
 ; CM:       ; %bb.0:
-; CM-NEXT:    ALU 17, @4, KC0[CB0:0-32], KC1[]
-; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T1, T0.X
+; CM-NEXT:    ALU 43, @4, KC0[CB0:0-32], KC1[]
+; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0, T1.X
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
 ; CM-NEXT:    ALU clause starting at 4:
-; CM-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
+; CM-NEXT:     SETGT * T0.W, literal.x, KC0[4].X,
+; CM-NEXT:    8388608(1.175494e-38), 0(0.000000e+00)
+; CM-NEXT:     CNDE T0.Y, PV.W, 1.0, literal.x,
+; CM-NEXT:     SETGT T0.Z, literal.y, KC0[3].W,
+; CM-NEXT:     SETGT * T1.W, literal.y, KC0[3].Z,
+; CM-NEXT:    1333788672(4.294967e+09), 8388608(1.175494e-38)
+; CM-NEXT:     CNDE T0.X, PV.W, 1.0, literal.x,
+; CM-NEXT:     CNDE T1.Y, T0.W, 0.0, literal.y,
+; CM-NEXT:     CNDE T1.Z, PV.Z, 1.0, literal.x,
+; CM-NEXT:     MUL_IEEE * T0.W, KC0[4].X, PV.Y,
+; CM-NEXT:    1333788672(4.294967e+09), 1107296256(3.200000e+01)
+; CM-NEXT:     LOG_IEEE T0.X (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE T0.Y, T0.W,
+; CM-NEXT:     LOG_IEEE T0.Z (MASKED), T0.W,
+; CM-NEXT:     LOG_IEEE * T0.W (MASKED), T0.W,
+; CM-NEXT:     CNDE T1.X, T0.Z, 0.0, literal.x,
+; CM-NEXT:     SETGT T2.Y, literal.y, KC0[3].Y,
+; CM-NEXT:     MUL_IEEE T0.Z, KC0[3].W, T1.Z,
+; CM-NEXT:     ADD * T0.W, PV.Y, -T1.Y,
+; CM-NEXT:    1107296256(3.200000e+01), 8388608(1.175494e-38)
+; CM-NEXT:     LOG_IEEE T0.X (MASKED), T0.Z,
+; CM-NEXT:     LOG_IEEE T0.Y, T0.Z,
+; CM-NEXT:     LOG_IEEE T0.Z (MASKED), T0.Z,
+; CM-NEXT:     LOG_IEEE * T0.W (MASKED), T0.Z,
+; CM-NEXT:     CNDE T2.X, T2.Y, 1.0, literal.x,
+; CM-NEXT:     CNDE T1.Y, T1.W, 0.0, literal.y,
+; CM-NEXT:     ADD T0.Z, PV.Y, -T1.X,
+; CM-NEXT:     MUL_IEEE * T1.W, KC0[3].Z, T0.X, BS:VEC_021/SCL_122
+; CM-NEXT:    1333788672(4.294967e+09), 1107296256(3.200000e+01)
+; CM-NEXT:     LOG_IEEE T0.X, T1.W,
+; CM-NEXT:     LOG_IEEE T0.Y (MASKED), T1.W,
+; CM-NEXT:     LOG_IEEE T0.Z (MASKED), T1.W,
+; CM-NEXT:     LOG_IEEE * T0.W (MASKED), T1.W,
+; CM-NEXT:     ADD T0.Y, PV.X, -T1.Y,
+; CM-NEXT:     CNDE T1.Z, T2.Y, 0.0, literal.x,
+; CM-NEXT:     MUL_IEEE * T1.W, KC0[3].Y, T2.X,
+; CM-NEXT:    1107296256(3.200000e+01), 0(0.000000e+00)
+; CM-NEXT:     LOG_IEEE T0.X, T1.W,
+; CM-NEXT:     LOG_IEEE T0.Y (MASKED), T1.W,
+; CM-NEXT:     LOG_IEEE T0.Z (MASKED), T1.W,
+; CM-NEXT:     LOG_IEEE * T0.W (MASKED), T1.W,
+; CM-NEXT:     ADD * T0.X, PV.X, -T1.Z,
+; CM-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
-; CM-NEXT:     LOG_IEEE T1.X (MASKED), KC0[4].X,
-; CM-NEXT:     LOG_IEEE T1.Y (MASKED), KC0[4].X,
-; CM-NEXT:     LOG_IEEE T1.Z (MASKED), KC0[4].X,
-; CM-NEXT:     LOG_IEEE * T1.W, KC0[4].X,
-; CM-NEXT:     LOG_IEEE T1.X (MASKED), KC0[3].W,
-; CM-NEXT:     LOG_IEEE T1.Y (MASKED), KC0[3].W,
-; CM-NEXT:     LOG_IEEE T1.Z, KC0[3].W,
-; CM-NEXT:     LOG_IEEE * T1.W (MASKED), KC0[3].W,
-; CM-NEXT:     LOG_IEEE T1.X (MASKED), KC0[3].Z,
-; CM-NEXT:     LOG_IEEE T1.Y, KC0[3].Z,
-; CM-NEXT:     LOG_IEEE T1.Z (MASKED), KC0[3].Z,
-; CM-NEXT:     LOG_IEEE * T1.W (MASKED), KC0[3].Z,
-; CM-NEXT:     LOG_IEEE T1.X, KC0[3].Y,
-; CM-NEXT:     LOG_IEEE T1.Y (MASKED), KC0[3].Y,
-; CM-NEXT:     LOG_IEEE T1.Z (MASKED), KC0[3].Y,
-; CM-NEXT:     LOG_IEEE * T1.W (MASKED), KC0[3].Y,
   %result = call <4 x float> @llvm.log2.v4f32(<4 x float> %in)
   store <4 x float> %result, ptr addrspace(1) %out
   ret void
 }
 
 define float @v_log2_f32(float %in) {
-; GCN-LABEL: v_log2_f32:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log2_f32:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x800000
+; GCN-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log2_f32:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log2_f32:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log2_f32:
 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %result = call float @llvm.log2.f32(float %in)
   ret float %result
 }
 
 define float @v_log2_fabs_f32(float %in) {
-; GCN-LABEL: v_log2_fabs_f32:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e64 v0, |v0|
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log2_fabs_f32:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x800000
+; GCN-SDAG-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e64 v0, |v0|, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log2_fabs_f32:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-GISEL-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v1
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-GISEL-NEXT:    v_mul_f32_e64 v0, |v0|, v1
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log2_fabs_f32:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log2_fabs_f32:
 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %fabs = call float @llvm.fabs.f32(float %in)
   %result = call float @llvm.log2.f32(float %fabs)
   ret float %result
 }
 
 define float @v_log2_fneg_fabs_f32(float %in) {
-; GCN-LABEL: v_log2_fneg_fabs_f32:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e64 v0, -|v0|
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log2_fneg_fabs_f32:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x80800000
+; GCN-SDAG-NEXT:    v_cmp_gt_f32_e64 vcc, |v0|, s4
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e64 v0, -|v0|, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log2_fneg_fabs_f32:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-GISEL-NEXT:    v_cmp_lt_f32_e64 vcc, -|v0|, v1
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-GISEL-NEXT:    v_mul_f32_e64 v0, -|v0|, v1
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log2_fneg_fabs_f32:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log2_fneg_fabs_f32:
 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %fabs = call float @llvm.fabs.f32(float %in)
   %fneg.fabs = fneg float %fabs
   %result = call float @llvm.log2.f32(float %fneg.fabs)
   ret float %result
 }
 
 define float @v_log2_fneg_f32(float %in) {
-; GCN-LABEL: v_log2_fneg_f32:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e64 v0, -v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log2_fneg_f32:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x80800000
+; GCN-SDAG-NEXT:    v_cmp_lt_f32_e32 vcc, s4, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e64 v0, -v0, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log2_fneg_f32:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-GISEL-NEXT:    v_cmp_lt_f32_e64 vcc, -v0, v1
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-GISEL-NEXT:    v_mul_f32_e64 v0, -v0, v1
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log2_fneg_f32:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log2_fneg_f32:
 ; CM:       ; %bb.0:

 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %result = call float @llvm.log2.f32(float %in)
   ret float %result
 }
 
 define float @v_log2_f32_ninf(float %in) {
-; GCN-LABEL: v_log2_f32_ninf:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log2_f32_ninf:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x800000
+; GCN-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log2_f32_ninf:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log2_f32_ninf:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log2_f32_ninf:
 ; CM:       ; %bb.0:

 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %result = call float @llvm.log2.f32(float %in)
   ret float %result
 }
 
 define float @v_log2_f32_nnan(float %in) {
-; GCN-LABEL: v_log2_f32_nnan:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log2_f32_nnan:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x800000
+; GCN-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log2_f32_nnan:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log2_f32_nnan:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log2_f32_nnan:
 ; CM:       ; %bb.0:

 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %result = call nnan float @llvm.log2.f32(float %in)
   ret float %result
 }
 
 define float @v_log2_f32_nnan_dynamic(float %in) #1 {
-; GCN-LABEL: v_log2_f32_nnan_dynamic:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log2_f32_nnan_dynamic:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x800000
+; GCN-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log2_f32_nnan_dynamic:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log2_f32_nnan_dynamic:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log2_f32_nnan_dynamic:
 ; CM:       ; %bb.0:

 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %result = call ninf float @llvm.log2.f32(float %in)
   ret float %result
 }
 
 define float @v_log2_f32_ninf_dynamic(float %in) #1 {
-; GCN-LABEL: v_log2_f32_ninf_dynamic:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log2_f32_ninf_dynamic:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x800000
+; GCN-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log2_f32_ninf_dynamic:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log2_f32_ninf_dynamic:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log2_f32_ninf_dynamic:
 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %result = call ninf float @llvm.log2.f32(float %in)
   ret float %result
 }
 
 define float @v_log2_f32_nnan_ninf(float %in) {
-; GCN-LABEL: v_log2_f32_nnan_ninf:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log2_f32_nnan_ninf:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x800000
+; GCN-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log2_f32_nnan_ninf:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log2_f32_nnan_ninf:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log2_f32_nnan_ninf:
 ; CM:       ; %bb.0:

 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %result = call nnan ninf float @llvm.log2.f32(float %in)
   ret float %result
 }
 
 define float @v_log2_f32_nnan_ninf_dynamic(float %in) #1 {
-; GCN-LABEL: v_log2_f32_nnan_ninf_dynamic:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log2_f32_nnan_ninf_dynamic:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x800000
+; GCN-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log2_f32_nnan_ninf_dynamic:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log2_f32_nnan_ninf_dynamic:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log2_f32_nnan_ninf_dynamic:
 ; CM:       ; %bb.0:

 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %result = call fast float @llvm.log2.f32(float %in)
   ret float %result
 }
 
 define float @v_log2_f32_dynamic_mode(float %in) #1 {
-; GCN-LABEL: v_log2_f32_dynamic_mode:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log2_f32_dynamic_mode:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x800000
+; GCN-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v2
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log2_f32_dynamic_mode:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log2_f32_dynamic_mode:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log2_f32_dynamic_mode:
 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %result = call float @llvm.log2.f32(float %in)
   ret float %result
 }
 
 define float @v_log2_f32_undef() {
-; GCN-LABEL: v_log2_f32_undef:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_log_f32_e32 v0, s4
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-SDAG-LABEL: v_log2_f32_undef:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    v_log_f32_e32 v0, s4
+; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-GISEL-LABEL: v_log2_f32_undef:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v0, 0x800000
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x4f800000
+; GCN-GISEL-NEXT:    v_mul_f32_e32 v1, s4, v1
+; GCN-GISEL-NEXT:    v_mul_f32_e64 v2, s4, 1.0
+; GCN-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, s4, v0
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc
+; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log2_f32_undef:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ;
 ; CM-LABEL: v_log2_f32_undef:
 ; CM:       ; %bb.0:
 ; CM-NEXT:    CF_END
 ; CM-NEXT:    PAD
   %result = call float @llvm.log2.f32(float undef)
   ret float %result
 }
 
 define float @v_log2_f32_0() {
 ; GCN-SDAG-LABEL: v_log2_f32_0:
 ; GCN-SDAG:       ; %bb.0:
 ; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-SDAG-NEXT:    v_log_f32_e32 v0, 0
+; GCN-SDAG-NEXT:    v_add_f32_e32 v0, 0xc2000000, v0
 ; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GCN-GISEL-LABEL: v_log2_f32_0:
 ; GCN-GISEL:       ; %bb.0:
 ; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-GISEL-NEXT:    v_mov_b32_e32 v0, 0xff800000
 ; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;

 }
 
 define float @v_log2_f32_from_fpext_math_f16(i16 %src0.i, i16 %src1.i) {
 ; SI-SDAG-LABEL: v_log2_f32_from_fpext_math_f16:
 ; SI-SDAG:       ; %bb.0:
 ; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-SDAG-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; SI-SDAG-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; SI-SDAG-NEXT:    s_mov_b32 s4, 0x800000
 ; SI-SDAG-NEXT:    v_add_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x4f800000
+; SI-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
+; SI-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; SI-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-GISEL-LABEL: v_log2_f32_from_fpext_math_f16:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-GISEL-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; SI-GISEL-NEXT:    v_cvt_f32_f16_e32 v1, v1
 ; SI-GISEL-NEXT:    v_add_f32_e32 v0, v0, v1
; GFX89-NEXT:    s_setpc_b64 s[30:31]
   %result = call float @llvm.log2.f32(float %fpext)
   ret float %result
 }
 
 define float @v_log2_f32_from_fpext_bf16(bfloat %src) {
 ; GCN-SDAG-LABEL: v_log2_f32_from_fpext_bf16:
 ; GCN-SDAG:       ; %bb.0:
 ; GCN-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SDAG-NEXT:    s_mov_b32 s4, 0x800000
+; GCN-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v2, 0x4f800000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GCN-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v2
 ; GCN-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, 0x42000000
+; GCN-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GCN-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; GCN-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GCN-GISEL-LABEL: v_log2_f32_from_fpext_bf16:
 ; GCN-GISEL:       ; %bb.0:
 ; GCN-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-GISEL-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; GCN-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; GCN-GISEL-NEXT:    s_setpc_b64 s[30:31]

 ; GFX89-GISEL-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; GFX89-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; GFX89-GISEL-NEXT:    s_setpc_b64 s[30:31]
   %fpext = fpext bfloat %src to float
   %result = call float @llvm.log2.f32(float %fpext)
   ret float %result
 }
 
+; FIXME: Fold out fp16_to_fp (FP_TO_FP16) on no-f16 targets
 define half @v_log2_f16(half %in) {
 ; SI-SDAG-LABEL: v_log2_f16:
 ; SI-SDAG:       ; %bb.0:
 ; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; SI-SDAG-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; SI-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; SI-SDAG-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-GISEL-LABEL: v_log2_f16:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-GISEL-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; SI-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; SI-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0

 
 define half @v_log2_fabs_f16(half %in) {
 ; SI-SDAG-LABEL: v_log2_fabs_f16:
 ; SI-SDAG:       ; %bb.0:
 ; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; SI-SDAG-NEXT:    v_cvt_f32_f16_e64 v0, |v0|
 ; SI-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; SI-SDAG-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-GISEL-LABEL: v_log2_fabs_f16:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-GISEL-NEXT:    v_cvt_f32_f16_e64 v0, |v0|
 ; SI-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; SI-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0

 
 define half @v_log2_fneg_fabs_f16(half %in) {
 ; SI-SDAG-LABEL: v_log2_fneg_fabs_f16:
 ; SI-SDAG:       ; %bb.0:
 ; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; SI-SDAG-NEXT:    v_cvt_f32_f16_e64 v0, -|v0|
 ; SI-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; SI-SDAG-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-GISEL-LABEL: v_log2_fneg_fabs_f16:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-GISEL-NEXT:    v_cvt_f32_f16_e64 v0, -|v0|
 ; SI-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; SI-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0

 
 define half @v_log2_fneg_f16(half %in) {
 ; SI-SDAG-LABEL: v_log2_fneg_f16:
 ; SI-SDAG:       ; %bb.0:
 ; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-SDAG-NEXT:    v_cvt_f16_f32_e64 v0, -v0
 ; SI-SDAG-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; SI-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; SI-SDAG-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-GISEL-LABEL: v_log2_fneg_f16:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-GISEL-NEXT:    v_cvt_f32_f16_e64 v0, -v0
 ; SI-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; SI-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0

 
 define half @v_log2_f16_fast(half %in) {
 ; SI-SDAG-LABEL: v_log2_f16_fast:
 ; SI-SDAG:       ; %bb.0:
 ; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; SI-SDAG-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; SI-SDAG-NEXT:    v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; SI-SDAG-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-GISEL-LABEL: v_log2_f16_fast:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-GISEL-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; SI-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; SI-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0

 ; SI-SDAG:       ; %bb.0:
 ; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; SI-SDAG-NEXT:    v_cvt_f16_f32_e32 v1, v1
 ; SI-SDAG-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; SI-SDAG-NEXT:    v_cvt_f32_f16_e32 v1, v1
 ; SI-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; SI-SDAG-NEXT:    v_log_f32_e32 v1, v1
+; SI-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; SI-SDAG-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; SI-SDAG-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; SI-SDAG-NEXT:    v_cvt_f32_f16_e32 v1, v1
 ; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-GISEL-LABEL: v_log2_v2f16:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-GISEL-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; SI-GISEL-NEXT:    v_cvt_f32_f16_e32 v1, v1
 ; SI-GISEL-NEXT:    v_log_f32_e32 v0, v0

 ; SI-SDAG:       ; %bb.0:
 ; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; SI-SDAG-NEXT:    v_cvt_f16_f32_e32 v1, v1
 ; SI-SDAG-NEXT:    v_cvt_f32_f16_e64 v0, |v0|
 ; SI-SDAG-NEXT:    v_cvt_f32_f16_e64 v1, |v1|
 ; SI-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; SI-SDAG-NEXT:    v_log_f32_e32 v1, v1
+; SI-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; SI-SDAG-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; SI-SDAG-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; SI-SDAG-NEXT:    v_cvt_f32_f16_e32 v1, v1
 ; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-GISEL-LABEL: v_log2_fabs_v2f16:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-GISEL-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
 ; SI-GISEL-NEXT:    v_and_b32_e32 v0, 0xffff, v0
 ; SI-GISEL-NEXT:    v_or_b32_e32 v0, v1, v0

 ; SI-SDAG-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
 ; SI-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
 ; SI-SDAG-NEXT:    v_or_b32_e32 v0, 0x80008000, v0
 ; SI-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
 ; SI-SDAG-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; SI-SDAG-NEXT:    v_cvt_f32_f16_e32 v1, v1
 ; SI-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; SI-SDAG-NEXT:    v_log_f32_e32 v1, v1
+; SI-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; SI-SDAG-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; SI-SDAG-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; SI-SDAG-NEXT:    v_cvt_f32_f16_e32 v1, v1
 ; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-GISEL-LABEL: v_log2_fneg_fabs_v2f16:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-GISEL-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
 ; SI-GISEL-NEXT:    v_and_b32_e32 v0, 0xffff, v0
 ; SI-GISEL-NEXT:    v_or_b32_e32 v0, v1, v0

 ; SI-SDAG-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
 ; SI-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
 ; SI-SDAG-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
 ; SI-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
 ; SI-SDAG-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; SI-SDAG-NEXT:    v_cvt_f32_f16_e32 v1, v1
 ; SI-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; SI-SDAG-NEXT:    v_log_f32_e32 v1, v1
+; SI-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; SI-SDAG-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; SI-SDAG-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; SI-SDAG-NEXT:    v_cvt_f32_f16_e32 v1, v1
 ; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-GISEL-LABEL: v_log2_fneg_v2f16:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-GISEL-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
 ; SI-GISEL-NEXT:    v_and_b32_e32 v0, 0xffff, v0
 ; SI-GISEL-NEXT:    v_or_b32_e32 v0, v1, v0

 ; SI-SDAG:       ; %bb.0:
 ; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; SI-SDAG-NEXT:    v_cvt_f16_f32_e32 v1, v1
 ; SI-SDAG-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; SI-SDAG-NEXT:    v_cvt_f32_f16_e32 v1, v1
 ; SI-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; SI-SDAG-NEXT:    v_log_f32_e32 v1, v1
+; SI-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; SI-SDAG-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; SI-SDAG-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; SI-SDAG-NEXT:    v_cvt_f32_f16_e32 v1, v1
 ; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-GISEL-LABEL: v_log2_v2f16_fast:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-GISEL-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; SI-GISEL-NEXT:    v_cvt_f32_f16_e32 v1, v1
 ; SI-GISEL-NEXT:    v_log_f32_e32 v0, v0

 declare half @llvm.fabs.f16(half) #2
 declare half @llvm.log2.f16(half) #2
 declare <2 x half> @llvm.log2.v2f16(<2 x half>) #2
 declare <2 x half> @llvm.fabs.v2f16(<2 x half>) #2
 
 attributes #0 = { "denormal-fp-math-f32"="ieee,preserve-sign" }
 attributes #1 = { "denormal-fp-math-f32"="dynamic,dynamic" }
 attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; SI: {{.*}}