[AArch64] Add tablegen patterns for faddp of two extracts

[dmgreen]

Summary

This adds some simple tablegen patterns for converting faddp v2f32 extractlow(Rn), v2f32 extracthigh(Rn) to faddp v4f32 Rn, v4f32 Rn using the q variants of the instructions, avoiding the extra ext needed to extract the high lanes. Only the bottom lanes of the new faddp are used, the second Rn operand is used as a placeholder. It uses Rn to prevent any false dependencies, but could equally by undef.

[david-arm]

llvm/lib/Target/AArch64/AArch64InstrInfo.td

8522

Hi @dmgreen, apologies for the drive-by comment, but I wonder if this needs a return type from extract_subvector in case it attempts to match the wrong subvector type? For example, in theory this may attempt to match

AArch64faddp (v1i32 extract_subvector (v4f32 FPR128:$Rn), (i64 0)),
                        (v1i32 extract_subvector (v4f32 FPR128:$Rn), (i64 2)))

as well as the pattern I presume you actually want to match, which is

AArch64faddp (v2i32 extract_subvector (v4f32 FPR128:$Rn), (i64 0)),
                        (v2i32 extract_subvector (v4f32 FPR128:$Rn), (i64 2)))

?

[dmgreen]

llvm/lib/Target/AArch64/AArch64InstrInfo.td

8522

Sorry I apparently missed this. v1f32 is neither a legal type, nor a valid input to AArch64faddp. I'm pretty sure that the only type this can be would be a v2f32. I can add them if you think it's better to be careful, but I don't believe it is necessary. Let me know if you think otherwise.

[david-arm]

LGTM!

llvm/lib/Target/AArch64/AArch64InstrInfo.td

8522

OK I see. Fair enough!

It also took me a while to understand that you are essentially transforming a FADDPv2f32 into a low(FADDPv4f32), which I see now. Perhaps having an explicit v2f32 type in here makes it more readable? But I'm not going to hold up the patch for it. :)

[dmgreen]

llvm/lib/Target/AArch64/AArch64InstrInfo.td

8522

Sounds good.

llvm/lib/Target/AArch64/AArch64InstrInfo.td

def : Pat<(f64 (any_fadd (vector_extract (v2f64 FPR128:$Rn), (i64 0)),
     // the low two lanes of a true v4f32 vector.
 def : Pat<(any_fadd (vector_extract (v4f32 FPR128:$Rn), (i64 0)),
                     (vector_extract (v4f32 FPR128:$Rn), (i64 1))),
           (f32 (FADDPv2i32p (EXTRACT_SUBREG FPR128:$Rn, dsub)))>;
 def : Pat<(any_fadd (vector_extract (v8f16 FPR128:$Rn), (i64 0)),
                     (vector_extract (v8f16 FPR128:$Rn), (i64 1))),
           (f16 (FADDPv2i16p (EXTRACT_SUBREG FPR128:$Rn, dsub)))>;
 
+// Prefer using the bottom lanes of faddp Rn, Rn compared to
+// faddp extractlow(Rn), extracthigh(Rn)
+def : Pat<(AArch64faddp (v2f32 (extract_subvector (v4f32 FPR128:$Rn), (i64 0))),
+                        (v2f32 (extract_subvector (v4f32 FPR128:$Rn), (i64 2)))),
+          (v2f32 (EXTRACT_SUBREG (FADDPv4f32 $Rn, $Rn), dsub))>;
+def : Pat<(AArch64faddp (v4f16 (extract_subvector (v8f16 FPR128:$Rn), (i64 0))),
+                        (v4f16 (extract_subvector (v8f16 FPR128:$Rn), (i64 4)))),
+          (v4f16 (EXTRACT_SUBREG (FADDPv8f16 $Rn, $Rn), dsub))>;
+
 // Scalar 64-bit shifts in FPR64 registers.
 def : Pat<(i64 (int_aarch64_neon_sshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
           (SSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
 def : Pat<(i64 (int_aarch64_neon_ushl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
           (USHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
 def : Pat<(i64 (int_aarch64_neon_srshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
           (SRSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
 def : Pat<(i64 (int_aarch64_neon_urshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),

llvm/test/CodeGen/AArch64/faddp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc --mtriple aarch64 < %s | FileCheck %s
+; RUN: llc --mtriple aarch64 -mattr=+fullfp16 < %s | FileCheck %s
 
 define float @faddp_2xfloat(<2 x float> %a) {
 ; CHECK-LABEL: faddp_2xfloat:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    faddp s0, v0.2s
 ; CHECK-NEXT:    ret
 entry:

 ; CHECK-NEXT:    zip2 v3.4s, v3.4s, v3.4s
 ; CHECK-NEXT:    ret
 entry:
   %s = shufflevector <16 x float> %a, <16 x float> poison, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
   %b = fadd reassoc <16 x float> %s, %a
   ret <16 x float> %b
 }
 
+define float @faddp_v4f32(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: faddp_v4f32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fadd v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    faddp v0.4s, v0.4s, v0.4s
+; CHECK-NEXT:    faddp s0, v0.2s
+; CHECK-NEXT:    ret
+  %1 = fadd <4 x float> %a, %b
+  %2 = shufflevector <4 x float> %1, <4 x float> poison, <2 x i32> <i32 0, i32 1>
+  %3 = shufflevector <4 x float> %1, <4 x float> poison, <2 x i32> <i32 2, i32 3>
+  %4 = tail call <2 x float> @llvm.aarch64.neon.faddp.v2f32(<2 x float> %2, <2 x float> %3)
+  %5 = shufflevector <2 x float> %4, <2 x float> poison, <2 x i32> <i32 1, i32 poison>
+  %6 = fadd <2 x float> %4, %5
+  %7 = extractelement <2 x float> %6, i64 0
+  ret float %7
+}
+
+define <4 x half> @faddp_v8f16(<8 x half> %a, <8 x half> %b) {
+; CHECK-LABEL: faddp_v8f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fadd v0.8h, v0.8h, v1.8h
+; CHECK-NEXT:    faddp v0.8h, v0.8h, v0.8h
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    ret
+  %1 = fadd <8 x half> %a, %b
+  %2 = shufflevector <8 x half> %1, <8 x half> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %3 = shufflevector <8 x half> %1, <8 x half> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+  %4 = tail call <4 x half> @llvm.aarch64.neon.faddp.v4f16(<4 x half> %2, <4 x half> %3)
+  ret <4 x half> %4
+}
+
+declare <2 x float> @llvm.aarch64.neon.faddp.v2f32(<2 x float>, <2 x float>)
+declare <4 x half> @llvm.aarch64.neon.faddp.v4f16(<4 x half>, <4 x half>)
 
 attributes #0 = { strictfp }
 
 declare <2 x float> @llvm.experimental.constrained.fadd.v2f32(<2 x float>, <2 x float>, metadata, metadata)
 declare <4 x float> @llvm.experimental.constrained.fadd.v4f32(<4 x float>, <4 x float>, metadata, metadata)
 declare <2 x double> @llvm.experimental.constrained.fadd.v2f64(<2 x double>, <2 x double>, metadata, metadata)