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Differential D152020

[RISCV] Split scheduler classes for vector min/max from compares.
ClosedPublic

Authored by craig.topper on Jun 2 2023, 12:04 PM.

Details

Reviewers
reames
frasercrmck
rogfer01
michaelmaitland
• pcwang-thead
Commits
rG8dd28c5682d6: [RISCV] Split scheduler classes for vector min/max from compares.
Summary

Compares write a mask result. Min/max write a full result. This
makes them sufficiently different to have their own classes.

Diff Detail

Event Timeline

craig.topper created this revision.Jun 2 2023, 12:04 PM
Herald added a project: Restricted Project. · View Herald TranscriptJun 2 2023, 12:04 PM
Herald added subscribers: jobnoorman, luke, VincentWu and 26 others. · View Herald Transcript
craig.topper requested review of this revision.Jun 2 2023, 12:04 PM
Herald added a project: Restricted Project. · View Herald TranscriptJun 2 2023, 12:04 PM
Herald added subscribers: eopXD, MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B236234: Diff 527927.Jun 2 2023, 12:56 PM
• pcwang-thead added a comment.Jun 4 2023, 8:12 PM

Should we modify VPseudoVMINMAX_VV_VX and VPseudoVMAX_VV_VF too?

craig.topper planned changes to this revision.Jun 4 2023, 8:57 PM
craig.topper updated this revision to Diff 529064.Jun 6 2023, 3:41 PM

Update the pseudoinstructions

Harbormaster completed remote builds in B237093: Diff 529064.Jun 6 2023, 7:27 PM
• pcwang-thead accepted this revision.Jun 6 2023, 8:00 PM

LGTM

This revision is now accepted and ready to land.Jun 6 2023, 8:00 PM
Closed by commit rG8dd28c5682d6: [RISCV] Split scheduler classes for vector min/max from compares. (authored by craig.topper). · Explain WhyJun 6 2023, 10:26 PM
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG8dd28c5682d6: [RISCV] Split scheduler classes for vector min/max from compares..

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
30 lines
26 lines
12 lines
40 lines

Diff 529161

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

Show First 20 Lines • Show All 644 Lines • ▼ Show 20 Lines
} }
multiclass VRCP_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> { multiclass VRCP_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>, def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>,
Sched<[WriteVFRecpV_WorstCase, ReadVFRecpV_WorstCase, Sched<[WriteVFRecpV_WorstCase, ReadVFRecpV_WorstCase,
ReadVMask]>; ReadVMask]>;
} }
multiclass VMINMAX_FV_V_F<string opcodestr, bits<6> funct6> {
def V : VALUVV<funct6, OPFVV, opcodestr # ".vv">,
Sched<[WriteVFMinMaxV_WorstCase, ReadVFMinMaxV_WorstCase,
ReadVFMinMaxV_WorstCase, ReadVMask]>;
def F : VALUVF<funct6, OPFVF, opcodestr # ".vf">,
Sched<[WriteVFMinMaxF_WorstCase, ReadVFMinMaxV_WorstCase,
ReadVFMinMaxF_WorstCase, ReadVMask]>;
}
multiclass VCMP_FV_V_F<string opcodestr, bits<6> funct6> { multiclass VCMP_FV_V_F<string opcodestr, bits<6> funct6> {
def V : VALUVV<funct6, OPFVV, opcodestr # ".vv">, def V : VALUVV<funct6, OPFVV, opcodestr # ".vv">,
Sched<[WriteVFCmpV_WorstCase, ReadVFCmpV_WorstCase, Sched<[WriteVFCmpV_WorstCase, ReadVFCmpV_WorstCase,
ReadVFCmpV_WorstCase, ReadVMask]>; ReadVFCmpV_WorstCase, ReadVMask]>;
def F : VALUVF<funct6, OPFVF, opcodestr # ".vf">, def F : VALUVF<funct6, OPFVF, opcodestr # ".vf">,
Sched<[WriteVFCmpF_WorstCase, ReadVFCmpV_WorstCase, Sched<[WriteVFCmpF_WorstCase, ReadVFCmpV_WorstCase,
ReadVFCmpF_WorstCase, ReadVMask]>; ReadVFCmpF_WorstCase, ReadVMask]>;
} }
▲ Show 20 Lines • Show All 138 Lines • ▼ Show 20 Linesmulticlass VNSHT_IV_V_X_I<string opcodestr, bits<6> funct6> {
def X : VALUVX<funct6, OPIVX, opcodestr # ".wx">, def X : VALUVX<funct6, OPIVX, opcodestr # ".wx">,
Sched<[WriteVNShiftX_WorstCase, ReadVNShiftV_WorstCase, Sched<[WriteVNShiftX_WorstCase, ReadVNShiftV_WorstCase,
ReadVNShiftX_WorstCase, ReadVMask]>; ReadVNShiftX_WorstCase, ReadVMask]>;
def I : VALUVI<funct6, opcodestr # ".wi", uimm5>, def I : VALUVI<funct6, opcodestr # ".wi", uimm5>,
Sched<[WriteVNShiftI_WorstCase, ReadVNShiftV_WorstCase, Sched<[WriteVNShiftI_WorstCase, ReadVNShiftV_WorstCase,
ReadVMask]>; ReadVMask]>;
} }
multiclass VMINMAX_IV_V_X<string opcodestr, bits<6> funct6> {
def V : VALUVV<funct6, OPIVV, opcodestr # ".vv">,
Sched<[WriteVIMinMaxV_WorstCase, ReadVIMinMaxV_WorstCase,
ReadVIMinMaxV_WorstCase, ReadVMask]>;
def X : VALUVX<funct6, OPIVX, opcodestr # ".vx">,
Sched<[WriteVIMinMaxX_WorstCase, ReadVIMinMaxV_WorstCase,
ReadVIMinMaxX_WorstCase, ReadVMask]>;
}
multiclass VCMP_IV_V_X_I<string opcodestr, bits<6> funct6> { multiclass VCMP_IV_V_X_I<string opcodestr, bits<6> funct6> {
def V : VALUVV<funct6, OPIVV, opcodestr # ".vv">, def V : VALUVV<funct6, OPIVV, opcodestr # ".vv">,
Sched<[WriteVICmpV_WorstCase, ReadVICmpV_WorstCase, Sched<[WriteVICmpV_WorstCase, ReadVICmpV_WorstCase,
ReadVICmpV_WorstCase, ReadVMask]>; ReadVICmpV_WorstCase, ReadVMask]>;
def X : VALUVX<funct6, OPIVX, opcodestr # ".vx">, def X : VALUVX<funct6, OPIVX, opcodestr # ".vx">,
Sched<[WriteVICmpX_WorstCase, ReadVICmpV_WorstCase, Sched<[WriteVICmpX_WorstCase, ReadVICmpV_WorstCase,
ReadVICmpX_WorstCase, ReadVMask]>; ReadVICmpX_WorstCase, ReadVMask]>;
def I : VALUVI<funct6, opcodestr # ".vi", simm5>, def I : VALUVI<funct6, opcodestr # ".vi", simm5>,
▲ Show 20 Lines • Show All 408 Lines • ▼ Show 20 Linesdef PseudoVMSGEU_VX_M_T : Pseudo<(outs VR:$vd, VRNoV0:$scratch),
(ins VR:$vs2, GPR:$rs1, VMaskOp:$vm), (ins VR:$vs2, GPR:$rs1, VMaskOp:$vm),
[], "vmsgeu.vx", "$vd, $vs2, $rs1$vm, $scratch">; [], "vmsgeu.vx", "$vd, $vs2, $rs1$vm, $scratch">;
def PseudoVMSGE_VX_M_T : Pseudo<(outs VR:$vd, VRNoV0:$scratch), def PseudoVMSGE_VX_M_T : Pseudo<(outs VR:$vd, VRNoV0:$scratch),
(ins VR:$vs2, GPR:$rs1, VMaskOp:$vm), (ins VR:$vs2, GPR:$rs1, VMaskOp:$vm),
[], "vmsge.vx", "$vd, $vs2, $rs1$vm, $scratch">; [], "vmsge.vx", "$vd, $vs2, $rs1$vm, $scratch">;
} }
// Vector Integer Min/Max Instructions // Vector Integer Min/Max Instructions
defm VMINU_V : VCMP_IV_V_X<"vminu", 0b000100>; defm VMINU_V : VMINMAX_IV_V_X<"vminu", 0b000100>;
defm VMIN_V : VCMP_IV_V_X<"vmin", 0b000101>; defm VMIN_V : VMINMAX_IV_V_X<"vmin", 0b000101>;
defm VMAXU_V : VCMP_IV_V_X<"vmaxu", 0b000110>; defm VMAXU_V : VMINMAX_IV_V_X<"vmaxu", 0b000110>;
defm VMAX_V : VCMP_IV_V_X<"vmax", 0b000111>; defm VMAX_V : VMINMAX_IV_V_X<"vmax", 0b000111>;
// Vector Single-Width Integer Multiply Instructions // Vector Single-Width Integer Multiply Instructions
defm VMUL_V : VMUL_MV_V_X<"vmul", 0b100101>; defm VMUL_V : VMUL_MV_V_X<"vmul", 0b100101>;
defm VMULH_V : VMUL_MV_V_X<"vmulh", 0b100111>; defm VMULH_V : VMUL_MV_V_X<"vmulh", 0b100111>;
defm VMULHU_V : VMUL_MV_V_X<"vmulhu", 0b100100>; defm VMULHU_V : VMUL_MV_V_X<"vmulhu", 0b100100>;
defm VMULHSU_V : VMUL_MV_V_X<"vmulhsu", 0b100110>; defm VMULHSU_V : VMUL_MV_V_X<"vmulhsu", 0b100110>;
// Vector Integer Divide Instructions // Vector Integer Divide Instructions
▲ Show 20 Lines • Show All 135 Lines • ▼ Show 20 Lines
defm VFREC7_V : VRCP_FV_VS2<"vfrec7.v", 0b010011, 0b00101>; defm VFREC7_V : VRCP_FV_VS2<"vfrec7.v", 0b010011, 0b00101>;
} }
let mayRaiseFPException = true in let mayRaiseFPException = true in
defm VFRSQRT7_V : VRCP_FV_VS2<"vfrsqrt7.v", 0b010011, 0b00100>; defm VFRSQRT7_V : VRCP_FV_VS2<"vfrsqrt7.v", 0b010011, 0b00100>;
// Vector Floating-Point MIN/MAX Instructions // Vector Floating-Point MIN/MAX Instructions
let mayRaiseFPException = true in { let mayRaiseFPException = true in {
defm VFMIN_V : VCMP_FV_V_F<"vfmin", 0b000100>; defm VFMIN_V : VMINMAX_FV_V_F<"vfmin", 0b000100>;
defm VFMAX_V : VCMP_FV_V_F<"vfmax", 0b000110>; defm VFMAX_V : VMINMAX_FV_V_F<"vfmax", 0b000110>;
} }
// Vector Floating-Point Sign-Injection Instructions // Vector Floating-Point Sign-Injection Instructions
defm VFSGNJ_V : VSGNJ_FV_V_F<"vfsgnj", 0b001000>; defm VFSGNJ_V : VSGNJ_FV_V_F<"vfsgnj", 0b001000>;
defm VFSGNJN_V : VSGNJ_FV_V_F<"vfsgnjn", 0b001001>; defm VFSGNJN_V : VSGNJ_FV_V_F<"vfsgnjn", 0b001001>;
defm VFSGNJX_V : VSGNJ_FV_V_F<"vfsgnjx", 0b001010>; defm VFSGNJX_V : VSGNJ_FV_V_F<"vfsgnjx", 0b001010>;
def : InstAlias<"vfneg.v $vd, $vs$vm", def : InstAlias<"vfneg.v $vd, $vs$vm",
▲ Show 20 Lines • Show All 386 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 2,642 Lines • ▼ Show 20 Lines foreach m = MxList in {
defm "" : VPseudoBinaryV_VX<m>, defm "" : VPseudoBinaryV_VX<m>,
Sched<[WriteVAALUX_MX, ReadVAALUV_MX, ReadVAALUX_MX, ReadVMask]>; Sched<[WriteVAALUX_MX, ReadVAALUV_MX, ReadVAALUX_MX, ReadVMask]>;
} }
} }
multiclass VPseudoVMINMAX_VV_VX { multiclass VPseudoVMINMAX_VV_VX {
foreach m = MxList in { foreach m = MxList in {
defvar mx = m.MX; defvar mx = m.MX;
defvar WriteVICmpV_MX = !cast<SchedWrite>("WriteVICmpV_" # mx); defvar WriteVIMinMaxV_MX = !cast<SchedWrite>("WriteVIMinMaxV_" # mx);
defvar WriteVICmpX_MX = !cast<SchedWrite>("WriteVICmpX_" # mx); defvar WriteVIMinMaxX_MX = !cast<SchedWrite>("WriteVIMinMaxX_" # mx);
defvar ReadVICmpV_MX = !cast<SchedRead>("ReadVICmpV_" # mx); defvar ReadVIMinMaxV_MX = !cast<SchedRead>("ReadVIMinMaxV_" # mx);
defvar ReadVICmpX_MX = !cast<SchedRead>("ReadVICmpX_" # mx); defvar ReadVIMinMaxX_MX = !cast<SchedRead>("ReadVIMinMaxX_" # mx);
defm "" : VPseudoBinaryV_VV<m>, defm "" : VPseudoBinaryV_VV<m>,
Sched<[WriteVICmpV_MX, ReadVICmpV_MX, ReadVICmpV_MX, ReadVMask]>; Sched<[WriteVIMinMaxV_MX, ReadVIMinMaxV_MX, ReadVIMinMaxV_MX, ReadVMask]>;
defm "" : VPseudoBinaryV_VX<m>, defm "" : VPseudoBinaryV_VX<m>,
Sched<[WriteVICmpX_MX, ReadVICmpV_MX, ReadVICmpX_MX, ReadVMask]>; Sched<[WriteVIMinMaxX_MX, ReadVIMinMaxV_MX, ReadVIMinMaxX_MX, ReadVMask]>;
} }
} }
multiclass VPseudoVMUL_VV_VX { multiclass VPseudoVMUL_VV_VX {
foreach m = MxList in { foreach m = MxList in {
defvar mx = m.MX; defvar mx = m.MX;
defvar WriteVIMulV_MX = !cast<SchedWrite>("WriteVIMulV_" # mx); defvar WriteVIMulV_MX = !cast<SchedWrite>("WriteVIMulV_" # mx);
defvar WriteVIMulX_MX = !cast<SchedWrite>("WriteVIMulX_" # mx); defvar WriteVIMulX_MX = !cast<SchedWrite>("WriteVIMulX_" # mx);
▲ Show 20 Lines • Show All 130 Lines • ▼ Show 20 Lines foreach m = f.MxList in {
Sched<[WriteVFSgnjF_MX, ReadVFSgnjV_MX, ReadVFSgnjF_MX, ReadVMask]>; Sched<[WriteVFSgnjF_MX, ReadVFSgnjV_MX, ReadVFSgnjF_MX, ReadVMask]>;
} }
} }
} }
multiclass VPseudoVMAX_VV_VF { multiclass VPseudoVMAX_VV_VF {
foreach m = MxListF in { foreach m = MxListF in {
defvar mx = m.MX; defvar mx = m.MX;
defvar WriteVFCmpV_MX = !cast<SchedWrite>("WriteVFCmpV_" # mx); defvar WriteVFMinMaxV_MX = !cast<SchedWrite>("WriteVFMinMaxV_" # mx);
defvar ReadVFCmpV_MX = !cast<SchedRead>("ReadVFCmpV_" # mx); defvar ReadVFMinMaxV_MX = !cast<SchedRead>("ReadVFMinMaxV_" # mx);
defm "" : VPseudoBinaryFV_VV<m>, defm "" : VPseudoBinaryFV_VV<m>,
Sched<[WriteVFCmpV_MX, ReadVFCmpV_MX, ReadVFCmpV_MX, ReadVMask]>; Sched<[WriteVFMinMaxV_MX, ReadVFMinMaxV_MX, ReadVFMinMaxV_MX, ReadVMask]>;
} }
foreach f = FPList in { foreach f = FPList in {
foreach m = f.MxList in { foreach m = f.MxList in {
defvar mx = m.MX; defvar mx = m.MX;
defvar WriteVFCmpF_MX = !cast<SchedWrite>("WriteVFCmpF_" # mx); defvar WriteVFMinMaxF_MX = !cast<SchedWrite>("WriteVFMinMaxF_" # mx);
defvar ReadVFCmpV_MX = !cast<SchedRead>("ReadVFCmpV_" # mx); defvar ReadVFMinMaxV_MX = !cast<SchedRead>("ReadVFMinMaxV_" # mx);
defvar ReadVFCmpF_MX = !cast<SchedRead>("ReadVFCmpF_" # mx); defvar ReadVFMinMaxF_MX = !cast<SchedRead>("ReadVFMinMaxF_" # mx);
defm "" : VPseudoBinaryV_VF<m, f>, defm "" : VPseudoBinaryV_VF<m, f>,
Sched<[WriteVFCmpF_MX, ReadVFCmpV_MX, ReadVFCmpF_MX, ReadVMask]>; Sched<[WriteVFMinMaxF_MX, ReadVFMinMaxV_MX, ReadVFMinMaxF_MX, ReadVMask]>;
} }
} }
} }
multiclass VPseudoVALU_VV_VF { multiclass VPseudoVALU_VV_VF {
foreach m = MxListF in { foreach m = MxListF in {
defvar mx = m.MX; defvar mx = m.MX;
defvar WriteVFALUV_MX = !cast<SchedWrite>("WriteVFALUV_" # mx); defvar WriteVFALUV_MX = !cast<SchedWrite>("WriteVFALUV_" # mx);
▲ Show 20 Lines • Show All 4,044 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

Show First 20 Lines • Show All 442 Lines • ▼ Show 20 Lines let Latency = 4, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVIALUX", [SiFive7VA], mx, IsWorstCase>; defm "" : LMULWriteResMX<"WriteVIALUX", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVIALUI", [SiFive7VA], mx, IsWorstCase>; defm "" : LMULWriteResMX<"WriteVIALUI", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICALUV", [SiFive7VA], mx, IsWorstCase>; defm "" : LMULWriteResMX<"WriteVICALUV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICALUX", [SiFive7VA], mx, IsWorstCase>; defm "" : LMULWriteResMX<"WriteVICALUX", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICALUI", [SiFive7VA], mx, IsWorstCase>; defm "" : LMULWriteResMX<"WriteVICALUI", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVShiftV", [SiFive7VA], mx, IsWorstCase>; defm "" : LMULWriteResMX<"WriteVShiftV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVShiftX", [SiFive7VA], mx, IsWorstCase>; defm "" : LMULWriteResMX<"WriteVShiftX", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVShiftI", [SiFive7VA], mx, IsWorstCase>; defm "" : LMULWriteResMX<"WriteVShiftI", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVIMinMaxV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVIMinMaxX", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVIMulV", [SiFive7VA], mx, IsWorstCase>; defm "" : LMULWriteResMX<"WriteVIMulV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVIMulX", [SiFive7VA], mx, IsWorstCase>; defm "" : LMULWriteResMX<"WriteVIMulX", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVIMulAddV", [SiFive7VA], mx, IsWorstCase>; defm "" : LMULWriteResMX<"WriteVIMulAddV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVIMulAddX", [SiFive7VA], mx, IsWorstCase>; defm "" : LMULWriteResMX<"WriteVIMulAddX", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVIMergeV", [SiFive7VA], mx, IsWorstCase>; defm "" : LMULWriteResMX<"WriteVIMergeV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVIMergeX", [SiFive7VA], mx, IsWorstCase>; defm "" : LMULWriteResMX<"WriteVIMergeX", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVIMergeI", [SiFive7VA], mx, IsWorstCase>; defm "" : LMULWriteResMX<"WriteVIMergeI", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVIMovV", [SiFive7VA], mx, IsWorstCase>; defm "" : LMULWriteResMX<"WriteVIMovV", [SiFive7VA], mx, IsWorstCase>;
▲ Show 20 Lines • Show All 92 Lines • ▼ Show 20 Lines let Latency = 8, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVFMulAddF", [SiFive7VA], mx, IsWorstCase>; defm "" : LMULWriteResMX<"WriteVFMulAddF", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFRecpV", [SiFive7VA], mx, IsWorstCase>; defm "" : LMULWriteResMX<"WriteVFRecpV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFCvtIToFV", [SiFive7VA], mx, IsWorstCase>; defm "" : LMULWriteResMX<"WriteVFCvtIToFV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFCvtFToIV", [SiFive7VA], mx, IsWorstCase>; defm "" : LMULWriteResMX<"WriteVFCvtFToIV", [SiFive7VA], mx, IsWorstCase>;
} }
let Latency = 4, ResourceCycles = [Cycles] in { let Latency = 4, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVFSgnjV", [SiFive7VA], mx, IsWorstCase>; defm "" : LMULWriteResMX<"WriteVFSgnjV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFSgnjF", [SiFive7VA], mx, IsWorstCase>; defm "" : LMULWriteResMX<"WriteVFSgnjF", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFMinMaxV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFMinMaxF", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFClassV", [SiFive7VA], mx, IsWorstCase>; defm "" : LMULWriteResMX<"WriteVFClassV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFMergeV", [SiFive7VA], mx, IsWorstCase>; defm "" : LMULWriteResMX<"WriteVFMergeV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFMovV", [SiFive7VA], mx, IsWorstCase>; defm "" : LMULWriteResMX<"WriteVFMovV", [SiFive7VA], mx, IsWorstCase>;
} }
// Mask results can't chain. // Mask results can't chain.
let Latency = !add(Cycles, 3), ResourceCycles = [Cycles] in { let Latency = !add(Cycles, 3), ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVFCmpV", [SiFive7VA], mx, IsWorstCase>; defm "" : LMULWriteResMX<"WriteVFCmpV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFCmpF", [SiFive7VA], mx, IsWorstCase>; defm "" : LMULWriteResMX<"WriteVFCmpF", [SiFive7VA], mx, IsWorstCase>;
▲ Show 20 Lines • Show All 284 Lines • ▼ Show 20 Lines
defm : LMULReadAdvance<"ReadVICALUV", 0>; defm : LMULReadAdvance<"ReadVICALUV", 0>;
defm : LMULReadAdvance<"ReadVICALUX", 0>; defm : LMULReadAdvance<"ReadVICALUX", 0>;
defm : LMULReadAdvance<"ReadVShiftV", 0>; defm : LMULReadAdvance<"ReadVShiftV", 0>;
defm : LMULReadAdvance<"ReadVShiftX", 0>; defm : LMULReadAdvance<"ReadVShiftX", 0>;
defm : LMULReadAdvanceW<"ReadVNShiftV", 0>; defm : LMULReadAdvanceW<"ReadVNShiftV", 0>;
defm : LMULReadAdvanceW<"ReadVNShiftX", 0>; defm : LMULReadAdvanceW<"ReadVNShiftX", 0>;
defm : LMULReadAdvance<"ReadVICmpV", 0>; defm : LMULReadAdvance<"ReadVICmpV", 0>;
defm : LMULReadAdvance<"ReadVICmpX", 0>; defm : LMULReadAdvance<"ReadVICmpX", 0>;
defm : LMULReadAdvance<"ReadVIMinMaxV", 0>;
defm : LMULReadAdvance<"ReadVIMinMaxX", 0>;
defm : LMULReadAdvance<"ReadVIMulV", 0>; defm : LMULReadAdvance<"ReadVIMulV", 0>;
defm : LMULReadAdvance<"ReadVIMulX", 0>; defm : LMULReadAdvance<"ReadVIMulX", 0>;
defm : LMULSEWReadAdvance<"ReadVIDivV", 0>; defm : LMULSEWReadAdvance<"ReadVIDivV", 0>;
defm : LMULSEWReadAdvance<"ReadVIDivX", 0>; defm : LMULSEWReadAdvance<"ReadVIDivX", 0>;
defm : LMULReadAdvanceW<"ReadVIWMulV", 0>; defm : LMULReadAdvanceW<"ReadVIWMulV", 0>;
defm : LMULReadAdvanceW<"ReadVIWMulX", 0>; defm : LMULReadAdvanceW<"ReadVIWMulX", 0>;
defm : LMULReadAdvance<"ReadVIMulAddV", 0>; defm : LMULReadAdvance<"ReadVIMulAddV", 0>;
defm : LMULReadAdvance<"ReadVIMulAddX", 0>; defm : LMULReadAdvance<"ReadVIMulAddX", 0>;
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defm "" : LMULReadAdvanceFW<"ReadVFWMulV", 0>; defm "" : LMULReadAdvanceFW<"ReadVFWMulV", 0>;
defm "" : LMULReadAdvanceFW<"ReadVFWMulF", 0>; defm "" : LMULReadAdvanceFW<"ReadVFWMulF", 0>;
defm "" : LMULReadAdvance<"ReadVFMulAddV", 0>; defm "" : LMULReadAdvance<"ReadVFMulAddV", 0>;
defm "" : LMULReadAdvance<"ReadVFMulAddF", 0>; defm "" : LMULReadAdvance<"ReadVFMulAddF", 0>;
defm "" : LMULReadAdvanceFW<"ReadVFWMulAddV", 0>; defm "" : LMULReadAdvanceFW<"ReadVFWMulAddV", 0>;
defm "" : LMULReadAdvanceFW<"ReadVFWMulAddF", 0>; defm "" : LMULReadAdvanceFW<"ReadVFWMulAddF", 0>;
defm "" : LMULSEWReadAdvanceF<"ReadVFSqrtV", 0>; defm "" : LMULSEWReadAdvanceF<"ReadVFSqrtV", 0>;
defm "" : LMULReadAdvance<"ReadVFRecpV", 0>; defm "" : LMULReadAdvance<"ReadVFRecpV", 0>;
defm "" : LMULReadAdvance<"ReadVFCmpV", 0>; defm "" : LMULReadAdvance<"ReadVFMinMaxV", 0>;
defm "" : LMULReadAdvance<"ReadVFCmpF", 0>; defm "" : LMULReadAdvance<"ReadVFMinMaxF", 0>;
defm "" : LMULReadAdvance<"ReadVFSgnjV", 0>; defm "" : LMULReadAdvance<"ReadVFSgnjV", 0>;
defm "" : LMULReadAdvance<"ReadVFSgnjF", 0>; defm "" : LMULReadAdvance<"ReadVFSgnjF", 0>;
defm "" : LMULReadAdvance<"ReadVFCmpV", 0>;
defm "" : LMULReadAdvance<"ReadVFCmpF", 0>;
defm "" : LMULReadAdvance<"ReadVFClassV", 0>; defm "" : LMULReadAdvance<"ReadVFClassV", 0>;
defm "" : LMULReadAdvance<"ReadVFMergeV", 0>; defm "" : LMULReadAdvance<"ReadVFMergeV", 0>;
defm "" : LMULReadAdvance<"ReadVFMergeF", 0>; defm "" : LMULReadAdvance<"ReadVFMergeF", 0>;
defm "" : LMULReadAdvance<"ReadVFMovF", 0>; defm "" : LMULReadAdvance<"ReadVFMovF", 0>;
defm "" : LMULReadAdvance<"ReadVFCvtIToFV", 0>; defm "" : LMULReadAdvance<"ReadVFCvtIToFV", 0>;
defm "" : LMULReadAdvance<"ReadVFCvtFToIV", 0>; defm "" : LMULReadAdvance<"ReadVFCvtFToIV", 0>;
defm "" : LMULReadAdvanceW<"ReadVFWCvtIToFV", 0>; defm "" : LMULReadAdvanceW<"ReadVFWCvtIToFV", 0>;
defm "" : LMULReadAdvanceFW<"ReadVFWCvtFToIV", 0>; defm "" : LMULReadAdvanceFW<"ReadVFWCvtFToIV", 0>;
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llvm/lib/Target/RISCV/RISCVScheduleV.td

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defm "" : LMULSchedWrites<"WriteVShiftV">; defm "" : LMULSchedWrites<"WriteVShiftV">;
defm "" : LMULSchedWrites<"WriteVShiftX">; defm "" : LMULSchedWrites<"WriteVShiftX">;
defm "" : LMULSchedWrites<"WriteVShiftI">; defm "" : LMULSchedWrites<"WriteVShiftI">;
// 11.7. Vector Narrowing Integer Right Shift Instructions // 11.7. Vector Narrowing Integer Right Shift Instructions
defm "" : LMULSchedWritesW<"WriteVNShiftV">; defm "" : LMULSchedWritesW<"WriteVNShiftV">;
defm "" : LMULSchedWritesW<"WriteVNShiftX">; defm "" : LMULSchedWritesW<"WriteVNShiftX">;
defm "" : LMULSchedWritesW<"WriteVNShiftI">; defm "" : LMULSchedWritesW<"WriteVNShiftI">;
// 11.8. Vector Integer Comparison Instructions // 11.8. Vector Integer Comparison Instructions
// 11.9. Vector Integer Min/Max Instructions
defm "" : LMULSchedWrites<"WriteVICmpV">; defm "" : LMULSchedWrites<"WriteVICmpV">;
defm "" : LMULSchedWrites<"WriteVICmpX">; defm "" : LMULSchedWrites<"WriteVICmpX">;
defm "" : LMULSchedWrites<"WriteVICmpI">; defm "" : LMULSchedWrites<"WriteVICmpI">;
// 11.9. Vector Integer Min/Max Instructions
defm "" : LMULSchedWrites<"WriteVIMinMaxV">;
defm "" : LMULSchedWrites<"WriteVIMinMaxX">;
// 11.10. Vector Single-Width Integer Multiply Instructions // 11.10. Vector Single-Width Integer Multiply Instructions
defm "" : LMULSchedWrites<"WriteVIMulV">; defm "" : LMULSchedWrites<"WriteVIMulV">;
defm "" : LMULSchedWrites<"WriteVIMulX">; defm "" : LMULSchedWrites<"WriteVIMulX">;
// 11.11. Vector Integer Divide Instructions // 11.11. Vector Integer Divide Instructions
defm "" : LMULSEWSchedWrites<"WriteVIDivV">; defm "" : LMULSEWSchedWrites<"WriteVIDivV">;
defm "" : LMULSEWSchedWrites<"WriteVIDivX">; defm "" : LMULSEWSchedWrites<"WriteVIDivX">;
// 11.12. Vector Widening Integer Multiply Instructions // 11.12. Vector Widening Integer Multiply Instructions
defm "" : LMULSchedWritesW<"WriteVIWMulV">; defm "" : LMULSchedWritesW<"WriteVIWMulV">;
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defm "" : LMULSchedWritesFW<"WriteVFWMulAddV">; defm "" : LMULSchedWritesFW<"WriteVFWMulAddV">;
defm "" : LMULSchedWritesFW<"WriteVFWMulAddF">; defm "" : LMULSchedWritesFW<"WriteVFWMulAddF">;
// 13.8. Vector Floating-Point Square-Root Instruction // 13.8. Vector Floating-Point Square-Root Instruction
defm "" : LMULSEWSchedWritesF<"WriteVFSqrtV">; defm "" : LMULSEWSchedWritesF<"WriteVFSqrtV">;
// 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction // 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction
// 13.10. Vector Floating-Point Reciprocal Estimate Instruction // 13.10. Vector Floating-Point Reciprocal Estimate Instruction
defm "" : LMULSchedWrites<"WriteVFRecpV">; defm "" : LMULSchedWrites<"WriteVFRecpV">;
// 13.11. Vector Floating-Point MIN/MAX Instructions // 13.11. Vector Floating-Point MIN/MAX Instructions
// 13.13. Vector Floating-Point Compare Instructions defm "" : LMULSchedWrites<"WriteVFMinMaxV">;
defm "" : LMULSchedWrites<"WriteVFCmpV">; defm "" : LMULSchedWrites<"WriteVFMinMaxF">;
defm "" : LMULSchedWrites<"WriteVFCmpF">;
// 13.12. Vector Floating-Point Sign-Injection Instructions // 13.12. Vector Floating-Point Sign-Injection Instructions
defm "" : LMULSchedWrites<"WriteVFSgnjV">; defm "" : LMULSchedWrites<"WriteVFSgnjV">;
defm "" : LMULSchedWrites<"WriteVFSgnjF">; defm "" : LMULSchedWrites<"WriteVFSgnjF">;
// 13.13. Vector Floating-Point Compare Instructions
defm "" : LMULSchedWrites<"WriteVFCmpV">;
defm "" : LMULSchedWrites<"WriteVFCmpF">;
// 13.14. Vector Floating-Point Classify Instruction // 13.14. Vector Floating-Point Classify Instruction
defm "" : LMULSchedWrites<"WriteVFClassV">; defm "" : LMULSchedWrites<"WriteVFClassV">;
// 13.15. Vector Floating-Point Merge Instruction // 13.15. Vector Floating-Point Merge Instruction
defm "" : LMULSchedWrites<"WriteVFMergeV">; defm "" : LMULSchedWrites<"WriteVFMergeV">;
// 13.16. Vector Floating-Point Move Instruction // 13.16. Vector Floating-Point Move Instruction
defm "" : LMULSchedWrites<"WriteVFMovV">; defm "" : LMULSchedWrites<"WriteVFMovV">;
// 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions // 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions
defm "" : LMULSchedWrites<"WriteVFCvtIToFV">; defm "" : LMULSchedWrites<"WriteVFCvtIToFV">;
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defm "" : LMULSchedReads<"ReadVICALUX">; defm "" : LMULSchedReads<"ReadVICALUX">;
// 11.6. Vector Single-Width Bit Shift Instructions // 11.6. Vector Single-Width Bit Shift Instructions
defm "" : LMULSchedReads<"ReadVShiftV">; defm "" : LMULSchedReads<"ReadVShiftV">;
defm "" : LMULSchedReads<"ReadVShiftX">; defm "" : LMULSchedReads<"ReadVShiftX">;
// 11.7. Vector Narrowing Integer Right Shift Instructions // 11.7. Vector Narrowing Integer Right Shift Instructions
defm "" : LMULSchedReadsW<"ReadVNShiftV">; defm "" : LMULSchedReadsW<"ReadVNShiftV">;
defm "" : LMULSchedReadsW<"ReadVNShiftX">; defm "" : LMULSchedReadsW<"ReadVNShiftX">;
// 11.8. Vector Integer Comparison Instructions // 11.8. Vector Integer Comparison Instructions
// 11.9. Vector Integer Min/Max Instructions
defm "" : LMULSchedReads<"ReadVICmpV">; defm "" : LMULSchedReads<"ReadVICmpV">;
defm "" : LMULSchedReads<"ReadVICmpX">; defm "" : LMULSchedReads<"ReadVICmpX">;
// 11.9. Vector Integer Min/Max Instructions
defm "" : LMULSchedReads<"ReadVIMinMaxV">;
defm "" : LMULSchedReads<"ReadVIMinMaxX">;
// 11.10. Vector Single-Width Integer Multiply Instructions // 11.10. Vector Single-Width Integer Multiply Instructions
defm "" : LMULSchedReads<"ReadVIMulV">; defm "" : LMULSchedReads<"ReadVIMulV">;
defm "" : LMULSchedReads<"ReadVIMulX">; defm "" : LMULSchedReads<"ReadVIMulX">;
// 11.11. Vector Integer Divide Instructions // 11.11. Vector Integer Divide Instructions
defm "" : LMULSEWSchedReads<"ReadVIDivV">; defm "" : LMULSEWSchedReads<"ReadVIDivV">;
defm "" : LMULSEWSchedReads<"ReadVIDivX">; defm "" : LMULSEWSchedReads<"ReadVIDivX">;
// 11.12. Vector Widening Integer Multiply Instructions // 11.12. Vector Widening Integer Multiply Instructions
defm "" : LMULSchedReadsW<"ReadVIWMulV">; defm "" : LMULSchedReadsW<"ReadVIWMulV">;
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defm "" : LMULSchedReadsFW<"ReadVFWMulAddV">; defm "" : LMULSchedReadsFW<"ReadVFWMulAddV">;
defm "" : LMULSchedReadsFW<"ReadVFWMulAddF">; defm "" : LMULSchedReadsFW<"ReadVFWMulAddF">;
// 13.8. Vector Floating-Point Square-Root Instruction // 13.8. Vector Floating-Point Square-Root Instruction
defm "" : LMULSEWSchedReadsF<"ReadVFSqrtV">; defm "" : LMULSEWSchedReadsF<"ReadVFSqrtV">;
// 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction // 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction
// 13.10. Vector Floating-Point Reciprocal Estimate Instruction // 13.10. Vector Floating-Point Reciprocal Estimate Instruction
defm "" : LMULSchedReads<"ReadVFRecpV">; defm "" : LMULSchedReads<"ReadVFRecpV">;
// 13.11. Vector Floating-Point MIN/MAX Instructions // 13.11. Vector Floating-Point MIN/MAX Instructions
// 13.13. Vector Floating-Point Compare Instructions defm "" : LMULSchedReads<"ReadVFMinMaxV">;
defm "" : LMULSchedReads<"ReadVFCmpV">; defm "" : LMULSchedReads<"ReadVFMinMaxF">;
defm "" : LMULSchedReads<"ReadVFCmpF">;
// 13.12. Vector Floating-Point Sign-Injection Instructions // 13.12. Vector Floating-Point Sign-Injection Instructions
defm "" : LMULSchedReads<"ReadVFSgnjV">; defm "" : LMULSchedReads<"ReadVFSgnjV">;
defm "" : LMULSchedReads<"ReadVFSgnjF">; defm "" : LMULSchedReads<"ReadVFSgnjF">;
// 13.13. Vector Floating-Point Compare Instructions
defm "" : LMULSchedReads<"ReadVFCmpV">;
defm "" : LMULSchedReads<"ReadVFCmpF">;
// 13.14. Vector Floating-Point Classify Instruction // 13.14. Vector Floating-Point Classify Instruction
defm "" : LMULSchedReads<"ReadVFClassV">; defm "" : LMULSchedReads<"ReadVFClassV">;
// 13.15. Vector Floating-Point Merge Instruction // 13.15. Vector Floating-Point Merge Instruction
defm "" : LMULSchedReads<"ReadVFMergeV">; defm "" : LMULSchedReads<"ReadVFMergeV">;
defm "" : LMULSchedReads<"ReadVFMergeF">; defm "" : LMULSchedReads<"ReadVFMergeF">;
// 13.16. Vector Floating-Point Move Instruction // 13.16. Vector Floating-Point Move Instruction
defm "" : LMULSchedReads<"ReadVFMovF">; defm "" : LMULSchedReads<"ReadVFMovF">;
// 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions // 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions
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defm "" : LMULWriteRes<"WriteVShiftX", []>; defm "" : LMULWriteRes<"WriteVShiftX", []>;
defm "" : LMULWriteRes<"WriteVShiftI", []>; defm "" : LMULWriteRes<"WriteVShiftI", []>;
defm "" : LMULWriteResW<"WriteVNShiftV", []>; defm "" : LMULWriteResW<"WriteVNShiftV", []>;
defm "" : LMULWriteResW<"WriteVNShiftX", []>; defm "" : LMULWriteResW<"WriteVNShiftX", []>;
defm "" : LMULWriteResW<"WriteVNShiftI", []>; defm "" : LMULWriteResW<"WriteVNShiftI", []>;
defm "" : LMULWriteRes<"WriteVICmpV", []>; defm "" : LMULWriteRes<"WriteVICmpV", []>;
defm "" : LMULWriteRes<"WriteVICmpX", []>; defm "" : LMULWriteRes<"WriteVICmpX", []>;
defm "" : LMULWriteRes<"WriteVICmpI", []>; defm "" : LMULWriteRes<"WriteVICmpI", []>;
defm "" : LMULWriteRes<"WriteVIMinMaxV", []>;
defm "" : LMULWriteRes<"WriteVIMinMaxX", []>;
defm "" : LMULWriteRes<"WriteVIMulV", []>; defm "" : LMULWriteRes<"WriteVIMulV", []>;
defm "" : LMULWriteRes<"WriteVIMulX", []>; defm "" : LMULWriteRes<"WriteVIMulX", []>;
defm "" : LMULSEWWriteRes<"WriteVIDivV", []>; defm "" : LMULSEWWriteRes<"WriteVIDivV", []>;
defm "" : LMULSEWWriteRes<"WriteVIDivX", []>; defm "" : LMULSEWWriteRes<"WriteVIDivX", []>;
defm "" : LMULWriteResW<"WriteVIWMulV", []>; defm "" : LMULWriteResW<"WriteVIWMulV", []>;
defm "" : LMULWriteResW<"WriteVIWMulX", []>; defm "" : LMULWriteResW<"WriteVIWMulX", []>;
defm "" : LMULWriteRes<"WriteVIMulAddV", []>; defm "" : LMULWriteRes<"WriteVIMulAddV", []>;
defm "" : LMULWriteRes<"WriteVIMulAddX", []>; defm "" : LMULWriteRes<"WriteVIMulAddX", []>;
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defm "" : LMULWriteResFW<"WriteVFWMulV", []>; defm "" : LMULWriteResFW<"WriteVFWMulV", []>;
defm "" : LMULWriteResFW<"WriteVFWMulF", []>; defm "" : LMULWriteResFW<"WriteVFWMulF", []>;
defm "" : LMULWriteRes<"WriteVFMulAddV", []>; defm "" : LMULWriteRes<"WriteVFMulAddV", []>;
defm "" : LMULWriteRes<"WriteVFMulAddF", []>; defm "" : LMULWriteRes<"WriteVFMulAddF", []>;
defm "" : LMULWriteResFW<"WriteVFWMulAddV", []>; defm "" : LMULWriteResFW<"WriteVFWMulAddV", []>;
defm "" : LMULWriteResFW<"WriteVFWMulAddF", []>; defm "" : LMULWriteResFW<"WriteVFWMulAddF", []>;
defm "" : LMULSEWWriteResF<"WriteVFSqrtV", []>; defm "" : LMULSEWWriteResF<"WriteVFSqrtV", []>;
defm "" : LMULWriteRes<"WriteVFRecpV", []>; defm "" : LMULWriteRes<"WriteVFRecpV", []>;
defm "" : LMULWriteRes<"WriteVFCmpV", []>; defm "" : LMULWriteRes<"WriteVFMinMaxV", []>;
defm "" : LMULWriteRes<"WriteVFCmpF", []>; defm "" : LMULWriteRes<"WriteVFMinMaxF", []>;
defm "" : LMULWriteRes<"WriteVFSgnjV", []>; defm "" : LMULWriteRes<"WriteVFSgnjV", []>;
defm "" : LMULWriteRes<"WriteVFSgnjF", []>; defm "" : LMULWriteRes<"WriteVFSgnjF", []>;
defm "" : LMULWriteRes<"WriteVFCmpV", []>;
defm "" : LMULWriteRes<"WriteVFCmpF", []>;
defm "" : LMULWriteRes<"WriteVFClassV", []>; defm "" : LMULWriteRes<"WriteVFClassV", []>;
defm "" : LMULWriteRes<"WriteVFMergeV", []>; defm "" : LMULWriteRes<"WriteVFMergeV", []>;
defm "" : LMULWriteRes<"WriteVFMovV", []>; defm "" : LMULWriteRes<"WriteVFMovV", []>;
defm "" : LMULWriteRes<"WriteVFCvtIToFV", []>; defm "" : LMULWriteRes<"WriteVFCvtIToFV", []>;
defm "" : LMULWriteRes<"WriteVFCvtFToIV", []>; defm "" : LMULWriteRes<"WriteVFCvtFToIV", []>;
defm "" : LMULWriteResW<"WriteVFWCvtIToFV", []>; defm "" : LMULWriteResW<"WriteVFWCvtIToFV", []>;
defm "" : LMULWriteResFW<"WriteVFWCvtFToIV", []>; defm "" : LMULWriteResFW<"WriteVFWCvtFToIV", []>;
defm "" : LMULWriteResFW<"WriteVFWCvtFToFV", []>; defm "" : LMULWriteResFW<"WriteVFWCvtFToFV", []>;
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defm "" : LMULReadAdvance<"ReadVICALUV", 0>; defm "" : LMULReadAdvance<"ReadVICALUV", 0>;
defm "" : LMULReadAdvance<"ReadVICALUX", 0>; defm "" : LMULReadAdvance<"ReadVICALUX", 0>;
defm "" : LMULReadAdvance<"ReadVShiftV", 0>; defm "" : LMULReadAdvance<"ReadVShiftV", 0>;
defm "" : LMULReadAdvance<"ReadVShiftX", 0>; defm "" : LMULReadAdvance<"ReadVShiftX", 0>;
defm "" : LMULReadAdvanceW<"ReadVNShiftV", 0>; defm "" : LMULReadAdvanceW<"ReadVNShiftV", 0>;
defm "" : LMULReadAdvanceW<"ReadVNShiftX", 0>; defm "" : LMULReadAdvanceW<"ReadVNShiftX", 0>;
defm "" : LMULReadAdvance<"ReadVICmpV", 0>; defm "" : LMULReadAdvance<"ReadVICmpV", 0>;
defm "" : LMULReadAdvance<"ReadVICmpX", 0>; defm "" : LMULReadAdvance<"ReadVICmpX", 0>;
defm "" : LMULReadAdvance<"ReadVIMinMaxV", 0>;
defm "" : LMULReadAdvance<"ReadVIMinMaxX", 0>;
defm "" : LMULReadAdvance<"ReadVIMulV", 0>; defm "" : LMULReadAdvance<"ReadVIMulV", 0>;
defm "" : LMULReadAdvance<"ReadVIMulX", 0>; defm "" : LMULReadAdvance<"ReadVIMulX", 0>;
defm "" : LMULSEWReadAdvance<"ReadVIDivV", 0>; defm "" : LMULSEWReadAdvance<"ReadVIDivV", 0>;
defm "" : LMULSEWReadAdvance<"ReadVIDivX", 0>; defm "" : LMULSEWReadAdvance<"ReadVIDivX", 0>;
defm "" : LMULReadAdvanceW<"ReadVIWMulV", 0>; defm "" : LMULReadAdvanceW<"ReadVIWMulV", 0>;
defm "" : LMULReadAdvanceW<"ReadVIWMulX", 0>; defm "" : LMULReadAdvanceW<"ReadVIWMulX", 0>;
defm "" : LMULReadAdvance<"ReadVIMulAddV", 0>; defm "" : LMULReadAdvance<"ReadVIMulAddV", 0>;
defm "" : LMULReadAdvance<"ReadVIMulAddX", 0>; defm "" : LMULReadAdvance<"ReadVIMulAddX", 0>;
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defm "" : LMULReadAdvanceFW<"ReadVFWMulV", 0>; defm "" : LMULReadAdvanceFW<"ReadVFWMulV", 0>;
defm "" : LMULReadAdvanceFW<"ReadVFWMulF", 0>; defm "" : LMULReadAdvanceFW<"ReadVFWMulF", 0>;
defm "" : LMULReadAdvance<"ReadVFMulAddV", 0>; defm "" : LMULReadAdvance<"ReadVFMulAddV", 0>;
defm "" : LMULReadAdvance<"ReadVFMulAddF", 0>; defm "" : LMULReadAdvance<"ReadVFMulAddF", 0>;
defm "" : LMULReadAdvanceFW<"ReadVFWMulAddV", 0>; defm "" : LMULReadAdvanceFW<"ReadVFWMulAddV", 0>;
defm "" : LMULReadAdvanceFW<"ReadVFWMulAddF", 0>; defm "" : LMULReadAdvanceFW<"ReadVFWMulAddF", 0>;
defm "" : LMULSEWReadAdvanceF<"ReadVFSqrtV", 0>; defm "" : LMULSEWReadAdvanceF<"ReadVFSqrtV", 0>;
defm "" : LMULReadAdvance<"ReadVFRecpV", 0>; defm "" : LMULReadAdvance<"ReadVFRecpV", 0>;
defm "" : LMULReadAdvance<"ReadVFCmpV", 0>; defm "" : LMULReadAdvance<"ReadVFMinMaxV", 0>;
defm "" : LMULReadAdvance<"ReadVFCmpF", 0>; defm "" : LMULReadAdvance<"ReadVFMinMaxF", 0>;
defm "" : LMULReadAdvance<"ReadVFSgnjV", 0>; defm "" : LMULReadAdvance<"ReadVFSgnjV", 0>;
defm "" : LMULReadAdvance<"ReadVFSgnjF", 0>; defm "" : LMULReadAdvance<"ReadVFSgnjF", 0>;
defm "" : LMULReadAdvance<"ReadVFCmpV", 0>;
defm "" : LMULReadAdvance<"ReadVFCmpF", 0>;
defm "" : LMULReadAdvance<"ReadVFClassV", 0>; defm "" : LMULReadAdvance<"ReadVFClassV", 0>;
defm "" : LMULReadAdvance<"ReadVFMergeV", 0>; defm "" : LMULReadAdvance<"ReadVFMergeV", 0>;
defm "" : LMULReadAdvance<"ReadVFMergeF", 0>; defm "" : LMULReadAdvance<"ReadVFMergeF", 0>;
defm "" : LMULReadAdvance<"ReadVFMovF", 0>; defm "" : LMULReadAdvance<"ReadVFMovF", 0>;
defm "" : LMULReadAdvance<"ReadVFCvtIToFV", 0>; defm "" : LMULReadAdvance<"ReadVFCvtIToFV", 0>;
defm "" : LMULReadAdvance<"ReadVFCvtFToIV", 0>; defm "" : LMULReadAdvance<"ReadVFCvtFToIV", 0>;
defm "" : LMULReadAdvanceW<"ReadVFWCvtIToFV", 0>; defm "" : LMULReadAdvanceW<"ReadVFWCvtIToFV", 0>;
defm "" : LMULReadAdvanceFW<"ReadVFWCvtFToIV", 0>; defm "" : LMULReadAdvanceFW<"ReadVFWCvtFToIV", 0>;
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