[llvm-exegesis] Add Target Memory Utility Functions

[aidengrossman]

Summary

This patch adds in several functions to ExegesisTarget that will assist
in setting up memory for the planned memory annotations.

[aidengrossman]

Rebase

[aidengrossman]

Format + rebase

[RKSimon]

Please remember to add context to the diffs with -UU999999 - https://www.llvm.org/docs/Phabricator.html#requesting-a-review-via-the-web-interface

[aidengrossman]

Rebase

[courbet]

llvm/tools/llvm-exegesis/lib/X86/Target.cpp

984

All these are extremely complex. Can't we insert a call to a separate module instead ?

Given that we don't actually care about measuring the setup code, we don't need to inline each function here.

[aidengrossman]

llvm/tools/llvm-exegesis/lib/X86/Target.cpp

984

I agree that they're complex and the readability is not great.

Theoretically, we could do it in a separate module and call into that, but the requirements for setting up a deterministic execution environment with regard to memory require that all the code has to be in blocks of fixed size at known addresses. I don't see any feasible way to do that by just implementing these functions in C/C++ in the llvm-exegesis code base. It's theoretically possible to have an implementation that lives outside of the main llvm-exegesis code base and gets built/linked in to the JITed snippet and emitted to the same block of memory, but decided against that approach since there was still a lot of complexity with that method and it seemed to be a less prominent path.

Very open to suggestions to improve the readability/complexity though since I'm sure I haven't explored the solution space that thoroughly.

[aidengrossman]

Address reviewer feedback (from dependent review), rebase.

[aidengrossman]

Rebase

[aidengrossman]

Rebase

[courbet]

llvm/tools/llvm-exegesis/lib/X86/Target.cpp

984

We discussed a couple solutions or this with Ondrej and Guillaume, for the record:

• Writing the code in syscalls in asm or c++ in a separate module and call to that: We agree that this would be very hard to maintain two separate modules.
• Writing this as textual asm here and using the snippet parsing facilities to transform the result to MCInsts: Still painful because there a a bunch of values that are not constant.

In the end we don;t really have a much better apporach than this oone, but we think that it could be made much more readable by refactoring, e.g. generateSyscall(SYS_munmap, ...) method, roundTo(4096, X86::RSI);

996

should this be using getpagesize() ?

[aidengrossman]

Address reviewer feedback.

llvm/tools/llvm-exegesis/lib/X86/Target.cpp

984

That would definitely improve readability! Thanks for the suggestion. I've done some refactoring to try and make things more readable based on your suggestions in addition to adding in comments where it seems like things aren't clear. Let me know what you think and if you have any other suggestions.

[aidengrossman]

Rebase

[aidengrossman]

@courbet This one should be ready for another round of review too when you get a chance. Thanks for all your time and patience so far with reviews!

[courbet]

General comment: all these blindly clobber registers (which is an issue, see my comment in D151025). Should we always save and restore registers ?

llvm/tools/llvm-exegesis/lib/X86/Target.cpp

994

PageSizeShift ?

998–1005

Another, maybe simpler option is: AND64ri register, -page_size

[courbet]

(BTW thanks for the refactoring, it makes everything much simpler to understand)

[courbet]

llvm/tools/llvm-exegesis/lib/X86/Target.cpp

1040

[nit] Use RDI for consistency with the rest of the file

1059

Please create a constant for this.

[aidengrossman]

Right, all these functions do clobber registers (at least currently). However, the only one that actually matters is configurePerfCounter as it is the only one that runs after the registers get initialized to their specified values. I have a TODO to fix this.

[courbet]

In D151023#4427407, @aidengrossman wrote:

Right, all these functions do clobber registers (at least currently).

Let's document this then :)

However, the only one that actually matters is configurePerfCounter as it is the only one that runs after the registers get initialized to their specified values. I have a TODO to fix this.

SG, let's do it now given that as such the code won't work as is.

[aidengrossman]

Address reviewer feedback

[aidengrossman]

Just added in register saving to configurePerfCounter() and noted that the functions may clobber registers in Target.h. Probably should've just done it to begin with. New changes should be ready for review.

llvm/tools/llvm-exegesis/lib/X86/Target.cpp

998–1005

I find the shift left/right pattern to be a little bit more intuitive since using an AND instruction involves understanding a bitwise "trick" when reading, but it definitely is shorter. I don't have any particularly strong feelings on this though, so if you want me to change it, just let me know.

[courbet]

llvm/tools/llvm-exegesis/lib/X86/Target.cpp

998–1005

I find the shift left/right pattern to be a little bit more intuitive since using an AND instruction involves understanding a bitwise "trick" when reading, but it definitely is shorter. I don't have any particularly strong feelings on this though, so if you want me to change it, just let me know.

No strong opinion, you can keep it as it if you want.

llvm/tools/llvm-exegesis/lib/Target.h

public:
   // Targets can use this to add target-specific passes in assembleToStream();
   virtual void addTargetSpecificPasses(PassManagerBase &PM) const {}
 
   // Generates code to move a constant into a the given register.
   // Precondition: Value must fit into Reg.
   virtual std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, unsigned Reg,
                                        const APInt &Value) const = 0;
 
+  // Generates the code for the lower munmap call. The code generated by this
+  // function may clobber registers.
+  virtual void generateLowerMunmap(std::vector<MCInst> &GeneratedCode) const {
+    report_fatal_error(
+        "generateLowerMunmap is not implemented on the current architecture");
+  }
+
+  // Generates the upper munmap call. The code generated by this function may
+  // clobber registers.
+  virtual void generateUpperMunmap(std::vector<MCInst> &GeneratedCode) const {
+    report_fatal_error(
+        "generateUpperMunmap is not implemented on the current architecture");
+  }
+
+  // Generates the code for an exit syscall. The code generated by this function
+  // may clobber registers.
+  virtual std::vector<MCInst> generateExitSyscall(unsigned ExitCode) const {
+    report_fatal_error(
+        "generateExitSyscall is not implemented on the current architecture");
+  }
+
+  // Generates the code to mmap a region of code. The code generated by this
+  // function may clobber registers.
+  virtual std::vector<MCInst>
+  generateMmap(intptr_t Address, size_t Length,
+               intptr_t FileDescriptorAddress) const {
+    report_fatal_error(
+        "generateMmap is not implemented on the current architecture");
+  }
+
+  // Generates the mmap code for the aux memory. The code generated by this
+  // function may clobber registers.
+  virtual void generateMmapAuxMem(std::vector<MCInst> &GeneratedCode) const {
+    report_fatal_error(
+        "generateMmapAuxMem is not implemented on the current architecture\n");
+  }
+
+  // Moves argument registers into other registers that won't get clobbered
+  // while making syscalls. The code generated by this function may clobber
+  // registers.
+  virtual void moveArgumentRegisters(std::vector<MCInst> &GeneratedCode) const {
+    report_fatal_error("moveArgumentRegisters is not implemented on the "
+                       "current architecture\n");
+  }
+
+  // Generates code to move argument registers, unmap memory above and below the
+  // snippet, and map the auxiliary memory into the subprocess. The code
+  // generated by this function may clobber registers.
+  virtual std::vector<MCInst> generateMemoryInitialSetup() const {
+    report_fatal_error("generateMemoryInitialSetup is not supported on the "
+                       "current architecture\n");
+  }
+
+  // Sets the stack register to the auxiliary memory so that operations
+  // requiring the stack can be formed (e.g., setting large registers). The code
+  // generated by this function may clobber registers.
+  virtual std::vector<MCInst> setStackRegisterToAuxMem() const {
+    report_fatal_error("setStackRegisterToAuxMem is not implemented on the "
+                       "current architectures");
+  }
+
+  virtual intptr_t getAuxiliaryMemoryStartAddress() const {
+    report_fatal_error("getAuxiliaryMemoryStartAddress is not implemented on "
+                       "the current architecture");
+  }
+
+  // Generates the necessary ioctl system calls to configure the perf counters.
+  // The code generated by this function preserves all registers if the
+  // parameter SaveRegisters is set to true.
+  virtual std::vector<MCInst> configurePerfCounter(long Request,
+                                                   bool SaveRegisters) const {
+    report_fatal_error(
+        "configurePerfCounter is not implemented on the current architecture");
+  }
+
+  // Gets the ABI dependent registers that are used to pass arguments in a
+  // function call.
+  virtual std::vector<unsigned> getArgumentRegisters() const {
+    report_fatal_error(
+        "getArgumentRegisters is not implemented on the current architecture");
+  };
+
+  // Gets the registers that might potentially need to be saved by while
+  // the setup in the test harness executes.
+  virtual std::vector<unsigned> getRegistersNeedSaving() const {
+    report_fatal_error("getRegistersNeedSaving is not implemented on the "
+                       "current architecture");
+  };
+
   // Returns the register pointing to scratch memory, or 0 if this target
   // does not support memory operands. The benchmark function uses the
   // default calling convention.
   virtual unsigned getScratchMemoryRegister(const Triple &) const { return 0; }
 
   // Fills memory operands with references to the address at [Reg] + Offset.
   virtual void fillMemoryOperands(InstructionTemplate &IT, unsigned Reg,
                                   unsigned Offset) const {

llvm/tools/llvm-exegesis/lib/X86/Target.cpp

 //===-- Target.cpp ----------------------------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 #include "../Target.h"
 
 #include "../Error.h"
 #include "../ParallelSnippetGenerator.h"
 #include "../SerialSnippetGenerator.h"
 #include "../SnippetGenerator.h"
+#include "../SubprocessMemory.h"
 #include "MCTargetDesc/X86BaseInfo.h"
 #include "MCTargetDesc/X86MCTargetDesc.h"
 #include "X86.h"
 #include "X86Counter.h"
 #include "X86RegisterInfo.h"
 #include "llvm/ADT/Sequence.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/MC/MCInstBuilder.h"

 #if defined(_MSC_VER) && (defined(_M_IX86) || defined(_M_X64))
 #include <immintrin.h>
 #include <intrin.h>
 #endif
 #if defined(_MSC_VER) && defined(_M_X64)
 #include <float.h> // For _clearfp in ~X86SavedState().
 #endif
 
+#ifdef __linux__
+#include <sys/mman.h>
+#include <sys/syscall.h>
+#include <unistd.h>
+#endif
+
 namespace llvm {
 namespace exegesis {
 
+static constexpr const intptr_t VAddressSpaceCeiling = 0x0000800000000000;
+
 // If a positive value is specified, we are going to use the LBR in
 // latency-mode.
 //
 // Note:
 //  -  A small value is preferred, but too low a value could result in
 //     throttling.
 //  -  A prime number is preferred to avoid always skipping certain blocks.
 //
#else
           "LBR counter requested without HAVE_LIBPFM, LIBPFM_HAS_FIELD_CYCLES, "
           "or running on Linux.",
           llvm::errc::invalid_argument);
 #endif
     }
     return ExegesisTarget::createCounter(CounterName, State, ProcessID);
   }
 
+  enum ArgumentRegisters { CodeSize = X86::R12, AuxiliaryMemoryFD = X86::R13 };
+
 private:
   void addTargetSpecificPasses(PassManagerBase &PM) const override;
 
   unsigned getScratchMemoryRegister(const Triple &TT) const override;
 
   unsigned getLoopCounterRegister(const Triple &) const override;
 
   unsigned getMaxMemoryAccessSize() const override { return 64; }
 
   Error randomizeTargetMCOperand(const Instruction &Instr, const Variable &Var,
                                  MCOperand &AssignedValue,
                                  const BitVector &ForbiddenRegs) const override;
 
   void fillMemoryOperands(InstructionTemplate &IT, unsigned Reg,
                           unsigned Offset) const override;
 
   void decrementLoopCounterAndJump(MachineBasicBlock &MBB,
                                    MachineBasicBlock &TargetMBB,
                                    const MCInstrInfo &MII) const override;
 
   std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, unsigned Reg,
                                const APInt &Value) const override;
 
+#ifdef __linux__
+  void generateLowerMunmap(std::vector<MCInst> &GeneratedCode) const override;
+
+  void generateUpperMunmap(std::vector<MCInst> &GeneratedCode) const override;
+
+  std::vector<MCInst> generateExitSyscall(unsigned ExitCode) const override;
+
+  std::vector<MCInst>
+  generateMmap(intptr_t Address, size_t Length,
+               intptr_t FileDescriptorAddress) const override;
+
+  void generateMmapAuxMem(std::vector<MCInst> &GeneratedCode) const override;
+
+  void moveArgumentRegisters(std::vector<MCInst> &GeneratedCode) const override;
+
+  std::vector<MCInst> generateMemoryInitialSetup() const override;
+
+  std::vector<MCInst> setStackRegisterToAuxMem() const override;
+
+  intptr_t getAuxiliaryMemoryStartAddress() const override;
+
+  std::vector<MCInst> configurePerfCounter(long Request, bool SaveRegisters) const override;
+
+  std::vector<unsigned> getArgumentRegisters() const override;
+
+  std::vector<unsigned> getRegistersNeedSaving() const override;
+#endif // __linux__
+
   ArrayRef<unsigned> getUnavailableRegisters() const override {
     if (DisableUpperSSERegisters)
       return ArrayRef(kUnavailableRegistersSSE,
                       sizeof(kUnavailableRegistersSSE) /
                           sizeof(kUnavailableRegistersSSE[0]));
 
     return ArrayRef(kUnavailableRegisters, std::size(kUnavailableRegisters));
   }
if (Reg == X86::MXCSR)
     return CI.loadImplicitRegAndFinalize(
         STI.getFeatureBits()[X86::FeatureAVX] ? X86::VLDMXCSR : X86::LDMXCSR,
         0x1f80);
   if (Reg == X86::FPCW)
     return CI.loadImplicitRegAndFinalize(X86::FLDCW16m, 0x37f);
   return {}; // Not yet implemented.
 }
 
+#ifdef __linux__
+
+void generateSyscall(long SyscallNumber, std::vector<MCInst> &GeneratedCode) {
+  GeneratedCode.push_back(
+      loadImmediate(X86::RAX, 64, APInt(64, SyscallNumber)));
+  GeneratedCode.push_back(MCInstBuilder(X86::SYSCALL));
+}
+
+void generateRoundToNearestPage(unsigned int Register,
+                                std::vector<MCInst> &GeneratedCode) {
+  int PageSizeShift = static_cast<int>(round(log2(getpagesize())));
+  // Round down to the nearest page by getting rid of the least significant bits
+  // representing location in the page. Shift right to get rid of this info and
+  // then shift back left.
+  GeneratedCode.push_back(MCInstBuilder(X86::SHR64ri)
+                              .addReg(Register)
+                              .addReg(Register)
+                              .addImm(PageSizeShift));
+  GeneratedCode.push_back(MCInstBuilder(X86::SHL64ri)
+                              .addReg(Register)
+                              .addReg(Register)
+                              .addImm(PageSizeShift));
+}
+
+void generateGetInstructionPointer(unsigned int ResultRegister,
+                                   std::vector<MCInst> &GeneratedCode) {
+  // Use a load effective address to get the current instruction pointer and put
+  // it into the result register.
+  GeneratedCode.push_back(MCInstBuilder(X86::LEA64r)
+                              .addReg(ResultRegister)
+                              .addReg(X86::RIP)
+                              .addImm(1)
+                              .addReg(0)
+                              .addImm(0)
+                              .addReg(0));
+}
+
+void ExegesisX86Target::generateLowerMunmap(
+    std::vector<MCInst> &GeneratedCode) const {
+  // Unmap starting at address zero
+  GeneratedCode.push_back(loadImmediate(X86::RDI, 64, APInt(64, 0)));
+  // Get the current instruction pointer so we know where to unmap up to.
+  generateGetInstructionPointer(X86::RSI, GeneratedCode);
+  generateRoundToNearestPage(X86::RSI, GeneratedCode);
+  // Subtract a page from the end of the unmap so we don't unmap the currently
+  // executing section.
+  GeneratedCode.push_back(MCInstBuilder(X86::SUB64ri32)
+                              .addReg(X86::RSI)
+                              .addReg(X86::RSI)
+                              .addImm(getpagesize()));
+  generateSyscall(SYS_munmap, GeneratedCode);
+}
+
+void ExegesisX86Target::generateUpperMunmap(
+    std::vector<MCInst> &GeneratedCode) const {
+  generateGetInstructionPointer(X86::R8, GeneratedCode);
+  // Load in the size of the snippet to RDI from from the argument register.
+  GeneratedCode.push_back(MCInstBuilder(X86::MOV64rr)
+                              .addReg(X86::RDI)
+                              .addReg(ArgumentRegisters::CodeSize));
+  // Add the length of the snippet (in %RDI) to the current instruction pointer
+  // (%R8) to get the address where we should start unmapping at.
+  GeneratedCode.push_back(MCInstBuilder(X86::ADD64rr)
+                              .addReg(X86::RDI)
+                              .addReg(X86::RDI)
+                              .addReg(X86::R8));
+  generateRoundToNearestPage(X86::RDI, GeneratedCode);
+  // Add a one page to the start address to ensure that we're above the snippet
+  // since the above function rounds down.
+  GeneratedCode.push_back(MCInstBuilder(X86::ADD64ri32)
+                              .addReg(X86::RDI)
+                              .addReg(X86::RDI)
+                              .addImm(getpagesize()));
+  // Unmap to just one page under the ceiling of the address space.
+  GeneratedCode.push_back(loadImmediate(
+      X86::RSI, 64, APInt(64, VAddressSpaceCeiling - getpagesize())));
+  GeneratedCode.push_back(MCInstBuilder(X86::SUB64rr)
+                              .addReg(X86::RSI)
+                              .addReg(X86::RSI)
+                              .addReg(X86::RDI));
+  generateSyscall(SYS_munmap, GeneratedCode);
+}
+
+std::vector<MCInst>
+ExegesisX86Target::generateExitSyscall(unsigned ExitCode) const {
+  std::vector<MCInst> ExitCallCode;
+  ExitCallCode.push_back(loadImmediate(X86::RDI, 64, APInt(64, ExitCode)));
+  generateSyscall(SYS_exit, ExitCallCode);
+  return ExitCallCode;
+}
+
+std::vector<MCInst>
+ExegesisX86Target::generateMmap(intptr_t Address, size_t Length,
+                                intptr_t FileDescriptorAddress) const {
+  std::vector<MCInst> MmapCode;
+  MmapCode.push_back(loadImmediate(X86::RDI, 64, APInt(64, Address)));
+  MmapCode.push_back(loadImmediate(X86::RSI, 64, APInt(64, Length)));
+  MmapCode.push_back(
+      loadImmediate(X86::RDX, 64, APInt(64, PROT_READ | PROT_WRITE)));
+  MmapCode.push_back(
+      loadImmediate(X86::R10, 64, APInt(64, MAP_SHARED | MAP_FIXED_NOREPLACE)));
+  // Copy file descriptor location from aux memory into R8
+  MmapCode.push_back(
+      loadImmediate(X86::R8, 64, APInt(64, FileDescriptorAddress)));
+  // Dereference file descriptor into FD argument register
+  MmapCode.push_back(MCInstBuilder(X86::MOV32rm)
+                         .addReg(X86::R8D)
+                         .addReg(X86::R8)
+                         .addImm(1)
+                         .addReg(0)
+                         .addImm(0)
+                         .addReg(0));
+  MmapCode.push_back(loadImmediate(X86::R9, 64, APInt(64, 0)));
+  generateSyscall(SYS_mmap, MmapCode);
+  return MmapCode;
+}
+
+void ExegesisX86Target::generateMmapAuxMem(
+    std::vector<MCInst> &GeneratedCode) const {
+  GeneratedCode.push_back(
+      loadImmediate(X86::RDI, 64, APInt(64, getAuxiliaryMemoryStartAddress())));
+  GeneratedCode.push_back(loadImmediate(
+      X86::RSI, 64, APInt(64, SubprocessMemory::AuxiliaryMemorySize)));
+  GeneratedCode.push_back(
+      loadImmediate(X86::RDX, 64, APInt(64, PROT_READ | PROT_WRITE)));
+  GeneratedCode.push_back(
+      loadImmediate(X86::R10, 64, APInt(64, MAP_SHARED | MAP_FIXED_NOREPLACE)));
+  GeneratedCode.push_back(MCInstBuilder(X86::MOV64rr)
+                              .addReg(X86::R8)
+                              .addReg(ArgumentRegisters::AuxiliaryMemoryFD));
+  GeneratedCode.push_back(loadImmediate(X86::R9, 64, APInt(64, 0)));
+  generateSyscall(SYS_mmap, GeneratedCode);
+}
+
+void ExegesisX86Target::moveArgumentRegisters(
+    std::vector<MCInst> &GeneratedCode) const {
+  GeneratedCode.push_back(MCInstBuilder(X86::MOV64rr)
+                              .addReg(ArgumentRegisters::CodeSize)
+                              .addReg(X86::RDI));
+  GeneratedCode.push_back(MCInstBuilder(X86::MOV64rr)
+                              .addReg(ArgumentRegisters::AuxiliaryMemoryFD)
+                              .addReg(X86::RSI));
+}
+
+std::vector<MCInst> ExegesisX86Target::generateMemoryInitialSetup() const {
+  std::vector<MCInst> MemoryInitialSetupCode;
+  moveArgumentRegisters(MemoryInitialSetupCode);
+  generateLowerMunmap(MemoryInitialSetupCode);
+  generateUpperMunmap(MemoryInitialSetupCode);
+  generateMmapAuxMem(MemoryInitialSetupCode);
+  return MemoryInitialSetupCode;
+}
+
+std::vector<MCInst> ExegesisX86Target::setStackRegisterToAuxMem() const {
+  // Moves %rsp to the end of the auxiliary memory
+  return {MCInstBuilder(X86::MOV64ri)
+              .addReg(X86::RSP)
+              .addImm(getAuxiliaryMemoryStartAddress() +
+                      SubprocessMemory::AuxiliaryMemorySize)};
+}
+
+intptr_t ExegesisX86Target::getAuxiliaryMemoryStartAddress() const {
+  // Return the second to last page in the virtual address space to try and
+  // prevent interference with memory annotations in the snippet
+  return VAddressSpaceCeiling - 2 * getpagesize();
+}
+
+void generateRegisterStackPush(unsigned int Register,
+                               std::vector<MCInst> &GeneratedCode) {
+  GeneratedCode.push_back(MCInstBuilder(X86::PUSH64r).addReg(Register));
+}
+
+void generateRegisterStackPop(unsigned int Register,
+                              std::vector<MCInst> &GeneratedCode) {
+  GeneratedCode.push_back(MCInstBuilder(X86::POP64r).addReg(Register));
+}
+
+std::vector<MCInst>
+ExegesisX86Target::configurePerfCounter(long Request, bool SaveRegisters) const {
+  std::vector<MCInst> ConfigurePerfCounterCode;
+  if(SaveRegisters) {
+    // Preservie RAX, RDI, and RSI by pushing them to the stack.
+    generateRegisterStackPush(X86::RAX, ConfigurePerfCounterCode);
+    generateRegisterStackPush(X86::RDI, ConfigurePerfCounterCode);
+    generateRegisterStackPush(X86::RSI, ConfigurePerfCounterCode);
+  }
+  ConfigurePerfCounterCode.push_back(
+      loadImmediate(X86::RDI, 64, APInt(64, getAuxiliaryMemoryStartAddress())));
+  ConfigurePerfCounterCode.push_back(MCInstBuilder(X86::MOV32rm)
+                                         .addReg(X86::EDI)
+                                         .addReg(X86::RDI)
+                                         .addImm(1)
+                                         .addReg(0)
+                                         .addImm(0)
+                                         .addReg(0));
+  ConfigurePerfCounterCode.push_back(
+      loadImmediate(X86::RSI, 64, APInt(64, Request)));
+  generateSyscall(SYS_ioctl, ConfigurePerfCounterCode);
+  if(SaveRegisters) {
+    // Restore RAX, RDI, and RSI, in reverse order.
+    generateRegisterStackPop(X86::RSI, ConfigurePerfCounterCode);
+    generateRegisterStackPop(X86::RIP, ConfigurePerfCounterCode);
+    generateRegisterStackPop(X86::RAX, ConfigurePerfCounterCode);
+  }
+  return ConfigurePerfCounterCode;
+}
+
+std::vector<unsigned> ExegesisX86Target::getArgumentRegisters() const {
+  return {X86::RDI, X86::RSI};
+}
+
+std::vector<unsigned> ExegesisX86Target::getRegistersNeedSaving() const {
+  return {X86::RAX, X86::RDI, X86::RSI};
+}
+
+#endif // __linux__
+
 // Instruction can have some variable operands, and we may want to see how
 // different operands affect performance. So for each operand position,
 // precompute all the possible choices we might care about,
 // and greedily generate all the possible combinations of choices.
 std::vector<InstructionTemplate> ExegesisX86Target::generateInstructionVariants(
     const Instruction &Instr, unsigned MaxConfigsPerOpcode) const {
   bool Exploration = false;
   SmallVector<SmallVector<MCOperand, 1>, 4> VariableChoices;

llvm/unittests/tools/llvm-exegesis/X86/TargetTest.cpp

 //===-- TargetTest.cpp -----------------------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "Target.h"
 
 #include <cassert>
 #include <memory>
 
 #include "MCTargetDesc/X86MCTargetDesc.h"
+#include "SubprocessMemory.h"
 #include "llvm/MC/TargetRegistry.h"
 #include "llvm/Support/TargetSelect.h"
 #include "gmock/gmock.h"
 #include "gtest/gtest.h"
 
 #include "llvm/MC/MCInstPrinter.h"
 
+#ifdef __linux__
+#include <sys/mman.h>
+#include <sys/syscall.h>
+#endif // __linux__
+
 namespace llvm {
 
 bool operator==(const MCOperand &a, const MCOperand &b) {
   if (a.isImm() && b.isImm())
     return a.getImm() == b.getImm();
   if (a.isReg() && b.isReg())
     return a.getReg() == b.getReg();
   return false;

 Matcher<MCInst> OpcodeIs(unsigned Opcode) {
   return Property(&MCInst::getOpcode, Eq(Opcode));
 }
 
 Matcher<MCInst> IsMovImmediate(unsigned Opcode, int64_t Reg, int64_t Value) {
   return AllOf(OpcodeIs(Opcode), ElementsAre(IsReg(Reg), IsImm(Value)));
 }
 
+Matcher<MCInst> IsMovRegToReg(unsigned Opcode, int64_t Reg1, int64_t Reg2) {
+  return AllOf(OpcodeIs(Opcode), ElementsAre(IsReg(Reg1), IsReg(Reg2)));
+}
+
 Matcher<MCInst> IsMovValueToStack(unsigned Opcode, int64_t Value,
                                   size_t Offset) {
   return AllOf(OpcodeIs(Opcode),
                ElementsAre(IsReg(X86::RSP), IsImm(1), IsReg(0), IsImm(Offset),
                            IsReg(0), IsImm(Value)));
 }
 
 Matcher<MCInst> IsMovValueFromStack(unsigned Opcode, unsigned Reg) {

 
 TEST_F(X86Core2TargetTest, AllowAsBackToBack) {
   EXPECT_TRUE(
       State.getExegesisTarget().allowAsBackToBack(getInstr(X86::ADD64rr)));
   EXPECT_FALSE(
       State.getExegesisTarget().allowAsBackToBack(getInstr(X86::LEA64r)));
 }
 
+#ifdef __linux__
+TEST_F(X86Core2TargetTest, GenerateLowerMunmapTest) {
+  std::vector<MCInst> GeneratedCode;
+  State.getExegesisTarget().generateLowerMunmap(GeneratedCode);
+  EXPECT_THAT(GeneratedCode,
+              ElementsAre(IsMovImmediate(X86::MOV64ri, X86::RDI, 0),
+                          OpcodeIs(X86::LEA64r), OpcodeIs(X86::SHR64ri),
+                          OpcodeIs(X86::SHL64ri), OpcodeIs(X86::SUB64ri32),
+                          IsMovImmediate(X86::MOV64ri, X86::RAX, SYS_munmap),
+                          OpcodeIs(X86::SYSCALL)));
+}
+
+TEST_F(X86Core2TargetTest, GenerateUpperMunmapTest) {
+  std::vector<MCInst> GeneratedCode;
+  State.getExegesisTarget().generateUpperMunmap(GeneratedCode);
+  EXPECT_THAT(
+      GeneratedCode,
+      ElementsAreArray({OpcodeIs(X86::LEA64r), OpcodeIs(X86::MOV64rr),
+                        OpcodeIs(X86::ADD64rr), OpcodeIs(X86::SHR64ri),
+                        OpcodeIs(X86::SHL64ri), OpcodeIs(X86::ADD64ri32),
+                        IsMovImmediate(X86::MOV64ri, X86::RSI,
+                                       0x0000800000000000 - getpagesize()),
+                        OpcodeIs(X86::SUB64rr),
+                        IsMovImmediate(X86::MOV64ri, X86::RAX, SYS_munmap),
+                        OpcodeIs(X86::SYSCALL)}));
+}
+
+TEST_F(X86Core2TargetTest, GenerateExitSyscallTest) {
+  EXPECT_THAT(State.getExegesisTarget().generateExitSyscall(127),
+              ElementsAre(IsMovImmediate(X86::MOV64ri, X86::RDI, 127),
+                          IsMovImmediate(X86::MOV64ri, X86::RAX, SYS_exit),
+                          OpcodeIs(X86::SYSCALL)));
+}
+
+TEST_F(X86Core2TargetTest, GenerateMmapTest) {
+  EXPECT_THAT(State.getExegesisTarget().generateMmap(0x1000, 4096, 0x2000),
+              ElementsAre(IsMovImmediate(X86::MOV64ri, X86::RDI, 0x1000),
+                          IsMovImmediate(X86::MOV64ri, X86::RSI, 4096),
+                          IsMovImmediate(X86::MOV64ri, X86::RDX,
+                                         PROT_READ | PROT_WRITE),
+                          IsMovImmediate(X86::MOV64ri, X86::R10,
+                                         MAP_SHARED | MAP_FIXED_NOREPLACE),
+                          IsMovImmediate(X86::MOV64ri, X86::R8, 0x2000),
+                          OpcodeIs(X86::MOV32rm),
+                          IsMovImmediate(X86::MOV64ri, X86::R9, 0),
+                          IsMovImmediate(X86::MOV64ri, X86::RAX, SYS_mmap),
+                          OpcodeIs(X86::SYSCALL)));
+}
+
+TEST_F(X86Core2TargetTest, GenerateMmapAuxMemTest) {
+  std::vector<MCInst> GeneratedCode;
+  State.getExegesisTarget().generateMmapAuxMem(GeneratedCode);
+  EXPECT_THAT(
+      GeneratedCode,
+      ElementsAre(
+          IsMovImmediate(
+              X86::MOV64ri, X86::RDI,
+              State.getExegesisTarget().getAuxiliaryMemoryStartAddress()),
+          IsMovImmediate(X86::MOV64ri, X86::RSI,
+                         SubprocessMemory::AuxiliaryMemorySize),
+          IsMovImmediate(X86::MOV64ri, X86::RDX, PROT_READ | PROT_WRITE),
+          IsMovImmediate(X86::MOV64ri, X86::R10,
+                         MAP_SHARED | MAP_FIXED_NOREPLACE),
+          OpcodeIs(X86::MOV64rr), IsMovImmediate(X86::MOV64ri, X86::R9, 0),
+          IsMovImmediate(X86::MOV64ri, X86::RAX, SYS_mmap),
+          OpcodeIs(X86::SYSCALL)));
+}
+
+TEST_F(X86Core2TargetTest, MoveArgumentRegistersTest) {
+  std::vector<MCInst> GeneratedCode;
+  State.getExegesisTarget().moveArgumentRegisters(GeneratedCode);
+  EXPECT_THAT(GeneratedCode,
+              ElementsAre(IsMovRegToReg(X86::MOV64rr, X86::R12, X86::RDI),
+                          IsMovRegToReg(X86::MOV64rr, X86::R13, X86::RSI)));
+}
+#endif // __linux__
+
 } // namespace
 } // namespace exegesis
 } // namespace llvm