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[mlir][arith] Add narrowing patterns for subi, divsi, and divui
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Authored by kuhar on Apr 29 2023, 2:19 PM.

Details

Summary

Each of these ops is compatible with only one extension kind and
produces an extra result bit.

I checked these transformation in Alive2:

  1. subi + extsi: https://alive2.llvm.org/ce/z/ipmZZA
  2. divsi + extsi: https://alive2.llvm.org/ce/z/fAcqUv
  3. divui + extui: https://alive2.llvm.org/ce/z/QZJpFp

Diff Detail

Event Timeline

kuhar created this revision.Apr 29 2023, 2:19 PM
Herald added a project: Restricted Project. · View Herald TranscriptApr 29 2023, 2:19 PM
kuhar requested review of this revision.Apr 29 2023, 2:19 PM
antiagainst accepted this revision.May 1 2023, 8:35 PM
antiagainst added inline comments.
mlir/lib/Dialect/Arith/Transforms/IntNarrowing.cpp
330

It would be helpful to indicate under what cases we need the extra bits. (max positive value - min negative value)

345

Similarly here, it would be helpful to indicate under what cases we need the extra bits.

363

Similarly here, it would be helpful to indicate under what cases we need the extra bits.

This revision is now accepted and ready to land.May 1 2023, 8:35 PM
kuhar updated this revision to Diff 518725.May 2 2023, 7:33 AM

Rebase. Add result bitwidth examples.
Update unsigned division not to require any extra bits.

kuhar edited the summary of this revision. (Show Details)May 2 2023, 7:34 AM
kuhar marked 3 inline comments as done.
kuhar added inline comments.
mlir/lib/Dialect/Arith/Transforms/IntNarrowing.cpp
363

Thanks, @antiagainst. This made me realize that unsigned division does not require any extra bits: https://alive2.llvm.org/ce/z/QZJpFp. I updated the implementation and the tests.

kuhar marked an inline comment as done.May 2 2023, 7:37 AM
kuhar updated this revision to Diff 518728.May 2 2023, 7:40 AM

Fix typo in a comment

This revision was landed with ongoing or failed builds.May 2 2023, 7:45 AM
This revision was automatically updated to reflect the committed changes.