[libc] Start to refactor riscv platform abstraction to support both 32 and 64 bits versions

[mikhail.ramalho]

Summary

This patch is the first in a series of patches to refactor the riscv
abstraction in libc to support both riscv32 and riscv64. This patch
enables the compilation of libc with LLVM_LIBC_FULL_BUILD=OFF and libm
disabled. This patch also fixes the strtol test cases so the tests
enabled by this libc configuration are now passing in riscv32 as well.

We updated the cmake file to match the new riscv32 arch and force
LIBC_TARGET_ARCHITECTURE to be "riscv" whenever we find "riscv32" or
"riscv64". This is required as LIBC_TARGET_ARCHITECTURE is used in the
path for several platform specific implementations.

A int get_except() is also added until to allow the compilation in
riscv32, until we implement the platform specific implementation for
this arch.

[mikhail.ramalho]

Renamed dirs riscv64 to riscv

[mikhail.ramalho]

ping

[michaelrj]

Overall LGTM, though are we sure that having the riscv 64 bit and 32 bit targets is the correct path? On other platforms so far we've separated the 32 bit and 64 bit targets.

[sivachandra]

This is fine. But, can you share the status of what works and what does not on riscv32 and also your riscv32 environment?

[mikhail.ramalho]

In D148797#4292915, @michaelrj wrote:

Overall LGTM, though are we sure that having the riscv 64 bit and 32 bit targets is the correct path? On other platforms so far we've separated the 32 bit and 64 bit targets.

My guess is that the code will just work... I believe the only change between the two targets is setjmp/longjmp, where the 64 bits version uses fld, ld, sd, fsd, and the 32 bits will need flw, lw, sw, fsw.

In D148797#4292916, @sivachandra wrote:

This is fine. But, can you share the status of what works and what does not on riscv32 and also your riscv32 environment?

Sure, in the commit message, you mean?

Right now, basic libc should compile, i.e., fullbuild=off and no libm.

For testing, I'm using:

root@qemuriscv32:~# uname -a
Linux qemuriscv32 6.1.20-yocto-standard #1 SMP PREEMPT Sat Mar 18 02:48:04 UTC 2023 riscv32 GNU/Linux

root@qemuriscv32:~# clang -v
clang version 16.0.1 (https://github.com/llvm/llvm-project cd89023f797900e4492da58b7bed36f702120011)
Target: riscv32-poky-linux
Thread model: posix
InstalledDir: /usr/bin
Found candidate GCC installation: /usr/bin/../lib/gcc/riscv32-poky-linux/12.2.0
Found candidate GCC installation: /usr/bin/../lib/riscv32-poky-linux/12.2.0
Selected GCC installation: /usr/bin/../lib/riscv32-poky-linux/12.2.0

For development, I'm using ToT clang.

[sivachandra]

In D148797#4293642, @mikhail.ramalho wrote:

My guess is that the code will just work... I believe the only change between the two targets is setjmp/longjmp, where the 64 bits version uses fld, ld, sd, fsd, and the 32 bits will need flw, lw, sw, fsw.

Are you able to validate your guess with testing?

In D148797#4292916, @sivachandra wrote:

This is fine. But, can you share the status of what works and what does not on riscv32 and also your riscv32 environment?

Sure, in the commit message, you mean?

Yes, in the commit message at the least.

For testing, I'm using:

root@qemuriscv32:~# uname -a
Linux qemuriscv32 6.1.20-yocto-standard #1 SMP PREEMPT Sat Mar 18 02:48:04 UTC 2023 riscv32 GNU/Linux

Can you start a discourse thread with detailed instructions on how to setup the riscv32 emulator? Or, feel free to send a riscv focused doc patch - we will figure out where and how exactly to land it during the review.

[mikhail.ramalho]

Are you able to validate your guess with testing?

For the current code, yes. I'm currently changing the floating-point code to properly handle UInt<128> and so far it's working properly. I'm not sure about the code when libc_full=ON is enabled but I'm only foreseeing the setjmp/longjmp issue I've mentioned.

I can send a bigger patch when both riscv32/64 are enabled if you fell that's a better approach.

Can you start a discourse thread with detailed instructions on how to setup the riscv32 emulator? Or, feel free to send a riscv focused doc patch - we will figure out where and how exactly to land it during the review.

Sure, I was planning to write a blog post about it too soon.

[mikhail.ramalho]

• Added details about the current status of the riscv32 port in the commit message
• Added LIBC_TARGET_ARCH_IS_ANY_RISCV and fix a syscall infinite recursion

[sivachandra]

This change LGTM in general. But, I would like to have instructions on how to test this before I accept it. Couple of reasons:

1. We want to have an estimate for the public CI.
2. Since this patch is unifying riscv64 and riscv32, I want to see how much of riscv32 actually works. Things like, if a riscv64 change does not work for riscv32, would we require that the contributor/patch author block on riscv32 changes?

[mikhail.ramalho]

Fixed strtol tests to pass in riscv32

[mikhail.ramalho]

• Fixed wrong define
• Rebased

[mikhail.ramalho]

Changed some defines to LIBC_TARGET_ARCH_IS_ANY_RISCV

[sivachandra]

In D148797#4299288, @sivachandra wrote:

This change LGTM in general. But, I would like to have instructions on how to test this before I accept it. Couple of reasons:

1. We want to have an estimate for the public CI.
2. Since this patch is unifying riscv64 and riscv32, I want to see how much of riscv32 actually works. Things like, if a riscv64 change does not work for riscv32, would we require that the contributor/patch author block on riscv32 changes?

I would like to see answers to the above questions before we can take this patch forward.

[mikhail.ramalho]

In D148797#4299288, @sivachandra wrote:

This change LGTM in general. But, I would like to have instructions on how to test this before I accept it. Couple of reasons:

1. We want to have an estimate for the public CI.

Sorry, I didn't understand the question. What do you mean by that?

2. Since this patch is unifying riscv64 and riscv32, I want to see how much of riscv32 actually works. Things like, if a riscv64 change does not work for riscv32, would we require that the contributor/patch author block on riscv32 changes?

So far most of the changes needed to port the code to rv32 are related to either UInt<128> not playing nice with the rest of the code or the need to use alternative syscalls (usually with the suffix 64). Once the current patches land, all the test cases with LIBC_FULL=OFF will pass.

Except for the assembly in longjmp/setjmp, the rest of the code should just work in rv32.

[michaelrj]

Every platform we support gets broken occasionally by patches that forget to take it into account. Without buildbots telling us when the platform is broken, then we can't fix it. An example for this would be the arm32 failing to update for several months and our strtol tests breaking on it, leading to this patch: https://reviews.llvm.org/D151935.
For this reason we require anyone adding a new platform to demonstrate their plan for supporting that platform through CI. You can look at the "CI Builders" section on this page for more details: https://libc.llvm.org/porting.html

[mikhail.ramalho]

Rebased

[mikhail.ramalho]

@sivachandra @michaelrj I'm working with @asb to bring a rv32 buildbot up this week.

I created a script that will copy all the test cases + test data to an rv32 image running on qemu, and then use CMake's -DCROSSCOMPILING flag to run the tests.

On my machine, it takes around 20 min to run ninja check-libc, but since the bots only do ninja libc-integration-tests, ninja libc-api-test, and ninja libc-unit-tests, each run should be faster than that.

May I ask if this addresses your comments? We'll need this patch + D158033 + D150211 to get rv32 compilation working.

[michaelrj]

If you have a plan for your buildbot then I think we can add RISC-V 32 as a supported platform. I've added some comments on this patch, but since I will be OOO soon I won't be able to give final approval.

libc/src/__support/OSUtil/linux/syscall.h

23

are syscalls exactly the same for RISC-V 32 and 64? If not, is it worthwhile to keep these separate?

libc/test/src/math/exhaustive/CMakeLists.txt

24 ↗

(On Diff #548235)

why do these all need atomic?

[mikhail.ramalho]

In D148797#4596926, @michaelrj wrote:

If you have a plan for your buildbot then I think we can add RISC-V 32 as a supported platform. I've added some comments on this patch, but since I will be OOO soon I won't be able to give final approval.

We should probably have it running by next week, I already submitted the required changes to llvm-zorg. It will be on staging for now, until we are sure that it's working properly.

libc/src/__support/OSUtil/linux/syscall.h

23

Do you mean the syscall numbers? The ones defined in syscall_numbers.h.inc?

If so, they are all guarded by the corresponding #ifdef __NR_*... This riscv/syscall.h file only defines the macros to call the syscalls.

libc/test/src/math/exhaustive/CMakeLists.txt

24 ↗

(On Diff #548235)

They were failing with a missing atomic dependency when using stdout, I'll re-run the tests without it now that we have a new interface for it.

[mikhail.ramalho]

• Make unit test static
• Fix some comments
• Rebased

[mikhail.ramalho]

• rebased

[mikhail.ramalho]

@sivachandra @michaelrj the rv32 buildbot is up on staging now: https://lab.llvm.org/staging/#/console

I believe this addresses the last of your comments for this PR.

[mikhail.ramalho]

Rebased

[mikhail.ramalho]

ping

[michaelrj]

LGTM, thank you for finishing this!

libc/cmake/modules/LLVMLibCArchitectures.cmake

 # the libc CMake infrastructure. Also, this is where we also check if the target
 # architecture is currently supported.
 if(LIBC_TARGET_ARCHITECTURE STREQUAL "arm")
   set(LIBC_TARGET_ARCHITECTURE_IS_ARM TRUE)
 elseif(LIBC_TARGET_ARCHITECTURE STREQUAL "aarch64")
   set(LIBC_TARGET_ARCHITECTURE_IS_AARCH64 TRUE)
 elseif(LIBC_TARGET_ARCHITECTURE STREQUAL "x86_64")
   set(LIBC_TARGET_ARCHITECTURE_IS_X86 TRUE)
-elseif(LIBC_TARGET_ARCHITECTURE STREQUAL "riscv32")
-  set(LIBC_TARGET_ARCHITECTURE_IS_RISCV32 TRUE)
 elseif(LIBC_TARGET_ARCHITECTURE STREQUAL "riscv64")
   set(LIBC_TARGET_ARCHITECTURE_IS_RISCV64 TRUE)
+  set(LIBC_TARGET_ARCHITECTURE "riscv")
+elseif(LIBC_TARGET_ARCHITECTURE STREQUAL "riscv32")
+  set(LIBC_TARGET_ARCHITECTURE_IS_RISCV32 TRUE)
+  set(LIBC_TARGET_ARCHITECTURE "riscv")
 else()
   message(FATAL_ERROR
           "Unsupported libc target architecture ${LIBC_TARGET_ARCHITECTURE}")
 endif()
 
 if(LIBC_TARGET_OS STREQUAL "baremetal")
   set(LIBC_TARGET_OS_IS_BAREMETAL TRUE)
 elseif(LIBC_TARGET_OS STREQUAL "linux")

libc/config/linux/app.h

struct TLSImage {
 
   // The alignment of the TLS layout. It assumed that the alignment
   // value is a power of 2.
   uintptr_t align;
 };
 
 #if defined(LIBC_TARGET_ARCH_IS_X86_64) ||                                     \
     defined(LIBC_TARGET_ARCH_IS_AARCH64) ||                                    \
-    defined(LIBC_TARGET_ARCH_IS_RISCV64)
+    defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
 // At the language level, argc is an int. But we use uint64_t as the x86_64
 // ABI specifies it as an 8 byte value. Likewise, in the ARM64 ABI, arguments
 // are usually passed in registers.  x0 is a doubleword register, so this is
 // 64 bit for aarch64 as well.
 typedef uintptr_t ArgcType;
 
 // At the language level, argv is a char** value. However, we use uint64_t as
 // ABIs specify the argv vector be an |argc| long array of 8-byte values.

libc/src/__support/FPUtil/FEnvImpl.h

 
 // The extra !defined(APPLE) condition is to cause x86_64 MacOS builds to use
 // the dummy implementations below. Once a proper x86_64 darwin fenv is set up,
 // the apple condition here should be removed.
 #elif defined(LIBC_TARGET_ARCH_IS_X86) && !defined(__APPLE__)
 #include "x86_64/FEnvImpl.h"
 #elif defined(LIBC_TARGET_ARCH_IS_ARM)
 #include "arm/FEnvImpl.h"
-#elif defined(LIBC_TARGET_ARCH_IS_RISCV32)
-#include "riscv32/FEnvImpl.h"
-#elif defined(LIBC_TARGET_ARCH_IS_RISCV64)
-#include "riscv64/FEnvImpl.h"
+#elif defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
+#include "riscv/FEnvImpl.h"
 #else
 
 namespace LIBC_NAMESPACE::fputil {
 
 // All dummy functions silently succeed.
 
 LIBC_INLINE int clear_except(int) { return 0; }
 

libc/src/__support/FPUtil/FMA.h

 #include "src/__support/macros/properties/cpu_features.h" // LIBC_TARGET_CPU_HAS_FMA
 
 #if defined(LIBC_TARGET_CPU_HAS_FMA)
 
 #if defined(LIBC_TARGET_ARCH_IS_X86_64)
 #include "x86_64/FMA.h"
 #elif defined(LIBC_TARGET_ARCH_IS_AARCH64)
 #include "aarch64/FMA.h"
-#elif defined(LIBC_TARGET_ARCH_IS_RISCV64)
-#include "riscv64/FMA.h"
+#elif defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
+#include "riscv/FMA.h"
 #elif defined(LIBC_TARGET_ARCH_IS_GPU)
 #include "gpu/FMA.h"
 #endif
 
 #else
 // FMA instructions are not available
 #include "generic/FMA.h"
 #include "src/__support/CPP/type_traits.h"

libc/src/__support/FPUtil/riscv/FEnvImpl.h

-//===-- riscv64 floating point env manipulation functions -------*- C++ -*-===//
+//===-- riscv floating point env manipulation functions ---------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV64_FENVIMPL_H
-#define LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV64_FENVIMPL_H
+#ifndef LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV_FENVIMPL_H
+#define LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV_FENVIMPL_H
 
 #include "src/__support/FPUtil/FPBits.h"
 #include "src/__support/macros/attributes.h" // For LIBC_INLINE_ASM
 #include "src/__support/macros/config.h"     // For LIBC_INLINE
 
 #include <fenv.h>
 #include <stdint.h>
 
LIBC_INLINE int set_env(const fenv_t *envp) {
   // We have to do the masking to preserve the reserved bits.
   FEnv::set_fcsr((status & 0xFF) | (FEnv::get_fcsr() & 0xFFFFFF00));
   return 0;
 }
 
 } // namespace fputil
 } // namespace LIBC_NAMESPACE
 
-#endif // LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV64_FENVIMPL_H
+#endif // LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV_FENVIMPL_H

libc/src/__support/FPUtil/riscv/FMA.h

-//===-- RISCV64 implementations of the fma function -------------*- C++ -*-===//
+//===-- RISCV implementations of the fma function ---------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV64_FMA_H
-#define LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV64_FMA_H
+#ifndef LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV_FMA_H
+#define LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV_FMA_H
 
 #include "src/__support/macros/attributes.h" // LIBC_INLINE
 #include "src/__support/macros/properties/architectures.h"
 #include "src/__support/macros/properties/cpu_features.h" // LIBC_TARGET_CPU_HAS_FMA
 
-#if !defined(LIBC_TARGET_ARCH_IS_RISCV64)
+#if !defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
 #error "Invalid include"
 #endif
 
 #if !defined(LIBC_TARGET_CPU_HAS_FMA)
 #error "FMA instructions are not supported"
 #endif
 
 #include "src/__support/CPP/type_traits.h"
LIBC_INLINE_ASM("fmadd.d %0, %1, %2, %3\n\t"
                   : "=f"(result)
                   : "f"(x), "f"(y), "f"(z));
   return result;
 }
 
 } // namespace fputil
 } // namespace LIBC_NAMESPACE
 
-#endif // LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV64_FMA_H
+#endif // LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV_FMA_H

libc/src/__support/FPUtil/riscv/sqrt.h

 //===-- Square root of IEEE 754 floating point numbers ----------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV64_SQRT_H
-#define LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV64_SQRT_H
+#ifndef LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV_SQRT_H
+#define LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV_SQRT_H
 
 #include "src/__support/common.h"
 #include "src/__support/macros/properties/architectures.h"
 
-#if !defined(LIBC_TARGET_ARCH_IS_RISCV64)
+#if !defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
 #error "Invalid include"
 #endif
 
 #include "src/__support/FPUtil/generic/sqrt.h"
 
 namespace LIBC_NAMESPACE {
 namespace fputil {
 
 template <> LIBC_INLINE float sqrt<float>(float x) {
   float result;
   __asm__ __volatile__("fsqrt.s %0, %1\n\t" : "=f"(result) : "f"(x));
   return result;
 }
 
 template <> LIBC_INLINE double sqrt<double>(double x) {
   double result;
   __asm__ __volatile__("fsqrt.d %0, %1\n\t" : "=f"(result) : "f"(x));
   return result;
 }
 
 } // namespace fputil
 } // namespace LIBC_NAMESPACE
 
-#endif // LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV64_SQRT_H
+#endif // LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV_SQRT_H

libc/src/__support/FPUtil/riscv32/FEnvImpl.h

-//===-- riscv32 floating point env manipulation functions -------*- C++ -*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV32_FENVIMPL_H
-#define LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV32_FENVIMPL_H
-
-#include "src/__support/FPUtil/FPBits.h"
-#include "src/__support/macros/attributes.h" // For LIBC_INLINE_ASM
-#include "src/__support/macros/config.h"     // For LIBC_INLINE
-
-#include <fenv.h>
-#include <stdint.h>
-
-namespace LIBC_NAMESPACE {
-namespace fputil {
-
-struct FEnv {
-  // We will ignore RMM and DYN rounding modes.
-  static constexpr uint32_t TONEAREST = 0x0;
-  static constexpr uint32_t TOWARDZERO = 0x1;
-  static constexpr uint32_t DOWNWARD = 0x2;
-  static constexpr uint32_t UPWARD = 0x3;
-
-  // These are the bit locations of the corresponding exceptions in fcsr.
-  static constexpr uint32_t INEXACT = 0x1;
-  static constexpr uint32_t UNDERFLOW = 0x2;
-  static constexpr uint32_t OVERFLOW = 0x4;
-  static constexpr uint32_t DIVBYZERO = 0x8;
-  static constexpr uint32_t INVALID = 0x10;
-
-  LIBC_INLINE static uint32_t get_frm() {
-    unsigned int rm;
-    LIBC_INLINE_ASM("frrm %0\n\t" : "=r"(rm));
-    return rm;
-  }
-
-  LIBC_INLINE static void set_frm(uint32_t rm) {
-    LIBC_INLINE_ASM("fsrm %0, %0\n\t" : "+r"(rm));
-  }
-
-  LIBC_INLINE static uint32_t get_fflags() {
-    unsigned int flags;
-    LIBC_INLINE_ASM("frflags %0\n\t" : "=r"(flags));
-    return flags;
-  }
-
-  LIBC_INLINE static void set_fflags(uint32_t flags) {
-    LIBC_INLINE_ASM("fsflags %0, %0\n\t" : "+r"(flags));
-  }
-
-  LIBC_INLINE static uint32_t get_fcsr() {
-    unsigned int fcsr;
-    LIBC_INLINE_ASM("frcsr %0\n\t" : "=r"(fcsr));
-    return fcsr;
-  }
-
-  LIBC_INLINE static void set_fcsr(uint32_t fcsr) {
-    LIBC_INLINE_ASM("fscsr %0, %0\n\t" : "+r"(fcsr));
-  }
-
-  LIBC_INLINE static int exception_bits_to_macro(uint32_t status) {
-    return (status & INVALID ? FE_INVALID : 0) |
-           (status & DIVBYZERO ? FE_DIVBYZERO : 0) |
-           (status & OVERFLOW ? FE_OVERFLOW : 0) |
-           (status & UNDERFLOW ? FE_UNDERFLOW : 0) |
-           (status & INEXACT ? FE_INEXACT : 0);
-  }
-
-  LIBC_INLINE static uint32_t exception_macro_to_bits(int except) {
-    return (except & FE_INVALID ? INVALID : 0) |
-           (except & FE_DIVBYZERO ? DIVBYZERO : 0) |
-           (except & FE_OVERFLOW ? OVERFLOW : 0) |
-           (except & FE_UNDERFLOW ? UNDERFLOW : 0) |
-           (except & FE_INEXACT ? INEXACT : 0);
-  }
-};
-
-// Since RISCV does not have exception enable bits, we will just return
-// the failure indicator.
-LIBC_INLINE int enable_except(int) { return -1; }
-
-// Always succeed.
-LIBC_INLINE int disable_except(int) { return 0; }
-
-// Always return "no exceptions enabled".
-LIBC_INLINE int get_except() { return 0; }
-
-LIBC_INLINE int clear_except(int excepts) {
-  uint32_t flags = FEnv::get_fflags();
-  uint32_t to_clear = FEnv::exception_macro_to_bits(excepts);
-  flags &= ~to_clear;
-  FEnv::set_fflags(flags);
-  return 0;
-}
-
-LIBC_INLINE int test_except(int excepts) {
-  uint32_t to_test = FEnv::exception_macro_to_bits(excepts);
-  uint32_t flags = FEnv::get_fflags();
-  return FEnv::exception_bits_to_macro(flags & to_test);
-}
-
-LIBC_INLINE int set_except(int excepts) {
-  uint32_t flags = FEnv::get_fflags();
-  FEnv::set_fflags(flags | FEnv::exception_macro_to_bits(excepts));
-  return 0;
-}
-
-LIBC_INLINE int raise_except(int excepts) {
-  // Since there are no traps, we just set the exception flags.
-  uint32_t flags = FEnv::get_fflags();
-  FEnv::set_fflags(flags | FEnv::exception_macro_to_bits(excepts));
-  return 0;
-}
-
-LIBC_INLINE int get_round() {
-  uint32_t rm = FEnv::get_frm();
-  switch (rm) {
-  case FEnv::TONEAREST:
-    return FE_TONEAREST;
-  case FEnv::DOWNWARD:
-    return FE_DOWNWARD;
-  case FEnv::UPWARD:
-    return FE_UPWARD;
-  case FEnv::TOWARDZERO:
-    return FE_TOWARDZERO;
-  default:
-    return -1; // Error value.
-  }
-  return 0;
-}
-
-LIBC_INLINE int set_round(int mode) {
-  uint32_t rm;
-  switch (mode) {
-  case FE_TONEAREST:
-    rm = FEnv::TONEAREST;
-    break;
-  case FE_DOWNWARD:
-    rm = FEnv::DOWNWARD;
-    break;
-  case FE_UPWARD:
-    rm = FEnv::UPWARD;
-    break;
-  case FE_TOWARDZERO:
-    rm = FEnv::TOWARDZERO;
-    break;
-  default:
-    return -1; // To indicate failure
-  }
-  FEnv::set_frm(rm);
-  return 0;
-}
-
-LIBC_INLINE int get_env(fenv_t *envp) {
-  uint32_t *state = reinterpret_cast<uint32_t *>(envp);
-  *state = FEnv::get_fcsr();
-  return 0;
-}
-
-LIBC_INLINE int set_env(const fenv_t *envp) {
-  if (envp == FE_DFL_ENV) {
-    FEnv::set_frm(FEnv::TONEAREST);
-    FEnv::set_fflags(0);
-    return 0;
-  }
-  uint32_t status = *reinterpret_cast<const uint32_t *>(envp);
-  // We have to do the masking to preserve the reserved bits.
-  FEnv::set_fcsr((status & 0xFF) | (FEnv::get_fcsr() & 0xFFFFFF00));
-  return 0;
-}
-
-} // namespace fputil
-} // namespace LIBC_NAMESPACE
-
-#endif // LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV32_FENVIMPL_H

libc/src/__support/FPUtil/sqrt.h

 #define LLVM_LIBC_SRC___SUPPORT_FPUTIL_SQRT_H
 
 #include "src/__support/macros/properties/architectures.h"
 
 #if defined(LIBC_TARGET_ARCH_IS_X86_64)
 #include "x86_64/sqrt.h"
 #elif defined(LIBC_TARGET_ARCH_IS_AARCH64)
 #include "aarch64/sqrt.h"
-#elif defined(LIBC_TARGET_ARCH_IS_RISCV64)
-#include "riscv64/sqrt.h"
+#elif defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
+#include "riscv/sqrt.h"
 #else
 #include "generic/sqrt.h"
 
 #endif
 #endif // LLVM_LIBC_SRC___SUPPORT_FPUTIL_SQRT_H

libc/src/__support/OSUtil/linux/riscv/CMakeLists.txt

 add_header_library(
-  linux_riscv64_util
+  linux_riscv_util
   HDRS
     syscall.h
   DEPENDS
     libc.src.__support.common
 )

libc/src/__support/OSUtil/linux/riscv/syscall.h

-//===--------- inline implementation of riscv64 syscalls ----------* C++ *-===//
+//===--------- inline implementation of riscv syscalls ------------* C++ *-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_LIBC_SRC___SUPPORT_OSUTIL_LINUX_RISCV64_SYSCALL_H
-#define LLVM_LIBC_SRC___SUPPORT_OSUTIL_LINUX_RISCV64_SYSCALL_H
+#ifndef LLVM_LIBC_SRC___SUPPORT_OSUTIL_LINUX_RISCV_SYSCALL_H
+#define LLVM_LIBC_SRC___SUPPORT_OSUTIL_LINUX_RISCV_SYSCALL_H
 
 #include "src/__support/common.h"
 
 #define REGISTER_DECL_0                                                        \
   register long a7 __asm__("a7") = number;                                     \
   register long a0 __asm__("a0");
 #define REGISTER_DECL_1                                                        \
   register long a7 __asm__("a7") = number;                                     \

 #undef REGISTER_CONSTRAINT_0
 #undef REGISTER_CONSTRAINT_1
 #undef REGISTER_CONSTRAINT_2
 #undef REGISTER_CONSTRAINT_3
 #undef REGISTER_CONSTRAINT_4
 #undef REGISTER_CONSTRAINT_5
 #undef REGISTER_CONSTRAINT_6
 
-#endif // LLVM_LIBC_SRC___SUPPORT_OSUTIL_LINUX_RISCV64_SYSCALL_H
+#endif // LLVM_LIBC_SRC___SUPPORT_OSUTIL_LINUX_RISCV_SYSCALL_H

libc/src/__support/OSUtil/linux/syscall.h

 #include "src/__support/macros/properties/architectures.h"
 
 #ifdef LIBC_TARGET_ARCH_IS_X86_64
 #include "x86_64/syscall.h"
 #elif defined(LIBC_TARGET_ARCH_IS_AARCH64)
 #include "aarch64/syscall.h"
 #elif defined(LIBC_TARGET_ARCH_IS_ARM)
 #include "arm/syscall.h"
-#elif defined(LIBC_TARGET_ARCH_IS_RISCV64)
-#include "riscv64/syscall.h"
+#elif defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
+#include "riscv/syscall.h"
 #endif
 
 namespace LIBC_NAMESPACE {
 
 template <typename R, typename... Ts>
 LIBC_INLINE R syscall_impl(long __number, Ts... ts) {
   static_assert(sizeof...(Ts) <= 6, "Too many arguments for syscall");
   return cpp::bit_or_static_cast<R>(syscall_impl(__number, (long)ts...));
 }
 
 } // namespace LIBC_NAMESPACE
 
 #endif // LLVM_LIBC_SRC___SUPPORT_OSUTIL_LINUX_SYSCALL_H

libc/src/__support/macros/properties/architectures.h

 #if (defined(__arm__) || defined(_M_ARM))
 #define LIBC_TARGET_ARCH_IS_ARM
 #endif
 
 #if defined(__aarch64__) || defined(__arm64__) || defined(_M_ARM64)
 #define LIBC_TARGET_ARCH_IS_AARCH64
 #endif
 
-#if (defined(LIBC_TARGET_ARCH_IS_AARCH64) || defined(LIBC_TARGET_ARCH_IS_ARM))
+#if defined(LIBC_TARGET_ARCH_IS_AARCH64) || defined(LIBC_TARGET_ARCH_IS_ARM)
 #define LIBC_TARGET_ARCH_IS_ANY_ARM
 #endif
 
 #if defined(__riscv) && (__riscv_xlen == 64)
 #define LIBC_TARGET_ARCH_IS_RISCV64
 #endif
 
 #if defined(__riscv) && (__riscv_xlen == 32)
 #define LIBC_TARGET_ARCH_IS_RISCV32
 #endif
 
-#if (defined(LIBC_TARGET_ARCH_IS_RISCV64) ||                                   \
-     defined(LIBC_TARGET_ARCH_IS_RISCV32))
+#if defined(LIBC_TARGET_ARCH_IS_RISCV64) || defined(LIBC_TARGET_ARCH_IS_RISCV32)
 #define LIBC_TARGET_ARCH_IS_ANY_RISCV
 #endif
 
 #endif // LLVM_LIBC_SRC___SUPPORT_MACROS_PROPERTIES_ARCHITECTURES_H

libc/src/__support/threads/linux/thread.cpp

| CLONE_SYSVSEM // Share a single list of System V semaphore adjustment
                     // values
     | CLONE_PARENT_SETTID  // Set child thread ID in |ptid| of the parent.
     | CLONE_CHILD_CLEARTID // Let the kernel clear the tid address
                            // wake the joining thread.
     | CLONE_SETTLS;        // Setup the thread pointer of the new thread.
 
 #ifdef LIBC_TARGET_ARCH_IS_AARCH64
 #define CLONE_RESULT_REGISTER "x0"
-#elif defined(LIBC_TARGET_ARCH_IS_RISCV64)
+#elif defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
 #define CLONE_RESULT_REGISTER "t0"
 #elif defined(LIBC_TARGET_ARCH_IS_X86_64)
 #define CLONE_RESULT_REGISTER "rax"
 #else
 #error "CLONE_RESULT_REGISTER not defined for your target architecture"
 #endif
 
 static constexpr ErrorOr<size_t> add_no_overflow(size_t lhs, size_t rhs) {
return reinterpret_cast<uintptr_t>(__builtin_frame_address(0))
          // on to the stack. So, we have to step past two 64-bit values to get
          // to the start args.
          + sizeof(uintptr_t) * 2;
 #elif defined(LIBC_TARGET_ARCH_IS_AARCH64)
   // The frame pointer after cloning the new thread in the Thread::run method
   // is set to the stack pointer where start args are stored. So, we fetch
   // from there.
   return reinterpret_cast<uintptr_t>(__builtin_frame_address(1));
-#elif defined(LIBC_TARGET_ARCH_IS_RISCV64)
+#elif defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
   // The current frame pointer is the previous stack pointer where the start
   // args are stored.
   return reinterpret_cast<uintptr_t>(__builtin_frame_address(0));
 #endif
 }
 
 [[gnu::noinline]] LIBC_INLINE void start_thread() {
   auto *start_args = reinterpret_cast<StartArgs *>(get_start_args_addr());
#if defined(LIBC_TARGET_ARCH_IS_X86_64)
   long register clone_result asm(CLONE_RESULT_REGISTER);
   clone_result = LIBC_NAMESPACE::syscall_impl<long>(
       SYS_clone, CLONE_SYSCALL_FLAGS, adjusted_stack,
       &attrib->tid,    // The address where the child tid is written
       &clear_tid->val, // The futex where the child thread status is signalled
       tls.tp           // The thread pointer value for the new thread.
   );
 #elif defined(LIBC_TARGET_ARCH_IS_AARCH64) ||                                  \
-    defined(LIBC_TARGET_ARCH_IS_RISCV64)
+    defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
   long register clone_result asm(CLONE_RESULT_REGISTER);
   clone_result = LIBC_NAMESPACE::syscall_impl<long>(
       SYS_clone, CLONE_SYSCALL_FLAGS, adjusted_stack,
       &attrib->tid,   // The address where the child tid is written
       tls.tp,         // The thread pointer value for the new thread.
       &clear_tid->val // The futex where the child thread status is signalled
   );
 #else

libc/src/__support/threads/thread.h

union ThreadReturnValue {
   int stdc_retval;
   constexpr ThreadReturnValue() : posix_retval(nullptr) {}
   constexpr ThreadReturnValue(int r) : stdc_retval(r) {}
   constexpr ThreadReturnValue(void *r) : posix_retval(r) {}
 };
 
 #if (defined(LIBC_TARGET_ARCH_IS_AARCH64) ||                                   \
      defined(LIBC_TARGET_ARCH_IS_X86_64) ||                                    \
-     defined(LIBC_TARGET_ARCH_IS_RISCV64))
+     defined(LIBC_TARGET_ARCH_IS_ANY_RISCV))
 constexpr unsigned int STACK_ALIGNMENT = 16;
 #endif
 // TODO: Provide stack alignment requirements for other architectures.
 
 enum class DetachState : uint32_t {
   JOINABLE = 0x11,
   EXITING = 0x22,
   DETACHED = 0x33

libc/src/setjmp/riscv/longjmp.cpp

 //===-- Implementation of longjmp -----------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "src/setjmp/longjmp.h"
 #include "src/__support/common.h"
 #include "src/__support/macros/properties/architectures.h"
 
 #include <setjmp.h>
 
-#if !defined(LIBC_TARGET_ARCH_IS_RISCV64)
+#if !defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
 #error "Invalid file include"
 #endif
 
 #define LOAD_IMPL(insns, reg, val)                                             \
   LIBC_INLINE_ASM(#insns " " #reg ", %0\n\t" : : "m"(val) :)
 
 #ifdef LIBC_TARGET_ARCH_IS_RISCV32
 #define LOAD(reg, val) LOAD_IMPL(lw, reg, val)

libc/src/setjmp/riscv/setjmp.cpp

 //===-- Implementation of setjmp ------------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "src/__support/common.h"
 #include "src/setjmp/setjmp_impl.h"
 
 #include <setjmp.h>
 
-#if !defined(LIBC_TARGET_ARCH_IS_RISCV64)
+#if !defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
 #error "Invalid file include"
 #endif
 
 #define STORE_IMPL(insns, reg, val)                                            \
   LIBC_INLINE_ASM(#insns " " #reg ", %0\n\t" : : "m"(val) :)
 
 #ifdef LIBC_TARGET_ARCH_IS_RISCV32
 #define STORE(reg, val) STORE_IMPL(sw, reg, val)

libc/test/src/fenv/enabled_exceptions_test.cpp

 #include "test/UnitTest/Test.h"
 
 #include <fenv.h>
 #include <signal.h>
 
 // This test enables an exception and verifies that raising that exception
 // triggers SIGFPE.
 TEST(LlvmLibcExceptionStatusTest, RaiseAndCrash) {
-#if defined(LIBC_TARGET_ARCH_IS_ANY_ARM) || defined(LIBC_TARGET_ARCH_IS_RISCV64)
+#if defined(LIBC_TARGET_ARCH_IS_ANY_ARM) ||                                    \
+    defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
   // Few Arm HW implementations do not trap exceptions. We skip this test
   // completely on such HW.
   //
   // Whether HW supports trapping exceptions or not is deduced by enabling an
   // exception and reading back to see if the exception got enabled. If the
   // exception did not get enabled, then it means that the HW does not support
   // trapping exceptions.
   LIBC_NAMESPACE::fputil::disable_except(FE_ALL_EXCEPT);

libc/test/src/fenv/feenableexcept_test.cpp

 #include "src/fenv/feenableexcept.h"
 #include "src/fenv/fegetexcept.h"
 
 #include "test/UnitTest/Test.h"
 
 #include <fenv.h>
 
 TEST(LlvmLibcFEnvTest, EnableTest) {
-#if defined(LIBC_TARGET_ARCH_IS_ANY_ARM) || defined(LIBC_TARGET_ARCH_IS_RISCV64)
+#if defined(LIBC_TARGET_ARCH_IS_ANY_ARM) ||                                    \
+    defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
   // Few Arm HW implementations do not trap exceptions. We skip this test
   // completely on such HW.
   //
   // Whether HW supports trapping exceptions or not is deduced by enabling an
   // exception and reading back to see if the exception got enabled. If the
   // exception did not get enabled, then it means that the HW does not support
   // trapping exceptions.
   LIBC_NAMESPACE::fedisableexcept(FE_ALL_EXCEPT);

libc/test/src/fenv/feholdexcept_test.cpp

 #include "src/__support/FPUtil/FEnvImpl.h"
 #include "src/__support/macros/properties/architectures.h"
 #include "test/UnitTest/FPExceptMatcher.h"
 #include "test/UnitTest/Test.h"
 
 #include <fenv.h>
 
 TEST(LlvmLibcFEnvTest, RaiseAndCrash) {
-#if defined(LIBC_TARGET_ARCH_IS_ANY_ARM) || defined(LIBC_TARGET_ARCH_IS_RISCV64)
+#if defined(LIBC_TARGET_ARCH_IS_ANY_ARM) ||                                    \
+    defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
   // Few Arm HW implementations do not trap exceptions. We skip this test
   // completely on such HW.
   //
   // Whether HW supports trapping exceptions or not is deduced by enabling an
   // exception and reading back to see if the exception got enabled. If the
   // exception did not get enabled, then it means that the HW does not support
   // trapping exceptions.
   LIBC_NAMESPACE::fputil::disable_except(FE_ALL_EXCEPT);