This is an archive of the discontinued LLVM Phabricator instance.

Differential D148733

[RISCV] Let assembler accept vector memory operands that have an explicit 0 offset.
ClosedPublic

Authored by craig.topper on Apr 19 2023, 11:31 AM.

Details

Reviewers
asb
reames
frasercrmck
rogfer01
kito-cheng
Commits
rG09b0f89c33f1: [RISCV] Let assembler accept vector memory operands that have an explicit 0…
Summary

Binutils allows vector instructions with memory operands that
have an explicit 0 offset like 'vle8.v v0, 0(a0)'.

We already have support for this in the parser because the same
thing is allowed for atomics.

This patch changes the AsmOperand and AsmString for the vector
memory instructions to allow this.

Diff Detail

Event Timeline

craig.topper created this revision.Apr 19 2023, 11:31 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 19 2023, 11:31 AM
Herald added subscribers: jobnoorman, luke, VincentWu and 25 others. · View Herald Transcript
craig.topper requested review of this revision.Apr 19 2023, 11:31 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 19 2023, 11:31 AM
Herald added subscribers: • pcwang-thead, eopXD, MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B226654: Diff 515028.Apr 19 2023, 12:07 PM
asb accepted this revision.Apr 19 2023, 10:45 PM

LGTM.

This revision is now accepted and ready to land.Apr 19 2023, 10:45 PM
This revision was landed with ongoing or failed builds.Apr 20 2023, 12:19 AM
Closed by commit rG09b0f89c33f1: [RISCV] Let assembler accept vector memory operands that have an explicit 0… (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG09b0f89c33f1: [RISCV] Let assembler accept vector memory operands that have an explicit 0….

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
62 lines
test/
MC/
RISCV/
rvv/
36 lines
30 lines
54 lines

Diff 515231

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

Show First 20 Lines • Show All 184 Lines • ▼ Show 20 Lines
// Instruction class templates // Instruction class templates
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in { let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
// unit-stride load vd, (rs1), vm // unit-stride load vd, (rs1), vm
class VUnitStrideLoad<RISCVWidth width, string opcodestr> class VUnitStrideLoad<RISCVWidth width, string opcodestr>
: RVInstVLU<0b000, width.Value{3}, LUMOPUnitStride, width.Value{2-0}, : RVInstVLU<0b000, width.Value{3}, LUMOPUnitStride, width.Value{2-0},
(outs VR:$vd), (outs VR:$vd),
(ins GPRMem:$rs1, VMaskOp:$vm), opcodestr, "$vd, (${rs1})$vm">; (ins GPRMemZeroOffset:$rs1, VMaskOp:$vm), opcodestr, "$vd, ${rs1}$vm">;
let vm = 1, RVVConstraint = NoConstraint in { let vm = 1, RVVConstraint = NoConstraint in {
// unit-stride whole register load vl<nf>r.v vd, (rs1) // unit-stride whole register load vl<nf>r.v vd, (rs1)
class VWholeLoad<bits<3> nf, RISCVWidth width, string opcodestr, RegisterClass VRC> class VWholeLoad<bits<3> nf, RISCVWidth width, string opcodestr, RegisterClass VRC>
: RVInstVLU<nf, width.Value{3}, LUMOPUnitStrideWholeReg, : RVInstVLU<nf, width.Value{3}, LUMOPUnitStrideWholeReg,
width.Value{2-0}, (outs VRC:$vd), (ins GPRMem:$rs1), width.Value{2-0}, (outs VRC:$vd), (ins GPRMemZeroOffset:$rs1),
opcodestr, "$vd, (${rs1})"> { opcodestr, "$vd, $rs1"> {
let Uses = []; let Uses = [];
} }
// unit-stride mask load vd, (rs1) // unit-stride mask load vd, (rs1)
class VUnitStrideLoadMask<string opcodestr> class VUnitStrideLoadMask<string opcodestr>
: RVInstVLU<0b000, LSWidth8.Value{3}, LUMOPUnitStrideMask, LSWidth8.Value{2-0}, : RVInstVLU<0b000, LSWidth8.Value{3}, LUMOPUnitStrideMask, LSWidth8.Value{2-0},
(outs VR:$vd), (outs VR:$vd),
(ins GPRMem:$rs1), opcodestr, "$vd, (${rs1})">; (ins GPRMemZeroOffset:$rs1), opcodestr, "$vd, $rs1">;
} // vm = 1, RVVConstraint = NoConstraint } // vm = 1, RVVConstraint = NoConstraint
// unit-stride fault-only-first load vd, (rs1), vm // unit-stride fault-only-first load vd, (rs1), vm
class VUnitStrideLoadFF<RISCVWidth width, string opcodestr> class VUnitStrideLoadFF<RISCVWidth width, string opcodestr>
: RVInstVLU<0b000, width.Value{3}, LUMOPUnitStrideFF, width.Value{2-0}, : RVInstVLU<0b000, width.Value{3}, LUMOPUnitStrideFF, width.Value{2-0},
(outs VR:$vd), (outs VR:$vd),
(ins GPRMem:$rs1, VMaskOp:$vm), opcodestr, "$vd, (${rs1})$vm">; (ins GPRMemZeroOffset:$rs1, VMaskOp:$vm), opcodestr, "$vd, ${rs1}$vm">;
// strided load vd, (rs1), rs2, vm // strided load vd, (rs1), rs2, vm
class VStridedLoad<RISCVWidth width, string opcodestr> class VStridedLoad<RISCVWidth width, string opcodestr>
: RVInstVLS<0b000, width.Value{3}, width.Value{2-0}, : RVInstVLS<0b000, width.Value{3}, width.Value{2-0},
(outs VR:$vd), (outs VR:$vd),
(ins GPRMem:$rs1, GPR:$rs2, VMaskOp:$vm), opcodestr, (ins GPRMemZeroOffset:$rs1, GPR:$rs2, VMaskOp:$vm), opcodestr,
"$vd, (${rs1}), $rs2$vm">; "$vd, $rs1, $rs2$vm">;
// indexed load vd, (rs1), vs2, vm // indexed load vd, (rs1), vs2, vm
class VIndexedLoad<RISCVMOP mop, RISCVWidth width, string opcodestr> class VIndexedLoad<RISCVMOP mop, RISCVWidth width, string opcodestr>
: RVInstVLX<0b000, width.Value{3}, mop, width.Value{2-0}, : RVInstVLX<0b000, width.Value{3}, mop, width.Value{2-0},
(outs VR:$vd), (outs VR:$vd),
(ins GPRMem:$rs1, VR:$vs2, VMaskOp:$vm), opcodestr, (ins GPRMemZeroOffset:$rs1, VR:$vs2, VMaskOp:$vm), opcodestr,
"$vd, (${rs1}), $vs2$vm">; "$vd, $rs1, $vs2$vm">;
// unit-stride segment load vd, (rs1), vm // unit-stride segment load vd, (rs1), vm
class VUnitStrideSegmentLoad<bits<3> nf, RISCVWidth width, string opcodestr> class VUnitStrideSegmentLoad<bits<3> nf, RISCVWidth width, string opcodestr>
: RVInstVLU<nf, width.Value{3}, LUMOPUnitStride, width.Value{2-0}, : RVInstVLU<nf, width.Value{3}, LUMOPUnitStride, width.Value{2-0},
(outs VR:$vd), (outs VR:$vd),
(ins GPRMem:$rs1, VMaskOp:$vm), opcodestr, "$vd, (${rs1})$vm">; (ins GPRMemZeroOffset:$rs1, VMaskOp:$vm), opcodestr, "$vd, ${rs1}$vm">;
// segment fault-only-first load vd, (rs1), vm // segment fault-only-first load vd, (rs1), vm
class VUnitStrideSegmentLoadFF<bits<3> nf, RISCVWidth width, string opcodestr> class VUnitStrideSegmentLoadFF<bits<3> nf, RISCVWidth width, string opcodestr>
: RVInstVLU<nf, width.Value{3}, LUMOPUnitStrideFF, width.Value{2-0}, : RVInstVLU<nf, width.Value{3}, LUMOPUnitStrideFF, width.Value{2-0},
(outs VR:$vd), (outs VR:$vd),
(ins GPRMem:$rs1, VMaskOp:$vm), opcodestr, "$vd, (${rs1})$vm">; (ins GPRMemZeroOffset:$rs1, VMaskOp:$vm), opcodestr, "$vd, ${rs1}$vm">;
// strided segment load vd, (rs1), rs2, vm // strided segment load vd, (rs1), rs2, vm
class VStridedSegmentLoad<bits<3> nf, RISCVWidth width, string opcodestr> class VStridedSegmentLoad<bits<3> nf, RISCVWidth width, string opcodestr>
: RVInstVLS<nf, width.Value{3}, width.Value{2-0}, : RVInstVLS<nf, width.Value{3}, width.Value{2-0},
(outs VR:$vd), (outs VR:$vd),
(ins GPRMem:$rs1, GPR:$rs2, VMaskOp:$vm), opcodestr, (ins GPRMemZeroOffset:$rs1, GPR:$rs2, VMaskOp:$vm), opcodestr,
"$vd, (${rs1}), $rs2$vm">; "$vd, $rs1, $rs2$vm">;
// indexed segment load vd, (rs1), vs2, vm // indexed segment load vd, (rs1), vs2, vm
class VIndexedSegmentLoad<bits<3> nf, RISCVMOP mop, RISCVWidth width, class VIndexedSegmentLoad<bits<3> nf, RISCVMOP mop, RISCVWidth width,
string opcodestr> string opcodestr>
: RVInstVLX<nf, width.Value{3}, mop, width.Value{2-0}, : RVInstVLX<nf, width.Value{3}, mop, width.Value{2-0},
(outs VR:$vd), (outs VR:$vd),
(ins GPRMem:$rs1, VR:$vs2, VMaskOp:$vm), opcodestr, (ins GPRMemZeroOffset:$rs1, VR:$vs2, VMaskOp:$vm), opcodestr,
"$vd, (${rs1}), $vs2$vm">; "$vd, $rs1, $vs2$vm">;
} // hasSideEffects = 0, mayLoad = 1, mayStore = 0 } // hasSideEffects = 0, mayLoad = 1, mayStore = 0
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in { let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
// unit-stride store vd, vs3, (rs1), vm // unit-stride store vd, vs3, (rs1), vm
class VUnitStrideStore<RISCVWidth width, string opcodestr> class VUnitStrideStore<RISCVWidth width, string opcodestr>
: RVInstVSU<0b000, width.Value{3}, SUMOPUnitStride, width.Value{2-0}, : RVInstVSU<0b000, width.Value{3}, SUMOPUnitStride, width.Value{2-0},
(outs), (ins VR:$vs3, GPRMem:$rs1, VMaskOp:$vm), opcodestr, (outs), (ins VR:$vs3, GPRMemZeroOffset:$rs1, VMaskOp:$vm), opcodestr,
"$vs3, (${rs1})$vm">; "$vs3, ${rs1}$vm">;
let vm = 1 in { let vm = 1 in {
// vs<nf>r.v vd, (rs1) // vs<nf>r.v vd, (rs1)
class VWholeStore<bits<3> nf, string opcodestr, RegisterClass VRC> class VWholeStore<bits<3> nf, string opcodestr, RegisterClass VRC>
: RVInstVSU<nf, 0, SUMOPUnitStrideWholeReg, : RVInstVSU<nf, 0, SUMOPUnitStrideWholeReg,
0b000, (outs), (ins VRC:$vs3, GPRMem:$rs1), 0b000, (outs), (ins VRC:$vs3, GPRMemZeroOffset:$rs1),
opcodestr, "$vs3, (${rs1})"> { opcodestr, "$vs3, $rs1"> {
let Uses = []; let Uses = [];
} }
// unit-stride mask store vd, vs3, (rs1) // unit-stride mask store vd, vs3, (rs1)
class VUnitStrideStoreMask<string opcodestr> class VUnitStrideStoreMask<string opcodestr>
: RVInstVSU<0b000, LSWidth8.Value{3}, SUMOPUnitStrideMask, LSWidth8.Value{2-0}, : RVInstVSU<0b000, LSWidth8.Value{3}, SUMOPUnitStrideMask, LSWidth8.Value{2-0},
(outs), (ins VR:$vs3, GPRMem:$rs1), opcodestr, (outs), (ins VR:$vs3, GPRMemZeroOffset:$rs1), opcodestr,
"$vs3, (${rs1})">; "$vs3, $rs1">;
} // vm = 1 } // vm = 1
// strided store vd, vs3, (rs1), rs2, vm // strided store vd, vs3, (rs1), rs2, vm
class VStridedStore<RISCVWidth width, string opcodestr> class VStridedStore<RISCVWidth width, string opcodestr>
: RVInstVSS<0b000, width.Value{3}, width.Value{2-0}, (outs), : RVInstVSS<0b000, width.Value{3}, width.Value{2-0}, (outs),
(ins VR:$vs3, GPRMem:$rs1, GPR:$rs2, VMaskOp:$vm), (ins VR:$vs3, GPRMemZeroOffset:$rs1, GPR:$rs2, VMaskOp:$vm),
opcodestr, "$vs3, (${rs1}), $rs2$vm">; opcodestr, "$vs3, $rs1, $rs2$vm">;
// indexed store vd, vs3, (rs1), vs2, vm // indexed store vd, vs3, (rs1), vs2, vm
class VIndexedStore<RISCVMOP mop, RISCVWidth width, string opcodestr> class VIndexedStore<RISCVMOP mop, RISCVWidth width, string opcodestr>
: RVInstVSX<0b000, width.Value{3}, mop, width.Value{2-0}, (outs), : RVInstVSX<0b000, width.Value{3}, mop, width.Value{2-0}, (outs),
(ins VR:$vs3, GPRMem:$rs1, VR:$vs2, VMaskOp:$vm), (ins VR:$vs3, GPRMemZeroOffset:$rs1, VR:$vs2, VMaskOp:$vm),
opcodestr, "$vs3, (${rs1}), $vs2$vm">; opcodestr, "$vs3, $rs1, $vs2$vm">;
// segment store vd, vs3, (rs1), vm // segment store vd, vs3, (rs1), vm
class VUnitStrideSegmentStore<bits<3> nf, RISCVWidth width, string opcodestr> class VUnitStrideSegmentStore<bits<3> nf, RISCVWidth width, string opcodestr>
: RVInstVSU<nf, width.Value{3}, SUMOPUnitStride, width.Value{2-0}, : RVInstVSU<nf, width.Value{3}, SUMOPUnitStride, width.Value{2-0},
(outs), (ins VR:$vs3, GPRMem:$rs1, VMaskOp:$vm), opcodestr, (outs), (ins VR:$vs3, GPRMemZeroOffset:$rs1, VMaskOp:$vm), opcodestr,
"$vs3, (${rs1})$vm">; "$vs3, ${rs1}$vm">;
// segment store vd, vs3, (rs1), rs2, vm // segment store vd, vs3, (rs1), rs2, vm
class VStridedSegmentStore<bits<3> nf, RISCVWidth width, string opcodestr> class VStridedSegmentStore<bits<3> nf, RISCVWidth width, string opcodestr>
: RVInstVSS<nf, width.Value{3}, width.Value{2-0}, (outs), : RVInstVSS<nf, width.Value{3}, width.Value{2-0}, (outs),
(ins VR:$vs3, GPRMem:$rs1, GPR:$rs2, VMaskOp:$vm), (ins VR:$vs3, GPRMemZeroOffset:$rs1, GPR:$rs2, VMaskOp:$vm),
opcodestr, "$vs3, (${rs1}), $rs2$vm">; opcodestr, "$vs3, $rs1, $rs2$vm">;
// segment store vd, vs3, (rs1), vs2, vm // segment store vd, vs3, (rs1), vs2, vm
class VIndexedSegmentStore<bits<3> nf, RISCVMOP mop, RISCVWidth width, class VIndexedSegmentStore<bits<3> nf, RISCVMOP mop, RISCVWidth width,
string opcodestr> string opcodestr>
: RVInstVSX<nf, width.Value{3}, mop, width.Value{2-0}, (outs), : RVInstVSX<nf, width.Value{3}, mop, width.Value{2-0}, (outs),
(ins VR:$vs3, GPRMem:$rs1, VR:$vs2, VMaskOp:$vm), (ins VR:$vs3, GPRMemZeroOffset:$rs1, VR:$vs2, VMaskOp:$vm),
opcodestr, "$vs3, (${rs1}), $vs2$vm">; opcodestr, "$vs3, $rs1, $vs2$vm">;
} // hasSideEffects = 0, mayLoad = 0, mayStore = 1 } // hasSideEffects = 0, mayLoad = 0, mayStore = 1
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
// op vd, vs2, vs1, vm // op vd, vs2, vs1, vm
class VALUVV<bits<6> funct6, RISCVVFormat opv, string opcodestr> class VALUVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
: RVInstVV<funct6, opv, (outs VR:$vd), : RVInstVV<funct6, opv, (outs VR:$vd),
(ins VR:$vs2, VR:$vs1, VMaskOp:$vm), (ins VR:$vs2, VR:$vs1, VMaskOp:$vm),
opcodestr, "$vd, $vs2, $vs1$vm">; opcodestr, "$vd, $vs2, $vs1$vm">;
▲ Show 20 Lines • Show All 1,463 Lines • Show Last 20 Lines

llvm/test/MC/RISCV/rvv/load.s

Show First 20 Lines • Show All 349 Lines • ▼ Show 20 Lines
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 07 64 85 e2 <unknown> # CHECK-UNKNOWN: 07 64 85 e2 <unknown>
vl8re64.v v8, (a0) vl8re64.v v8, (a0)
# CHECK-INST: vl8re64.v v8, (a0) # CHECK-INST: vl8re64.v v8, (a0)
# CHECK-ENCODING: [0x07,0x74,0x85,0xe2] # CHECK-ENCODING: [0x07,0x74,0x85,0xe2]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 07 74 85 e2 <unknown> # CHECK-UNKNOWN: 07 74 85 e2 <unknown>
vlm.v v0, 0(a0)
# CHECK-INST: vlm.v v0, (a0)
# CHECK-ENCODING: [0x07,0x00,0xb5,0x02]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 07 00 b5 02 <unknown>
vle8.v v8, 0(a0)
# CHECK-INST: vle8.v v8, (a0)
# CHECK-ENCODING: [0x07,0x04,0x05,0x02]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 07 04 05 02 <unknown>
vle8ff.v v8, 0(a0), v0.t
# CHECK-INST: vle8ff.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x04,0x05,0x01]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 07 04 05 01 <unknown>
vlse16.v v8, 0(a0), a1, v0.t
# CHECK-INST: vlse16.v v8, (a0), a1, v0.t
# CHECK-ENCODING: [0x07,0x54,0xb5,0x08]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 07 54 b5 08 <unknown>
vluxei32.v v8, 0(a0), v4
# CHECK-INST: vluxei32.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x64,0x45,0x06]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 07 64 45 06 <unknown>
vloxei64.v v8, 0(a0), v4
# CHECK-INST: vloxei64.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x74,0x45,0x0e]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 07 74 45 0e <unknown>

llvm/test/MC/RISCV/rvv/store.s

Show First 20 Lines • Show All 223 Lines • ▼ Show 20 Lines
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 27 0c 85 62 <unknown> # CHECK-UNKNOWN: 27 0c 85 62 <unknown>
vs8r.v v24, (a0) vs8r.v v24, (a0)
# CHECK-INST: vs8r.v v24, (a0) # CHECK-INST: vs8r.v v24, (a0)
# CHECK-ENCODING: [0x27,0x0c,0x85,0xe2] # CHECK-ENCODING: [0x27,0x0c,0x85,0xe2]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 27 0c 85 e2 <unknown> # CHECK-UNKNOWN: 27 0c 85 e2 <unknown>
vsm.v v24, 0(a0)
# CHECK-INST: vsm.v v24, (a0)
# CHECK-ENCODING: [0x27,0x0c,0xb5,0x02]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 27 0c b5 02 <unknown>
vse8.v v24, 0(a0), v0.t
# CHECK-INST: vse8.v v24, (a0), v0.t
# CHECK-ENCODING: [0x27,0x0c,0x05,0x00]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 27 0c 05 00 <unknown>
vsse16.v v24, 0(a0), a1, v0.t
# CHECK-INST: vsse16.v v24, (a0), a1, v0.t
# CHECK-ENCODING: [0x27,0x5c,0xb5,0x08]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 27 5c b5 08 <unknown>
vsuxei8.v v24, 0(a0), v4, v0.t
# CHECK-INST: vsuxei8.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x0c,0x45,0x04]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 27 0c 45 04 <unknown>
vsoxei32.v v24, 0(a0), v4, v0.t
# CHECK-INST: vsoxei32.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x6c,0x45,0x0c]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 27 6c 45 0c <unknown>

llvm/test/MC/RISCV/rvv/zvlsseg.s

Show First 20 Lines • Show All 3,026 Lines • ▼ Show 20 Lines
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 27 7c 45 ec <unknown> # CHECK-UNKNOWN: 27 7c 45 ec <unknown>
vsoxseg8ei64.v v24, (a0), v4 vsoxseg8ei64.v v24, (a0), v4
# CHECK-INST: vsoxseg8ei64.v v24, (a0), v4 # CHECK-INST: vsoxseg8ei64.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x7c,0x45,0xee] # CHECK-ENCODING: [0x27,0x7c,0x45,0xee]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 27 7c 45 ee <unknown> # CHECK-UNKNOWN: 27 7c 45 ee <unknown>
vlseg2e8.v v8, 0(a0), v0.t
# CHECK-INST: vlseg2e8.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x04,0x05,0x20]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 07 04 05 20 <unknown>
vlseg2e16ff.v v8, 0(a0)
# CHECK-INST: vlseg2e16ff.v v8, (a0)
# CHECK-ENCODING: [0x07,0x54,0x05,0x23]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 07 54 05 23 <unknown>
vlsseg2e8.v v8, 0(a0), a1
# CHECK-INST: vlsseg2e8.v v8, (a0), a1
# CHECK-ENCODING: [0x07,0x04,0xb5,0x2a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 07 04 b5 2a <unknown>
vluxseg3ei16.v v8, 0(a0), v4
# CHECK-INST: vluxseg3ei16.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x54,0x45,0x46]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 07 54 45 46 <unknown>
vloxseg4ei64.v v8, 0(a0), v4, v0.t
# CHECK-INST: vloxseg4ei64.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x74,0x45,0x6c]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 07 74 45 6c <unknown>
vsseg5e32.v v24, 0(a0), v0.t
# CHECK-INST: vsseg5e32.v v24, (a0), v0.t
# CHECK-ENCODING: [0x27,0x6c,0x05,0x80]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 27 6c 05 80 <unknown>
vssseg2e8.v v24, 0(a0), a1, v0.t
# CHECK-INST: vssseg2e8.v v24, (a0), a1, v0.t
# CHECK-ENCODING: [0x27,0x0c,0xb5,0x28]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 27 0c b5 28 <unknown>
vsoxseg7ei16.v v24, 0(a0), v4
# CHECK-INST: vsoxseg7ei16.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x5c,0x45,0xce]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 27 5c 45 ce <unknown>
vsuxseg6ei32.v v24, 0(a0), v4, v0.t
# CHECK-INST: vsuxseg6ei32.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x6c,0x45,0xa4]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 27 6c 45 a4 <unknown>