[AArch64] Peep SELECT_CC patterns that match smin(a,0) and smax(a,0).

[cameron.mcinally]

Summary

GitHub Issue #61767

With a previous patch to canonicalize SPF to min/max intrinsics (a266af721153), we saw a 6% performance regression from our out-of-tree compiler on 372.smithwa.

This patch attempts to recover from the SPF canonicalization by peeping smin(a,0) and smax(a,0) SELECT_CC patterns during AArch64ISelLowering. We'll match the following patterns:

(SELECT_CC setgt, lhs, 0, lhs, 0) -> (BIC lhs, (SRA lhs, typesize-1))
(SELECT_CC setlt, lhs, 0, lhs, 0) -> (AND lhs, (SRA lhs, typesize-1))

Notice that there's some noise in the existing test cases. They haven't been run through update_llc_test_checks.py since the assembly comments for constants have been added. I will update those tests pre-commit if that will help.

[dmgreen]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

8945

Is this checking both operands for zero because they might still be different zeroes?

llvm/test/CodeGen/AArch64/min-max-peep.ll

2 ↗

(On Diff #513275)

CHECK would never match both +cssc base cases, but the CSSC cases should all be the same between global and sdag, from the look of it. Can they share the same prefix and remove CHECK?

[cameron.mcinally]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

8945

I wasn't certain a Constant 0 would share the same SDValue across nodes and already had the ConstantSDNodes from the code above. That was the only motivation. What do you think?

llvm/test/CodeGen/AArch64/min-max-peep.ll

2 ↗

(On Diff #513275)

I'll give that a shot.

I copied this pattern from the existing min-max.ll test, but I now see that it only differs for i8, i16, and vectors. This change is restricted to i32 and i64.

[cameron.mcinally]

Update CSSC checks as requested.

[dmgreen]

Thanks. LGTM

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

8945

It's a little subtle but there is actually two different zeros, depending on whether the constant is opaque or not. I was originally thinking of suggesting the code just checked for RHS == FVal, but the way you have it sounds better.

llvm/test/CodeGen/AArch64/min-max-peep.ll

7 ↗

(On Diff #513363)

I would use "peephole" or "combine", as peeps is not something I've seen elsewhere.

2 ↗

(On Diff #513275)

Looks good thanks. It may be worth adding i8 and i16 sized too. They should get legalized to i32, so should work the same way,

[cameron.mcinally]

"peep" -> "combine" and i8 /i16 tests added. If you see any problems, I'll fix up post-commit. Thanks, David.

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

if (CC == ISD::SETGT && RHSC && RHSC->isAllOnes() && CTVal && CFVal &&
         LHS.getValueType() == TVal.getValueType()) {
       EVT VT = LHS.getValueType();
       SDValue Shift =
           DAG.getNode(ISD::SRA, dl, VT, LHS,
                       DAG.getConstant(VT.getSizeInBits() - 1, dl, VT));
       return DAG.getNode(ISD::OR, dl, VT, Shift, DAG.getConstant(1, dl, VT));
     }
 
+    // Check for SMAX(lhs, 0) and SMIN(lhs, 0) patterns.
+    // (SELECT_CC setgt, lhs, 0, lhs, 0) -> (BIC lhs, (SRA lhs, typesize-1))
+    // (SELECT_CC setlt, lhs, 0, lhs, 0) -> (AND lhs, (SRA lhs, typesize-1))
+    // Both require less instructions than compare and conditional select.
+    if ((CC == ISD::SETGT || CC == ISD::SETLT) && LHS == TVal &&
+        RHSC && RHSC->isZero() && CFVal && CFVal->isZero() &&
+        LHS.getValueType() == RHS.getValueType()) {
+      EVT VT = LHS.getValueType();
+      SDValue Shift =
+          DAG.getNode(ISD::SRA, dl, VT, LHS,
+                      DAG.getConstant(VT.getSizeInBits() - 1, dl, VT));
+
+      if (CC == ISD::SETGT)
+        Shift = DAG.getNOT(dl, Shift, VT);
+
+      return DAG.getNode(ISD::AND, dl, VT, LHS, Shift);
+    }
+
     unsigned Opcode = AArch64ISD::CSEL;
 
     // If both the TVal and the FVal are constants, see if we can swap them in
     // order to for a CSINV or CSINC out of them.
     if (CTVal && CFVal && CTVal->isAllOnes() && CFVal->isZero()) {
       std::swap(TVal, FVal);
       std::swap(CTVal, CFVal);
       CC = ISD::getSetCCInverse(CC, LHS.getValueType());

llvm/test/CodeGen/AArch64/fpclamptosat.ll

 }
 
 ; i16 saturate
 
 define i16 @stest_f64i16(double %x) {
 ; CHECK-LABEL: stest_f64i16:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    fcvtzs w8, d0
-; CHECK-NEXT:    mov w9, #32767
+; CHECK-NEXT:    mov w9, #32767 // =0x7fff
 ; CHECK-NEXT:    cmp w8, w9
 ; CHECK-NEXT:    csel w8, w8, w9, lt
-; CHECK-NEXT:    mov w9, #-32768
+; CHECK-NEXT:    mov w9, #-32768 // =0xffff8000
 ; CHECK-NEXT:    cmn w8, #8, lsl #12 // =32768
 ; CHECK-NEXT:    csel w0, w8, w9, gt
 ; CHECK-NEXT:    ret
 entry:
   %conv = fptosi double %x to i32
   %0 = icmp slt i32 %conv, 32767
   %spec.store.select = select i1 %0, i32 %conv, i32 32767
   %1 = icmp sgt i32 %spec.store.select, -32768
   %spec.store.select7 = select i1 %1, i32 %spec.store.select, i32 -32768
   %conv6 = trunc i32 %spec.store.select7 to i16
   ret i16 %conv6
 }
 
 define i16 @utest_f64i16(double %x) {
 ; CHECK-LABEL: utest_f64i16:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    fcvtzu w8, d0
-; CHECK-NEXT:    mov w9, #65535
+; CHECK-NEXT:    mov w9, #65535 // =0xffff
 ; CHECK-NEXT:    cmp w8, w9
 ; CHECK-NEXT:    csel w0, w8, w9, lo
 ; CHECK-NEXT:    ret
 entry:
   %conv = fptoui double %x to i32
   %0 = icmp ult i32 %conv, 65535
   %spec.store.select = select i1 %0, i32 %conv, i32 65535
   %conv6 = trunc i32 %spec.store.select to i16
   ret i16 %conv6
 }
 
 define i16 @ustest_f64i16(double %x) {
 ; CHECK-LABEL: ustest_f64i16:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    fcvtzs w8, d0
-; CHECK-NEXT:    mov w9, #65535
+; CHECK-NEXT:    mov w9, #65535 // =0xffff
 ; CHECK-NEXT:    cmp w8, w9
 ; CHECK-NEXT:    csel w8, w8, w9, lt
 ; CHECK-NEXT:    bic w0, w8, w8, asr #31
 ; CHECK-NEXT:    ret
 entry:
   %conv = fptosi double %x to i32
   %0 = icmp slt i32 %conv, 65535
   %spec.store.select = select i1 %0, i32 %conv, i32 65535
   %1 = icmp sgt i32 %spec.store.select, 0
   %spec.store.select7 = select i1 %1, i32 %spec.store.select, i32 0
   %conv6 = trunc i32 %spec.store.select7 to i16
   ret i16 %conv6
 }
 
 define i16 @stest_f32i16(float %x) {
 ; CHECK-LABEL: stest_f32i16:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    mov w9, #32767
+; CHECK-NEXT:    mov w9, #32767 // =0x7fff
 ; CHECK-NEXT:    cmp w8, w9
 ; CHECK-NEXT:    csel w8, w8, w9, lt
-; CHECK-NEXT:    mov w9, #-32768
+; CHECK-NEXT:    mov w9, #-32768 // =0xffff8000
 ; CHECK-NEXT:    cmn w8, #8, lsl #12 // =32768
 ; CHECK-NEXT:    csel w0, w8, w9, gt
 ; CHECK-NEXT:    ret
 entry:
   %conv = fptosi float %x to i32
   %0 = icmp slt i32 %conv, 32767
   %spec.store.select = select i1 %0, i32 %conv, i32 32767
   %1 = icmp sgt i32 %spec.store.select, -32768
   %spec.store.select7 = select i1 %1, i32 %spec.store.select, i32 -32768
   %conv6 = trunc i32 %spec.store.select7 to i16
   ret i16 %conv6
 }
 
 define i16 @utest_f32i16(float %x) {
 ; CHECK-LABEL: utest_f32i16:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    fcvtzu w8, s0
-; CHECK-NEXT:    mov w9, #65535
+; CHECK-NEXT:    mov w9, #65535 // =0xffff
 ; CHECK-NEXT:    cmp w8, w9
 ; CHECK-NEXT:    csel w0, w8, w9, lo
 ; CHECK-NEXT:    ret
 entry:
   %conv = fptoui float %x to i32
   %0 = icmp ult i32 %conv, 65535
   %spec.store.select = select i1 %0, i32 %conv, i32 65535
   %conv6 = trunc i32 %spec.store.select to i16
   ret i16 %conv6
 }
 
 define i16 @ustest_f32i16(float %x) {
 ; CHECK-LABEL: ustest_f32i16:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    mov w9, #65535
+; CHECK-NEXT:    mov w9, #65535 // =0xffff
 ; CHECK-NEXT:    cmp w8, w9
 ; CHECK-NEXT:    csel w8, w8, w9, lt
 ; CHECK-NEXT:    bic w0, w8, w8, asr #31
 ; CHECK-NEXT:    ret
 entry:
   %conv = fptosi float %x to i32
   %0 = icmp slt i32 %conv, 65535
   %spec.store.select = select i1 %0, i32 %conv, i32 65535
   %1 = icmp sgt i32 %spec.store.select, 0
   %spec.store.select7 = select i1 %1, i32 %spec.store.select, i32 0
   %conv6 = trunc i32 %spec.store.select7 to i16
   ret i16 %conv6
 }
 
 define i16 @stest_f16i16(half %x) {
 ; CHECK-CVT-LABEL: stest_f16i16:
 ; CHECK-CVT:       // %bb.0: // %entry
 ; CHECK-CVT-NEXT:    fcvt s0, h0
-; CHECK-CVT-NEXT:    mov w9, #32767
+; CHECK-CVT-NEXT:    mov w9, #32767 // =0x7fff
 ; CHECK-CVT-NEXT:    fcvtzs w8, s0
 ; CHECK-CVT-NEXT:    cmp w8, w9
 ; CHECK-CVT-NEXT:    csel w8, w8, w9, lt
-; CHECK-CVT-NEXT:    mov w9, #-32768
+; CHECK-CVT-NEXT:    mov w9, #-32768 // =0xffff8000
 ; CHECK-CVT-NEXT:    cmn w8, #8, lsl #12 // =32768
 ; CHECK-CVT-NEXT:    csel w0, w8, w9, gt
 ; CHECK-CVT-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: stest_f16i16:
 ; CHECK-FP16:       // %bb.0: // %entry
 ; CHECK-FP16-NEXT:    fcvtzs w8, h0
-; CHECK-FP16-NEXT:    mov w9, #32767
+; CHECK-FP16-NEXT:    mov w9, #32767 // =0x7fff
 ; CHECK-FP16-NEXT:    cmp w8, w9
 ; CHECK-FP16-NEXT:    csel w8, w8, w9, lt
-; CHECK-FP16-NEXT:    mov w9, #-32768
+; CHECK-FP16-NEXT:    mov w9, #-32768 // =0xffff8000
 ; CHECK-FP16-NEXT:    cmn w8, #8, lsl #12 // =32768
 ; CHECK-FP16-NEXT:    csel w0, w8, w9, gt
 ; CHECK-FP16-NEXT:    ret
 entry:
   %conv = fptosi half %x to i32
   %0 = icmp slt i32 %conv, 32767
   %spec.store.select = select i1 %0, i32 %conv, i32 32767
   %1 = icmp sgt i32 %spec.store.select, -32768
   %spec.store.select7 = select i1 %1, i32 %spec.store.select, i32 -32768
   %conv6 = trunc i32 %spec.store.select7 to i16
   ret i16 %conv6
 }
 
 define i16 @utesth_f16i16(half %x) {
 ; CHECK-CVT-LABEL: utesth_f16i16:
 ; CHECK-CVT:       // %bb.0: // %entry
 ; CHECK-CVT-NEXT:    fcvt s0, h0
-; CHECK-CVT-NEXT:    mov w9, #65535
+; CHECK-CVT-NEXT:    mov w9, #65535 // =0xffff
 ; CHECK-CVT-NEXT:    fcvtzu w8, s0
 ; CHECK-CVT-NEXT:    cmp w8, w9
 ; CHECK-CVT-NEXT:    csel w0, w8, w9, lo
 ; CHECK-CVT-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: utesth_f16i16:
 ; CHECK-FP16:       // %bb.0: // %entry
 ; CHECK-FP16-NEXT:    fcvtzu w8, h0
-; CHECK-FP16-NEXT:    mov w9, #65535
+; CHECK-FP16-NEXT:    mov w9, #65535 // =0xffff
 ; CHECK-FP16-NEXT:    cmp w8, w9
 ; CHECK-FP16-NEXT:    csel w0, w8, w9, lo
 ; CHECK-FP16-NEXT:    ret
 entry:
   %conv = fptoui half %x to i32
   %0 = icmp ult i32 %conv, 65535
   %spec.store.select = select i1 %0, i32 %conv, i32 65535
   %conv6 = trunc i32 %spec.store.select to i16
   ret i16 %conv6
 }
 
 define i16 @ustest_f16i16(half %x) {
 ; CHECK-CVT-LABEL: ustest_f16i16:
 ; CHECK-CVT:       // %bb.0: // %entry
 ; CHECK-CVT-NEXT:    fcvt s0, h0
-; CHECK-CVT-NEXT:    mov w9, #65535
+; CHECK-CVT-NEXT:    mov w9, #65535 // =0xffff
 ; CHECK-CVT-NEXT:    fcvtzs w8, s0
 ; CHECK-CVT-NEXT:    cmp w8, w9
 ; CHECK-CVT-NEXT:    csel w8, w8, w9, lt
 ; CHECK-CVT-NEXT:    bic w0, w8, w8, asr #31
 ; CHECK-CVT-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: ustest_f16i16:
 ; CHECK-FP16:       // %bb.0: // %entry
 ; CHECK-FP16-NEXT:    fcvtzs w8, h0
-; CHECK-FP16-NEXT:    mov w9, #65535
+; CHECK-FP16-NEXT:    mov w9, #65535 // =0xffff
 ; CHECK-FP16-NEXT:    cmp w8, w9
 ; CHECK-FP16-NEXT:    csel w8, w8, w9, lt
 ; CHECK-FP16-NEXT:    bic w0, w8, w8, asr #31
 ; CHECK-FP16-NEXT:    ret
 entry:
   %conv = fptosi half %x to i32
   %0 = icmp slt i32 %conv, 65535
   %spec.store.select = select i1 %0, i32 %conv, i32 65535

 }
 
 ; i16 saturate
 
 define i16 @stest_f64i16_mm(double %x) {
 ; CHECK-LABEL: stest_f64i16_mm:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    fcvtzs w8, d0
-; CHECK-NEXT:    mov w9, #32767
+; CHECK-NEXT:    mov w9, #32767 // =0x7fff
 ; CHECK-NEXT:    cmp w8, w9
 ; CHECK-NEXT:    csel w8, w8, w9, lt
-; CHECK-NEXT:    mov w9, #-32768
+; CHECK-NEXT:    mov w9, #-32768 // =0xffff8000
 ; CHECK-NEXT:    cmn w8, #8, lsl #12 // =32768
 ; CHECK-NEXT:    csel w0, w8, w9, gt
 ; CHECK-NEXT:    ret
 entry:
   %conv = fptosi double %x to i32
   %spec.store.select = call i32 @llvm.smin.i32(i32 %conv, i32 32767)
   %spec.store.select7 = call i32 @llvm.smax.i32(i32 %spec.store.select, i32 -32768)
   %conv6 = trunc i32 %spec.store.select7 to i16
   ret i16 %conv6
 }
 
 define i16 @utest_f64i16_mm(double %x) {
 ; CHECK-LABEL: utest_f64i16_mm:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    fcvtzu w8, d0
-; CHECK-NEXT:    mov w9, #65535
+; CHECK-NEXT:    mov w9, #65535 // =0xffff
 ; CHECK-NEXT:    cmp w8, w9
 ; CHECK-NEXT:    csel w0, w8, w9, lo
 ; CHECK-NEXT:    ret
 entry:
   %conv = fptoui double %x to i32
   %spec.store.select = call i32 @llvm.umin.i32(i32 %conv, i32 65535)
   %conv6 = trunc i32 %spec.store.select to i16
   ret i16 %conv6
 }
 
 define i16 @ustest_f64i16_mm(double %x) {
 ; CHECK-LABEL: ustest_f64i16_mm:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    fcvtzs w8, d0
-; CHECK-NEXT:    mov w9, #65535
+; CHECK-NEXT:    mov w9, #65535 // =0xffff
 ; CHECK-NEXT:    cmp w8, w9
 ; CHECK-NEXT:    csel w8, w8, w9, lt
-; CHECK-NEXT:    cmp w8, #0
-; CHECK-NEXT:    csel w0, w8, wzr, gt
+; CHECK-NEXT:    bic w0, w8, w8, asr #31
 ; CHECK-NEXT:    ret
 entry:
   %conv = fptosi double %x to i32
   %spec.store.select = call i32 @llvm.smin.i32(i32 %conv, i32 65535)
   %spec.store.select7 = call i32 @llvm.smax.i32(i32 %spec.store.select, i32 0)
   %conv6 = trunc i32 %spec.store.select7 to i16
   ret i16 %conv6
 }
 
 define i16 @stest_f32i16_mm(float %x) {
 ; CHECK-LABEL: stest_f32i16_mm:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    mov w9, #32767
+; CHECK-NEXT:    mov w9, #32767 // =0x7fff
 ; CHECK-NEXT:    cmp w8, w9
 ; CHECK-NEXT:    csel w8, w8, w9, lt
-; CHECK-NEXT:    mov w9, #-32768
+; CHECK-NEXT:    mov w9, #-32768 // =0xffff8000
 ; CHECK-NEXT:    cmn w8, #8, lsl #12 // =32768
 ; CHECK-NEXT:    csel w0, w8, w9, gt
 ; CHECK-NEXT:    ret
 entry:
   %conv = fptosi float %x to i32
   %spec.store.select = call i32 @llvm.smin.i32(i32 %conv, i32 32767)
   %spec.store.select7 = call i32 @llvm.smax.i32(i32 %spec.store.select, i32 -32768)
   %conv6 = trunc i32 %spec.store.select7 to i16
   ret i16 %conv6
 }
 
 define i16 @utest_f32i16_mm(float %x) {
 ; CHECK-LABEL: utest_f32i16_mm:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    fcvtzu w8, s0
-; CHECK-NEXT:    mov w9, #65535
+; CHECK-NEXT:    mov w9, #65535 // =0xffff
 ; CHECK-NEXT:    cmp w8, w9
 ; CHECK-NEXT:    csel w0, w8, w9, lo
 ; CHECK-NEXT:    ret
 entry:
   %conv = fptoui float %x to i32
   %spec.store.select = call i32 @llvm.umin.i32(i32 %conv, i32 65535)
   %conv6 = trunc i32 %spec.store.select to i16
   ret i16 %conv6
 }
 
 define i16 @ustest_f32i16_mm(float %x) {
 ; CHECK-LABEL: ustest_f32i16_mm:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    mov w9, #65535
+; CHECK-NEXT:    mov w9, #65535 // =0xffff
 ; CHECK-NEXT:    cmp w8, w9
 ; CHECK-NEXT:    csel w8, w8, w9, lt
-; CHECK-NEXT:    cmp w8, #0
-; CHECK-NEXT:    csel w0, w8, wzr, gt
+; CHECK-NEXT:    bic w0, w8, w8, asr #31
 ; CHECK-NEXT:    ret
 entry:
   %conv = fptosi float %x to i32
   %spec.store.select = call i32 @llvm.smin.i32(i32 %conv, i32 65535)
   %spec.store.select7 = call i32 @llvm.smax.i32(i32 %spec.store.select, i32 0)
   %conv6 = trunc i32 %spec.store.select7 to i16
   ret i16 %conv6
 }
 
 define i16 @stest_f16i16_mm(half %x) {
 ; CHECK-CVT-LABEL: stest_f16i16_mm:
 ; CHECK-CVT:       // %bb.0: // %entry
 ; CHECK-CVT-NEXT:    fcvt s0, h0
-; CHECK-CVT-NEXT:    mov w9, #32767
+; CHECK-CVT-NEXT:    mov w9, #32767 // =0x7fff
 ; CHECK-CVT-NEXT:    fcvtzs w8, s0
 ; CHECK-CVT-NEXT:    cmp w8, w9
 ; CHECK-CVT-NEXT:    csel w8, w8, w9, lt
-; CHECK-CVT-NEXT:    mov w9, #-32768
+; CHECK-CVT-NEXT:    mov w9, #-32768 // =0xffff8000
 ; CHECK-CVT-NEXT:    cmn w8, #8, lsl #12 // =32768
 ; CHECK-CVT-NEXT:    csel w0, w8, w9, gt
 ; CHECK-CVT-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: stest_f16i16_mm:
 ; CHECK-FP16:       // %bb.0: // %entry
 ; CHECK-FP16-NEXT:    fcvtzs w8, h0
-; CHECK-FP16-NEXT:    mov w9, #32767
+; CHECK-FP16-NEXT:    mov w9, #32767 // =0x7fff
 ; CHECK-FP16-NEXT:    cmp w8, w9
 ; CHECK-FP16-NEXT:    csel w8, w8, w9, lt
-; CHECK-FP16-NEXT:    mov w9, #-32768
+; CHECK-FP16-NEXT:    mov w9, #-32768 // =0xffff8000
 ; CHECK-FP16-NEXT:    cmn w8, #8, lsl #12 // =32768
 ; CHECK-FP16-NEXT:    csel w0, w8, w9, gt
 ; CHECK-FP16-NEXT:    ret
 entry:
   %conv = fptosi half %x to i32
   %spec.store.select = call i32 @llvm.smin.i32(i32 %conv, i32 32767)
   %spec.store.select7 = call i32 @llvm.smax.i32(i32 %spec.store.select, i32 -32768)
   %conv6 = trunc i32 %spec.store.select7 to i16
   ret i16 %conv6
 }
 
 define i16 @utesth_f16i16_mm(half %x) {
 ; CHECK-CVT-LABEL: utesth_f16i16_mm:
 ; CHECK-CVT:       // %bb.0: // %entry
 ; CHECK-CVT-NEXT:    fcvt s0, h0
-; CHECK-CVT-NEXT:    mov w9, #65535
+; CHECK-CVT-NEXT:    mov w9, #65535 // =0xffff
 ; CHECK-CVT-NEXT:    fcvtzu w8, s0
 ; CHECK-CVT-NEXT:    cmp w8, w9
 ; CHECK-CVT-NEXT:    csel w0, w8, w9, lo
 ; CHECK-CVT-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: utesth_f16i16_mm:
 ; CHECK-FP16:       // %bb.0: // %entry
 ; CHECK-FP16-NEXT:    fcvtzu w8, h0
-; CHECK-FP16-NEXT:    mov w9, #65535
+; CHECK-FP16-NEXT:    mov w9, #65535 // =0xffff
 ; CHECK-FP16-NEXT:    cmp w8, w9
 ; CHECK-FP16-NEXT:    csel w0, w8, w9, lo
 ; CHECK-FP16-NEXT:    ret
 entry:
   %conv = fptoui half %x to i32
   %spec.store.select = call i32 @llvm.umin.i32(i32 %conv, i32 65535)
   %conv6 = trunc i32 %spec.store.select to i16
   ret i16 %conv6
 }
 
 define i16 @ustest_f16i16_mm(half %x) {
 ; CHECK-CVT-LABEL: ustest_f16i16_mm:
 ; CHECK-CVT:       // %bb.0: // %entry
 ; CHECK-CVT-NEXT:    fcvt s0, h0
-; CHECK-CVT-NEXT:    mov w9, #65535
+; CHECK-CVT-NEXT:    mov w9, #65535 // =0xffff
 ; CHECK-CVT-NEXT:    fcvtzs w8, s0
 ; CHECK-CVT-NEXT:    cmp w8, w9
 ; CHECK-CVT-NEXT:    csel w8, w8, w9, lt
-; CHECK-CVT-NEXT:    cmp w8, #0
-; CHECK-CVT-NEXT:    csel w0, w8, wzr, gt
+; CHECK-CVT-NEXT:    bic w0, w8, w8, asr #31
 ; CHECK-CVT-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: ustest_f16i16_mm:
 ; CHECK-FP16:       // %bb.0: // %entry
 ; CHECK-FP16-NEXT:    fcvtzs w8, h0
-; CHECK-FP16-NEXT:    mov w9, #65535
+; CHECK-FP16-NEXT:    mov w9, #65535 // =0xffff
 ; CHECK-FP16-NEXT:    cmp w8, w9
 ; CHECK-FP16-NEXT:    csel w8, w8, w9, lt
-; CHECK-FP16-NEXT:    cmp w8, #0
-; CHECK-FP16-NEXT:    csel w0, w8, wzr, gt
+; CHECK-FP16-NEXT:    bic w0, w8, w8, asr #31
 ; CHECK-FP16-NEXT:    ret
 entry:
   %conv = fptosi half %x to i32
   %spec.store.select = call i32 @llvm.smin.i32(i32 %conv, i32 65535)
   %spec.store.select7 = call i32 @llvm.smax.i32(i32 %spec.store.select, i32 0)
   %conv6 = trunc i32 %spec.store.select7 to i16
   ret i16 %conv6
 }

llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll

 declare  i64 @llvm.fptosi.sat.i64.f32 (float)
 declare i100 @llvm.fptosi.sat.i100.f32(float)
 declare i128 @llvm.fptosi.sat.i128.f32(float)
 
 define i1 @test_signed_i1_f32(float %f) nounwind {
 ; CHECK-LABEL: test_signed_i1_f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    cmp w8, #0
-; CHECK-NEXT:    csel w8, w8, wzr, lt
-; CHECK-NEXT:    cmp w8, #0
+; CHECK-NEXT:    ands w8, w8, w8, asr #31
 ; CHECK-NEXT:    csinv w8, w8, wzr, ge
 ; CHECK-NEXT:    and w0, w8, #0x1
 ; CHECK-NEXT:    ret
     %x = call i1 @llvm.fptosi.sat.i1.f32(float %f)
     ret i1 %x
 }
 
 define i8 @test_signed_i8_f32(float %f) nounwind {
 ; CHECK-LABEL: test_signed_i8_f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs w9, s0
-; CHECK-NEXT:    mov w8, #127
+; CHECK-NEXT:    mov w8, #127 // =0x7f
 ; CHECK-NEXT:    cmp w9, #127
 ; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    mov w9, #-128
+; CHECK-NEXT:    mov w9, #-128 // =0xffffff80
 ; CHECK-NEXT:    cmn w8, #128
 ; CHECK-NEXT:    csel w0, w8, w9, gt
 ; CHECK-NEXT:    ret
     %x = call i8 @llvm.fptosi.sat.i8.f32(float %f)
     ret i8 %x
 }
 
 define i13 @test_signed_i13_f32(float %f) nounwind {
 ; CHECK-LABEL: test_signed_i13_f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs w9, s0
-; CHECK-NEXT:    mov w8, #4095
+; CHECK-NEXT:    mov w8, #4095 // =0xfff
 ; CHECK-NEXT:    cmp w9, #4095
 ; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    mov w9, #-4096
+; CHECK-NEXT:    mov w9, #-4096 // =0xfffff000
 ; CHECK-NEXT:    cmn w8, #1, lsl #12 // =4096
 ; CHECK-NEXT:    csel w0, w8, w9, gt
 ; CHECK-NEXT:    ret
     %x = call i13 @llvm.fptosi.sat.i13.f32(float %f)
     ret i13 %x
 }
 
 define i16 @test_signed_i16_f32(float %f) nounwind {
 ; CHECK-LABEL: test_signed_i16_f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    mov w9, #32767
+; CHECK-NEXT:    mov w9, #32767 // =0x7fff
 ; CHECK-NEXT:    cmp w8, w9
 ; CHECK-NEXT:    csel w8, w8, w9, lt
-; CHECK-NEXT:    mov w9, #-32768
+; CHECK-NEXT:    mov w9, #-32768 // =0xffff8000
 ; CHECK-NEXT:    cmn w8, #8, lsl #12 // =32768
 ; CHECK-NEXT:    csel w0, w8, w9, gt
 ; CHECK-NEXT:    ret
     %x = call i16 @llvm.fptosi.sat.i16.f32(float %f)
     ret i16 %x
 }
 
 define i19 @test_signed_i19_f32(float %f) nounwind {
 ; CHECK-LABEL: test_signed_i19_f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    mov w9, #262143
+; CHECK-NEXT:    mov w9, #262143 // =0x3ffff
 ; CHECK-NEXT:    cmp w8, w9
 ; CHECK-NEXT:    csel w8, w8, w9, lt
-; CHECK-NEXT:    mov w9, #-262144
+; CHECK-NEXT:    mov w9, #-262144 // =0xfffc0000
 ; CHECK-NEXT:    cmn w8, #64, lsl #12 // =262144
 ; CHECK-NEXT:    csel w0, w8, w9, gt
 ; CHECK-NEXT:    ret
     %x = call i19 @llvm.fptosi.sat.i19.f32(float %f)
     ret i19 %x
 }
 
 define i32 @test_signed_i32_f32(float %f) nounwind {
 ; CHECK-LABEL: test_signed_i32_f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs w0, s0
 ; CHECK-NEXT:    ret
     %x = call i32 @llvm.fptosi.sat.i32.f32(float %f)
     ret i32 %x
 }
 
 define i50 @test_signed_i50_f32(float %f) nounwind {
 ; CHECK-LABEL: test_signed_i50_f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs x8, s0
-; CHECK-NEXT:    mov x9, #562949953421311
+; CHECK-NEXT:    mov x9, #562949953421311 // =0x1ffffffffffff
 ; CHECK-NEXT:    cmp x8, x9
 ; CHECK-NEXT:    csel x8, x8, x9, lt
-; CHECK-NEXT:    mov x9, #-562949953421312
+; CHECK-NEXT:    mov x9, #-562949953421312 // =0xfffe000000000000
 ; CHECK-NEXT:    cmp x8, x9
 ; CHECK-NEXT:    csel x0, x8, x9, gt
 ; CHECK-NEXT:    ret
     %x = call i50 @llvm.fptosi.sat.i50.f32(float %f)
     ret i50 %x
 }
 
 define i64 @test_signed_i64_f32(float %f) nounwind {
 ; CHECK-LABEL: test_signed_i64_f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs x0, s0
 ; CHECK-NEXT:    ret
     %x = call i64 @llvm.fptosi.sat.i64.f32(float %f)
     ret i64 %x
 }
 
 define i100 @test_signed_i100_f32(float %f) nounwind {
 ; CHECK-LABEL: test_signed_i100_f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str d8, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    str x30, [sp, #8] // 8-byte Folded Spill
 ; CHECK-NEXT:    fmov s8, s0
 ; CHECK-NEXT:    bl __fixsfti
 ; CHECK-NEXT:    movi v0.2s, #241, lsl #24
-; CHECK-NEXT:    mov w8, #1895825407
-; CHECK-NEXT:    mov x10, #34359738367
+; CHECK-NEXT:    mov w8, #1895825407 // =0x70ffffff
+; CHECK-NEXT:    mov x10, #34359738367 // =0x7ffffffff
 ; CHECK-NEXT:    ldr x30, [sp, #8] // 8-byte Folded Reload
 ; CHECK-NEXT:    fcmp s8, s0
 ; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    mov x8, #-34359738368
+; CHECK-NEXT:    mov x8, #-34359738368 // =0xfffffff800000000
 ; CHECK-NEXT:    csel x9, xzr, x0, lt
 ; CHECK-NEXT:    csel x8, x8, x1, lt
 ; CHECK-NEXT:    fcmp s8, s0
 ; CHECK-NEXT:    csel x8, x10, x8, gt
 ; CHECK-NEXT:    csinv x9, x9, xzr, le
 ; CHECK-NEXT:    fcmp s8, s8
 ; CHECK-NEXT:    csel x0, xzr, x9, vs
 ; CHECK-NEXT:    csel x1, xzr, x8, vs
 ; CHECK-NEXT:    ldr d8, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
     %x = call i100 @llvm.fptosi.sat.i100.f32(float %f)
     ret i100 %x
 }
 
 define i128 @test_signed_i128_f32(float %f) nounwind {
 ; CHECK-LABEL: test_signed_i128_f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str d8, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    str x30, [sp, #8] // 8-byte Folded Spill
 ; CHECK-NEXT:    fmov s8, s0
 ; CHECK-NEXT:    bl __fixsfti
 ; CHECK-NEXT:    movi v0.2s, #255, lsl #24
-; CHECK-NEXT:    mov w8, #2130706431
-; CHECK-NEXT:    mov x10, #9223372036854775807
+; CHECK-NEXT:    mov w8, #2130706431 // =0x7effffff
+; CHECK-NEXT:    mov x10, #9223372036854775807 // =0x7fffffffffffffff
 ; CHECK-NEXT:    ldr x30, [sp, #8] // 8-byte Folded Reload
 ; CHECK-NEXT:    fcmp s8, s0
 ; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    mov x8, #-9223372036854775808
+; CHECK-NEXT:    mov x8, #-9223372036854775808 // =0x8000000000000000
 ; CHECK-NEXT:    csel x9, xzr, x0, lt
 ; CHECK-NEXT:    csel x8, x8, x1, lt
 ; CHECK-NEXT:    fcmp s8, s0
 ; CHECK-NEXT:    csel x8, x10, x8, gt
 ; CHECK-NEXT:    csinv x9, x9, xzr, le
 ; CHECK-NEXT:    fcmp s8, s8
 ; CHECK-NEXT:    csel x0, xzr, x9, vs
 ; CHECK-NEXT:    csel x1, xzr, x8, vs

 declare  i64 @llvm.fptosi.sat.i64.f64 (double)
 declare i100 @llvm.fptosi.sat.i100.f64(double)
 declare i128 @llvm.fptosi.sat.i128.f64(double)
 
 define i1 @test_signed_i1_f64(double %f) nounwind {
 ; CHECK-LABEL: test_signed_i1_f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs w8, d0
-; CHECK-NEXT:    cmp w8, #0
-; CHECK-NEXT:    csel w8, w8, wzr, lt
-; CHECK-NEXT:    cmp w8, #0
+; CHECK-NEXT:    ands w8, w8, w8, asr #31
 ; CHECK-NEXT:    csinv w8, w8, wzr, ge
 ; CHECK-NEXT:    and w0, w8, #0x1
 ; CHECK-NEXT:    ret
     %x = call i1 @llvm.fptosi.sat.i1.f64(double %f)
     ret i1 %x
 }
 
 define i8 @test_signed_i8_f64(double %f) nounwind {
 ; CHECK-LABEL: test_signed_i8_f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs w9, d0
-; CHECK-NEXT:    mov w8, #127
+; CHECK-NEXT:    mov w8, #127 // =0x7f
 ; CHECK-NEXT:    cmp w9, #127
 ; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    mov w9, #-128
+; CHECK-NEXT:    mov w9, #-128 // =0xffffff80
 ; CHECK-NEXT:    cmn w8, #128
 ; CHECK-NEXT:    csel w0, w8, w9, gt
 ; CHECK-NEXT:    ret
     %x = call i8 @llvm.fptosi.sat.i8.f64(double %f)
     ret i8 %x
 }
 
 define i13 @test_signed_i13_f64(double %f) nounwind {
 ; CHECK-LABEL: test_signed_i13_f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs w9, d0
-; CHECK-NEXT:    mov w8, #4095
+; CHECK-NEXT:    mov w8, #4095 // =0xfff
 ; CHECK-NEXT:    cmp w9, #4095
 ; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    mov w9, #-4096
+; CHECK-NEXT:    mov w9, #-4096 // =0xfffff000
 ; CHECK-NEXT:    cmn w8, #1, lsl #12 // =4096
 ; CHECK-NEXT:    csel w0, w8, w9, gt
 ; CHECK-NEXT:    ret
     %x = call i13 @llvm.fptosi.sat.i13.f64(double %f)
     ret i13 %x
 }
 
 define i16 @test_signed_i16_f64(double %f) nounwind {
 ; CHECK-LABEL: test_signed_i16_f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs w8, d0
-; CHECK-NEXT:    mov w9, #32767
+; CHECK-NEXT:    mov w9, #32767 // =0x7fff
 ; CHECK-NEXT:    cmp w8, w9
 ; CHECK-NEXT:    csel w8, w8, w9, lt
-; CHECK-NEXT:    mov w9, #-32768
+; CHECK-NEXT:    mov w9, #-32768 // =0xffff8000
 ; CHECK-NEXT:    cmn w8, #8, lsl #12 // =32768
 ; CHECK-NEXT:    csel w0, w8, w9, gt
 ; CHECK-NEXT:    ret
     %x = call i16 @llvm.fptosi.sat.i16.f64(double %f)
     ret i16 %x
 }
 
 define i19 @test_signed_i19_f64(double %f) nounwind {
 ; CHECK-LABEL: test_signed_i19_f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs w8, d0
-; CHECK-NEXT:    mov w9, #262143
+; CHECK-NEXT:    mov w9, #262143 // =0x3ffff
 ; CHECK-NEXT:    cmp w8, w9
 ; CHECK-NEXT:    csel w8, w8, w9, lt
-; CHECK-NEXT:    mov w9, #-262144
+; CHECK-NEXT:    mov w9, #-262144 // =0xfffc0000
 ; CHECK-NEXT:    cmn w8, #64, lsl #12 // =262144
 ; CHECK-NEXT:    csel w0, w8, w9, gt
 ; CHECK-NEXT:    ret
     %x = call i19 @llvm.fptosi.sat.i19.f64(double %f)
     ret i19 %x
 }
 
 define i32 @test_signed_i32_f64(double %f) nounwind {
 ; CHECK-LABEL: test_signed_i32_f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs w0, d0
 ; CHECK-NEXT:    ret
     %x = call i32 @llvm.fptosi.sat.i32.f64(double %f)
     ret i32 %x
 }
 
 define i50 @test_signed_i50_f64(double %f) nounwind {
 ; CHECK-LABEL: test_signed_i50_f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs x8, d0
-; CHECK-NEXT:    mov x9, #562949953421311
+; CHECK-NEXT:    mov x9, #562949953421311 // =0x1ffffffffffff
 ; CHECK-NEXT:    cmp x8, x9
 ; CHECK-NEXT:    csel x8, x8, x9, lt
-; CHECK-NEXT:    mov x9, #-562949953421312
+; CHECK-NEXT:    mov x9, #-562949953421312 // =0xfffe000000000000
 ; CHECK-NEXT:    cmp x8, x9
 ; CHECK-NEXT:    csel x0, x8, x9, gt
 ; CHECK-NEXT:    ret
     %x = call i50 @llvm.fptosi.sat.i50.f64(double %f)
     ret i50 %x
 }
 
 define i64 @test_signed_i64_f64(double %f) nounwind {
 ; CHECK-LABEL: test_signed_i64_f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtzs x0, d0
 ; CHECK-NEXT:    ret
     %x = call i64 @llvm.fptosi.sat.i64.f64(double %f)
     ret i64 %x
 }
 
 define i100 @test_signed_i100_f64(double %f) nounwind {
 ; CHECK-LABEL: test_signed_i100_f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str d8, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    str x30, [sp, #8] // 8-byte Folded Spill
 ; CHECK-NEXT:    fmov d8, d0
 ; CHECK-NEXT:    bl __fixdfti
-; CHECK-NEXT:    mov x8, #-4170333254945079296
-; CHECK-NEXT:    mov x10, #34359738367
+; CHECK-NEXT:    mov x8, #-4170333254945079296 // =0xc620000000000000
+; CHECK-NEXT:    mov x10, #34359738367 // =0x7ffffffff
 ; CHECK-NEXT:    ldr x30, [sp, #8] // 8-byte Folded Reload
 ; CHECK-NEXT:    fmov d0, x8
-; CHECK-NEXT:    mov x8, #5053038781909696511
+; CHECK-NEXT:    mov x8, #5053038781909696511 // =0x461fffffffffffff
 ; CHECK-NEXT:    fcmp d8, d0
 ; CHECK-NEXT:    fmov d0, x8
-; CHECK-NEXT:    mov x8, #-34359738368
+; CHECK-NEXT:    mov x8, #-34359738368 // =0xfffffff800000000
 ; CHECK-NEXT:    csel x9, xzr, x0, lt
 ; CHECK-NEXT:    csel x8, x8, x1, lt
 ; CHECK-NEXT:    fcmp d8, d0
 ; CHECK-NEXT:    csel x8, x10, x8, gt
 ; CHECK-NEXT:    csinv x9, x9, xzr, le
 ; CHECK-NEXT:    fcmp d8, d8
 ; CHECK-NEXT:    csel x0, xzr, x9, vs
 ; CHECK-NEXT:    csel x1, xzr, x8, vs
 ; CHECK-NEXT:    ldr d8, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
     %x = call i100 @llvm.fptosi.sat.i100.f64(double %f)
     ret i100 %x
 }
 
 define i128 @test_signed_i128_f64(double %f) nounwind {
 ; CHECK-LABEL: test_signed_i128_f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str d8, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    str x30, [sp, #8] // 8-byte Folded Spill
 ; CHECK-NEXT:    fmov d8, d0
 ; CHECK-NEXT:    bl __fixdfti
-; CHECK-NEXT:    mov x8, #-4044232465378705408
-; CHECK-NEXT:    mov x10, #9223372036854775807
+; CHECK-NEXT:    mov x8, #-4044232465378705408 // =0xc7e0000000000000
+; CHECK-NEXT:    mov x10, #9223372036854775807 // =0x7fffffffffffffff
 ; CHECK-NEXT:    ldr x30, [sp, #8] // 8-byte Folded Reload
 ; CHECK-NEXT:    fmov d0, x8
-; CHECK-NEXT:    mov x8, #5179139571476070399
+; CHECK-NEXT:    mov x8, #5179139571476070399 // =0x47dfffffffffffff
 ; CHECK-NEXT:    fcmp d8, d0
 ; CHECK-NEXT:    fmov d0, x8
-; CHECK-NEXT:    mov x8, #-9223372036854775808
+; CHECK-NEXT:    mov x8, #-9223372036854775808 // =0x8000000000000000
 ; CHECK-NEXT:    csel x9, xzr, x0, lt
 ; CHECK-NEXT:    csel x8, x8, x1, lt
 ; CHECK-NEXT:    fcmp d8, d0
 ; CHECK-NEXT:    csel x8, x10, x8, gt
 ; CHECK-NEXT:    csinv x9, x9, xzr, le
 ; CHECK-NEXT:    fcmp d8, d8
 ; CHECK-NEXT:    csel x0, xzr, x9, vs
 ; CHECK-NEXT:    csel x1, xzr, x8, vs

 declare i100 @llvm.fptosi.sat.i100.f16(half)
 declare i128 @llvm.fptosi.sat.i128.f16(half)
 
 define i1 @test_signed_i1_f16(half %f) nounwind {
 ; CHECK-CVT-LABEL: test_signed_i1_f16:
 ; CHECK-CVT:       // %bb.0:
 ; CHECK-CVT-NEXT:    fcvt s0, h0
 ; CHECK-CVT-NEXT:    fcvtzs w8, s0
-; CHECK-CVT-NEXT:    cmp w8, #0
-; CHECK-CVT-NEXT:    csel w8, w8, wzr, lt
-; CHECK-CVT-NEXT:    cmp w8, #0
+; CHECK-CVT-NEXT:    ands w8, w8, w8, asr #31
 ; CHECK-CVT-NEXT:    csinv w8, w8, wzr, ge
 ; CHECK-CVT-NEXT:    and w0, w8, #0x1
 ; CHECK-CVT-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: test_signed_i1_f16:
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    fcvtzs w8, h0
-; CHECK-FP16-NEXT:    cmp w8, #0
-; CHECK-FP16-NEXT:    csel w8, w8, wzr, lt
-; CHECK-FP16-NEXT:    cmp w8, #0
+; CHECK-FP16-NEXT:    ands w8, w8, w8, asr #31
 ; CHECK-FP16-NEXT:    csinv w8, w8, wzr, ge
 ; CHECK-FP16-NEXT:    and w0, w8, #0x1
 ; CHECK-FP16-NEXT:    ret
     %x = call i1 @llvm.fptosi.sat.i1.f16(half %f)
     ret i1 %x
 }
 
 define i8 @test_signed_i8_f16(half %f) nounwind {
 ; CHECK-CVT-LABEL: test_signed_i8_f16:
 ; CHECK-CVT:       // %bb.0:
 ; CHECK-CVT-NEXT:    fcvt s0, h0
-; CHECK-CVT-NEXT:    mov w8, #127
+; CHECK-CVT-NEXT:    mov w8, #127 // =0x7f
 ; CHECK-CVT-NEXT:    fcvtzs w9, s0
 ; CHECK-CVT-NEXT:    cmp w9, #127
 ; CHECK-CVT-NEXT:    csel w8, w9, w8, lt
-; CHECK-CVT-NEXT:    mov w9, #-128
+; CHECK-CVT-NEXT:    mov w9, #-128 // =0xffffff80
 ; CHECK-CVT-NEXT:    cmn w8, #128
 ; CHECK-CVT-NEXT:    csel w0, w8, w9, gt
 ; CHECK-CVT-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: test_signed_i8_f16:
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    fcvtzs w9, h0
-; CHECK-FP16-NEXT:    mov w8, #127
+; CHECK-FP16-NEXT:    mov w8, #127 // =0x7f
 ; CHECK-FP16-NEXT:    cmp w9, #127
 ; CHECK-FP16-NEXT:    csel w8, w9, w8, lt
-; CHECK-FP16-NEXT:    mov w9, #-128
+; CHECK-FP16-NEXT:    mov w9, #-128 // =0xffffff80
 ; CHECK-FP16-NEXT:    cmn w8, #128
 ; CHECK-FP16-NEXT:    csel w0, w8, w9, gt
 ; CHECK-FP16-NEXT:    ret
     %x = call i8 @llvm.fptosi.sat.i8.f16(half %f)
     ret i8 %x
 }
 
 define i13 @test_signed_i13_f16(half %f) nounwind {
 ; CHECK-CVT-LABEL: test_signed_i13_f16:
 ; CHECK-CVT:       // %bb.0:
 ; CHECK-CVT-NEXT:    fcvt s0, h0
-; CHECK-CVT-NEXT:    mov w8, #4095
+; CHECK-CVT-NEXT:    mov w8, #4095 // =0xfff
 ; CHECK-CVT-NEXT:    fcvtzs w9, s0
 ; CHECK-CVT-NEXT:    cmp w9, #4095
 ; CHECK-CVT-NEXT:    csel w8, w9, w8, lt
-; CHECK-CVT-NEXT:    mov w9, #-4096
+; CHECK-CVT-NEXT:    mov w9, #-4096 // =0xfffff000
 ; CHECK-CVT-NEXT:    cmn w8, #1, lsl #12 // =4096
 ; CHECK-CVT-NEXT:    csel w0, w8, w9, gt
 ; CHECK-CVT-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: test_signed_i13_f16:
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    fcvtzs w9, h0
-; CHECK-FP16-NEXT:    mov w8, #4095
+; CHECK-FP16-NEXT:    mov w8, #4095 // =0xfff
 ; CHECK-FP16-NEXT:    cmp w9, #4095
 ; CHECK-FP16-NEXT:    csel w8, w9, w8, lt
-; CHECK-FP16-NEXT:    mov w9, #-4096
+; CHECK-FP16-NEXT:    mov w9, #-4096 // =0xfffff000
 ; CHECK-FP16-NEXT:    cmn w8, #1, lsl #12 // =4096
 ; CHECK-FP16-NEXT:    csel w0, w8, w9, gt
 ; CHECK-FP16-NEXT:    ret
     %x = call i13 @llvm.fptosi.sat.i13.f16(half %f)
     ret i13 %x
 }
 
 define i16 @test_signed_i16_f16(half %f) nounwind {
 ; CHECK-CVT-LABEL: test_signed_i16_f16:
 ; CHECK-CVT:       // %bb.0:
 ; CHECK-CVT-NEXT:    fcvt s0, h0
-; CHECK-CVT-NEXT:    mov w9, #32767
+; CHECK-CVT-NEXT:    mov w9, #32767 // =0x7fff
 ; CHECK-CVT-NEXT:    fcvtzs w8, s0
 ; CHECK-CVT-NEXT:    cmp w8, w9
 ; CHECK-CVT-NEXT:    csel w8, w8, w9, lt
-; CHECK-CVT-NEXT:    mov w9, #-32768
+; CHECK-CVT-NEXT:    mov w9, #-32768 // =0xffff8000
 ; CHECK-CVT-NEXT:    cmn w8, #8, lsl #12 // =32768
 ; CHECK-CVT-NEXT:    csel w0, w8, w9, gt
 ; CHECK-CVT-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: test_signed_i16_f16:
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    fcvtzs w8, h0
-; CHECK-FP16-NEXT:    mov w9, #32767
+; CHECK-FP16-NEXT:    mov w9, #32767 // =0x7fff
 ; CHECK-FP16-NEXT:    cmp w8, w9
 ; CHECK-FP16-NEXT:    csel w8, w8, w9, lt
-; CHECK-FP16-NEXT:    mov w9, #-32768
+; CHECK-FP16-NEXT:    mov w9, #-32768 // =0xffff8000
 ; CHECK-FP16-NEXT:    cmn w8, #8, lsl #12 // =32768
 ; CHECK-FP16-NEXT:    csel w0, w8, w9, gt
 ; CHECK-FP16-NEXT:    ret
     %x = call i16 @llvm.fptosi.sat.i16.f16(half %f)
     ret i16 %x
 }
 
 define i19 @test_signed_i19_f16(half %f) nounwind {
 ; CHECK-CVT-LABEL: test_signed_i19_f16:
 ; CHECK-CVT:       // %bb.0:
 ; CHECK-CVT-NEXT:    fcvt s0, h0
-; CHECK-CVT-NEXT:    mov w9, #262143
+; CHECK-CVT-NEXT:    mov w9, #262143 // =0x3ffff
 ; CHECK-CVT-NEXT:    fcvtzs w8, s0
 ; CHECK-CVT-NEXT:    cmp w8, w9
 ; CHECK-CVT-NEXT:    csel w8, w8, w9, lt
-; CHECK-CVT-NEXT:    mov w9, #-262144
+; CHECK-CVT-NEXT:    mov w9, #-262144 // =0xfffc0000
 ; CHECK-CVT-NEXT:    cmn w8, #64, lsl #12 // =262144
 ; CHECK-CVT-NEXT:    csel w0, w8, w9, gt
 ; CHECK-CVT-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: test_signed_i19_f16:
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    fcvtzs w8, h0
-; CHECK-FP16-NEXT:    mov w9, #262143
+; CHECK-FP16-NEXT:    mov w9, #262143 // =0x3ffff
 ; CHECK-FP16-NEXT:    cmp w8, w9
 ; CHECK-FP16-NEXT:    csel w8, w8, w9, lt
-; CHECK-FP16-NEXT:    mov w9, #-262144
+; CHECK-FP16-NEXT:    mov w9, #-262144 // =0xfffc0000
 ; CHECK-FP16-NEXT:    cmn w8, #64, lsl #12 // =262144
 ; CHECK-FP16-NEXT:    csel w0, w8, w9, gt
 ; CHECK-FP16-NEXT:    ret
     %x = call i19 @llvm.fptosi.sat.i19.f16(half %f)
     ret i19 %x
 }
 
 define i32 @test_signed_i32_f16(half %f) nounwind {
; CHECK-FP16-NEXT:    ret
     %x = call i32 @llvm.fptosi.sat.i32.f16(half %f)
     ret i32 %x
 }
 
 define i50 @test_signed_i50_f16(half %f) nounwind {
 ; CHECK-CVT-LABEL: test_signed_i50_f16:
 ; CHECK-CVT:       // %bb.0:
 ; CHECK-CVT-NEXT:    fcvt s0, h0
-; CHECK-CVT-NEXT:    mov x9, #562949953421311
+; CHECK-CVT-NEXT:    mov x9, #562949953421311 // =0x1ffffffffffff
 ; CHECK-CVT-NEXT:    fcvtzs x8, s0
 ; CHECK-CVT-NEXT:    cmp x8, x9
 ; CHECK-CVT-NEXT:    csel x8, x8, x9, lt
-; CHECK-CVT-NEXT:    mov x9, #-562949953421312
+; CHECK-CVT-NEXT:    mov x9, #-562949953421312 // =0xfffe000000000000
 ; CHECK-CVT-NEXT:    cmp x8, x9
 ; CHECK-CVT-NEXT:    csel x0, x8, x9, gt
 ; CHECK-CVT-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: test_signed_i50_f16:
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    fcvtzs x8, h0
-; CHECK-FP16-NEXT:    mov x9, #562949953421311
+; CHECK-FP16-NEXT:    mov x9, #562949953421311 // =0x1ffffffffffff
 ; CHECK-FP16-NEXT:    cmp x8, x9
 ; CHECK-FP16-NEXT:    csel x8, x8, x9, lt
-; CHECK-FP16-NEXT:    mov x9, #-562949953421312
+; CHECK-FP16-NEXT:    mov x9, #-562949953421312 // =0xfffe000000000000
 ; CHECK-FP16-NEXT:    cmp x8, x9
 ; CHECK-FP16-NEXT:    csel x0, x8, x9, gt
 ; CHECK-FP16-NEXT:    ret
     %x = call i50 @llvm.fptosi.sat.i50.f16(half %f)
     ret i50 %x
 }
 
 define i64 @test_signed_i64_f16(half %f) nounwind {

 ; CHECK-LABEL: test_signed_i100_f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str d8, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    fcvt s8, h0
 ; CHECK-NEXT:    str x30, [sp, #8] // 8-byte Folded Spill
 ; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    bl __fixsfti
 ; CHECK-NEXT:    movi v0.2s, #241, lsl #24
-; CHECK-NEXT:    mov w8, #1895825407
-; CHECK-NEXT:    mov x10, #34359738367
+; CHECK-NEXT:    mov w8, #1895825407 // =0x70ffffff
+; CHECK-NEXT:    mov x10, #34359738367 // =0x7ffffffff
 ; CHECK-NEXT:    ldr x30, [sp, #8] // 8-byte Folded Reload
 ; CHECK-NEXT:    fcmp s8, s0
 ; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    mov x8, #-34359738368
+; CHECK-NEXT:    mov x8, #-34359738368 // =0xfffffff800000000
 ; CHECK-NEXT:    csel x9, xzr, x0, lt
 ; CHECK-NEXT:    csel x8, x8, x1, lt
 ; CHECK-NEXT:    fcmp s8, s0
 ; CHECK-NEXT:    csel x8, x10, x8, gt
 ; CHECK-NEXT:    csinv x9, x9, xzr, le
 ; CHECK-NEXT:    fcmp s8, s8
 ; CHECK-NEXT:    csel x0, xzr, x9, vs
 ; CHECK-NEXT:    csel x1, xzr, x8, vs
 ; CHECK-NEXT:    ldr d8, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
     %x = call i100 @llvm.fptosi.sat.i100.f16(half %f)
     ret i100 %x
 }
 
 define i128 @test_signed_i128_f16(half %f) nounwind {
 ; CHECK-LABEL: test_signed_i128_f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str d8, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    fcvt s8, h0
 ; CHECK-NEXT:    str x30, [sp, #8] // 8-byte Folded Spill
 ; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    bl __fixsfti
 ; CHECK-NEXT:    movi v0.2s, #255, lsl #24
-; CHECK-NEXT:    mov w8, #2130706431
-; CHECK-NEXT:    mov x10, #9223372036854775807
+; CHECK-NEXT:    mov w8, #2130706431 // =0x7effffff
+; CHECK-NEXT:    mov x10, #9223372036854775807 // =0x7fffffffffffffff
 ; CHECK-NEXT:    ldr x30, [sp, #8] // 8-byte Folded Reload
 ; CHECK-NEXT:    fcmp s8, s0
 ; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    mov x8, #-9223372036854775808
+; CHECK-NEXT:    mov x8, #-9223372036854775808 // =0x8000000000000000
 ; CHECK-NEXT:    csel x9, xzr, x0, lt
 ; CHECK-NEXT:    csel x8, x8, x1, lt
 ; CHECK-NEXT:    fcmp s8, s0
 ; CHECK-NEXT:    csel x8, x10, x8, gt
 ; CHECK-NEXT:    csinv x9, x9, xzr, le
 ; CHECK-NEXT:    fcmp s8, s8
 ; CHECK-NEXT:    csel x0, xzr, x9, vs
 ; CHECK-NEXT:    csel x1, xzr, x8, vs
 ; CHECK-NEXT:    ldr d8, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
     %x = call i128 @llvm.fptosi.sat.i128.f16(half %f)
     ret i128 %x
 }

llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll

 ; CHECK-NEXT:    adrp x8, .LCPI14_0
 ; CHECK-NEXT:    str q0, [sp] // 16-byte Folded Spill
 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI14_0]
 ; CHECK-NEXT:    bl __getf2
 ; CHECK-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
 ; CHECK-NEXT:    mov w19, w0
 ; CHECK-NEXT:    bl __fixtfsi
 ; CHECK-NEXT:    cmp w19, #0
-; CHECK-NEXT:    mov w8, #-2147483648
+; CHECK-NEXT:    mov w8, #-2147483648 // =0x80000000
 ; CHECK-NEXT:    csel w19, w8, w0, lt
 ; CHECK-NEXT:    adrp x8, .LCPI14_1
 ; CHECK-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI14_1]
 ; CHECK-NEXT:    bl __gttf2
 ; CHECK-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
-; CHECK-NEXT:    mov w8, #2147483647
+; CHECK-NEXT:    mov w8, #2147483647 // =0x7fffffff
 ; CHECK-NEXT:    cmp w0, #0
 ; CHECK-NEXT:    csel w19, w8, w19, gt
 ; CHECK-NEXT:    mov v1.16b, v0.16b
 ; CHECK-NEXT:    bl __unordtf2
 ; CHECK-NEXT:    cmp w0, #0
 ; CHECK-NEXT:    csel w8, wzr, w19, ne
 ; CHECK-NEXT:    ldp x30, x19, [sp, #16] // 16-byte Folded Reload
 ; CHECK-NEXT:    fmov s0, w8

 ; CHECK-NEXT:    str q1, [sp, #16] // 16-byte Folded Spill
 ; CHECK-NEXT:    bl __getf2
 ; CHECK-NEXT:    ldr q0, [sp, #32] // 16-byte Folded Reload
 ; CHECK-NEXT:    mov w19, w0
 ; CHECK-NEXT:    bl __fixtfsi
 ; CHECK-NEXT:    adrp x8, .LCPI15_1
 ; CHECK-NEXT:    ldr q0, [sp, #32] // 16-byte Folded Reload
 ; CHECK-NEXT:    cmp w19, #0
-; CHECK-NEXT:    mov w20, #-2147483648
+; CHECK-NEXT:    mov w20, #-2147483648 // =0x80000000
 ; CHECK-NEXT:    csel w19, w20, w0, lt
 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI15_1]
 ; CHECK-NEXT:    str q1, [sp] // 16-byte Folded Spill
 ; CHECK-NEXT:    bl __gttf2
 ; CHECK-NEXT:    ldr q0, [sp, #32] // 16-byte Folded Reload
-; CHECK-NEXT:    mov w21, #2147483647
+; CHECK-NEXT:    mov w21, #2147483647 // =0x7fffffff
 ; CHECK-NEXT:    cmp w0, #0
 ; CHECK-NEXT:    csel w19, w21, w19, gt
 ; CHECK-NEXT:    mov v1.16b, v0.16b
 ; CHECK-NEXT:    bl __unordtf2
 ; CHECK-NEXT:    ldr q0, [sp, #48] // 16-byte Folded Reload
 ; CHECK-NEXT:    cmp w0, #0
 ; CHECK-NEXT:    ldr q1, [sp, #16] // 16-byte Folded Reload
 ; CHECK-NEXT:    csel w22, wzr, w19, ne

 ; CHECK-NEXT:    str q1, [sp, #16] // 16-byte Folded Spill
 ; CHECK-NEXT:    bl __getf2
 ; CHECK-NEXT:    ldr q0, [sp, #32] // 16-byte Folded Reload
 ; CHECK-NEXT:    mov w19, w0
 ; CHECK-NEXT:    bl __fixtfsi
 ; CHECK-NEXT:    adrp x8, .LCPI16_1
 ; CHECK-NEXT:    ldr q0, [sp, #32] // 16-byte Folded Reload
 ; CHECK-NEXT:    cmp w19, #0
-; CHECK-NEXT:    mov w20, #-2147483648
+; CHECK-NEXT:    mov w20, #-2147483648 // =0x80000000
 ; CHECK-NEXT:    csel w19, w20, w0, lt
 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI16_1]
 ; CHECK-NEXT:    str q1, [sp] // 16-byte Folded Spill
 ; CHECK-NEXT:    bl __gttf2
 ; CHECK-NEXT:    ldr q0, [sp, #32] // 16-byte Folded Reload
-; CHECK-NEXT:    mov w21, #2147483647
+; CHECK-NEXT:    mov w21, #2147483647 // =0x7fffffff
 ; CHECK-NEXT:    cmp w0, #0
 ; CHECK-NEXT:    csel w19, w21, w19, gt
 ; CHECK-NEXT:    mov v1.16b, v0.16b
 ; CHECK-NEXT:    bl __unordtf2
 ; CHECK-NEXT:    ldr q0, [sp, #48] // 16-byte Folded Reload
 ; CHECK-NEXT:    cmp w0, #0
 ; CHECK-NEXT:    ldr q1, [sp, #16] // 16-byte Folded Reload
 ; CHECK-NEXT:    csel w22, wzr, w19, ne

 ; CHECK-NEXT:    str q1, [sp, #32] // 16-byte Folded Spill
 ; CHECK-NEXT:    bl __getf2
 ; CHECK-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
 ; CHECK-NEXT:    mov w19, w0
 ; CHECK-NEXT:    bl __fixtfsi
 ; CHECK-NEXT:    adrp x8, .LCPI17_1
 ; CHECK-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
 ; CHECK-NEXT:    cmp w19, #0
-; CHECK-NEXT:    mov w20, #-2147483648
+; CHECK-NEXT:    mov w20, #-2147483648 // =0x80000000
 ; CHECK-NEXT:    csel w19, w20, w0, lt
 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI17_1]
 ; CHECK-NEXT:    str q1, [sp, #16] // 16-byte Folded Spill
 ; CHECK-NEXT:    bl __gttf2
 ; CHECK-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
-; CHECK-NEXT:    mov w21, #2147483647
+; CHECK-NEXT:    mov w21, #2147483647 // =0x7fffffff
 ; CHECK-NEXT:    cmp w0, #0
 ; CHECK-NEXT:    csel w19, w21, w19, gt
 ; CHECK-NEXT:    mov v1.16b, v0.16b
 ; CHECK-NEXT:    bl __unordtf2
 ; CHECK-NEXT:    ldp q1, q0, [sp, #32] // 32-byte Folded Reload
 ; CHECK-NEXT:    cmp w0, #0
 ; CHECK-NEXT:    csel w22, wzr, w19, ne
 ; CHECK-NEXT:    bl __getf2
; CHECK-NEXT:    ret
     ret <2 x i32> %x
 }
 
 define <2 x i50> @test_signed_v2f32_v2i50(<2 x float> %f) {
 ; CHECK-LABEL: test_signed_v2f32_v2i50:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    mov x8, #562949953421311
+; CHECK-NEXT:    mov x8, #562949953421311 // =0x1ffffffffffff
 ; CHECK-NEXT:    fcvtzs x10, s0
-; CHECK-NEXT:    mov x11, #-562949953421312
+; CHECK-NEXT:    mov x11, #-562949953421312 // =0xfffe000000000000
 ; CHECK-NEXT:    fcvtzs x9, s1
 ; CHECK-NEXT:    cmp x9, x8
 ; CHECK-NEXT:    csel x9, x9, x8, lt
 ; CHECK-NEXT:    cmp x9, x11
 ; CHECK-NEXT:    csel x9, x9, x11, gt
 ; CHECK-NEXT:    cmp x10, x8
 ; CHECK-NEXT:    csel x8, x10, x8, lt
 ; CHECK-NEXT:    cmp x8, x11

 ; CHECK-NEXT:    .cfi_offset b9, -56
 ; CHECK-NEXT:    .cfi_offset b10, -64
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    mov s8, v0.s[1]
 ; CHECK-NEXT:    str q0, [sp] // 16-byte Folded Spill
 ; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    bl __fixsfti
 ; CHECK-NEXT:    movi v9.2s, #241, lsl #24
-; CHECK-NEXT:    mov w8, #1895825407
-; CHECK-NEXT:    mov x21, #-34359738368
-; CHECK-NEXT:    mov x22, #34359738367
+; CHECK-NEXT:    mov w8, #1895825407 // =0x70ffffff
+; CHECK-NEXT:    mov x21, #-34359738368 // =0xfffffff800000000
+; CHECK-NEXT:    mov x22, #34359738367 // =0x7ffffffff
 ; CHECK-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
 ; CHECK-NEXT:    fmov s10, w8
 ; CHECK-NEXT:    // kill: def $s0 killed $s0 killed $q0
 ; CHECK-NEXT:    fcmp s8, s9
 ; CHECK-NEXT:    csel x8, xzr, x0, lt
 ; CHECK-NEXT:    csel x9, x21, x1, lt
 ; CHECK-NEXT:    fcmp s8, s10
 ; CHECK-NEXT:    csel x9, x22, x9, gt

 ; CHECK-NEXT:    .cfi_offset b9, -56
 ; CHECK-NEXT:    .cfi_offset b10, -64
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    mov s8, v0.s[1]
 ; CHECK-NEXT:    str q0, [sp] // 16-byte Folded Spill
 ; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    bl __fixsfti
 ; CHECK-NEXT:    movi v9.2s, #255, lsl #24
-; CHECK-NEXT:    mov w8, #2130706431
-; CHECK-NEXT:    mov x21, #-9223372036854775808
-; CHECK-NEXT:    mov x22, #9223372036854775807
+; CHECK-NEXT:    mov w8, #2130706431 // =0x7effffff
+; CHECK-NEXT:    mov x21, #-9223372036854775808 // =0x8000000000000000
+; CHECK-NEXT:    mov x22, #9223372036854775807 // =0x7fffffffffffffff
 ; CHECK-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
 ; CHECK-NEXT:    fmov s10, w8
 ; CHECK-NEXT:    // kill: def $s0 killed $s0 killed $q0
 ; CHECK-NEXT:    fcmp s8, s9
 ; CHECK-NEXT:    csel x8, xzr, x0, lt
 ; CHECK-NEXT:    csel x9, x21, x1, lt
 ; CHECK-NEXT:    fcmp s8, s10
 ; CHECK-NEXT:    csel x9, x22, x9, gt
; CHECK-NEXT:    ret
     %x = call <4 x i32> @llvm.fptosi.sat.v4f32.v4i32(<4 x float> %f)
     ret <4 x i32> %x
 }
 
 define <4 x i50> @test_signed_v4f32_v4i50(<4 x float> %f) {
 ; CHECK-LABEL: test_signed_v4f32_v4i50:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT:    mov x9, #562949953421311
-; CHECK-NEXT:    mov x10, #-562949953421312
+; CHECK-NEXT:    mov x9, #562949953421311 // =0x1ffffffffffff
+; CHECK-NEXT:    mov x10, #-562949953421312 // =0xfffe000000000000
 ; CHECK-NEXT:    fcvtzs x12, s0
 ; CHECK-NEXT:    mov s2, v1.s[1]
 ; CHECK-NEXT:    fcvtzs x8, s1
 ; CHECK-NEXT:    mov s1, v0.s[1]
 ; CHECK-NEXT:    cmp x8, x9
 ; CHECK-NEXT:    fcvtzs x11, s2
 ; CHECK-NEXT:    csel x8, x8, x9, lt
 ; CHECK-NEXT:    cmp x8, x10

 ; CHECK-NEXT:    .cfi_offset b8, -80
 ; CHECK-NEXT:    .cfi_offset b9, -88
 ; CHECK-NEXT:    .cfi_offset b10, -96
 ; CHECK-NEXT:    mov s8, v0.s[1]
 ; CHECK-NEXT:    str q0, [sp, #16] // 16-byte Folded Spill
 ; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    bl __fixsfti
 ; CHECK-NEXT:    movi v9.2s, #241, lsl #24
-; CHECK-NEXT:    mov w8, #1895825407
-; CHECK-NEXT:    mov x25, #-34359738368
+; CHECK-NEXT:    mov w8, #1895825407 // =0x70ffffff
+; CHECK-NEXT:    mov x25, #-34359738368 // =0xfffffff800000000
 ; CHECK-NEXT:    ldr q0, [sp, #16] // 16-byte Folded Reload
-; CHECK-NEXT:    mov x26, #34359738367
+; CHECK-NEXT:    mov x26, #34359738367 // =0x7ffffffff
 ; CHECK-NEXT:    fmov s10, w8
 ; CHECK-NEXT:    fcmp s8, s9
 ; CHECK-NEXT:    ext v0.16b, v0.16b, v0.16b, #8
 ; CHECK-NEXT:    csel x8, xzr, x0, lt
 ; CHECK-NEXT:    csel x9, x25, x1, lt
 ; CHECK-NEXT:    fcmp s8, s10
 ; CHECK-NEXT:    str q0, [sp] // 16-byte Folded Spill
 ; CHECK-NEXT:    // kill: def $s0 killed $s0 killed $q0

 ; CHECK-NEXT:    .cfi_offset b8, -80
 ; CHECK-NEXT:    .cfi_offset b9, -88
 ; CHECK-NEXT:    .cfi_offset b10, -96
 ; CHECK-NEXT:    mov s8, v0.s[1]
 ; CHECK-NEXT:    str q0, [sp, #16] // 16-byte Folded Spill
 ; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    bl __fixsfti
 ; CHECK-NEXT:    movi v9.2s, #255, lsl #24
-; CHECK-NEXT:    mov w8, #2130706431
-; CHECK-NEXT:    mov x25, #-9223372036854775808
+; CHECK-NEXT:    mov w8, #2130706431 // =0x7effffff
+; CHECK-NEXT:    mov x25, #-9223372036854775808 // =0x8000000000000000
 ; CHECK-NEXT:    ldr q0, [sp, #16] // 16-byte Folded Reload
-; CHECK-NEXT:    mov x26, #9223372036854775807
+; CHECK-NEXT:    mov x26, #9223372036854775807 // =0x7fffffffffffffff
 ; CHECK-NEXT:    fmov s10, w8
 ; CHECK-NEXT:    fcmp s8, s9
 ; CHECK-NEXT:    ext v0.16b, v0.16b, v0.16b, #8
 ; CHECK-NEXT:    csel x8, xzr, x0, lt
 ; CHECK-NEXT:    csel x9, x25, x1, lt
 ; CHECK-NEXT:    fcmp s8, s10
 ; CHECK-NEXT:    str q0, [sp] // 16-byte Folded Spill
 ; CHECK-NEXT:    // kill: def $s0 killed $s0 killed $q0

 declare <2 x i128> @llvm.fptosi.sat.v2f64.v2i128(<2 x double>)
 
 define <2 x i1> @test_signed_v2f64_v2i1(<2 x double> %f) {
 ; CHECK-LABEL: test_signed_v2f64_v2i1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov d1, v0.d[1]
 ; CHECK-NEXT:    fcvtzs w9, d0
 ; CHECK-NEXT:    fcvtzs w8, d1
-; CHECK-NEXT:    cmp w8, #0
-; CHECK-NEXT:    csel w8, w8, wzr, lt
-; CHECK-NEXT:    cmp w8, #0
+; CHECK-NEXT:    ands w8, w8, w8, asr #31
 ; CHECK-NEXT:    csinv w8, w8, wzr, ge
-; CHECK-NEXT:    cmp w9, #0
-; CHECK-NEXT:    csel w9, w9, wzr, lt
-; CHECK-NEXT:    cmp w9, #0
+; CHECK-NEXT:    ands w9, w9, w9, asr #31
 ; CHECK-NEXT:    csinv w9, w9, wzr, ge
 ; CHECK-NEXT:    fmov s0, w9
 ; CHECK-NEXT:    mov v0.s[1], w8
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
 ; CHECK-NEXT:    ret
     %x = call <2 x i1> @llvm.fptosi.sat.v2f64.v2i1(<2 x double> %f)
     ret <2 x i1> %x
 }
 
 define <2 x i8> @test_signed_v2f64_v2i8(<2 x double> %f) {
 ; CHECK-LABEL: test_signed_v2f64_v2i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov d1, v0.d[1]
-; CHECK-NEXT:    mov w8, #127
+; CHECK-NEXT:    mov w8, #127 // =0x7f
 ; CHECK-NEXT:    fcvtzs w10, d0
-; CHECK-NEXT:    mov w11, #-128
+; CHECK-NEXT:    mov w11, #-128 // =0xffffff80
 ; CHECK-NEXT:    fcvtzs w9, d1
 ; CHECK-NEXT:    cmp w9, #127
 ; CHECK-NEXT:    csel w9, w9, w8, lt
 ; CHECK-NEXT:    cmn w9, #128
 ; CHECK-NEXT:    csel w9, w9, w11, gt
 ; CHECK-NEXT:    cmp w10, #127
 ; CHECK-NEXT:    csel w8, w10, w8, lt
 ; CHECK-NEXT:    cmn w8, #128
 ; CHECK-NEXT:    csel w8, w8, w11, gt
 ; CHECK-NEXT:    fmov s0, w8
 ; CHECK-NEXT:    mov v0.s[1], w9
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
 ; CHECK-NEXT:    ret
     %x = call <2 x i8> @llvm.fptosi.sat.v2f64.v2i8(<2 x double> %f)
     ret <2 x i8> %x
 }
 
 define <2 x i13> @test_signed_v2f64_v2i13(<2 x double> %f) {
 ; CHECK-LABEL: test_signed_v2f64_v2i13:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov d1, v0.d[1]
-; CHECK-NEXT:    mov w8, #4095
+; CHECK-NEXT:    mov w8, #4095 // =0xfff
 ; CHECK-NEXT:    fcvtzs w10, d0
-; CHECK-NEXT:    mov w11, #-4096
+; CHECK-NEXT:    mov w11, #-4096 // =0xfffff000
 ; CHECK-NEXT:    fcvtzs w9, d1
 ; CHECK-NEXT:    cmp w9, #4095
 ; CHECK-NEXT:    csel w9, w9, w8, lt
 ; CHECK-NEXT:    cmn w9, #1, lsl #12 // =4096
 ; CHECK-NEXT:    csel w9, w9, w11, gt
 ; CHECK-NEXT:    cmp w10, #4095
 ; CHECK-NEXT:    csel w8, w10, w8, lt
 ; CHECK-NEXT:    cmn w8, #1, lsl #12 // =4096
 ; CHECK-NEXT:    csel w8, w8, w11, gt
 ; CHECK-NEXT:    fmov s0, w8
 ; CHECK-NEXT:    mov v0.s[1], w9
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
 ; CHECK-NEXT:    ret
     %x = call <2 x i13> @llvm.fptosi.sat.v2f64.v2i13(<2 x double> %f)
     ret <2 x i13> %x
 }
 
 define <2 x i16> @test_signed_v2f64_v2i16(<2 x double> %f) {
 ; CHECK-LABEL: test_signed_v2f64_v2i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov d1, v0.d[1]
-; CHECK-NEXT:    mov w8, #32767
+; CHECK-NEXT:    mov w8, #32767 // =0x7fff
 ; CHECK-NEXT:    fcvtzs w10, d0
-; CHECK-NEXT:    mov w11, #-32768
+; CHECK-NEXT:    mov w11, #-32768 // =0xffff8000
 ; CHECK-NEXT:    fcvtzs w9, d1
 ; CHECK-NEXT:    cmp w9, w8
 ; CHECK-NEXT:    csel w9, w9, w8, lt
 ; CHECK-NEXT:    cmn w9, #8, lsl #12 // =32768
 ; CHECK-NEXT:    csel w9, w9, w11, gt
 ; CHECK-NEXT:    cmp w10, w8
 ; CHECK-NEXT:    csel w8, w10, w8, lt
 ; CHECK-NEXT:    cmn w8, #8, lsl #12 // =32768
 ; CHECK-NEXT:    csel w8, w8, w11, gt
 ; CHECK-NEXT:    fmov s0, w8
 ; CHECK-NEXT:    mov v0.s[1], w9
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
 ; CHECK-NEXT:    ret
     %x = call <2 x i16> @llvm.fptosi.sat.v2f64.v2i16(<2 x double> %f)
     ret <2 x i16> %x
 }
 
 define <2 x i19> @test_signed_v2f64_v2i19(<2 x double> %f) {
 ; CHECK-LABEL: test_signed_v2f64_v2i19:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov d1, v0.d[1]
-; CHECK-NEXT:    mov w8, #262143
+; CHECK-NEXT:    mov w8, #262143 // =0x3ffff
 ; CHECK-NEXT:    fcvtzs w10, d0
-; CHECK-NEXT:    mov w11, #-262144
+; CHECK-NEXT:    mov w11, #-262144 // =0xfffc0000
 ; CHECK-NEXT:    fcvtzs w9, d1
 ; CHECK-NEXT:    cmp w9, w8
 ; CHECK-NEXT:    csel w9, w9, w8, lt
 ; CHECK-NEXT:    cmn w9, #64, lsl #12 // =262144
 ; CHECK-NEXT:    csel w9, w9, w11, gt
 ; CHECK-NEXT:    cmp w10, w8
 ; CHECK-NEXT:    csel w8, w10, w8, lt
 ; CHECK-NEXT:    cmn w8, #64, lsl #12 // =262144
; CHECK-NEXT:    ret
     %x = call <2 x i32> @llvm.fptosi.sat.v2f64.v2i32(<2 x double> %f)
     ret <2 x i32> %x
 }
 
 define <2 x i50> @test_signed_v2f64_v2i50(<2 x double> %f) {
 ; CHECK-LABEL: test_signed_v2f64_v2i50:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov d1, v0.d[1]
-; CHECK-NEXT:    mov x8, #562949953421311
+; CHECK-NEXT:    mov x8, #562949953421311 // =0x1ffffffffffff
 ; CHECK-NEXT:    fcvtzs x10, d0
-; CHECK-NEXT:    mov x11, #-562949953421312
+; CHECK-NEXT:    mov x11, #-562949953421312 // =0xfffe000000000000
 ; CHECK-NEXT:    fcvtzs x9, d1
 ; CHECK-NEXT:    cmp x9, x8
 ; CHECK-NEXT:    csel x9, x9, x8, lt
 ; CHECK-NEXT:    cmp x9, x11
 ; CHECK-NEXT:    csel x9, x9, x11, gt
 ; CHECK-NEXT:    cmp x10, x8
 ; CHECK-NEXT:    csel x8, x10, x8, lt
 ; CHECK-NEXT:    cmp x8, x11

 ; CHECK-NEXT:    .cfi_offset w30, -40
 ; CHECK-NEXT:    .cfi_offset b8, -48
 ; CHECK-NEXT:    .cfi_offset b9, -56
 ; CHECK-NEXT:    .cfi_offset b10, -64
 ; CHECK-NEXT:    mov d8, v0.d[1]
 ; CHECK-NEXT:    str q0, [sp] // 16-byte Folded Spill
 ; CHECK-NEXT:    fmov d0, d8
 ; CHECK-NEXT:    bl __fixdfti
-; CHECK-NEXT:    mov x8, #-4170333254945079296
-; CHECK-NEXT:    mov x21, #-34359738368
-; CHECK-NEXT:    mov x22, #34359738367
+; CHECK-NEXT:    mov x8, #-4170333254945079296 // =0xc620000000000000
+; CHECK-NEXT:    mov x21, #-34359738368 // =0xfffffff800000000
+; CHECK-NEXT:    mov x22, #34359738367 // =0x7ffffffff
 ; CHECK-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
 ; CHECK-NEXT:    fmov d9, x8
-; CHECK-NEXT:    mov x8, #5053038781909696511
+; CHECK-NEXT:    mov x8, #5053038781909696511 // =0x461fffffffffffff
 ; CHECK-NEXT:    fcmp d8, d9
 ; CHECK-NEXT:    fmov d10, x8
 ; CHECK-NEXT:    csel x8, xzr, x0, lt
 ; CHECK-NEXT:    csel x9, x21, x1, lt
 ; CHECK-NEXT:    fcmp d8, d10
 ; CHECK-NEXT:    csel x9, x22, x9, gt
 ; CHECK-NEXT:    csinv x8, x8, xzr, le
 ; CHECK-NEXT:    fcmp d8, d8

 ; CHECK-NEXT:    .cfi_offset w30, -40
 ; CHECK-NEXT:    .cfi_offset b8, -48
 ; CHECK-NEXT:    .cfi_offset b9, -56
 ; CHECK-NEXT:    .cfi_offset b10, -64
 ; CHECK-NEXT:    mov d8, v0.d[1]
 ; CHECK-NEXT:    str q0, [sp] // 16-byte Folded Spill
 ; CHECK-NEXT:    fmov d0, d8
 ; CHECK-NEXT:    bl __fixdfti
-; CHECK-NEXT:    mov x8, #-4044232465378705408
-; CHECK-NEXT:    mov x21, #-9223372036854775808
-; CHECK-NEXT:    mov x22, #9223372036854775807
+; CHECK-NEXT:    mov x8, #-4044232465378705408 // =0xc7e0000000000000
+; CHECK-NEXT:    mov x21, #-9223372036854775808 // =0x8000000000000000
+; CHECK-NEXT:    mov x22, #9223372036854775807 // =0x7fffffffffffffff
 ; CHECK-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
 ; CHECK-NEXT:    fmov d9, x8
-; CHECK-NEXT:    mov x8, #5179139571476070399
+; CHECK-NEXT:    mov x8, #5179139571476070399 // =0x47dfffffffffffff
 ; CHECK-NEXT:    fcmp d8, d9
 ; CHECK-NEXT:    fmov d10, x8
 ; CHECK-NEXT:    csel x8, xzr, x0, lt
 ; CHECK-NEXT:    csel x9, x21, x1, lt
 ; CHECK-NEXT:    fcmp d8, d10
 ; CHECK-NEXT:    csel x9, x22, x9, gt
 ; CHECK-NEXT:    csinv x8, x8, xzr, le
 ; CHECK-NEXT:    fcmp d8, d8

 define <4 x i50> @test_signed_v4f16_v4i50(<4 x half> %f) {
 ; CHECK-CVT-LABEL: test_signed_v4f16_v4i50:
 ; CHECK-CVT:       // %bb.0:
 ; CHECK-CVT-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-CVT-NEXT:    mov h1, v0.h[1]
 ; CHECK-CVT-NEXT:    fcvt s2, h0
 ; CHECK-CVT-NEXT:    mov h3, v0.h[2]
 ; CHECK-CVT-NEXT:    mov h0, v0.h[3]
-; CHECK-CVT-NEXT:    mov x8, #562949953421311
-; CHECK-CVT-NEXT:    mov x11, #-562949953421312
+; CHECK-CVT-NEXT:    mov x8, #562949953421311 // =0x1ffffffffffff
+; CHECK-CVT-NEXT:    mov x11, #-562949953421312 // =0xfffe000000000000
 ; CHECK-CVT-NEXT:    fcvt s1, h1
 ; CHECK-CVT-NEXT:    fcvtzs x9, s2
 ; CHECK-CVT-NEXT:    fcvt s0, h0
 ; CHECK-CVT-NEXT:    cmp x9, x8
 ; CHECK-CVT-NEXT:    fcvtzs x10, s1
 ; CHECK-CVT-NEXT:    fcvt s1, h3
 ; CHECK-CVT-NEXT:    csel x9, x9, x8, lt
 ; CHECK-CVT-NEXT:    cmp x9, x11

 ; CHECK-CVT-NEXT:    csel x3, x8, x11, gt
 ; CHECK-CVT-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: test_signed_v4f16_v4i50:
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-FP16-NEXT:    mov h1, v0.h[1]
 ; CHECK-FP16-NEXT:    fcvtzs x9, h0
-; CHECK-FP16-NEXT:    mov x8, #562949953421311
-; CHECK-FP16-NEXT:    mov x11, #-562949953421312
+; CHECK-FP16-NEXT:    mov x8, #562949953421311 // =0x1ffffffffffff
+; CHECK-FP16-NEXT:    mov x11, #-562949953421312 // =0xfffe000000000000
 ; CHECK-FP16-NEXT:    cmp x9, x8
 ; CHECK-FP16-NEXT:    fcvtzs x10, h1
 ; CHECK-FP16-NEXT:    mov h1, v0.h[2]
 ; CHECK-FP16-NEXT:    csel x9, x9, x8, lt
 ; CHECK-FP16-NEXT:    mov h0, v0.h[3]
 ; CHECK-FP16-NEXT:    cmp x9, x11
 ; CHECK-FP16-NEXT:    csel x0, x9, x11, gt
 ; CHECK-FP16-NEXT:    cmp x10, x8

 ; CHECK-NEXT:    .cfi_offset b10, -96
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    mov h1, v0.h[1]
 ; CHECK-NEXT:    str q0, [sp] // 16-byte Folded Spill
 ; CHECK-NEXT:    fcvt s8, h1
 ; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    bl __fixsfti
 ; CHECK-NEXT:    movi v9.2s, #241, lsl #24
-; CHECK-NEXT:    mov w8, #1895825407
+; CHECK-NEXT:    mov w8, #1895825407 // =0x70ffffff
 ; CHECK-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
-; CHECK-NEXT:    mov x25, #-34359738368
-; CHECK-NEXT:    mov x26, #34359738367
+; CHECK-NEXT:    mov x25, #-34359738368 // =0xfffffff800000000
+; CHECK-NEXT:    mov x26, #34359738367 // =0x7ffffffff
 ; CHECK-NEXT:    fmov s10, w8
 ; CHECK-NEXT:    fcmp s8, s9
 ; CHECK-NEXT:    mov h0, v0.h[2]
 ; CHECK-NEXT:    csel x8, xzr, x0, lt
 ; CHECK-NEXT:    csel x9, x25, x1, lt
 ; CHECK-NEXT:    fcmp s8, s10
 ; CHECK-NEXT:    csel x9, x26, x9, gt
 ; CHECK-NEXT:    csinv x8, x8, xzr, le

 ; CHECK-NEXT:    .cfi_offset b10, -96
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    mov h1, v0.h[1]
 ; CHECK-NEXT:    str q0, [sp] // 16-byte Folded Spill
 ; CHECK-NEXT:    fcvt s8, h1
 ; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    bl __fixsfti
 ; CHECK-NEXT:    movi v9.2s, #255, lsl #24
-; CHECK-NEXT:    mov w8, #2130706431
+; CHECK-NEXT:    mov w8, #2130706431 // =0x7effffff
 ; CHECK-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
-; CHECK-NEXT:    mov x25, #-9223372036854775808
-; CHECK-NEXT:    mov x26, #9223372036854775807
+; CHECK-NEXT:    mov x25, #-9223372036854775808 // =0x8000000000000000
+; CHECK-NEXT:    mov x26, #9223372036854775807 // =0x7fffffffffffffff
 ; CHECK-NEXT:    fmov s10, w8
 ; CHECK-NEXT:    fcmp s8, s9
 ; CHECK-NEXT:    mov h0, v0.h[2]
 ; CHECK-NEXT:    csel x8, xzr, x0, lt
 ; CHECK-NEXT:    csel x9, x25, x1, lt
 ; CHECK-NEXT:    fcmp s8, s10
 ; CHECK-NEXT:    csel x9, x26, x9, gt
 ; CHECK-NEXT:    csinv x8, x8, xzr, le

 declare <8 x i128> @llvm.fptosi.sat.v8f16.v8i128(<8 x half>)
 
 define <8 x i1> @test_signed_v8f16_v8i1(<8 x half> %f) {
 ; CHECK-CVT-LABEL: test_signed_v8f16_v8i1:
 ; CHECK-CVT:       // %bb.0:
 ; CHECK-CVT-NEXT:    fcvtl2 v1.4s, v0.8h
 ; CHECK-CVT-NEXT:    fcvtl v0.4s, v0.4h
 ; CHECK-CVT-NEXT:    mov s2, v1.s[1]
+; CHECK-CVT-NEXT:    mov s3, v1.s[2]
+; CHECK-CVT-NEXT:    mov s4, v1.s[3]
+; CHECK-CVT-NEXT:    mov s5, v0.s[1]
 ; CHECK-CVT-NEXT:    fcvtzs w9, s1
-; CHECK-CVT-NEXT:    fcvtzs w13, s0
+; CHECK-CVT-NEXT:    fcvtzs w10, s0
+; CHECK-CVT-NEXT:    mov s1, v0.s[2]
+; CHECK-CVT-NEXT:    mov s0, v0.s[3]
 ; CHECK-CVT-NEXT:    fcvtzs w8, s2
-; CHECK-CVT-NEXT:    mov s2, v1.s[2]
-; CHECK-CVT-NEXT:    mov s1, v1.s[3]
-; CHECK-CVT-NEXT:    cmp w8, #0
-; CHECK-CVT-NEXT:    csel w8, w8, wzr, lt
-; CHECK-CVT-NEXT:    fcvtzs w10, s2
-; CHECK-CVT-NEXT:    cmp w8, #0
-; CHECK-CVT-NEXT:    mov s2, v0.s[1]
+; CHECK-CVT-NEXT:    fcvtzs w11, s3
+; CHECK-CVT-NEXT:    fcvtzs w12, s4
+; CHECK-CVT-NEXT:    fcvtzs w13, s5
+; CHECK-CVT-NEXT:    ands w8, w8, w8, asr #31
 ; CHECK-CVT-NEXT:    csinv w8, w8, wzr, ge
-; CHECK-CVT-NEXT:    cmp w9, #0
-; CHECK-CVT-NEXT:    csel w9, w9, wzr, lt
-; CHECK-CVT-NEXT:    fcvtzs w11, s1
-; CHECK-CVT-NEXT:    cmp w9, #0
-; CHECK-CVT-NEXT:    mov s1, v0.s[2]
+; CHECK-CVT-NEXT:    ands w9, w9, w9, asr #31
 ; CHECK-CVT-NEXT:    csinv w9, w9, wzr, ge
-; CHECK-CVT-NEXT:    cmp w10, #0
-; CHECK-CVT-NEXT:    csel w10, w10, wzr, lt
-; CHECK-CVT-NEXT:    fcvtzs w12, s2
-; CHECK-CVT-NEXT:    cmp w10, #0
-; CHECK-CVT-NEXT:    mov s0, v0.s[3]
-; CHECK-CVT-NEXT:    csinv w10, w10, wzr, ge
-; CHECK-CVT-NEXT:    cmp w11, #0
-; CHECK-CVT-NEXT:    csel w11, w11, wzr, lt
-; CHECK-CVT-NEXT:    fmov s2, w9
-; CHECK-CVT-NEXT:    cmp w11, #0
+; CHECK-CVT-NEXT:    ands w11, w11, w11, asr #31
 ; CHECK-CVT-NEXT:    csinv w11, w11, wzr, ge
-; CHECK-CVT-NEXT:    cmp w12, #0
-; CHECK-CVT-NEXT:    csel w12, w12, wzr, lt
-; CHECK-CVT-NEXT:    cmp w12, #0
+; CHECK-CVT-NEXT:    ands w12, w12, w12, asr #31
 ; CHECK-CVT-NEXT:    csinv w12, w12, wzr, ge
-; CHECK-CVT-NEXT:    cmp w13, #0
-; CHECK-CVT-NEXT:    csel w13, w13, wzr, lt
-; CHECK-CVT-NEXT:    cmp w13, #0
-; CHECK-CVT-NEXT:    csinv w9, w13, wzr, ge
-; CHECK-CVT-NEXT:    fcvtzs w13, s1
+; CHECK-CVT-NEXT:    ands w13, w13, w13, asr #31
+; CHECK-CVT-NEXT:    csinv w13, w13, wzr, ge
+; CHECK-CVT-NEXT:    ands w10, w10, w10, asr #31
+; CHECK-CVT-NEXT:    csinv w10, w10, wzr, ge
+; CHECK-CVT-NEXT:    fmov s2, w9
+; CHECK-CVT-NEXT:    fcvtzs w9, s1
+; CHECK-CVT-NEXT:    fmov s3, w10
 ; CHECK-CVT-NEXT:    mov v2.s[1], w8
-; CHECK-CVT-NEXT:    fmov s1, w9
-; CHECK-CVT-NEXT:    cmp w13, #0
-; CHECK-CVT-NEXT:    csel w8, w13, wzr, lt
+; CHECK-CVT-NEXT:    ands w8, w9, w9, asr #31
+; CHECK-CVT-NEXT:    csinv w8, w8, wzr, ge
 ; CHECK-CVT-NEXT:    fcvtzs w9, s0
-; CHECK-CVT-NEXT:    cmp w8, #0
-; CHECK-CVT-NEXT:    mov v1.s[1], w12
+; CHECK-CVT-NEXT:    mov v3.s[1], w13
+; CHECK-CVT-NEXT:    mov v2.s[2], w11
+; CHECK-CVT-NEXT:    mov v3.s[2], w8
+; CHECK-CVT-NEXT:    ands w8, w9, w9, asr #31
 ; CHECK-CVT-NEXT:    csinv w8, w8, wzr, ge
-; CHECK-CVT-NEXT:    cmp w9, #0
-; CHECK-CVT-NEXT:    csel w9, w9, wzr, lt
-; CHECK-CVT-NEXT:    mov v2.s[2], w10
-; CHECK-CVT-NEXT:    cmp w9, #0
-; CHECK-CVT-NEXT:    mov v1.s[2], w8
-; CHECK-CVT-NEXT:    csinv w8, w9, wzr, ge
-; CHECK-CVT-NEXT:    mov v2.s[3], w11
-; CHECK-CVT-NEXT:    mov v1.s[3], w8
-; CHECK-CVT-NEXT:    uzp1 v0.8h, v1.8h, v2.8h
+; CHECK-CVT-NEXT:    mov v2.s[3], w12
+; CHECK-CVT-NEXT:    mov v3.s[3], w8
+; CHECK-CVT-NEXT:    uzp1 v0.8h, v3.8h, v2.8h
 ; CHECK-CVT-NEXT:    xtn v0.8b, v0.8h
 ; CHECK-CVT-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: test_signed_v8f16_v8i1:
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    movi v1.2d, #0000000000000000
 ; CHECK-FP16-NEXT:    fcvtzs v0.8h, v0.8h
 ; CHECK-FP16-NEXT:    movi v2.2d, #0xffffffffffffffff
 ; CHECK-FP16-NEXT:    smin v0.8h, v0.8h, v1.8h
 ; CHECK-FP16-NEXT:    smax v0.8h, v0.8h, v2.8h
 ; CHECK-FP16-NEXT:    xtn v0.8b, v0.8h
 ; CHECK-FP16-NEXT:    ret
     %x = call <8 x i1> @llvm.fptosi.sat.v8f16.v8i1(<8 x half> %f)
     ret <8 x i1> %x
 }
 
 define <8 x i8> @test_signed_v8f16_v8i8(<8 x half> %f) {
 ; CHECK-CVT-LABEL: test_signed_v8f16_v8i8:
 ; CHECK-CVT:       // %bb.0:
 ; CHECK-CVT-NEXT:    fcvtl2 v1.4s, v0.8h
-; CHECK-CVT-NEXT:    mov w8, #127
+; CHECK-CVT-NEXT:    mov w8, #127 // =0x7f
 ; CHECK-CVT-NEXT:    fcvtl v0.4s, v0.4h
-; CHECK-CVT-NEXT:    mov w10, #-128
+; CHECK-CVT-NEXT:    mov w10, #-128 // =0xffffff80
 ; CHECK-CVT-NEXT:    mov s2, v1.s[1]
 ; CHECK-CVT-NEXT:    fcvtzs w11, s1
 ; CHECK-CVT-NEXT:    fcvtzs w15, s0
 ; CHECK-CVT-NEXT:    fcvtzs w9, s2
 ; CHECK-CVT-NEXT:    mov s2, v1.s[2]
 ; CHECK-CVT-NEXT:    mov s1, v1.s[3]
 ; CHECK-CVT-NEXT:    cmp w9, #127
 ; CHECK-CVT-NEXT:    csel w9, w9, w8, lt
; CHECK-FP16-NEXT:    ret
     %x = call <8 x i8> @llvm.fptosi.sat.v8f16.v8i8(<8 x half> %f)
     ret <8 x i8> %x
 }
 
 define <8 x i13> @test_signed_v8f16_v8i13(<8 x half> %f) {
 ; CHECK-CVT-LABEL: test_signed_v8f16_v8i13:
 ; CHECK-CVT:       // %bb.0:
 ; CHECK-CVT-NEXT:    fcvtl2 v1.4s, v0.8h
-; CHECK-CVT-NEXT:    mov w8, #4095
+; CHECK-CVT-NEXT:    mov w8, #4095 // =0xfff
 ; CHECK-CVT-NEXT:    fcvtl v0.4s, v0.4h
-; CHECK-CVT-NEXT:    mov w10, #-4096
+; CHECK-CVT-NEXT:    mov w10, #-4096 // =0xfffff000
 ; CHECK-CVT-NEXT:    mov s2, v1.s[1]
 ; CHECK-CVT-NEXT:    fcvtzs w11, s1
 ; CHECK-CVT-NEXT:    fcvtzs w15, s0
 ; CHECK-CVT-NEXT:    fcvtzs w9, s2
 ; CHECK-CVT-NEXT:    mov s2, v1.s[2]
 ; CHECK-CVT-NEXT:    mov s1, v1.s[3]
 ; CHECK-CVT-NEXT:    cmp w9, #4095
 ; CHECK-CVT-NEXT:    csel w9, w9, w8, lt
; CHECK-FP16-NEXT:    ret
     %x = call <8 x i13> @llvm.fptosi.sat.v8f16.v8i13(<8 x half> %f)
     ret <8 x i13> %x
 }
 
 define <8 x i16> @test_signed_v8f16_v8i16(<8 x half> %f) {
 ; CHECK-CVT-LABEL: test_signed_v8f16_v8i16:
 ; CHECK-CVT:       // %bb.0:
 ; CHECK-CVT-NEXT:    fcvtl2 v1.4s, v0.8h
-; CHECK-CVT-NEXT:    mov w8, #32767
+; CHECK-CVT-NEXT:    mov w8, #32767 // =0x7fff
 ; CHECK-CVT-NEXT:    fcvtl v0.4s, v0.4h
-; CHECK-CVT-NEXT:    mov w10, #-32768
+; CHECK-CVT-NEXT:    mov w10, #-32768 // =0xffff8000
 ; CHECK-CVT-NEXT:    mov s2, v1.s[1]
 ; CHECK-CVT-NEXT:    fcvtzs w11, s1
 ; CHECK-CVT-NEXT:    fcvtzs w15, s0
 ; CHECK-CVT-NEXT:    fcvtzs w9, s2
 ; CHECK-CVT-NEXT:    mov s2, v1.s[2]
 ; CHECK-CVT-NEXT:    mov s1, v1.s[3]
 ; CHECK-CVT-NEXT:    cmp w9, w8
 ; CHECK-CVT-NEXT:    csel w9, w9, w8, lt
; CHECK-NEXT:    ret
     %x = call <8 x i32> @llvm.fptosi.sat.v8f16.v8i32(<8 x half> %f)
     ret <8 x i32> %x
 }
 
 define <8 x i50> @test_signed_v8f16_v8i50(<8 x half> %f) {
 ; CHECK-CVT-LABEL: test_signed_v8f16_v8i50:
 ; CHECK-CVT:       // %bb.0:
 ; CHECK-CVT-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-CVT-NEXT:    mov x8, #562949953421311
-; CHECK-CVT-NEXT:    mov x12, #-562949953421312
+; CHECK-CVT-NEXT:    mov x8, #562949953421311 // =0x1ffffffffffff
+; CHECK-CVT-NEXT:    mov x12, #-562949953421312 // =0xfffe000000000000
 ; CHECK-CVT-NEXT:    fcvt s5, h0
 ; CHECK-CVT-NEXT:    mov h2, v1.h[1]
 ; CHECK-CVT-NEXT:    fcvt s3, h1
 ; CHECK-CVT-NEXT:    mov h4, v1.h[2]
 ; CHECK-CVT-NEXT:    mov h1, v1.h[3]
 ; CHECK-CVT-NEXT:    fcvtzs x10, s5
 ; CHECK-CVT-NEXT:    fcvt s2, h2
 ; CHECK-CVT-NEXT:    fcvtzs x9, s3

 ; CHECK-CVT-NEXT:    csel x8, x11, x8, lt
 ; CHECK-CVT-NEXT:    cmp x8, x12
 ; CHECK-CVT-NEXT:    csel x3, x8, x12, gt
 ; CHECK-CVT-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: test_signed_v8f16_v8i50:
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-FP16-NEXT:    mov x8, #562949953421311
-; CHECK-FP16-NEXT:    mov x11, #-562949953421312
+; CHECK-FP16-NEXT:    mov x8, #562949953421311 // =0x1ffffffffffff
+; CHECK-FP16-NEXT:    mov x11, #-562949953421312 // =0xfffe000000000000
 ; CHECK-FP16-NEXT:    mov h2, v1.h[1]
 ; CHECK-FP16-NEXT:    fcvtzs x9, h1
 ; CHECK-FP16-NEXT:    mov h3, v1.h[2]
 ; CHECK-FP16-NEXT:    mov h1, v1.h[3]
 ; CHECK-FP16-NEXT:    cmp x9, x8
 ; CHECK-FP16-NEXT:    fcvtzs x10, h2
 ; CHECK-FP16-NEXT:    csel x9, x9, x8, lt
 ; CHECK-FP16-NEXT:    cmp x9, x11

 ; CHECK-NEXT:    mov x19, x8
 ; CHECK-NEXT:    ext v0.16b, v0.16b, v0.16b, #8
 ; CHECK-NEXT:    str q0, [sp, #32] // 16-byte Folded Spill
 ; CHECK-NEXT:    mov h0, v0.h[1]
 ; CHECK-NEXT:    fcvt s8, h0
 ; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    bl __fixsfti
 ; CHECK-NEXT:    movi v10.2s, #241, lsl #24
-; CHECK-NEXT:    mov w8, #1895825407
+; CHECK-NEXT:    mov w8, #1895825407 // =0x70ffffff
 ; CHECK-NEXT:    ldr q0, [sp, #32] // 16-byte Folded Reload
-; CHECK-NEXT:    mov x25, #-34359738368
-; CHECK-NEXT:    mov x22, #34359738367
+; CHECK-NEXT:    mov x25, #-34359738368 // =0xfffffff800000000
+; CHECK-NEXT:    mov x22, #34359738367 // =0x7ffffffff
 ; CHECK-NEXT:    fmov s9, w8
 ; CHECK-NEXT:    fcmp s8, s10
 ; CHECK-NEXT:    mov h0, v0.h[3]
 ; CHECK-NEXT:    csel x8, x25, x1, lt
 ; CHECK-NEXT:    csel x9, xzr, x0, lt
 ; CHECK-NEXT:    fcmp s8, s9
 ; CHECK-NEXT:    csinv x9, x9, xzr, le
 ; CHECK-NEXT:    csel x8, x22, x8, gt

 ; CHECK-NEXT:    str q0, [sp, #48] // 16-byte Folded Spill
 ; CHECK-NEXT:    mov x19, x8
 ; CHECK-NEXT:    ext v0.16b, v0.16b, v0.16b, #8
 ; CHECK-NEXT:    fcvt s8, h0
 ; CHECK-NEXT:    str q0, [sp, #32] // 16-byte Folded Spill
 ; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    bl __fixsfti
 ; CHECK-NEXT:    movi v10.2s, #255, lsl #24
-; CHECK-NEXT:    mov w8, #2130706431
+; CHECK-NEXT:    mov w8, #2130706431 // =0x7effffff
 ; CHECK-NEXT:    ldr q0, [sp, #32] // 16-byte Folded Reload
-; CHECK-NEXT:    mov x21, #-9223372036854775808
-; CHECK-NEXT:    mov x22, #9223372036854775807
+; CHECK-NEXT:    mov x21, #-9223372036854775808 // =0x8000000000000000
+; CHECK-NEXT:    mov x22, #9223372036854775807 // =0x7fffffffffffffff
 ; CHECK-NEXT:    fmov s9, w8
 ; CHECK-NEXT:    fcmp s8, s10
 ; CHECK-NEXT:    mov h0, v0.h[1]
 ; CHECK-NEXT:    csel x8, xzr, x0, lt
 ; CHECK-NEXT:    csel x9, x21, x1, lt
 ; CHECK-NEXT:    fcmp s8, s9
 ; CHECK-NEXT:    csel x9, x22, x9, gt
 ; CHECK-NEXT:    csinv x8, x8, xzr, le

 }
 
 
 
 define <16 x i8> @test_signed_v16f16_v16i8(<16 x half> %f) {
 ; CHECK-CVT-LABEL: test_signed_v16f16_v16i8:
 ; CHECK-CVT:       // %bb.0:
 ; CHECK-CVT-NEXT:    fcvtl2 v2.4s, v1.8h
-; CHECK-CVT-NEXT:    mov w8, #127
+; CHECK-CVT-NEXT:    mov w8, #127 // =0x7f
 ; CHECK-CVT-NEXT:    fcvtl v1.4s, v1.4h
-; CHECK-CVT-NEXT:    mov w9, #-128
+; CHECK-CVT-NEXT:    mov w9, #-128 // =0xffffff80
 ; CHECK-CVT-NEXT:    mov s3, v2.s[1]
 ; CHECK-CVT-NEXT:    fcvtzs w11, s2
 ; CHECK-CVT-NEXT:    fcvtzs w10, s3
 ; CHECK-CVT-NEXT:    mov s3, v2.s[2]
 ; CHECK-CVT-NEXT:    mov s2, v2.s[3]
 ; CHECK-CVT-NEXT:    cmp w10, #127
 ; CHECK-CVT-NEXT:    csel w10, w10, w8, lt
 ; CHECK-CVT-NEXT:    fcvtzs w12, s3
; CHECK-FP16-NEXT:    ret
     %x = call <16 x i8> @llvm.fptosi.sat.v16f16.v16i8(<16 x half> %f)
     ret <16 x i8> %x
 }
 
 define <16 x i16> @test_signed_v16f16_v16i16(<16 x half> %f) {
 ; CHECK-CVT-LABEL: test_signed_v16f16_v16i16:
 ; CHECK-CVT:       // %bb.0:
 ; CHECK-CVT-NEXT:    fcvtl2 v2.4s, v0.8h
-; CHECK-CVT-NEXT:    mov w8, #32767
+; CHECK-CVT-NEXT:    mov w8, #32767 // =0x7fff
 ; CHECK-CVT-NEXT:    fcvtl v0.4s, v0.4h
-; CHECK-CVT-NEXT:    mov w9, #-32768
+; CHECK-CVT-NEXT:    mov w9, #-32768 // =0xffff8000
 ; CHECK-CVT-NEXT:    mov s3, v2.s[1]
 ; CHECK-CVT-NEXT:    fcvtzs w11, s2
 ; CHECK-CVT-NEXT:    fcvtzs w10, s3
 ; CHECK-CVT-NEXT:    mov s3, v2.s[2]
 ; CHECK-CVT-NEXT:    mov s2, v2.s[3]
 ; CHECK-CVT-NEXT:    cmp w10, w8
 ; CHECK-CVT-NEXT:    csel w10, w10, w8, lt
 ; CHECK-CVT-NEXT:    fcvtzs w12, s3
; CHECK-FP16-NEXT:    ret
     %x = call <16 x i16> @llvm.fptosi.sat.v16f16.v16i16(<16 x half> %f)
     ret <16 x i16> %x
 }
 
 define <8 x i8> @test_signed_v8f64_v8i8(<8 x double> %f) {
 ; CHECK-LABEL: test_signed_v8f64_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov d4, v3.d[1]
-; CHECK-NEXT:    mov w8, #127
+; CHECK-NEXT:    mov w8, #127 // =0x7f
 ; CHECK-NEXT:    fcvtzs w10, d3
-; CHECK-NEXT:    mov w11, #-128
+; CHECK-NEXT:    mov w11, #-128 // =0xffffff80
 ; CHECK-NEXT:    mov d3, v1.d[1]
 ; CHECK-NEXT:    fcvtzs w13, d2
 ; CHECK-NEXT:    fcvtzs w15, d1
 ; CHECK-NEXT:    mov d1, v0.d[1]
 ; CHECK-NEXT:    fcvtzs w9, d4
 ; CHECK-NEXT:    mov d4, v2.d[1]
 ; CHECK-NEXT:    fcvtzs w14, d3
 ; CHECK-NEXT:    cmp w9, #127
; CHECK-NEXT:    ret
     %x = call <8 x i8> @llvm.fptosi.sat.v8f64.v8i8(<8 x double> %f)
     ret <8 x i8> %x
 }
 
 define <16 x i8> @test_signed_v16f64_v16i8(<16 x double> %f) {
 ; CHECK-LABEL: test_signed_v16f64_v16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov d16, v0.d[1]
-; CHECK-NEXT:    mov w8, #127
+; CHECK-NEXT:    mov w8, #127 // =0x7f
 ; CHECK-NEXT:    fcvtzs w11, d0
-; CHECK-NEXT:    mov w9, #-128
+; CHECK-NEXT:    mov w9, #-128 // =0xffffff80
 ; CHECK-NEXT:    mov d0, v2.d[1]
 ; CHECK-NEXT:    fcvtzs w13, d1
 ; CHECK-NEXT:    fcvtzs w10, d16
 ; CHECK-NEXT:    mov d16, v1.d[1]
 ; CHECK-NEXT:    fcvtzs w14, d0
 ; CHECK-NEXT:    cmp w10, #127
 ; CHECK-NEXT:    csel w10, w10, w8, lt
 ; CHECK-NEXT:    fcvtzs w12, d16
; CHECK-NEXT:    ret
     %x = call <16 x i8> @llvm.fptosi.sat.v16f64.v16i8(<16 x double> %f)
     ret <16 x i8> %x
 }
 
 define <8 x i16> @test_signed_v8f64_v8i16(<8 x double> %f) {
 ; CHECK-LABEL: test_signed_v8f64_v8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov d4, v3.d[1]
-; CHECK-NEXT:    mov w8, #32767
+; CHECK-NEXT:    mov w8, #32767 // =0x7fff
 ; CHECK-NEXT:    fcvtzs w10, d3
-; CHECK-NEXT:    mov w11, #-32768
+; CHECK-NEXT:    mov w11, #-32768 // =0xffff8000
 ; CHECK-NEXT:    mov d3, v1.d[1]
 ; CHECK-NEXT:    fcvtzs w13, d2
 ; CHECK-NEXT:    fcvtzs w15, d1
 ; CHECK-NEXT:    mov d1, v0.d[1]
 ; CHECK-NEXT:    fcvtzs w9, d4
 ; CHECK-NEXT:    mov d4, v2.d[1]
 ; CHECK-NEXT:    fcvtzs w14, d3
 ; CHECK-NEXT:    cmp w9, w8
; CHECK-NEXT:    ret
     %x = call <8 x i16> @llvm.fptosi.sat.v8f64.v8i16(<8 x double> %f)
     ret <8 x i16> %x
 }
 
 define <16 x i16> @test_signed_v16f64_v16i16(<16 x double> %f) {
 ; CHECK-LABEL: test_signed_v16f64_v16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov d16, v3.d[1]
-; CHECK-NEXT:    mov w9, #32767
+; CHECK-NEXT:    mov w9, #32767 // =0x7fff
 ; CHECK-NEXT:    fcvtzs w11, d3
-; CHECK-NEXT:    mov w8, #-32768
+; CHECK-NEXT:    mov w8, #-32768 // =0xffff8000
 ; CHECK-NEXT:    mov d3, v1.d[1]
 ; CHECK-NEXT:    fcvtzs w14, d2
 ; CHECK-NEXT:    fcvtzs w15, d1
 ; CHECK-NEXT:    mov d1, v7.d[1]
 ; CHECK-NEXT:    fcvtzs w10, d16
 ; CHECK-NEXT:    mov d16, v2.d[1]
 ; CHECK-NEXT:    mov d2, v0.d[1]
 ; CHECK-NEXT:    fcvtzs w18, d0

llvm/test/CodeGen/AArch64/min-max-combine.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple=aarch64-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-ISEL
+; RUN: llc -mtriple=aarch64-eabi %s -o - -mattr=cssc | FileCheck %s --check-prefixes=CHECK-CSSC
+; RUN: llc -mtriple=aarch64-eabi -global-isel %s -o - | FileCheck %s --check-prefixes=CHECK-GLOBAL
+; RUN: llc -mtriple=aarch64-eabi -global-isel %s -o - -mattr=cssc | FileCheck %s --check-prefixes=CHECK-CSSC
+
+; These tests check for @llvm.smax, @llvm.smin combines.
+
+; SMAX
+
+declare i8 @llvm.smax.i8(i8 %a, i8 %b) readnone
+
+define i8 @smaxi8_zero(i8 %a) {
+; CHECK-ISEL-LABEL: smaxi8_zero:
+; CHECK-ISEL:       // %bb.0:
+; CHECK-ISEL-NEXT:    sxtb w8, w0
+; CHECK-ISEL-NEXT:    bic w0, w8, w8, asr #31
+; CHECK-ISEL-NEXT:    ret
+;
+; CHECK-CSSC-LABEL: smaxi8_zero:
+; CHECK-CSSC:       // %bb.0:
+; CHECK-CSSC-NEXT:    sxtb w8, w0
+; CHECK-CSSC-NEXT:    smax w0, w8, #0
+; CHECK-CSSC-NEXT:    ret
+;
+; CHECK-GLOBAL-LABEL: smaxi8_zero:
+; CHECK-GLOBAL:       // %bb.0:
+; CHECK-GLOBAL-NEXT:    sxtb w8, w0
+; CHECK-GLOBAL-NEXT:    cmp w8, #0
+; CHECK-GLOBAL-NEXT:    csel w0, w0, wzr, gt
+; CHECK-GLOBAL-NEXT:    ret
+  %c = call i8 @llvm.smax.i8(i8 %a, i8 0)
+  ret i8 %c
+}
+
+declare i16 @llvm.smax.i16(i16 %a, i16 %b) readnone
+
+define i16 @smaxi16_zero(i16 %a) {
+; CHECK-ISEL-LABEL: smaxi16_zero:
+; CHECK-ISEL:       // %bb.0:
+; CHECK-ISEL-NEXT:    sxth w8, w0
+; CHECK-ISEL-NEXT:    bic w0, w8, w8, asr #31
+; CHECK-ISEL-NEXT:    ret
+;
+; CHECK-CSSC-LABEL: smaxi16_zero:
+; CHECK-CSSC:       // %bb.0:
+; CHECK-CSSC-NEXT:    sxth w8, w0
+; CHECK-CSSC-NEXT:    smax w0, w8, #0
+; CHECK-CSSC-NEXT:    ret
+;
+; CHECK-GLOBAL-LABEL: smaxi16_zero:
+; CHECK-GLOBAL:       // %bb.0:
+; CHECK-GLOBAL-NEXT:    sxth w8, w0
+; CHECK-GLOBAL-NEXT:    cmp w8, #0
+; CHECK-GLOBAL-NEXT:    csel w0, w0, wzr, gt
+; CHECK-GLOBAL-NEXT:    ret
+  %c = call i16 @llvm.smax.i16(i16 %a, i16 0)
+  ret i16 %c
+}
+
+declare i32 @llvm.smax.i32(i32 %a, i32 %b) readnone
+
+define i32 @smaxi32_zero(i32 %a) {
+; CHECK-ISEL-LABEL: smaxi32_zero:
+; CHECK-ISEL:       // %bb.0:
+; CHECK-ISEL-NEXT:    bic w0, w0, w0, asr #31
+; CHECK-ISEL-NEXT:    ret
+;
+; CHECK-CSSC-LABEL: smaxi32_zero:
+; CHECK-CSSC:       // %bb.0:
+; CHECK-CSSC-NEXT:    smax w0, w0, #0
+; CHECK-CSSC-NEXT:    ret
+;
+; CHECK-GLOBAL-LABEL: smaxi32_zero:
+; CHECK-GLOBAL:       // %bb.0:
+; CHECK-GLOBAL-NEXT:    cmp w0, #0
+; CHECK-GLOBAL-NEXT:    csel w0, w0, wzr, gt
+; CHECK-GLOBAL-NEXT:    ret
+  %c = call i32 @llvm.smax.i32(i32 %a, i32 0)
+  ret i32 %c
+}
+
+declare i64 @llvm.smax.i64(i64 %a, i64 %b) readnone
+
+define i64 @smaxi64_zero(i64 %a) {
+; CHECK-ISEL-LABEL: smaxi64_zero:
+; CHECK-ISEL:       // %bb.0:
+; CHECK-ISEL-NEXT:    bic x0, x0, x0, asr #63
+; CHECK-ISEL-NEXT:    ret
+;
+; CHECK-CSSC-LABEL: smaxi64_zero:
+; CHECK-CSSC:       // %bb.0:
+; CHECK-CSSC-NEXT:    smax x0, x0, #0
+; CHECK-CSSC-NEXT:    ret
+;
+; CHECK-GLOBAL-LABEL: smaxi64_zero:
+; CHECK-GLOBAL:       // %bb.0:
+; CHECK-GLOBAL-NEXT:    cmp x0, #0
+; CHECK-GLOBAL-NEXT:    csel x0, x0, xzr, gt
+; CHECK-GLOBAL-NEXT:    ret
+  %c = call i64 @llvm.smax.i64(i64 %a, i64 0)
+  ret i64 %c
+}
+
+; SMIN
+
+declare i8 @llvm.smin.i8(i8 %a, i8 %b) readnone
+
+define i8 @smini8_zero(i8 %a) {
+; CHECK-ISEL-LABEL: smini8_zero:
+; CHECK-ISEL:       // %bb.0:
+; CHECK-ISEL-NEXT:    sxtb w8, w0
+; CHECK-ISEL-NEXT:    and w0, w8, w8, asr #31
+; CHECK-ISEL-NEXT:    ret
+;
+; CHECK-CSSC-LABEL: smini8_zero:
+; CHECK-CSSC:       // %bb.0:
+; CHECK-CSSC-NEXT:    sxtb w8, w0
+; CHECK-CSSC-NEXT:    smin w0, w8, #0
+; CHECK-CSSC-NEXT:    ret
+;
+; CHECK-GLOBAL-LABEL: smini8_zero:
+; CHECK-GLOBAL:       // %bb.0:
+; CHECK-GLOBAL-NEXT:    sxtb w8, w0
+; CHECK-GLOBAL-NEXT:    cmp w8, #0
+; CHECK-GLOBAL-NEXT:    csel w0, w0, wzr, lt
+; CHECK-GLOBAL-NEXT:    ret
+  %c = call i8 @llvm.smin.i8(i8 %a, i8 0)
+  ret i8 %c
+}
+
+declare i16 @llvm.smin.i16(i16 %a, i16 %b) readnone
+
+define i16 @smini16_zero(i16 %a) {
+; CHECK-ISEL-LABEL: smini16_zero:
+; CHECK-ISEL:       // %bb.0:
+; CHECK-ISEL-NEXT:    sxth w8, w0
+; CHECK-ISEL-NEXT:    and w0, w8, w8, asr #31
+; CHECK-ISEL-NEXT:    ret
+;
+; CHECK-CSSC-LABEL: smini16_zero:
+; CHECK-CSSC:       // %bb.0:
+; CHECK-CSSC-NEXT:    sxth w8, w0
+; CHECK-CSSC-NEXT:    smin w0, w8, #0
+; CHECK-CSSC-NEXT:    ret
+;
+; CHECK-GLOBAL-LABEL: smini16_zero:
+; CHECK-GLOBAL:       // %bb.0:
+; CHECK-GLOBAL-NEXT:    sxth w8, w0
+; CHECK-GLOBAL-NEXT:    cmp w8, #0
+; CHECK-GLOBAL-NEXT:    csel w0, w0, wzr, lt
+; CHECK-GLOBAL-NEXT:    ret
+  %c = call i16 @llvm.smin.i16(i16 %a, i16 0)
+  ret i16 %c
+}
+
+declare i32 @llvm.smin.i32(i32 %a, i32 %b) readnone
+
+define i32 @smini32_zero(i32 %a) {
+; CHECK-ISEL-LABEL: smini32_zero:
+; CHECK-ISEL:       // %bb.0:
+; CHECK-ISEL-NEXT:    and w0, w0, w0, asr #31
+; CHECK-ISEL-NEXT:    ret
+;
+; CHECK-CSSC-LABEL: smini32_zero:
+; CHECK-CSSC:       // %bb.0:
+; CHECK-CSSC-NEXT:    smin w0, w0, #0
+; CHECK-CSSC-NEXT:    ret
+;
+; CHECK-GLOBAL-LABEL: smini32_zero:
+; CHECK-GLOBAL:       // %bb.0:
+; CHECK-GLOBAL-NEXT:    cmp w0, #0
+; CHECK-GLOBAL-NEXT:    csel w0, w0, wzr, lt
+; CHECK-GLOBAL-NEXT:    ret
+  %c = call i32 @llvm.smin.i32(i32 %a, i32 0)
+  ret i32 %c
+}
+
+declare i64 @llvm.smin.i64(i64 %a, i64 %b) readnone
+
+define i64 @smini64_zero(i64 %a) {
+; CHECK-ISEL-LABEL: smini64_zero:
+; CHECK-ISEL:       // %bb.0:
+; CHECK-ISEL-NEXT:    and x0, x0, x0, asr #63
+; CHECK-ISEL-NEXT:    ret
+;
+; CHECK-CSSC-LABEL: smini64_zero:
+; CHECK-CSSC:       // %bb.0:
+; CHECK-CSSC-NEXT:    smin x0, x0, #0
+; CHECK-CSSC-NEXT:    ret
+;
+; CHECK-GLOBAL-LABEL: smini64_zero:
+; CHECK-GLOBAL:       // %bb.0:
+; CHECK-GLOBAL-NEXT:    cmp x0, #0
+; CHECK-GLOBAL-NEXT:    csel x0, x0, xzr, lt
+; CHECK-GLOBAL-NEXT:    ret
+  %c = call i64 @llvm.smin.i64(i64 %a, i64 0)
+  ret i64 %c
+}