[AMDGPU] Update Subtarget isWave32 method to ignore the wave32 feature pre-gfx9

[skc7]

Summary

si-optimize-exec-masking pass is generating saveexec_b32 ops based on isWave32() without checking if target generation > gfx10 targets.
This patch updates isWave32 method to check for gfx10 and above targets and whether subtarget has FeatureWavefrontSize32.

Test case is added to check if si-optimize-exec-masking pass generates S_ANDN2_SAVEEXEC_B32 or S_ANDN2_SAVEEXEC_B64 correctly.

[arsenm]

The correct way to address this would be to make isWave32 ignore the wave32 feature pre-gfx9

[arsenm]

If we’re going to do this, no changes should be needed in SIFrameLowering. The wavesize set in the subtarget constructor would be adjusted to consistently apply this everywhere. The prolog code is a very minor piece of this

[skc7]

In D148142#4378978, @arsenm wrote:

If we’re going to do this, no changes should be needed in SIFrameLowering. The wavesize set in the subtarget constructor would be adjusted to consistently apply this everywhere. The prolog code is a very minor piece of this

@arsenm isWave32() method in GCNSubtarget class needs to be updated to ignore wave32 feature pre-gfx9 ?

[skc7]

Update test.

[arsenm]

You can achieve this in the subtarget constructor by setting the wavefrontsize member. This would also be a strategy change vs. the AMDGPURemoveIncompatibleFunctions and doesn't belong in a patch to fix the saveexec combine

llvm/test/CodeGen/AMDGPU/saveexec-xor-optimize.mir

2 ↗

(On Diff #526897)

The exec masking issue is not solved by this. The pass itself needs to check whether the 32-bit saveexec operations are legal (i.e. gfx10). It's not directly broken because of wave32

21 ↗

(On Diff #526897)

the saveexec isn't supposed to exist in the input

llvm/lib/Target/AMDGPU/GCNSubtarget.h

   void getPostRAMutations(
       std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
       const override;
 
   std::unique_ptr<ScheduleDAGMutation>
   createFillMFMAShadowMutation(const TargetInstrInfo *TII) const;
 
   bool isWave32() const {
-    return getWavefrontSize() == 32;
+    return (getGeneration() >= AMDGPUSubtarget::GFX10) &&
+           hasFeature(AMDGPU::FeatureWavefrontSize32) &&
+           (getWavefrontSize() == 32);
   }
 
   bool isWave64() const {
     return getWavefrontSize() == 64;
   }
 
   const TargetRegisterClass *getBoolRC() const {
     return getRegisterInfo()->getBoolRC();

llvm/test/CodeGen/AMDGPU/saveexec-xor-optimize-wave32.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
+# RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32 -run-pass=si-optimize-exec-masking -verify-machineinstrs %s -o - | FileCheck --check-prefixes=GFX10 %s
+# RUN: llc -march=amdgcn -mcpu=gfx90a -mattr=+wavefrontsize32 -run-pass=si-optimize-exec-masking -verify-machineinstrs %s -o - | FileCheck --check-prefixes=GFX9 %s
+
+---
+
+name: s_or_saveexec_xor_combine_b32
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $sgpr0
+    ; GFX10-LABEL: name: s_or_saveexec_xor_combine_b32
+    ; GFX10: liveins: $sgpr0
+    ; GFX10-NEXT: {{  $}}
+    ; GFX10-NEXT: $sgpr0 = S_ANDN2_SAVEEXEC_B32 $sgpr0, implicit-def $exec, implicit-def $scc, implicit $exec
+    ; GFX9-LABEL: name: s_or_saveexec_xor_combine_b32
+    ; GFX9: liveins: $sgpr0
+    ; GFX9-NEXT: {{  $}}
+    ; GFX9-NEXT: renamable $sgpr0 = S_OR_SAVEEXEC_B32 killed renamable $sgpr0, implicit-def $exec, implicit-def $scc, implicit $exec
+    ; GFX9-NEXT: $exec_lo = S_XOR_B32 $exec_lo, renamable $sgpr0, implicit-def $scc
+    renamable $sgpr0 = S_OR_SAVEEXEC_B32 killed renamable $sgpr0, implicit-def $exec, implicit-def $scc, implicit $exec
+    $exec_lo = S_XOR_B32 $exec_lo, renamable $sgpr0, implicit-def $scc
+...